/* * Copyright 2018 NXP. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. **********************************************************************************************************************/ /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Pins v4.1 processor: MKV11Z128xxx7 package_id: MKV11Z128VLF7 mcu_data: ksdk2_0 processor_version: 4.0.0 board: HVP-KV11Z75M pin_labels: - {pin_num: '26', pin_signal: PTA20/RESET_b, label: 'J3[10]/U2[21]/U5[11]/SW1/''/RESET''/''/RESET_ISOLATED''', identifier: RESET} - {pin_num: '36', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/FTM3_FLT0, label: USER_LED_2, identifier: LED_RED} - {pin_num: '43', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART0_RX/FTM0_CH2/FTM3_CH2/I2C0_SCL, label: 'MB_J11[B20]/MB_U9[4]/MB_USER_LED/J4[B20]/USER_LED', identifier: LED_GREEN} - {pin_num: '17', pin_signal: PTA0/UART0_CTS_b/FTM0_CH5/EWM_IN/SWD_CLK, label: 'J3[4]/U4[11]/U5[13]/SWCLK/SWDCLK_ISOLATED'} - {pin_num: '1', pin_signal: VDD1, label: 3V3} - {pin_num: '22', pin_signal: VDD22, label: 3V3} - {pin_num: '9', pin_signal: VDDA, label: 3V3A} - {pin_num: '10', pin_signal: VREFH, label: 3V3A} - {pin_num: '11', pin_signal: VREFL, label: AGND} - {pin_num: '2', pin_signal: VSS2, label: GND} - {pin_num: '12', pin_signal: VSSA, label: AGND} - {pin_num: '23', pin_signal: VSS23, label: GND} - {pin_num: '3', pin_signal: ADC0_SE1/ADC0_DP1/ADC1_SE0/PTE16/SPI0_PCS0/UART1_TX/FTM_CLKIN0/FTM0_FLT3, label: 'MB_J11[B8]/MB_TP41/MB_BEMF_sense_C/MB_Phase_C/J4[B8]/BEMF_C', identifier: BEMF_C} - {pin_num: '4', pin_signal: ADC0_DM1/ADC0_SE5/ADC1_SE5/PTE17/LLWU_P19/SPI0_SCK/UART1_RX/FTM_CLKIN1/LPTMR0_ALT3, label: 'MB_J11[A9]/MB_U2A[1]/MB_TP5/MB_Ipfc2/J4[A9]/I_pfc2', identifier: I_PFC2} - {pin_num: '5', pin_signal: ADC0_SE6/ADC1_SE1/ADC1_DP1/PTE18/LLWU_P20/SPI0_SOUT/UART1_CTS_b/I2C0_SDA/SPI0_SIN, label: 'MB_J11[B3]/MB_U8B[7]/MB_TP34/MB_I_sense_DCB/J4[B3]/I_dcb', identifier: I_DCB} - {pin_num: '6', pin_signal: ADC0_SE7/ADC1_SE7/ADC1_DM1/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL/SPI0_SOUT, label: 'MB_J11[A5]/MB_U8A[1]/MB_TP37/MB_I_sense_C/J4[A5]/I_phC', identifier: I_PH_C} - {pin_num: '7', pin_signal: ADC0_SE0/ADC0_DP0/PTE20/FTM1_CH0/UART0_TX, label: 'MB_J11[A5]/MB_U8A[1]/MB_TP37/MB_I_sense_C/J4[A5]/I_phC', identifier: I_PH_C_2} - {pin_num: '8', pin_signal: ADC0_SE4/ADC0_DM0/PTE21/FTM1_CH1/UART0_RX, label: 'MB_J11[B4]/MB_TP31/MB_V_sense_DCB/MB_DCB_Pos/J4[B4]/U_dcb', identifier: U_DCB} - {pin_num: '15', pin_signal: PTE24/CAN0_TX/FTM0_CH0/I2C0_SCL/EWM_OUT_b, label: 'MB_J11[A14]/MB_U12[18]/MB_PWM_AT/J4[A14]/PWM0', identifier: PWM_AT} - {pin_num: '16', pin_signal: PTE25/LLWU_P21/CAN0_RX/FTM0_CH1/I2C0_SDA/EWM_IN, label: 'MB_J11[A15]/MB_U12[12]/MB_PWM_AB/J4[A15]/PWM1', identifier: PWM_AB} - {pin_num: '13', pin_signal: CMP1_IN5/CMP0_IN5/PTE29/FTM0_CH2/FTM_CLKIN0, label: 'MB_J9[5]/MB_J11[B16]/MB_TP19/MB_ENC_Index/J4[B16]/TM2', identifier: ENC_INDEX} - {pin_num: '14', pin_signal: ADC1_SE4/CMP1_IN4/DAC0_OUT/PTE30/FTM0_CH3/FTM_CLKIN1, label: 'MB_J11[A3]/MB_U11A[1]/MB_TP45/MB_I_sense_A/J4[A3]/I_phA', identifier: I_PH_A} - {pin_num: '18', pin_signal: PTA1/UART0_RX/FTM2_CH0/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1/FTM4_CH0, label: 'MB_J9[3]/MB_J11[B14]/MB_TP13/MB_ENC_PhaseA/J4[B14]/TM0', identifier: ENC_PHASE_A} - {pin_num: '19', pin_signal: PTA2/UART0_TX/FTM2_CH1/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/FTM4_CH1, label: 'MB_J9[4]/MB_J11[B15]/MB_TP17/MB_ENC_PhaseB/J4[B15]/TM1', identifier: ENC_PHASE_B} - {pin_num: '20', pin_signal: PTA3/UART0_RTS_b/FTM0_CH0/FTM2_FLT0/EWM_OUT_b/SWD_DIO, label: 'J3[2]/U4[3]/U5[14]/SWDIO/SWDIO_ISOLATED'} - {pin_num: '21', pin_signal: PTA4/LLWU_P3/FTM0_CH1/FTM4_FLT0/FTM0_FLT3/NMI_b, label: 'MB_J11[B22]/MB_PFC_zc_1/J4[B22]/MB_TP_26', identifier: PFC_ZC_1} - {pin_num: '24', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/FTM3_CH2, label: 'MB_J11[B28]/MB_Q3[1]/MB_Relay/J4[B28]/Relay', identifier: RELAY} - {pin_num: '25', pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, label: 'MB_J11[A26]/MB_U9[2]/MB_TP35/MB_FAULT_2/MB_Over-voltage_FAULT/J4[A26]/FAULT_2', identifier: FAULT_2} - {pin_num: '27', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX, label: 'MB_J11[B6]/MB_TP44/MB_BEMF_sense_A/MB_Phase_A/J4[B6]/BEMF_A', identifier: BEMF_A} - {pin_num: '29', pin_signal: ADC0_SE10/ADC1_SE10/ADC1_DM2/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3, label: 'MB_J11[B7]/MB_TP43/MB_BEMF_sense_B/MB_Phase_B/J4[B7]/BEMF_B', identifier: BEMF_B} - {pin_num: '28', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX, label: 'MB_J11[A4]/MB_U11B[7]/MB_TP40/MB_I_sense_B/J4[A4]/I_phB', identifier: I_PH_B} - {pin_num: '30', pin_signal: ADC1_SE2/ADC1_DP2/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0, label: 'MB_J11[A7]/MB_TP18/MB_Vin/J4[A7]/V_in', identifier: V_IN} - {pin_num: '31', pin_signal: PTB16/UART0_RX/FTM_CLKIN2/CAN0_TX/EWM_IN, label: 'MB_J3[2]/MB_J11[B27]/MB_U1[12]/MB_U3[26]/MB_TP2/MB_TP10/MB_RxD/J4[B27]/RxD', identifier: RXD} - {pin_num: '32', pin_signal: PTB17/UART0_TX/FTM_CLKIN1/CAN0_RX/EWM_OUT_b, label: 'MB_J1[3]/MB_J11[B26]/MB_U1[13]/MB_U3[25]/MB_TP3/MB_TP7/MB_TxD/J4[B26]/TxD', identifier: TXD} - {pin_num: '33', pin_signal: ADC1_SE11/PTC0/SPI0_PCS4/PDB_EXTRG0/CMP0_OUT/FTM0_FLT0/SPI0_PCS0, label: 'MB_J11[A25]/MB_U12[11]/MB_TP28/MB_FAULT/MB_FAULT_1/MB_PFC_overcurrent/J4[A25]/FAULT_1', identifier: FAULT_1} - {pin_num: '34', pin_signal: ADC1_SE3/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FTM2_CH0, label: 'MB_J11[B9]/MB_U12[2]/MB_TP38/MB_IPM_temp/J4[B9]/Temp_IPM', identifier: TEMP_IPM} - {pin_num: '35', pin_signal: ADC0_SE11/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FTM2_CH1, label: 'MB_J11[A8]/MB_U2B[7]/MB_TP14/MB_Ipfc1/J4[A8]/I_pfc1', identifier: I_PFC1} - {pin_num: '37', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, label: 'MB_J11[A17]/MB_U12[13]/MB_PWM_BB/J4[A17]/PWM3', identifier: PWM_BB} - {pin_num: '38', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2, label: 'MB_J11[A16]/MB_U12[19]/MB_PWM_BT/J4[A16]/PWM2', identifier: PWM_BT} - {pin_num: '39', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB_EXTRG1/UART0_RX/I2C0_SCL, label: 'MB_J11[A6]/MB_TP16/MB_TACHO/J4[A6]/TACHO', identifier: TACHO} - {pin_num: '40', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/UART0_TX/I2C0_SDA, label: 'MB_J11[B21]/MB_PFC_zc_2/J4[B21]/MB_TP_27', identifier: PFC_ZC_2} - {pin_num: '41', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART0_CTS_b/FTM0_CH0/UART1_RX/FTM3_CH0, label: 'MB_J2[4]/MB_J3[4]/MB_J11[A32]/MB_RxD_1/MB_RxD_EXT/U6[14]/J4[A32]/RxD1/UART1_TGT_MCU', identifier: RXD_1;UART_RX_TGTMCU} - {pin_num: '42', pin_signal: ADC0_SE2/PTD1/SPI0_SCK/UART0_RTS_b/FTM0_CH1/UART1_TX/FTM3_CH1, label: 'MB_J1[1]/MB_J2[3]/MB_J11[A31]/MB_TxD_1/MB_TxD_EXT/U6[13]/J4[A31]/TxD_1/UART1_TX_TGTMCU', identifier: TXD_1;UART_TX_TGTMCU} - {pin_num: '45', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FTM2_CH0/EWM_IN/SPI0_PCS0, label: 'MB_J11[A18]/MB_U12[20]/MB_PWM_CT/J4[A18]/PWM4', identifier: PWM_CT} - {pin_num: '46', pin_signal: ADC0_SE3/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FTM2_CH1/EWM_OUT_b/SPI0_SCK, label: 'MB_J11[A19]/MB_U12[14]/MB_PWM_CB/J4[A19]/PWM5', identifier: PWM_CB} - {pin_num: '44', pin_signal: PTD3/SPI0_SIN/UART0_TX/FTM0_CH3/FTM3_CH3/I2C0_SDA, label: 'MB_J11[B25]/MB_U9[2]/MB_TP_35/MB_MCU_BRAKE/J4[B25]/MCU_BRAKE', identifier: MCU_BRAKE} - {pin_num: '47', pin_signal: ADC1_SE6/PTD6/LLWU_P15/FTM4_CH0/UART0_RX/FTM0_CH0/FTM1_CH0/FTM0_FLT0/SPI0_SOUT, label: 'MB_J11[A22]/MB_U14[4]/MB_TP15/MB_PWM_PFC2/J4[A22]/PWM8', identifier: PWM_PFC2} - {pin_num: '48', pin_signal: PTD7/FTM4_CH1/UART0_TX/FTM0_CH1/FTM1_CH1/FTM0_FLT1/SPI0_SIN, label: 'MB_J11[A23]/MB_U14[2]/MB_TP12/MB_PWM_PFC1/J4[A23]/PWM9', identifier: PWM_PFC1} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ #include "fsl_common.h" #include "fsl_port.h" #include "fsl_gpio.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); BOARD_InitDEBUG_UARTPins(); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitMC_PWMPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '15', peripheral: FTM0, signal: 'CH, 0', pin_signal: PTE24/CAN0_TX/FTM0_CH0/I2C0_SCL/EWM_OUT_b, direction: OUTPUT} - {pin_num: '37', peripheral: FTM0, signal: 'CH, 3', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, direction: OUTPUT} - {pin_num: '38', peripheral: FTM0, signal: 'CH, 2', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2, direction: OUTPUT} - {pin_num: '45', peripheral: FTM0, signal: 'CH, 4', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FTM2_CH0/EWM_IN/SPI0_PCS0, direction: OUTPUT} - {pin_num: '46', peripheral: FTM0, signal: 'CH, 5', pin_signal: ADC0_SE3/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FTM2_CH1/EWM_OUT_b/SPI0_SCK, direction: OUTPUT} - {pin_num: '16', peripheral: FTM0, signal: 'CH, 1', pin_signal: PTE25/LLWU_P21/CAN0_RX/FTM0_CH1/I2C0_SDA/EWM_IN, direction: OUTPUT} - {pin_num: '33', peripheral: FTM0, signal: 'FLT, 0', pin_signal: ADC1_SE11/PTC0/SPI0_PCS4/PDB_EXTRG0/CMP0_OUT/FTM0_FLT0/SPI0_PCS0} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitMC_PWMPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitMC_PWMPins(void) { /* Port C Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortC); /* Port D Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortD); /* Port E Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortE); /* PORTC0 (pin 33) is configured as FTM0_FLT0 */ PORT_SetPinMux(MB_FAULT_1_PORT, MB_FAULT_1_PIN, kPORT_MuxAlt6); /* PORTC4 (pin 37) is configured as FTM0_CH3 */ PORT_SetPinMux(MB_PWM_BB_PORT, MB_PWM_BB_PIN, kPORT_MuxAlt4); /* PORTC5 (pin 38) is configured as FTM0_CH2 */ PORT_SetPinMux(MB_PWM_BT_PORT, MB_PWM_BT_PIN, kPORT_MuxAlt7); /* PORTD4 (pin 45) is configured as FTM0_CH4 */ PORT_SetPinMux(MB_PWM_CT_PORT, MB_PWM_CT_PIN, kPORT_MuxAlt4); /* PORTD5 (pin 46) is configured as FTM0_CH5 */ PORT_SetPinMux(MB_PWM_CB_PORT, MB_PWM_CB_PIN, kPORT_MuxAlt4); /* PORTE24 (pin 15) is configured as FTM0_CH0 */ PORT_SetPinMux(MB_PWM_AT_PORT, MB_PWM_AT_PIN, kPORT_MuxAlt3); /* PORTE25 (pin 16) is configured as FTM0_CH1 */ PORT_SetPinMux(MB_PWM_AB_PORT, MB_PWM_AB_PIN, kPORT_MuxAlt3); SIM->SOPT4 = ((SIM->SOPT4 & /* Mask bits to zero which are setting */ (~(SIM_SOPT4_FTM0FLT0_MASK))) /* FTM0 Fault 0 Select: FTM0_FLT0 pin. */ | SIM_SOPT4_FTM0FLT0(SOPT4_FTM0FLT0_FTM)); SIM->SOPT8 = ((SIM->SOPT8 & /* Mask bits to zero which are setting */ (~(SIM_SOPT8_FTM0OCH0SRC_MASK | SIM_SOPT8_FTM0OCH1SRC_MASK | SIM_SOPT8_FTM0OCH2SRC_MASK | SIM_SOPT8_FTM0OCH3SRC_MASK | SIM_SOPT8_FTM0OCH4SRC_MASK | SIM_SOPT8_FTM0OCH5SRC_MASK))) /* FTM0 channel 0 output PWM/OCMP mode source select: FTM0CH0 pin is the output of FTM0 channel 0 * PWM/OCMP. */ | SIM_SOPT8_FTM0OCH0SRC(SOPT8_FTM0OCH0SRC_NO_MODULATION) /* FTM0 channel 1 output PWM/OCMP mode source select: FTM0CH1 pin is the output of FTM0 channel 1 * PWM/OCMP. */ | SIM_SOPT8_FTM0OCH1SRC(SOPT8_FTM0OCH1SRC_NO_MODULATION) /* FTM0 channel 2 output PWM/OCMP mode source select: FTM0CH2 pin is the output of FTM0 channel 2 * PWM/OCMP. */ | SIM_SOPT8_FTM0OCH2SRC(SOPT8_FTM0OCH2SRC_NO_MODULATION) /* FTM0 channel 3 output PWM/OCMP mode source select: FTM0CH3 pin is the output of FTM0 channel 3 * PWM/OCMP. */ | SIM_SOPT8_FTM0OCH3SRC(SOPT8_FTM0OCH3SRC_NO_MODULATION) /* FTM0 channel 4 output PWM/OCMP mode source select: FTM0CH4 pin is the output of FTM0 channel 4 * PWM/OCMP. */ | SIM_SOPT8_FTM0OCH4SRC(SOPT8_FTM0OCH4SRC_NO_MODULATION) /* FTM0 channel 5 output PWM/OCMP mode source select: FTM0CH5 pin is the output of FTM0 channel 5 * PWM/OCMP. */ | SIM_SOPT8_FTM0OCH5SRC(SOPT8_FTM0OCH5SRC_NO_MODULATION)); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitPFCPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '40', peripheral: CMP0, signal: 'IN, 1', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/UART0_TX/I2C0_SDA} - {pin_num: '24', peripheral: GPIOA, signal: 'GPIO, 18', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/FTM3_CH2, direction: OUTPUT, gpio_init_state: 'false'} - {pin_num: '48', peripheral: FTM0, signal: 'CH, 1', pin_signal: PTD7/FTM4_CH1/UART0_TX/FTM0_CH1/FTM1_CH1/FTM0_FLT1/SPI0_SIN, direction: OUTPUT} - {pin_num: '47', peripheral: FTM0, signal: 'CH, 0', pin_signal: ADC1_SE6/PTD6/LLWU_P15/FTM4_CH0/UART0_RX/FTM0_CH0/FTM1_CH0/FTM0_FLT0/SPI0_SOUT, direction: OUTPUT} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitPFCPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitPFCPins(void) { /* Port A Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortA); /* Port C Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortC); /* Port D Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortD); gpio_pin_config_t RELAY_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTA18 (pin 24) */ GPIO_PinInit(MB_RELAY_GPIO, MB_RELAY_PIN, &RELAY_config); /* PORTA18 (pin 24) is configured as PTA18 */ PORT_SetPinMux(MB_RELAY_PORT, MB_RELAY_PIN, kPORT_MuxAsGpio); /* PORTC7 (pin 40) is configured as CMP0_IN1 */ PORT_SetPinMux(MB_PFC_ZC_2_PORT, MB_PFC_ZC_2_PIN, kPORT_PinDisabledOrAnalog); /* PORTD6 (pin 47) is configured as FTM0_CH0 */ PORT_SetPinMux(MB_PWM_PFC2_PORT, MB_PWM_PFC2_PIN, kPORT_MuxAlt4); /* PORTD7 (pin 48) is configured as FTM0_CH1 */ PORT_SetPinMux(MB_PWM_PFC1_PORT, MB_PWM_PFC1_PIN, kPORT_MuxAlt4); SIM->SOPT8 = ((SIM->SOPT8 & /* Mask bits to zero which are setting */ (~(SIM_SOPT8_FTM0OCH0SRC_MASK | SIM_SOPT8_FTM0OCH1SRC_MASK))) /* FTM0 channel 0 output PWM/OCMP mode source select: FTM0CH0 pin is the output of FTM0 channel * 0 PWM/OCMP. */ | SIM_SOPT8_FTM0OCH0SRC(SOPT8_FTM0OCH0SRC_NO_MODULATION) /* FTM0 channel 1 output PWM/OCMP mode source select: FTM0CH1 pin is the output of FTM0 channel * 1 PWM/OCMP. */ | SIM_SOPT8_FTM0OCH1SRC(SOPT8_FTM0OCH1SRC_NO_MODULATION)); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitANA_SENSPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '5', peripheral: ADC0, signal: 'SE, 6', pin_signal: ADC0_SE6/ADC1_SE1/ADC1_DP1/PTE18/LLWU_P20/SPI0_SOUT/UART1_CTS_b/I2C0_SDA/SPI0_SIN} - {pin_num: '8', peripheral: ADC0, signal: 'SE, 4', pin_signal: ADC0_SE4/ADC0_DM0/PTE21/FTM1_CH1/UART0_RX} - {pin_num: '34', peripheral: ADC1, signal: 'SE, 3', pin_signal: ADC1_SE3/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FTM2_CH0} - {pin_num: '28', peripheral: ADC0, signal: 'SE, 9', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX} - {pin_num: '7', peripheral: ADC0, signal: 'SE, 0', pin_signal: ADC0_SE0/ADC0_DP0/PTE20/FTM1_CH0/UART0_TX} - {pin_num: '14', peripheral: ADC1, signal: 'SE, 4', pin_signal: ADC1_SE4/CMP1_IN4/DAC0_OUT/PTE30/FTM0_CH3/FTM_CLKIN1} - {pin_num: '6', peripheral: ADC1, signal: 'SE, 7', pin_signal: ADC0_SE7/ADC1_SE7/ADC1_DM1/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL/SPI0_SOUT} - {pin_num: '39', peripheral: CMP0, signal: 'IN, 0', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB_EXTRG1/UART0_RX/I2C0_SCL} - {pin_num: '30', peripheral: ADC1, signal: 'SE, 2', pin_signal: ADC1_SE2/ADC1_DP2/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0} - {pin_num: '35', peripheral: ADC0, signal: 'SE, 11', pin_signal: ADC0_SE11/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FTM2_CH1} - {pin_num: '4', peripheral: ADC0, signal: 'SE, 5', pin_signal: ADC0_DM1/ADC0_SE5/ADC1_SE5/PTE17/LLWU_P19/SPI0_SCK/UART1_RX/FTM_CLKIN1/LPTMR0_ALT3} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitANA_SENSPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitANA_SENSPins(void) { /* Port B Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortB); /* Port C Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortC); /* Port E Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortE); /* PORTB1 (pin 28) is configured as ADC0_SE9 */ PORT_SetPinMux(MB_I_PH_B_PORT, MB_I_PH_B_PIN, kPORT_PinDisabledOrAnalog); /* PORTB3 (pin 30) is configured as ADC1_SE2 */ PORT_SetPinMux(MB_V_IN_PORT, MB_V_IN_PIN, kPORT_PinDisabledOrAnalog); /* PORTC1 (pin 34) is configured as ADC1_SE3 */ PORT_SetPinMux(MB_TEMP_IPM_PORT, MB_TEMP_IPM_PIN, kPORT_PinDisabledOrAnalog); /* PORTC2 (pin 35) is configured as ADC0_SE11 */ PORT_SetPinMux(MB_I_PFC1_PORT, MB_I_PFC1_PIN, kPORT_PinDisabledOrAnalog); /* PORTC6 (pin 39) is configured as CMP0_IN0 */ PORT_SetPinMux(MB_TACHO_PORT, MB_TACHO_PIN, kPORT_PinDisabledOrAnalog); /* PORTE17 (pin 4) is configured as ADC0_SE5 */ PORT_SetPinMux(MB_I_PFC2_PORT, MB_I_PFC2_PIN, kPORT_PinDisabledOrAnalog); /* PORTE18 (pin 5) is configured as ADC0_SE6 */ PORT_SetPinMux(MB_I_DCB_PORT, MB_I_DCB_PIN, kPORT_PinDisabledOrAnalog); /* PORTE19 (pin 6) is configured as ADC1_SE7 */ PORT_SetPinMux(MB_I_PH_C_PORT, MB_I_PH_C_PIN, kPORT_PinDisabledOrAnalog); /* PORTE20 (pin 7) is configured as ADC0_SE0 */ PORT_SetPinMux(MB_I_PH_C_2_PORT, MB_I_PH_C_2_PIN, kPORT_PinDisabledOrAnalog); /* PORTE21 (pin 8) is configured as ADC0_SE4 */ PORT_SetPinMux(MB_U_DCB_PORT, MB_U_DCB_PIN, kPORT_PinDisabledOrAnalog); /* PORTE30 (pin 14) is configured as ADC1_SE4 */ PORT_SetPinMux(MB_I_PH_A_PORT, MB_I_PH_A_PIN, kPORT_PinDisabledOrAnalog); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitBEMFPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '27', peripheral: ADC0, signal: 'SE, 8', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX} - {pin_num: '29', peripheral: ADC0, signal: 'SE, 10', pin_signal: ADC0_SE10/ADC1_SE10/ADC1_DM2/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3} - {pin_num: '3', peripheral: ADC0, signal: 'SE, 1', pin_signal: ADC0_SE1/ADC0_DP1/ADC1_SE0/PTE16/SPI0_PCS0/UART1_TX/FTM_CLKIN0/FTM0_FLT3} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitBEMFPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitBEMFPins(void) { /* Port B Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortB); /* Port E Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortE); /* PORTB0 (pin 27) is configured as ADC0_SE8 */ PORT_SetPinMux(MB_BEMF_A_PORT, MB_BEMF_A_PIN, kPORT_PinDisabledOrAnalog); /* PORTB2 (pin 29) is configured as ADC0_SE10 */ PORT_SetPinMux(MB_BEMF_B_PORT, MB_BEMF_B_PIN, kPORT_PinDisabledOrAnalog); /* PORTE16 (pin 3) is configured as ADC0_SE1 */ PORT_SetPinMux(MB_BEMF_C_PORT, MB_BEMF_C_PIN, kPORT_PinDisabledOrAnalog); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitENCPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '13', peripheral: GPIOE, signal: 'GPIO, 29', pin_signal: CMP1_IN5/CMP0_IN5/PTE29/FTM0_CH2/FTM_CLKIN0, direction: INPUT} - {pin_num: '18', peripheral: FTM2, signal: 'QD_PH, A', pin_signal: PTA1/UART0_RX/FTM2_CH0/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1/FTM4_CH0} - {pin_num: '19', peripheral: FTM2, signal: 'QD_PH, B', pin_signal: PTA2/UART0_TX/FTM2_CH1/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/FTM4_CH1} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitENCPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitENCPins(void) { /* Port A Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortA); /* Port E Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortE); gpio_pin_config_t ENC_INDEX_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTE29 (pin 13) */ GPIO_PinInit(MB_ENC_INDEX_GPIO, MB_ENC_INDEX_PIN, &ENC_INDEX_config); /* PORTA1 (pin 18) is configured as FTM2_QD_PHA */ PORT_SetPinMux(MB_ENC_PHASE_A_PORT, MB_ENC_PHASE_A_PIN, kPORT_MuxAlt5); /* PORTA2 (pin 19) is configured as FTM2_QD_PHB */ PORT_SetPinMux(MB_ENC_PHASE_B_PORT, MB_ENC_PHASE_B_PIN, kPORT_MuxAlt5); /* PORTE29 (pin 13) is configured as PTE29 */ PORT_SetPinMux(MB_ENC_INDEX_PORT, MB_ENC_INDEX_PIN, kPORT_MuxAsGpio); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitUSB_UARTPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '32', peripheral: UART0, signal: TX, pin_signal: PTB17/UART0_TX/FTM_CLKIN1/CAN0_RX/EWM_OUT_b, direction: OUTPUT} - {pin_num: '31', peripheral: UART0, signal: RX, pin_signal: PTB16/UART0_RX/FTM_CLKIN2/CAN0_TX/EWM_IN} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitUSB_UARTPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitUSB_UARTPins(void) { /* Port B Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortB); /* PORTB16 (pin 31) is configured as UART0_RX */ PORT_SetPinMux(MB_RXD_PORT, MB_RXD_PIN, kPORT_MuxAlt3); /* PORTB17 (pin 32) is configured as UART0_TX */ PORT_SetPinMux(MB_TXD_PORT, MB_TXD_PIN, kPORT_MuxAlt3); SIM->SOPT5 = ((SIM->SOPT5 & /* Mask bits to zero which are setting */ (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK))) /* UART 0 Transmit Data Source Select: UART0_TX pin. */ | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX) /* UART 0 Receive Data Source Select: UART0_RX pin. */ | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX)); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitEXT_UARTPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '42', peripheral: UART1, signal: TX, pin_signal: ADC0_SE2/PTD1/SPI0_SCK/UART0_RTS_b/FTM0_CH1/UART1_TX/FTM3_CH1, identifier: TXD_1, direction: OUTPUT} - {pin_num: '41', peripheral: UART1, signal: RX, pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART0_CTS_b/FTM0_CH0/UART1_RX/FTM3_CH0, identifier: RXD_1} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitEXT_UARTPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitEXT_UARTPins(void) { /* Port D Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortD); /* PORTD0 (pin 41) is configured as UART1_RX */ PORT_SetPinMux(MB_RXD_1_PORT, MB_RXD_1_PIN, kPORT_MuxAlt5); /* PORTD1 (pin 42) is configured as UART1_TX */ PORT_SetPinMux(MB_TXD_1_PORT, MB_TXD_1_PIN, kPORT_MuxAlt5); SIM->SOPT5 = ((SIM->SOPT5 & /* Mask bits to zero which are setting */ (~(SIM_SOPT5_UART1TXSRC_MASK | SIM_SOPT5_UART1RXSRC_MASK))) /* UART 1 Transmit Data Source Select: UART1_TX pin. */ | SIM_SOPT5_UART1TXSRC(SOPT5_UART1TXSRC_UART_TX) /* UART 1 Receive Data Source Select: UART1_RX pin. */ | SIM_SOPT5_UART1RXSRC(SOPT5_UART1RXSRC_UART_RX)); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitBRAKEPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '44', peripheral: GPIOD, signal: 'GPIO, 3', pin_signal: PTD3/SPI0_SIN/UART0_TX/FTM0_CH3/FTM3_CH3/I2C0_SDA, direction: OUTPUT, gpio_init_state: 'false'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitBRAKEPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitBRAKEPins(void) { /* Port D Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortD); gpio_pin_config_t MCU_BRAKE_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTD3 (pin 44) */ GPIO_PinInit(MB_MCU_BRAKE_GPIO, MB_MCU_BRAKE_PIN, &MCU_BRAKE_config); /* PORTD3 (pin 44) is configured as PTD3 */ PORT_SetPinMux(MB_MCU_BRAKE_PORT, MB_MCU_BRAKE_PIN, kPORT_MuxAsGpio); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* MB_InitMISCPins: - options: {prefix: MB_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '25', peripheral: GPIOA, signal: 'GPIO, 19', pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, direction: INPUT} - {peripheral: ADC0, signal: 'TRG, A', pin_signal: PDB0_CH0_TriggerA} - {peripheral: ADC0, signal: 'TRG, B', pin_signal: PDB0_CH0_TriggerB} - {peripheral: ADC1, signal: 'TRG, A', pin_signal: PDB0_CH1_TriggerA} - {peripheral: ADC1, signal: 'TRG, B', pin_signal: PDB0_CH1_TriggerB} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : MB_InitMISCPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void MB_InitMISCPins(void) { /* Port A Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortA); gpio_pin_config_t FAULT_2_config = { .pinDirection = kGPIO_DigitalInput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTA19 (pin 25) */ GPIO_PinInit(MB_FAULT_2_GPIO, MB_FAULT_2_PIN, &FAULT_2_config); /* PORTA19 (pin 25) is configured as PTA19 */ PORT_SetPinMux(MB_FAULT_2_PORT, MB_FAULT_2_PIN, kPORT_MuxAsGpio); SIM->SOPT7 = ((SIM->SOPT7 & /* Mask bits to zero which are setting */ (~(SIM_SOPT7_ADC0ALTTRGEN_MASK | SIM_SOPT7_ADC1ALTTRGEN_MASK))) /* Enable alternative conversion triggers for ADC0. * : PDB0 CH0 triggers ADC0. */ | SIM_SOPT7_ADC0ALTTRGEN(SOPT7_ADC0ALTTRGEN_PDB0) /* Enable alternative conversion triggers for ADC1. * : PDB0 CH1 triggers ADC1. */ | SIM_SOPT7_ADC1ALTTRGEN(SOPT7_ADC1ALTTRGEN_PDB0)); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitPins: - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'} - pin_list: [] * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void BOARD_InitPins(void) { } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitDEBUG_UARTPins: - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '41', peripheral: UART1, signal: RX, pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART0_CTS_b/FTM0_CH0/UART1_RX/FTM3_CH0, identifier: UART_RX_TGTMCU} - {pin_num: '42', peripheral: UART1, signal: TX, pin_signal: ADC0_SE2/PTD1/SPI0_SCK/UART0_RTS_b/FTM0_CH1/UART1_TX/FTM3_CH1, identifier: UART_TX_TGTMCU, direction: OUTPUT} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitDEBUG_UARTPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void BOARD_InitDEBUG_UARTPins(void) { /* Port D Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortD); /* PORTD0 (pin 41) is configured as UART1_RX */ PORT_SetPinMux(BOARD_UART_RX_TGTMCU_PORT, BOARD_UART_RX_TGTMCU_PIN, kPORT_MuxAlt5); /* PORTD1 (pin 42) is configured as UART1_TX */ PORT_SetPinMux(BOARD_UART_TX_TGTMCU_PORT, BOARD_UART_TX_TGTMCU_PIN, kPORT_MuxAlt5); SIM->SOPT5 = ((SIM->SOPT5 & /* Mask bits to zero which are setting */ (~(SIM_SOPT5_UART1TXSRC_MASK | SIM_SOPT5_UART1RXSRC_MASK))) /* UART 1 Transmit Data Source Select: UART1_TX pin. */ | SIM_SOPT5_UART1TXSRC(SOPT5_UART1TXSRC_UART_TX) /* UART 1 Receive Data Source Select: UART1_RX pin. */ | SIM_SOPT5_UART1RXSRC(SOPT5_UART1RXSRC_UART_RX)); } /* clang-format off */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitLEDsPins: - options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '36', peripheral: GPIOC, signal: 'GPIO, 3', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/FTM3_FLT0, direction: OUTPUT, gpio_init_state: 'false'} - {pin_num: '43', peripheral: GPIOD, signal: 'GPIO, 2', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART0_RX/FTM0_CH2/FTM3_CH2/I2C0_SCL, direction: OUTPUT, gpio_init_state: 'false'} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ /* FUNCTION ************************************************************************************************************ * * Function Name : BOARD_InitLEDsPins * Description : Configures pin routing and optionally pin electrical features. * * END ****************************************************************************************************************/ void BOARD_InitLEDsPins(void) { /* Port C Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortC); /* Port D Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortD); gpio_pin_config_t LED_RED_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTC3 (pin 36) */ GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config); gpio_pin_config_t LED_GREEN_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; /* Initialize GPIO functionality on pin PTD2 (pin 43) */ GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config); /* PORTC3 (pin 36) is configured as PTC3 */ PORT_SetPinMux(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, kPORT_MuxAsGpio); /* PORTD2 (pin 43) is configured as PTD2 */ PORT_SetPinMux(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, kPORT_MuxAsGpio); } /*********************************************************************************************************************** * EOF **********************************************************************************************************************/