/* * Copyright 2019 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. **********************************************************************************************************************/ /* * How to setup clock using clock driver functions: * * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock * and flash clock are in allowed range during clock mode switch. * * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. * * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and * internal reference clock(MCGIRCLK). Follow the steps to setup: * * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. * * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig * explicitly to setup MCGIRCLK. * * 3). Don't need to configure FLL explicitly, because if target mode is FLL * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, * if the target mode is not FLL mode, the FLL is disabled. * * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. * * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. */ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Clocks v7.0 processor: MKM35Z512xxx7 package_id: MKM35Z512VLQ7 mcu_data: ksdk2_0 processor_version: 0.0.1 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ #include "fsl_smc.h" #include "fsl_irtc.h" #include "clock_config.h" /******************************************************************************* * Definitions ******************************************************************************/ #define IRTC_OSC_CAP0P 0U /*!< RTC oscillator 0pF capacitor load */ #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */ #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */ /******************************************************************************* * Variables ******************************************************************************/ /* System clock frequency. */ extern uint32_t SystemCoreClock; /******************************************************************************* * Code ******************************************************************************/ /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_FllStableDelay * Description : This function is used to delay for FLL stable. * *END**************************************************************************/ static void CLOCK_CONFIG_FllStableDelay(void) { uint32_t i = 30000U; while (i--) { __NOP(); } } /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_EnableRtcOsc * Description : This function is used to configuring RTC oscillator * Param capLoad : RTC oscillator capacity load * *END**************************************************************************/ static void CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad) { /* Wait RTC POR finished before accessing RTC registers. */ while (!(SIM->MISC_CTL & SIM_MISC_CTL_RTC_OSC32K_INIT_MASK)) { } if ((RTC->GP_DATA_REG & 0x01U) != 0U) { /* Only if the Rtc oscillator is not already enabled */ /* Set the specified capacitor configuration for the RTC oscillator */ IRTC_SetOscCapLoad(RTC, capLoad); /* Enable the RTC 32KHz oscillator */ RTC->GP_DATA_REG &= ~0x01U; } } /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { BOARD_BootClockRUN(); } /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockRUN called_from_default_init: true outputs: - {id: Bus_clock.outFreq, value: 71.991296/3 MHz} - {id: Core_clock.outFreq, value: 71.991296 MHz} - {id: Flash_clock.outFreq, value: 71.991296/3 MHz} - {id: LPO_clock.outFreq, value: 1 kHz} - {id: MCGIRCLK.outFreq, value: 32.768 kHz} - {id: OSC32KSELCLK.outFreq, value: 32.768 kHz} - {id: OSCERCLK.outFreq, value: 8 MHz} - {id: PLLFLLCLK.outFreq, value: 71.991296 MHz} - {id: System_clock.outFreq, value: 71.991296 MHz} settings: - {id: MCGMode, value: FEE} - {id: MCG.CLKS.sel, value: MCG.PLLS} - {id: MCG.FCRDIV.scale, value: '1', locked: true} - {id: MCG.FLL_mul.scale, value: '2197', locked: true} - {id: MCG.IRCS.sel, value: MCG.SLOW_IRCLK} - {id: MCG.IREFS.sel, value: MCG.FRDIV} - {id: MCG.OSCSEL.sel, value: SIM.RTC32KCLK} - {id: MCG.PLL32KREFSEL.sel, value: MCG.FRDIV} - {id: MCG_C1_IRCLKEN_CFG, value: Enabled} - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower} - {id: MCG_C2_RANGE0_CFG, value: High} - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High} - {id: OSC_CR_ERCLKEN_CFG, value: Enabled} - {id: SIM.ADCTRGSEL.sel, value: SIM.ADC_asynchronous_clk} - {id: SIM.AFECLKSEL.sel, value: MCG.MCGFLLCLK} - {id: SIM.CLKDIVBUS.scale, value: '3', locked: true} - {id: SIM.CLKDIVSYS.scale, value: '1', locked: true} - {id: SIM.CLKOUTSEL.sel, value: PMC.LPOCLK} - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK} - {id: SIM.RTCCLKSEL.sel, value: MCG.MCGIRCLK} - {id: SIM.XBARCLKOUTSEL.sel, value: PMC.LPOCLK} - {id: XBARCLKOUTConfig, value: 'no'} sources: - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true} - {id: RTC.OSC32kHz.outFreq, value: 32.768 kHz, enabled: true} - {id: SIM.ADC_asynchronous_clk.outFreq, value: 1.255 MHz} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ const mcg_config_t mcgConfig_BOARD_BootClockRUN = { .mcgMode = kMCG_ModeFEE, /* FEE - FLL Engaged External */ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */ .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */ .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ .oscsel = kMCG_OscselRtc, /* Selects 32 kHz RTC Oscillator */ .pll0Config = { .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ .refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockRUN = { .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */ .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */ .clkdiv1 = 0x2000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /3, FLASHCLKMODE: /1 */ }; const osc_config_t oscConfig_BOARD_BootClockRUN = { .freq = 8000000U, /* Oscillator frequency: 8000000Hz */ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */ .oscerConfig = { .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */ } }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ void BOARD_BootClockRUN(void) { /* Use RTC_CLKIN input clock directly. */ CLOCK_SetXtal32Freq(32768U); /* Set the system clock dividers in SIM to safe value. */ CLOCK_SetSimSafeDivs(); /* Enable RTC oscillator. */ CLOCK_CONFIG_EnableRtcOsc((IRTC_OSC_CAP0P)); /* Initializes OSC0 according to board configuration. */ CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN); CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq); /* Set MCG to FEE mode. */ CLOCK_BootToFeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, mcgConfig_BOARD_BootClockRUN.frdiv, mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay); /* Configure the Internal Reference clock (MCGIRCLK). */ CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs, mcgConfig_BOARD_BootClockRUN.fcrdiv); /* Set the clock configuration in SIM module. */ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; } /******************************************************************************* ********************* Configuration BOARD_BootClockVLPR *********************** ******************************************************************************/ /* clang-format off */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockVLPR outputs: - {id: Bus_clock.outFreq, value: 1 MHz} - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'} - {id: Flash_clock.outFreq, value: 1 MHz} - {id: LPO_clock.outFreq, value: 1 kHz} - {id: MCGIRCLK.outFreq, value: 4 MHz} - {id: System_clock.outFreq, value: 4 MHz} settings: - {id: powerMode, value: VLPR} - {id: MCG.FCRDIV.scale, value: '1'} - {id: MCG.FRDIV.scale, value: '32'} - {id: MCG_C1_IRCLKEN_CFG, value: Enabled} - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower} - {id: MCG_C2_RANGE0_CFG, value: High} - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High} - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC18PF} - {id: SIM.CLKDIVBUS.scale, value: '4'} sources: - {id: OSC.OSC.outFreq, value: 8 MHz} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /* clang-format on */ /******************************************************************************* * Variables for BOARD_BootClockVLPR configuration ******************************************************************************/ const mcg_config_t mcgConfig_BOARD_BootClockVLPR = { .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ .drs = kMCG_DrsLow, /* Low frequency range */ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ .pll0Config = { .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockVLPR = { .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */ .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */ .clkdiv1 = 0x3000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /4, FLASHCLKMODE: /1 */ }; const osc_config_t oscConfig_BOARD_BootClockVLPR = { .freq = 0U, /* Oscillator frequency: 0Hz */ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */ .oscerConfig = { .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ } }; /******************************************************************************* * Code for BOARD_BootClockVLPR configuration ******************************************************************************/ void BOARD_BootClockVLPR(void) { /* Set the system clock dividers in SIM to safe value. */ CLOCK_SetSimSafeDivs(); /* Set MCG to BLPI mode. */ CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs, mcgConfig_BOARD_BootClockVLPR.irclkEnableMode); /* Set the clock configuration in SIM module. */ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR); /* Set VLPR power mode. */ SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) SMC_SetPowerModeVlpr(SMC, false); #else SMC_SetPowerModeVlpr(SMC); #endif while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) { } /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK; }