ELF( 9 L9 4 (@pG@pG@pGpGpGpGpMLMD)F Fi`ipILID9 FI FID9@!aap $M'4#F"!(F#F"!(F#F"!(F #F"!(F#F"!(F#F"!(Fp0~I ID09"pp# qKq$qk%q rr sJss%s tt uJuuu vv wJww%wF 0ppq%Eqq8%q rrsBss $s ttuBuu`!u0_IID`   ZHrYI `" bXIawOHHD 0LIMLID 1 FII FID99  pGDL ai@I FID9=I FID1(9I FID9 pF5L ai1I FID9`.I FID1 *I FID9 p pGF%$O FaiHHD8F1 0B8F`8F ya@@(5566I8FID9 # F@*Ґ J:bpG H` HAapGCPpG @@ظ@@@@@VJF zDXB@(!C!p!pq"BqqqrpGp FDI@yDJ9Z" )҂@?I@b=I`@=HBa aiԡx  Cxy  CC!y C!zCyCayIC(`p%I@yD9Z" )҂@!I@d@ HaI `i x [ Cx C y[[ CKy Cyy[ C  CB`ipGi yKyRR Cyy[ C  CapG@@@@pKBЙBШB pI" cJhBKNBh 0@C ICh 0@C!@ C` phC@@@?@ FF I & pG(! SIGABRT: Abnormal terminationpF F m-(x(d , x( piFp  @LPC5461x MT25QL128 SPIFI, !/!I$ > %%%% %C %C % % %%%C%C&I  ((      1 1 1 1 I8  I I8 4 ! I8 "I#7I$I%I&I 'I(I) * +,-./4  04 14 24 34 44 5.:;9? I6.:;9? 7.:;9G8.:;9? I 9.:;9? :.:;9G ;.:;9? I<.:;9? =.:;9G>.:;9? I@?.:;9? @@.:;9G@A.:;9? I@ B.:;9? @ C.:;9G@ D1E1F1XYWG1XYWH.1I.1@J.1@ K.1L.< 4 I? M.< 4 ? NIOPI:;9QI4 R S TUVW1X4I ,Y4I Z4I[4I,\4I]4I 4 ^4I ,4 _4I4 `4I,4 a4I4 b41 ,c41d41,e41f1g1hI iIjIkI 4 lI ,4 mI4 n1 o1p4I ? q4I? < r4I,s4It5Iu;v=w%x<%%.,armcc+|    (armcc+|  (armcc+|  (armcc+|  (armcc+|    0A|06&A~0\XA|\A}0<^B~ 0:A~0>A|  0jAxDvo{ 0" 0  0"B~ 0A|02A~ \D \&  \@^A|0A~ 00 A~ 0 A~0A~0$4A|0X A~C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621]  signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_t8 Pint16_t9 Pint32_t: Pint64_t; Puint8_t> Puint16_t? Puint32_t@ Puint64_tA Pint_least8_tG Pint_least16_tH Pint_least32_tI Pint_least64_tJ Puint_least8_tM Puint_least16_tN Puint_least32_tO Puint_least64_tP Pint_fast8_tU Pint_fast16_tV Pint_fast32_tW Pint_fast64_tX Puint_fast8_t[ Puint_fast16_t\ Puint_fast32_t] Puint_fast64_t^ Pintptr_te Puintptr_tf Pintmax_tj!Puintmax_tk!dQ .\devices\LPC54608\LPC54608.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL1280)  IRQnNotAvail_IRQnNonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnWDT_BOD_IRQnDMA0_IRQnGINT0_IRQnGINT1_IRQnPIN_INT0_IRQnPIN_INT1_IRQnPIN_INT2_IRQnPIN_INT3_IRQnUTICK0_IRQnMRT0_IRQn CTIMER0_IRQn CTIMER1_IRQn SCT0_IRQn CTIMER3_IRQn FLEXCOMM0_IRQnFLEXCOMM1_IRQnFLEXCOMM2_IRQnFLEXCOMM3_IRQnFLEXCOMM4_IRQnFLEXCOMM5_IRQnFLEXCOMM6_IRQnFLEXCOMM7_IRQnADC0_SEQA_IRQnADC0_SEQB_IRQnADC0_THCMP_IRQnDMIC0_IRQnHWVAD0_IRQnUSB0_NEEDCLK_IRQnUSB0_IRQnRTC_IRQnReserved46_IRQnReserved47_IRQnPIN_INT4_IRQn PIN_INT5_IRQn!PIN_INT6_IRQn"PIN_INT7_IRQn#CTIMER2_IRQn$CTIMER4_IRQn%RIT_IRQn&SPIFI0_IRQn'FLEXCOMM8_IRQn(FLEXCOMM9_IRQn)SDIO_IRQn*CAN0_IRQ0_IRQn+CAN0_IRQ1_IRQn,CAN1_IRQ0_IRQn-CAN1_IRQ1_IRQn.USB1_IRQn/USB1_NEEDCLK_IRQn0ETHERNET_IRQn1ETHERNET_PMT_IRQn2ETHERNET_MACLP_IRQn3EEPROM_IRQn4LCD_IRQn5SHA_IRQn6SMARTCARD0_IRQn7SMARTCARD1_IRQn8PIRQn_Type* tCTRL#INSEL# SEQ_CTRL# SEQ_GDAT0# :RESERVED_0I#  DATf# THR0_LOW#PTHR1_LOW#TTHR0_HIGH#XTHR1_HIGH#\CHAN_THRSEL#`INTEN#dFLAGS#hSTARTUP#lCALIB#ptYYt PADC_Type*$ASYNCPRESETCTRL#ASYNCPRESETCTRLSET#ASYNCPRESETCTRLCLR# :RESERVED_0v# ASYNCAPBCLKCTRL#ASYNCAPBCLKCTRLSET#ASYNCAPBCLKCTRLCLR# :RESERVED_1#ASYNCAPBCLKSELA# PASYNC_SYSCON_Type'* :RESERVED_02#TEST#:RESERVED_1[#CCCR#NBTP#TSCC# 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HCCONTROLCURRENTED#$HCBULKHEADED#(HCBULKCURRENTED#,HCDONEHEAD#0HCFMINTERVAL#4HCFMREMAINING#8HCFMNUMBER#<HCPERIODICSTART#@HCLSTHRESHOLD#DHCRHDESCRIPTORA#HHCRHDESCRIPTORB#LHCRHSTATUS#PHCRHPORTSTATUS#T:RESERVED_0J#XPORTMODE#\PUSBFSH_TypeIV*ǘ@DEVCMDSTAT#INFO#EPLISTSTART#DATABUFSTART# LPM#EPSKIP#EPINUSE#EPBUFCFG#INTSTAT# INTEN#$INTSETSTAT#(:RESERVED_0K#,EPTOGGLE#4:RESERVED_1L#8ULPIDEBUG#<PUSBHSD_Type9KY*TCAPLENGTH_CHIPID#HCSPARAMS#HCCPARAMS#FLADJ_FRINDEX# ATL_PTD_BASE_ADDR#ISO_PTD_BASE_ADDR#INT_PTD_BASE_ADDR#DATA_PAYLOAD_BASE_ADDR#USBCMD# USBSTS#$USBINTR#(PORTSC1#,ATL_PTD_DONE_MAP#0ATL_PTD_SKIP_MAP#4ISO_PTD_DONE_MAP#8ISO_PTD_SKIP_MAP#<INT_PTD_DONE_MAP#@INT_PTD_SKIP_MAP#DLAST_PTD_INUSE#HUTMIPLUS_ULPI_DEBUG#LPORTMODE#PPUSBHSH_Type[L[* CTRL#STAT#CFG#CAPCLR# CAPnN#PUTICK_Type8N^*MOD#TC#FEED#TV# ӝ:RESERVED_0N#WARNINT#WINDOW#PWWDT_TypeN_*4NY"OotpInit$O#NǞY%Y"7OotpEnableBankWriteMaskGO#NY%Y"iOotpDisableBankWriteMaskyO#NY%Y%Y%Y%Y"OotpEnableBankWriteLockO# NY%Y%Y%Y%Y"OotpEnableBankReadLockP#NY%Y%Y%Y"#PotpProgramReg?P#YRESERVED_0XP#NY"vPrngReadP#,NY"PotpGetDriverVersionP#0POTP_API_TypeO`*¢DusbdApiBase#Y RESERVED_0P#otpApiBaseJQ#8aesApiBase#<secureApiBase#@PtBQ"FQPROM_API_TypeP`C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] L unsigned intPsize_t, devices\LPC54608\drivers\fsl_spifi.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128t_BoolPspifi_interrupt_enable_t<>Pspifi_spi_mode_tEPspifi_dual_mode_tLPspifi_data_direction_tSPspifi_command_format_tA\Pspifi_command_type_thPspifi_command_tV|)_spifi_config timeoutI#csHighTime:#disablePrefetch#disableCachePrefech#isFeedbackClock#spiMode#isReadFullClockCycle#dualMode#Pspifi_config_t)_spifi_transferdata#dataSizeU#":Pspifi_transfer_tW<SPIFI_SetCommandAddress$base$Yaddr"X<<SPIFI_SetIntermediateData$base$Yval<SPIFI_SetCacheLimit$base$Yval<SPIFI_EnableInterrupt$base$Ymask<SPIFI_DisableInterrupt$base$Ymask<SPIFI_EnableDMA$base$enable;SPIFI_GetDataRegisterAddressY$basea__resultY<SPIFI_WriteData$base$Ydata; SPIFI_ReadDataY$basea__resultY9 SPIFI_ResetCommand$base8 SPIFI_GetStatusFlagY$basea__resultY _status_tkStatus_SPIFI_IdlepkStatus_SPIFI_BusyqkStatus_SPIFI_Errorr _spifi_interrupt_enablekSPIFI_CommandFinishInterruptEnable@ _spifi_spi_modekSPIFI_SPISckLow kSPIFI_SPISckHigh  _spifi_dual_modekSPIFI_QuadMode kSPIFI_DualMode  _spifi_data_directionkSPIFI_DataInput kSPIFI_DataOutput  _spifi_command_formatkSPIFI_CommandAllSerial kSPIFI_CommandDataQuad kSPIFI_CommandOpcodeSerial kSPIFI_CommandAllQuad _spifi_command_typekSPIFI_CommandOpcodeOnly kSPIFI_CommandOpcodeAddrOneByte kSPIFI_CommandOpcodeAddrTwoBytes kSPIFI_CommandOpcodeAddrThreeBytes kSPIFI_CommandOpcodeAddrFourBytes kSPIFI_CommandNoOpcodeAddrThreeBytes kSPIFI_CommandNoOpcodeAddrFourBytes _spifi_status_flagskSPIFI_MemoryCommandWriteFinished kSPIFI_CommandWriteFinished kSPIFI_InterruptRequest )_spifi_commanddataLenI#isPollMode#direction#intermediateBytes:#format3#typeQ#opcode:#0  devices\LPC54608\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128`_BoolPclock_ip_name_tPclock_name_t Pasync_clock_src_tr Pclock_attach_id_t Pclock_div_name_tPclock_flashtim_tEPpll_config_t Ppll_setup_thPpll_error_tPclock_usb_src_tPusb_pll_pselaPusb_pll_setup_t<CLOCK_SetFLASHAccessCycles$>clks\tmpY;#CLOCK_GetAsyncApbClkSrca__result<CLOCK_SetBypassPLL$bypass;CLOCK_IsSystemPLLLockeda__result;CLOCK_IsUsbPLLLockeda__result;CLOCK_IsAudioPLLLockeda__result<CLOCK_Enable_SysOsc$enable< CLOCK_DisableUsbDevicefs0Clock$clk9CLOCK_EnableClock$clk\indexY9CLOCK_DisableClock$clk\indexY_clock_ip_namekCLOCK_IpInvalid kCLOCK_Rom kCLOCK_Sram1 kCLOCK_Sram2 kCLOCK_Sram3 kCLOCK_Flash kCLOCK_Fmc kCLOCK_Eeprom kCLOCK_Spifi kCLOCK_InputMux kCLOCK_Iocon kCLOCK_Gpio0 kCLOCK_Gpio1 kCLOCK_Gpio2 kCLOCK_Gpio3 kCLOCK_Pint kCLOCK_Gint kCLOCK_Dma kCLOCK_Crc kCLOCK_Wwdt kCLOCK_Rtc kCLOCK_Adc0 kCLOCK_MrtkCLOCK_RitkCLOCK_Sct0kCLOCK_Mcan0kCLOCK_Mcan1kCLOCK_Utick kCLOCK_FlexComm0 kCLOCK_FlexComm1 kCLOCK_FlexComm2 kCLOCK_FlexComm3kCLOCK_FlexComm4kCLOCK_FlexComm5kCLOCK_FlexComm6kCLOCK_FlexComm7kCLOCK_MinUart0 kCLOCK_MinUart1 kCLOCK_MinUart2 kCLOCK_MinUart3kCLOCK_MinUart4kCLOCK_MinUart5kCLOCK_MinUart6kCLOCK_MinUart7kCLOCK_LSpi0 kCLOCK_LSpi1 kCLOCK_LSpi2 kCLOCK_LSpi3kCLOCK_LSpi4kCLOCK_LSpi5kCLOCK_LSpi6kCLOCK_LSpi7kCLOCK_BI2c0 kCLOCK_BI2c1 kCLOCK_BI2c2 kCLOCK_BI2c3kCLOCK_BI2c4kCLOCK_BI2c5kCLOCK_BI2c6kCLOCK_BI2c7kCLOCK_FlexI2s0 kCLOCK_FlexI2s1 kCLOCK_FlexI2s2 kCLOCK_FlexI2s3kCLOCK_FlexI2s4kCLOCK_FlexI2s5kCLOCK_FlexI2s6kCLOCK_FlexI2s7kCLOCK_DMickCLOCK_Ct32b2kCLOCK_Usbd0kCLOCK_Ct32b0kCLOCK_Ct32b1kCLOCK_BodyBias0kCLOCK_EzhArchB0kCLOCK_LcdkCLOCK_SdiokCLOCK_Usbh1kCLOCK_Usbd1kCLOCK_UsbRam1kCLOCK_EmckCLOCK_EthkCLOCK_Gpio4 kCLOCK_Gpio5 kCLOCK_Aes kCLOCK_Otp kCLOCK_Rng kCLOCK_FlexComm8kCLOCK_FlexComm9kCLOCK_MinUart8kCLOCK_MinUart9kCLOCK_LSpi8kCLOCK_LSpi9kCLOCK_BI2c8kCLOCK_BI2c9kCLOCK_FlexI2s8kCLOCK_FlexI2s9kCLOCK_Usbhmr0kCLOCK_Usbhsl0kCLOCK_Sha0kCLOCK_SmartCard0kCLOCK_SmartCard1kCLOCK_Ct32b3 kCLOCK_Ct32b4_clock_namekCLOCK_CoreSysClk kCLOCK_BusClk kCLOCK_ClockOut kCLOCK_FroHf kCLOCK_SpiFi kCLOCK_Adc kCLOCK_Usb0 kCLOCK_Usb1 kCLOCK_UsbPll kCLOCK_Mclk kCLOCK_Sct kCLOCK_SDio kCLOCK_EMC kCLOCK_LCD kCLOCK_MCAN0 kCLOCK_MCAN1 kCLOCK_Fro12M kCLOCK_ExtClk kCLOCK_PllOut kCLOCK_UsbClk kClock_WdtOsc kCLOCK_Frg kCLOCK_Dmic kCLOCK_AsyncApbClk kCLOCK_FlexI2S kCLOCK_Flexcomm0 kCLOCK_Flexcomm1 kCLOCK_Flexcomm2 kCLOCK_Flexcomm3 kCLOCK_Flexcomm4 kCLOCK_Flexcomm5 kCLOCK_Flexcomm6 kCLOCK_Flexcomm7 kCLOCK_Flexcomm8 !kCLOCK_Flexcomm9 "_async_clock_srckCLOCK_AsyncMainClk kCLOCK_AsyncFro12Mhz kCLOCK_AsyncAudioPllClk kCLOCK_AsyncI2cClkFc6 4_clock_attach_idkFRO12M_to_MAIN_CLKkEXT_CLK_to_MAIN_CLKkWDT_OSC_to_MAIN_CLKkFRO_HF_to_MAIN_CLKkSYS_PLL_to_MAIN_CLKkOSC32K_to_MAIN_CLKkMAIN_CLK_to_CLKOUTkEXT_CLK_to_CLKOUTkWDT_OSC_to_CLKOUTkFRO_HF_to_CLKOUTkSYS_PLL_to_CLKOUTkUSB_PLL_to_CLKOUTkAUDIO_PLL_to_CLKOUTkOSC32K_OSC_to_CLKOUTkFRO12M_to_SYS_PLLkEXT_CLK_to_SYS_PLLkWDT_OSC_to_SYS_PLLkOSC32K_to_SYS_PLLkNONE_to_SYS_PLLkFRO12M_to_AUDIO_PLLkEXT_CLK_to_AUDIO_PLLkNONE_to_AUDIO_PLLkMAIN_CLK_to_SPIFI_CLKkSYS_PLL_to_SPIFI_CLKkUSB_PLL_to_SPIFI_CLKkFRO_HF_to_SPIFI_CLKkAUDIO_PLL_to_SPIFI_CLKkNONE_to_SPIFI_CLKkFRO_HF_to_ADC_CLK kSYS_PLL_to_ADC_CLK kUSB_PLL_to_ADC_CLK kAUDIO_PLL_to_ADC_CLK kNONE_to_ADC_CLK kFRO_HF_to_USB0_CLK kSYS_PLL_to_USB0_CLK kUSB_PLL_to_USB0_CLK kNONE_to_USB0_CLK kFRO_HF_to_USB1_CLK kSYS_PLL_to_USB1_CLK kUSB_PLL_to_USB1_CLK kNONE_to_USB1_CLK kFRO12M_to_FLEXCOMM0 kFRO_HF_to_FLEXCOMM0 kAUDIO_PLL_to_FLEXCOMM0 kMCLK_to_FLEXCOMM0 kFRG_to_FLEXCOMM0 kNONE_to_FLEXCOMM0 kFRO12M_to_FLEXCOMM1 kFRO_HF_to_FLEXCOMM1 kAUDIO_PLL_to_FLEXCOMM1 kMCLK_to_FLEXCOMM1 kFRG_to_FLEXCOMM1 kNONE_to_FLEXCOMM1 kFRO12M_to_FLEXCOMM2kFRO_HF_to_FLEXCOMM2kAUDIO_PLL_to_FLEXCOMM2kMCLK_to_FLEXCOMM2kFRG_to_FLEXCOMM2kNONE_to_FLEXCOMM2kFRO12M_to_FLEXCOMM3kFRO_HF_to_FLEXCOMM3kAUDIO_PLL_to_FLEXCOMM3kMCLK_to_FLEXCOMM3kFRG_to_FLEXCOMM3kNONE_to_FLEXCOMM3kFRO12M_to_FLEXCOMM4kFRO_HF_to_FLEXCOMM4kAUDIO_PLL_to_FLEXCOMM4kMCLK_to_FLEXCOMM4kFRG_to_FLEXCOMM4kNONE_to_FLEXCOMM4kFRO12M_to_FLEXCOMM5kFRO_HF_to_FLEXCOMM5kAUDIO_PLL_to_FLEXCOMM5kMCLK_to_FLEXCOMM5kFRG_to_FLEXCOMM5kNONE_to_FLEXCOMM5kFRO12M_to_FLEXCOMM6kFRO_HF_to_FLEXCOMM6kAUDIO_PLL_to_FLEXCOMM6kMCLK_to_FLEXCOMM6kFRG_to_FLEXCOMM6kNONE_to_FLEXCOMM6kFRO12M_to_FLEXCOMM7kFRO_HF_to_FLEXCOMM7kAUDIO_PLL_to_FLEXCOMM7kMCLK_to_FLEXCOMM7kFRG_to_FLEXCOMM7kNONE_to_FLEXCOMM7kFRO12M_to_FLEXCOMM8kFRO_HF_to_FLEXCOMM8kAUDIO_PLL_to_FLEXCOMM8kMCLK_to_FLEXCOMM8kFRG_to_FLEXCOMM8kNONE_to_FLEXCOMM8kFRO12M_to_FLEXCOMM9kFRO_HF_to_FLEXCOMM9kAUDIO_PLL_to_FLEXCOMM9kMCLK_to_FLEXCOMM9kFRG_to_FLEXCOMM9kNONE_to_FLEXCOMM9kFRO_HF_to_MCLKkAUDIO_PLL_to_MCLKkNONE_to_MCLKkMAIN_CLK_to_FRGkSYS_PLL_to_FRGkFRO12M_to_FRGkFRO_HF_to_FRGkNONE_to_FRGkFRO12M_to_DMICkFRO_HF_DIV_to_DMICkAUDIO_PLL_to_DMICkMCLK_to_DMICkNONE_to_DMICkMCLK_to_SCT_CLKkSYS_PLL_to_SCT_CLKkFRO_HF_to_SCT_CLKkAUDIO_PLL_to_SCT_CLKkNONE_to_SCT_CLKkMCLK_to_SDIO_CLKkSYS_PLL_to_SDIO_CLKkUSB_PLL_to_SDIO_CLKkFRO_HF_to_SDIO_CLKkAUDIO_PLL_to_SDIO_CLKkNONE_to_SDIO_CLKkMCLK_to_LCD_CLKkLCDCLKIN_to_LCD_CLKkFRO_HF_to_LCD_CLKkNONE_to_LCD_CLKkMAIN_CLK_to_ASYNC_APBkFRO12M_to_ASYNC_APBkAUDIO_PLL_to_ASYNC_APBkI2C_CLK_FC6_to_ASYNC_APBkNONE_to_NONE8_clock_div_namekCLOCK_DivSystickClk kCLOCK_DivArmTrClkDiv kCLOCK_DivCan0Clk kCLOCK_DivCan1Clk kCLOCK_DivSmartCard0Clk kCLOCK_DivSmartCard1Clk kCLOCK_DivAhbClk kCLOCK_DivClkOut !kCLOCK_DivFrohfClk "kCLOCK_DivSpifiClk $kCLOCK_DivAdcAsyncClk %kCLOCK_DivUsb0Clk &kCLOCK_DivUsb1Clk 'kCLOCK_DivFrg (kCLOCK_DivDmicClk *kCLOCK_DivMClk +kCLOCK_DivLcdClk ,kCLOCK_DivSctClk -kCLOCK_DivEmcClk .kCLOCK_DivSdioClk /:_clock_flashtimkCLOCK_Flash1Cycle kCLOCK_Flash2Cycle kCLOCK_Flash3Cycle kCLOCK_Flash4Cycle kCLOCK_Flash5Cycle kCLOCK_Flash6Cycle kCLOCK_Flash7Cycle kCLOCK_Flash8Cycle kCLOCK_Flash9Cycle ):_pll_config desiredRateY#inputRateY#flagsY#);_pll_setuppllctrlY#pllndecY#pllpdecY#pllmdecY# pllRateY#audpllfracY#flagsY#=_pll_errorkStatus_PLL_Success kStatus_PLL_OutputTooLow kStatus_PLL_OutputTooHigh kStatus_PLL_InputTooLow kStatus_PLL_InputTooHigh kStatus_PLL_OutsideIntLimit kStatus_PLL_CCOTooLow kStatus_PLL_CCOTooHigh >_clock_usb_srckCLOCK_UsbSrcFro kCLOCK_UsbSrcSystemPll kCLOCK_UsbSrcMainClock kCLOCK_UsbSrcUsbPll kCLOCK_UsbSrcNone ?_usb_pll_pselpSel_Divide_1 pSel_Divide_2 pSel_Divide_4 pSel_Divide_8 )@_usb_pll_setup msel:#psel:#nsel:#direct#bypass#fbsel#inputRateY# ..\FlashOS.HComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128( unsigned longunsigned shortcharunsigned char)FlashDevice!Vers#DevName#DevType#DevAdr#szDev#szPage#Res#valEmpty#toProg#toErase#sectors#)FlashSectorsszSector#AddrSector# .\devices\LPC54608\drivers\fsl_spifi.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128_BoolPspifi_interrupt_enable_t@>Pspifi_spi_mode_tEPspifi_dual_mode_tLPspifi_data_direction_tSPspifi_command_format_tE\Pspifi_command_type_thPspifi_command_tZ|)_spifi_config timeoutI#csHighTime:#disablePrefetch#disableCachePrefech#isFeedbackClock#spiMode#isReadFullClockCycle#dualMode#Pspifi_config_t)_spifi_transferdata#dataSizeU#":Pspifi_transfer_tY"X<<SPIFI_SetIntermediateData$base$Yval<SPIFI_SetCacheLimit$base$Yval<SPIFI_EnableInterrupt$base$Ymask<SPIFI_DisableInterrupt$base$Ymask;SPIFI_GetStatusFlagY$basea__resultY<SPIFI_EnableDMA$base$enable;SPIFI_GetDataRegisterAddressY$basea__resultY9SPIFI_SetCommandAddress$base$Yaddr9 SPIFI_ResetCommand$base9 SPIFI_WriteData$base$Ydata8 SPIFI_ReadDataY$basea__resultY _status_tkStatus_SPIFI_IdlepkStatus_SPIFI_BusyqkStatus_SPIFI_Errorr _spifi_interrupt_enablekSPIFI_CommandFinishInterruptEnable@ _spifi_spi_modekSPIFI_SPISckLow kSPIFI_SPISckHigh  _spifi_dual_modekSPIFI_QuadMode kSPIFI_DualMode  _spifi_data_directionkSPIFI_DataInput kSPIFI_DataOutput  _spifi_command_formatkSPIFI_CommandAllSerial kSPIFI_CommandDataQuad kSPIFI_CommandOpcodeSerial kSPIFI_CommandAllQuad _spifi_command_typekSPIFI_CommandOpcodeOnly kSPIFI_CommandOpcodeAddrOneByte kSPIFI_CommandOpcodeAddrTwoBytes kSPIFI_CommandOpcodeAddrThreeBytes kSPIFI_CommandOpcodeAddrFourBytes kSPIFI_CommandNoOpcodeAddrThreeBytes kSPIFI_CommandNoOpcodeAddrFourBytes _spifi_status_flagskSPIFI_MemoryCommandWriteFinished kSPIFI_CommandWriteFinished kSPIFI_InterruptRequest )_spifi_commanddataLenI#isPollMode#direction#intermediateBytes:#format5#typeS#opcode:# devices\LPC54608\drivers\fsl_power.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128pd_bitskPDRUNCFG_LP_REG kPDRUNCFG_PD_FRO_EN kPDRUNCFG_PD_TS kPDRUNCFG_PD_BOD_RESET kPDRUNCFG_PD_BOD_INTR kPDRUNCFG_PD_VD2_ANA kPDRUNCFG_PD_ADC0 kPDRUNCFG_PD_RAM0 kPDRUNCFG_PD_RAM1 kPDRUNCFG_PD_RAM2 kPDRUNCFG_PD_RAM3 kPDRUNCFG_PD_ROM kPDRUNCFG_PD_VDDA kPDRUNCFG_PD_WDT_OSC kPDRUNCFG_PD_USB0_PHY kPDRUNCFG_PD_SYS_PLL0 kPDRUNCFG_PD_VREFP kPDRUNCFG_PD_FLASH_BG kPDRUNCFG_PD_VD3 kPDRUNCFG_PD_VD4 kPDRUNCFG_PD_VD5 kPDRUNCFG_PD_VD6 kPDRUNCFG_REQ_DELAY kPDRUNCFG_FORCE_RBB kPDRUNCFG_PD_USB1_PHYkPDRUNCFG_PD_USB_PLLkPDRUNCFG_PD_AUDIO_PLLkPDRUNCFG_PD_SYS_OSCkPDRUNCFG_PD_EEPROMkPDRUNCFG_PD_rngkPDRUNCFG_ForceUnsignedPpd_bit_tO_power_mode_configkPmu_Sleep kPmu_Deep_Sleep kPmu_Deep_PowerDown Ppower_mode_cfg_tW<lPOWER_EnablePD$en<POWER_EnableDeepSleep<POWER_DisableDeepSleep<POWER_PowerDownFlash< POWER_PowerUpFlash9 xPOWER_DisablePD$enL devices\LPC54608\drivers\fsl_common.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128 _status_groupskStatusGroup_Generic kStatusGroup_FLASH kStatusGroup_LPSPI kStatusGroup_FLEXIO_SPI kStatusGroup_DSPI kStatusGroup_FLEXIO_UART kStatusGroup_FLEXIO_I2C kStatusGroup_LPI2C kStatusGroup_UART kStatusGroup_I2C kStatusGroup_LPSCI kStatusGroup_LPUART kStatusGroup_SPI kStatusGroup_XRDC kStatusGroup_SEMA42 kStatusGroup_SDHC kStatusGroup_SDMMC kStatusGroup_SAI kStatusGroup_MCG kStatusGroup_SCG kStatusGroup_SDSPI kStatusGroup_FLEXIO_I2S kStatusGroup_FLEXIO_MCULCD kStatusGroup_FLASHIAP kStatusGroup_FLEXCOMM_I2C kStatusGroup_I2S kStatusGroup_IUART kStatusGroup_SDRAMC #kStatusGroup_POWER 'kStatusGroup_ENET (kStatusGroup_PHY )kStatusGroup_TRGMUX *kStatusGroup_SMARTCARD +kStatusGroup_LMEM ,kStatusGroup_QSPI -kStatusGroup_DMA 2kStatusGroup_EDMA 3kStatusGroup_DMAMGR 4kStatusGroup_FLEXCAN 5kStatusGroup_LTC 6kStatusGroup_FLEXIO_CAMERA 7kStatusGroup_LPC_SPI 8kStatusGroup_LPC_USART 9kStatusGroup_DMIC :kStatusGroup_SDIF ;kStatusGroup_SPIFI <kStatusGroup_OTP =kStatusGroup_MCAN >kStatusGroup_CAAM ?kStatusGroup_ECSPI @kStatusGroup_USDHC AkStatusGroup_ESAI EkStatusGroup_FLEXSPI FkStatusGroup_NOTIFIER bkStatusGroup_DebugConsole ckStatusGroup_ApplicationRangeStart d _generic_statuskStatus_Success kStatus_Fail kStatus_ReadOnly kStatus_OutOfRange kStatus_InvalidArgument kStatus_Timeout kStatus_NoTransferInProgress Pstatus_t< EnableIRQ$interrupt< DisableIRQ$interrupt;DisableGlobalIRQYa__resultY\regPrimaskY<EnableGlobalIRQ$Yprimask< devices\LPC54608\drivers\fsl_spifi.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128h4"X<^"`W`W""V8@ SPIFI_GetInstanceY$basea__resultY\instanceY FlashDev.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128DL .\devices\LPC54608\drivers\fsl_iocon.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128P|)_iocon_group!portY#!pinY#!modefuncY#Piocon_group_t="E.<IOCON_SetPinMuxing$base$ppinArray$YarrayLength\iY"l9IOCON_PinMuxSet$base$:port$:pin$Ymodefunc4  .\devices\LPC54608\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128L _BoolPclock_ip_name_tPclock_name_t Pasync_clock_src_ts Pclock_attach_id_t Pclock_div_name_tPclock_flashtim_tFPpll_config_t!Ppll_setup_tiPpll_error_tPclock_usb_src_tPusb_pll_pselbPusb_pll_setup_t<CLOCK_DisableClock$clk\indexY<CLOCK_SetFLASHAccessCycles$@clks\tmpY;#CLOCK_GetAsyncApbClkSrca__result<CLOCK_SetBypassPLL$bypass;CLOCK_IsSystemPLLLockeda__result;CLOCK_IsUsbPLLLockeda__result;CLOCK_IsAudioPLLLockeda__result<CLOCK_Enable_SysOsc$enable< CLOCK_DisableUsbDevicefs0Clock$clk9CLOCK_EnableClock$clk\indexY_clock_ip_namekCLOCK_IpInvalid kCLOCK_Rom kCLOCK_Sram1 kCLOCK_Sram2 kCLOCK_Sram3 kCLOCK_Flash kCLOCK_Fmc kCLOCK_Eeprom kCLOCK_Spifi kCLOCK_InputMux kCLOCK_Iocon kCLOCK_Gpio0 kCLOCK_Gpio1 kCLOCK_Gpio2 kCLOCK_Gpio3 kCLOCK_Pint kCLOCK_Gint kCLOCK_Dma kCLOCK_Crc kCLOCK_Wwdt kCLOCK_Rtc kCLOCK_Adc0 kCLOCK_MrtkCLOCK_RitkCLOCK_Sct0kCLOCK_Mcan0kCLOCK_Mcan1kCLOCK_Utick kCLOCK_FlexComm0 kCLOCK_FlexComm1 kCLOCK_FlexComm2 kCLOCK_FlexComm3kCLOCK_FlexComm4kCLOCK_FlexComm5kCLOCK_FlexComm6kCLOCK_FlexComm7kCLOCK_MinUart0 kCLOCK_MinUart1 kCLOCK_MinUart2 kCLOCK_MinUart3kCLOCK_MinUart4kCLOCK_MinUart5kCLOCK_MinUart6kCLOCK_MinUart7kCLOCK_LSpi0 kCLOCK_LSpi1 kCLOCK_LSpi2 kCLOCK_LSpi3kCLOCK_LSpi4kCLOCK_LSpi5kCLOCK_LSpi6kCLOCK_LSpi7kCLOCK_BI2c0 kCLOCK_BI2c1 kCLOCK_BI2c2 kCLOCK_BI2c3kCLOCK_BI2c4kCLOCK_BI2c5kCLOCK_BI2c6kCLOCK_BI2c7kCLOCK_FlexI2s0 kCLOCK_FlexI2s1 kCLOCK_FlexI2s2 kCLOCK_FlexI2s3kCLOCK_FlexI2s4kCLOCK_FlexI2s5kCLOCK_FlexI2s6kCLOCK_FlexI2s7kCLOCK_DMickCLOCK_Ct32b2kCLOCK_Usbd0kCLOCK_Ct32b0kCLOCK_Ct32b1kCLOCK_BodyBias0kCLOCK_EzhArchB0kCLOCK_LcdkCLOCK_SdiokCLOCK_Usbh1kCLOCK_Usbd1kCLOCK_UsbRam1kCLOCK_EmckCLOCK_EthkCLOCK_Gpio4 kCLOCK_Gpio5 kCLOCK_Aes kCLOCK_Otp kCLOCK_Rng kCLOCK_FlexComm8kCLOCK_FlexComm9kCLOCK_MinUart8kCLOCK_MinUart9kCLOCK_LSpi8kCLOCK_LSpi9kCLOCK_BI2c8kCLOCK_BI2c9kCLOCK_FlexI2s8kCLOCK_FlexI2s9kCLOCK_Usbhmr0kCLOCK_Usbhsl0kCLOCK_Sha0kCLOCK_SmartCard0kCLOCK_SmartCard1kCLOCK_Ct32b3 kCLOCK_Ct32b4_clock_namekCLOCK_CoreSysClk kCLOCK_BusClk kCLOCK_ClockOut kCLOCK_FroHf kCLOCK_SpiFi kCLOCK_Adc kCLOCK_Usb0 kCLOCK_Usb1 kCLOCK_UsbPll kCLOCK_Mclk kCLOCK_Sct kCLOCK_SDio kCLOCK_EMC kCLOCK_LCD kCLOCK_MCAN0 kCLOCK_MCAN1 kCLOCK_Fro12M kCLOCK_ExtClk kCLOCK_PllOut kCLOCK_UsbClk kClock_WdtOsc kCLOCK_Frg kCLOCK_Dmic kCLOCK_AsyncApbClk kCLOCK_FlexI2S kCLOCK_Flexcomm0 kCLOCK_Flexcomm1 kCLOCK_Flexcomm2 kCLOCK_Flexcomm3 kCLOCK_Flexcomm4 kCLOCK_Flexcomm5 kCLOCK_Flexcomm6 kCLOCK_Flexcomm7 kCLOCK_Flexcomm8 !kCLOCK_Flexcomm9 "_async_clock_srckCLOCK_AsyncMainClk kCLOCK_AsyncFro12Mhz kCLOCK_AsyncAudioPllClk kCLOCK_AsyncI2cClkFc6 5_clock_attach_idkFRO12M_to_MAIN_CLKkEXT_CLK_to_MAIN_CLKkWDT_OSC_to_MAIN_CLKkFRO_HF_to_MAIN_CLKkSYS_PLL_to_MAIN_CLKkOSC32K_to_MAIN_CLKkMAIN_CLK_to_CLKOUTkEXT_CLK_to_CLKOUTkWDT_OSC_to_CLKOUTkFRO_HF_to_CLKOUTkSYS_PLL_to_CLKOUTkUSB_PLL_to_CLKOUTkAUDIO_PLL_to_CLKOUTkOSC32K_OSC_to_CLKOUTkFRO12M_to_SYS_PLLkEXT_CLK_to_SYS_PLLkWDT_OSC_to_SYS_PLLkOSC32K_to_SYS_PLLkNONE_to_SYS_PLLkFRO12M_to_AUDIO_PLLkEXT_CLK_to_AUDIO_PLLkNONE_to_AUDIO_PLLkMAIN_CLK_to_SPIFI_CLKkSYS_PLL_to_SPIFI_CLKkUSB_PLL_to_SPIFI_CLKkFRO_HF_to_SPIFI_CLKkAUDIO_PLL_to_SPIFI_CLKkNONE_to_SPIFI_CLKkFRO_HF_to_ADC_CLK kSYS_PLL_to_ADC_CLK kUSB_PLL_to_ADC_CLK kAUDIO_PLL_to_ADC_CLK kNONE_to_ADC_CLK kFRO_HF_to_USB0_CLK kSYS_PLL_to_USB0_CLK kUSB_PLL_to_USB0_CLK kNONE_to_USB0_CLK kFRO_HF_to_USB1_CLK kSYS_PLL_to_USB1_CLK kUSB_PLL_to_USB1_CLK kNONE_to_USB1_CLK kFRO12M_to_FLEXCOMM0 kFRO_HF_to_FLEXCOMM0 kAUDIO_PLL_to_FLEXCOMM0 kMCLK_to_FLEXCOMM0 kFRG_to_FLEXCOMM0 kNONE_to_FLEXCOMM0 kFRO12M_to_FLEXCOMM1 kFRO_HF_to_FLEXCOMM1 kAUDIO_PLL_to_FLEXCOMM1 kMCLK_to_FLEXCOMM1 kFRG_to_FLEXCOMM1 kNONE_to_FLEXCOMM1 kFRO12M_to_FLEXCOMM2kFRO_HF_to_FLEXCOMM2kAUDIO_PLL_to_FLEXCOMM2kMCLK_to_FLEXCOMM2kFRG_to_FLEXCOMM2kNONE_to_FLEXCOMM2kFRO12M_to_FLEXCOMM3kFRO_HF_to_FLEXCOMM3kAUDIO_PLL_to_FLEXCOMM3kMCLK_to_FLEXCOMM3kFRG_to_FLEXCOMM3kNONE_to_FLEXCOMM3kFRO12M_to_FLEXCOMM4kFRO_HF_to_FLEXCOMM4kAUDIO_PLL_to_FLEXCOMM4kMCLK_to_FLEXCOMM4kFRG_to_FLEXCOMM4kNONE_to_FLEXCOMM4kFRO12M_to_FLEXCOMM5kFRO_HF_to_FLEXCOMM5kAUDIO_PLL_to_FLEXCOMM5kMCLK_to_FLEXCOMM5kFRG_to_FLEXCOMM5kNONE_to_FLEXCOMM5kFRO12M_to_FLEXCOMM6kFRO_HF_to_FLEXCOMM6kAUDIO_PLL_to_FLEXCOMM6kMCLK_to_FLEXCOMM6kFRG_to_FLEXCOMM6kNONE_to_FLEXCOMM6kFRO12M_to_FLEXCOMM7kFRO_HF_to_FLEXCOMM7kAUDIO_PLL_to_FLEXCOMM7kMCLK_to_FLEXCOMM7kFRG_to_FLEXCOMM7kNONE_to_FLEXCOMM7kFRO12M_to_FLEXCOMM8kFRO_HF_to_FLEXCOMM8kAUDIO_PLL_to_FLEXCOMM8kMCLK_to_FLEXCOMM8kFRG_to_FLEXCOMM8kNONE_to_FLEXCOMM8kFRO12M_to_FLEXCOMM9kFRO_HF_to_FLEXCOMM9kAUDIO_PLL_to_FLEXCOMM9kMCLK_to_FLEXCOMM9kFRG_to_FLEXCOMM9kNONE_to_FLEXCOMM9kFRO_HF_to_MCLKkAUDIO_PLL_to_MCLKkNONE_to_MCLKkMAIN_CLK_to_FRGkSYS_PLL_to_FRGkFRO12M_to_FRGkFRO_HF_to_FRGkNONE_to_FRGkFRO12M_to_DMICkFRO_HF_DIV_to_DMICkAUDIO_PLL_to_DMICkMCLK_to_DMICkNONE_to_DMICkMCLK_to_SCT_CLKkSYS_PLL_to_SCT_CLKkFRO_HF_to_SCT_CLKkAUDIO_PLL_to_SCT_CLKkNONE_to_SCT_CLKkMCLK_to_SDIO_CLKkSYS_PLL_to_SDIO_CLKkUSB_PLL_to_SDIO_CLKkFRO_HF_to_SDIO_CLKkAUDIO_PLL_to_SDIO_CLKkNONE_to_SDIO_CLKkMCLK_to_LCD_CLKkLCDCLKIN_to_LCD_CLKkFRO_HF_to_LCD_CLKkNONE_to_LCD_CLKkMAIN_CLK_to_ASYNC_APBkFRO12M_to_ASYNC_APBkAUDIO_PLL_to_ASYNC_APBkI2C_CLK_FC6_to_ASYNC_APBkNONE_to_NONE8_clock_div_namekCLOCK_DivSystickClk kCLOCK_DivArmTrClkDiv kCLOCK_DivCan0Clk kCLOCK_DivCan1Clk kCLOCK_DivSmartCard0Clk kCLOCK_DivSmartCard1Clk kCLOCK_DivAhbClk kCLOCK_DivClkOut !kCLOCK_DivFrohfClk "kCLOCK_DivSpifiClk $kCLOCK_DivAdcAsyncClk %kCLOCK_DivUsb0Clk &kCLOCK_DivUsb1Clk 'kCLOCK_DivFrg (kCLOCK_DivDmicClk *kCLOCK_DivMClk +kCLOCK_DivLcdClk ,kCLOCK_DivSctClk -kCLOCK_DivEmcClk .kCLOCK_DivSdioClk /:_clock_flashtimkCLOCK_Flash1Cycle kCLOCK_Flash2Cycle kCLOCK_Flash3Cycle kCLOCK_Flash4Cycle kCLOCK_Flash5Cycle kCLOCK_Flash6Cycle kCLOCK_Flash7Cycle kCLOCK_Flash8Cycle kCLOCK_Flash9Cycle ):_pll_config desiredRateY#inputRateY#flagsY#);_pll_setuppllctrlY#pllndecY#pllpdecY#pllmdecY# pllRateY#audpllfracY#flagsY#=_pll_errorkStatus_PLL_Success kStatus_PLL_OutputTooLow kStatus_PLL_OutputTooHigh kStatus_PLL_InputTooLow kStatus_PLL_InputTooHigh kStatus_PLL_OutsideIntLimit kStatus_PLL_CCOTooLow kStatus_PLL_CCOTooHigh >_clock_usb_srckCLOCK_UsbSrcFro kCLOCK_UsbSrcSystemPll kCLOCK_UsbSrcMainClock kCLOCK_UsbSrcUsbPll kCLOCK_UsbSrcNone ?_usb_pll_pselpSel_Divide_1 pSel_Divide_2 pSel_Divide_4 pSel_Divide_8 )@_usb_pll_setup msel:#psel:#nsel:#direct#bypass#fbsel#inputRateY# FlashPrg.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128Pintunsigned longunsigned char"93SPIFI_CheckIfFinished\valY@devices\LPC54608\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128@\> CLOCK_SetupFROClockingU@iiFreqYi___resultUKZusb_adjY"FX^fdevices\\LPC54608\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128<__asm___11_fsl_clock_c_d9f3d481____REVSHdevices\\LPC54608\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128 __asm___11_fsl_clock_c_d9f3d481____REV16 devices\LPC54608\drivers\fsl_spifi.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128.I o*^b3P cC@?RSPIFI_GetDefaultConfigiconfig-?^SPIFI_InitibaseӕiconfigF[a(Jdovac~aFYJThfY?qSPIFI_DeinitibaseӕFauoacaf?ySPIFI_SetCommandibaseӕSicmd@FY|fYeY?SPIFI_SetMemoryCommand.|ibaseӕ-icmdFY fYeYdevices\LPC54608\drivers\fsl_spifi.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128Ys_spifiClock y"Ys_spifiBasesݕ y"devices\\LPC54608\\drivers\\fsl_spifi.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128T__asm___11_fsl_spifi_c_d2a84ddf____REVSHdevices\\LPC54608\\drivers\\fsl_spifi.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128__asm___11_fsl_spifi_c_d2a84ddf____REV16FlashDev.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128pFlashDevice y"dFlashPrg.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128$ intunsigned longunsigned char"Iʹ6bFЄ.0=fe?BSPIFI_EnableQuadMode6\FTVFfnĄ?LSPIFI_InitPins\?ZSPIFI_InitCommands<d>Init<Diadr}iclkjifncW^__resultP\>UnInit0ifncD^__resultP>EraseChip^__resultP8F|f>EraseSectoriadr&^__resultP<F|fFFfgnp>BlankCheckiadriszipat^__resultP>ProgramPageiadriszibuf^__resultPfZiaZjtF|$0fFFNPfgnpF\^fnĄIIodNcl0Ix|oo ooFlashPrg.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621] D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128pcommand y"pconfig^ @y"pbase_adrY y"FlashPrg.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128 __asm___10_FlashPrg_c_21f264b4____REVSH FlashPrg.cComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]D:\working_SVN\UV_Setup\ARM\ARM\Flash\LPC5460x_MT25QL128__asm___10_FlashPrg_c_21f264b4____REV16XL devices\LPC54608\drivers\fsl_power.hfsl_common.hK devices\LPC54608\drivers\fsl_clock.cfsl_power.h@:~": ~   k  ~ 1z7 |x` C:\\Keil_v5\\ARM\\PACK\\ARM\\CMSIS\\5.0.1\\CMSIS\\Include\\cmsis_armcc.hx` C:\\Keil_v5\\ARM\\PACK\\ARM\\CMSIS\\5.0.1\\CMSIS\\Include\\cmsis_armcc.h|s devices\LPC54608\drivers\devices\LPC54608\drivers\fsl_spifi.cfsl_spifi.hfsl_spifi.cXL devices\LPC54608\drivers\fsl_spifi.hfsl_common.h devices\LPC54608\drivers\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\LPC54608\fsl_common.hassert.hstdbool.hstdint.hstring.hfsl_device_registers.hfsl_clock.hfsl_reset.h devices\LPC54608\drivers\.\devices\LPC54608\C:\Keil_v5\ARM\ARMCC\Bin\..\include\fsl_clock.hfsl_device_registers.hstdint.hstdbool.hassert.hZ devices\LPC54608\drivers\fsl_spifi.cfsl_clock.hfsl_spifi.h z  ~%$ 1} {+ | ~ 1} {% {~ ~cx` C:\\Keil_v5\\ARM\\PACK\\ARM\\CMSIS\\5.0.1\\CMSIS\\Include\\cmsis_armcc.hx` C:\\Keil_v5\\ARM\\PACK\\ARM\\CMSIS\\5.0.1\\CMSIS\\Include\\cmsis_armcc.h<1 FlashDev.c..\FlashOS.Htk .\devices\LPC54608\drivers\FlashPrg.c..\FlashOS.Hfsl_iocon.hfsl_spifi.htj .\devices\LPC54608\.\devices\LPC54608\drivers\drivers\fsl_spifi.hfsl_common.hy .\devices\LPC54608\drivers\.\devices\LPC54608\fsl_iocon.hfsl_common.hdrivers\fsl_iocon.h .\devices\LPC54608\C:\Keil_v5\ARM\ARMCC\Bin\..\include\drivers\fsl_clock.hfsl_device_registers.hstdint.hstdbool.hassert.h .\devices\LPC54608\C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include\LPC54608.hcore_cm4.hsystem_LPC54608.hPD C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hPD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h,# ..\FlashOS.Hz .\devices\LPC54608\FlashPrg.cdrivers\fsl_spifi.hdrivers\fsl_clock.hdrivers\fsl_iocon.h2 2 }2,},,,,,,&D~ &4- ( Y,,-%  mh+,- K  nKoKo  }@% &.- } ~~ + }{ x` C:\\Keil_v5\\ARM\\PACK\\ARM\\CMSIS\\5.0.1\\CMSIS\\Include\\cmsis_armcc.h x` C:\\Keil_v5\\ARM\\PACK\\ARM\\CMSIS\\5.0.1\\CMSIS\\Include\\cmsis_armcc.h}^}(:QBHQX^QPVXP4P4Z}4}}}>@}@}">}}"}4RQ4ZP&Q4PQQPPVbQT`PltP>BQBhTlT>FPFhUlU">PPPPQ}l}} } j}(jl}}}}}}}$(}(}}$} DF}F} } D}}}SRQPn~RRlzPDHPTUZlURlTQZd P lVRQPPUP$2R$*Q$.P _FSL_POWER_H_ "(MAKE_PD_BITS(reg,slot) ((reg << 8) | slot))PDRCFG0 0x0U*PDRCFG1 0x1U_FSL_SPIFI_H_ !/FSL_SPIFI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) _FSL_COMMON_H_ "#$%+7MAKE_STATUS(group,code) ((((group)*100) + (code))):MAKE_VERSION(major,minor,bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))=DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U>DEBUG_CONSOLE_DEVICE_TYPE_UART 1U?DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U@DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3UADEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4UBDEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5UCDEBUG_CONSOLE_DEVICE_TYPE_IUART 6UMIN(a,b) ((a) < (b) ? (a) : (b))MAX(a,b) ((a) > (b) ? (a) : (b))ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))USEC_TO_COUNT(us,clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)COUNT_TO_USEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)MSEC_TO_COUNT(ms,clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)COUNT_TO_MSEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)!_FSL_CLOCK_H_ #$%&> CLK_GATE_REG_OFFSET_SHIFT)CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)AHB_CLK_CTRL0 0AHB_CLK_CTRL1 1AHB_CLK_CTRL2 2ASYNC_CLK_CTRL0 3MUX_A(m,choice) (((m) << 0) | ((choice + 1) << 8))MUX_B(m,choice) (((m) << 12) | ((choice + 1) << 20))MUX_C(m,choice) (((m) << 24) | ((choice + 1) << 32))MUX_D(m,choice) (((m) << 36) | ((choice + 1) << 44))MUX_E(m,choice) (((m) << 48) | ((choice + 1) << 56))CM_MAINCLKSELA 0CM_MAINCLKSELB 1CM_CLKOUTCLKSELA 2CM_SYSPLLCLKSEL 4CM_AUDPLLCLKSEL 6CM_SPIFICLKSEL 8CM_ADCASYNCCLKSEL 9CM_USB0CLKSEL 10CM_USB1CLKSEL 11CM_FXCOMCLKSEL0 12CM_FXCOMCLKSEL1 13CM_FXCOMCLKSEL2 14CM_FXCOMCLKSEL3 15CM_FXCOMCLKSEL4 16CM_FXCOMCLKSEL5 17CM_FXCOMCLKSEL6 18CM_FXCOMCLKSEL7 19CM_FXCOMCLKSEL8 20CM_FXCOMCLKSEL9 21CM_MCLKCLKSEL 24CM_FRGCLKSEL 26CM_DMICCLKSEL 27CM_SCTCLKSEL 28CM_LCDCLKSEL 29CM_SDIOCLKSEL 30CM_ASYNCAPB 31PLL_CONFIGFLAG_USEINRATE (1 << 0)PLL_CONFIGFLAG_FORCENOFRACT (1 << 2)PLL_SETUPFLAG_POWERUP (1 << 0)PLL_SETUPFLAG_WAITLOCK (1 << 1)PLL_SETUPFLAG_ADGVOLT (1 << 2)!PAGE_SIZE (256)#READ (0)$WRITE_ENABLE (1)%WRITE_REGISTER (2)&GET_STATUS (3)'PROGRAM_PAGE (4)(ERASE_SECTOR (5))BULK_ERASE (6)*COMMAND_NUM (7)_FSL_SPIFI_H_ !/FSL_SPIFI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) _FSL_IOCON_H_ "2LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))DIOCON_FUNC0 0x0EIOCON_FUNC1 0x1FIOCON_FUNC2 0x2GIOCON_FUNC3 0x3HIOCON_FUNC4 0x4IIOCON_FUNC5 0x5JIOCON_FUNC6 0x6KIOCON_FUNC7 0x7LIOCON_FUNC8 0x8MIOCON_FUNC9 0x9NIOCON_FUNC10 0xAOIOCON_FUNC11 0xBPIOCON_FUNC12 0xCQIOCON_FUNC13 0xDRIOCON_FUNC14 0xESIOCON_FUNC15 0xFTIOCON_MODE_INACT (0x0 << 4)UIOCON_MODE_PULLDOWN (0x1 << 4)VIOCON_MODE_PULLUP (0x2 << 4)WIOCON_MODE_REPEATER (0x3 << 4)XIOCON_HYS_EN (0x1 << 6)YIOCON_GPIO_MODE (0x1 << 6)ZIOCON_I2C_SLEW (0x1 << 6)[IOCON_INV_EN (0x1 << 7)\IOCON_ANALOG_EN (0x0 << 8)]IOCON_DIGITAL_EN (0x1 << 8)^IOCON_STDI2C_EN (0x1 << 9)_IOCON_FASTI2C_EN (0x3 << 9)`IOCON_INPFILT_OFF (0x1 << 9)aIOCON_INPFILT_ON (0x0 << 9)bIOCON_OPENDRAIN_EN (0x1 << 11)cIOCON_S_MODE_0CLK (0x0 << 12)dIOCON_S_MODE_1CLK (0x1 << 12)eIOCON_S_MODE_2CLK (0x2 << 12)fIOCON_S_MODE_3CLK (0x3 << 12)gIOCON_S_MODE(clks) ((clks) << 12)hIOCON_CLKDIV(div) ((div) << 14)!_FSL_CLOCK_H_ #$%&> CLK_GATE_REG_OFFSET_SHIFT)CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)AHB_CLK_CTRL0 0AHB_CLK_CTRL1 1AHB_CLK_CTRL2 2ASYNC_CLK_CTRL0 3MUX_A(m,choice) (((m) << 0) | ((choice + 1) << 8))MUX_B(m,choice) (((m) << 12) | ((choice + 1) << 20))MUX_C(m,choice) (((m) << 24) | ((choice + 1) << 32))MUX_D(m,choice) (((m) << 36) | ((choice + 1) << 44))MUX_E(m,choice) (((m) << 48) | ((choice + 1) << 56))CM_MAINCLKSELA 0CM_MAINCLKSELB 1CM_CLKOUTCLKSELA 2CM_SYSPLLCLKSEL 4CM_AUDPLLCLKSEL 6CM_SPIFICLKSEL 8CM_ADCASYNCCLKSEL 9CM_USB0CLKSEL 10CM_USB1CLKSEL 11CM_FXCOMCLKSEL0 12CM_FXCOMCLKSEL1 13CM_FXCOMCLKSEL2 14CM_FXCOMCLKSEL3 15CM_FXCOMCLKSEL4 16CM_FXCOMCLKSEL5 17CM_FXCOMCLKSEL6 18CM_FXCOMCLKSEL7 19CM_FXCOMCLKSEL8 20CM_FXCOMCLKSEL9 21CM_MCLKCLKSEL 24CM_FRGCLKSEL 26CM_DMICCLKSEL 27CM_SCTCLKSEL 28CM_LCDCLKSEL 29CM_SDIOCLKSEL 30CM_ASYNCAPB 31PLL_CONFIGFLAG_USEINRATE (1 << 0)PLL_CONFIGFLAG_FORCENOFRACT (1 << 2)PLL_SETUPFLAG_POWERUP (1 << 0)PLL_SETUPFLAG_WAITLOCK (1 << 1)PLL_SETUPFLAG_ADGVOLT (1 << 2)D_LPC54608_H_ HMCU_MEM_MAP_VERSION 0x0100UJMCU_MEM_MAP_VERSION_MINOR 0x0001UWNUMBER_OF_INT_VECTORS 73__MPU_PRESENT 1__NVIC_PRIO_BITS 3__Vendor_SysTickConfig 0__FPU_PRESENT 1ADC_CTRL_CLKDIV_MASK (0xFFU)ADC_CTRL_CLKDIV_SHIFT (0U)ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)ADC_CTRL_ASYNMODE_MASK (0x100U)ADC_CTRL_ASYNMODE_SHIFT (8U)ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)ADC_CTRL_RESOL_MASK (0x600U)ADC_CTRL_RESOL_SHIFT (9U)ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)ADC_CTRL_BYPASSCAL_MASK (0x800U)ADC_CTRL_BYPASSCAL_SHIFT (11U)ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)ADC_CTRL_TSAMP_MASK (0x7000U)ADC_CTRL_TSAMP_SHIFT (12U)ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)ADC_INSEL_SEL_MASK (0x3U)ADC_INSEL_SEL_SHIFT (0U)ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)ADC_SEQ_CTRL_START_MASK (0x4000000U)ADC_SEQ_CTRL_START_SHIFT (26U)ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)ADC_SEQ_CTRL_BURST_MASK (0x8000000U)ADC_SEQ_CTRL_BURST_SHIFT (27U)ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)ADC_SEQ_CTRL_MODE_MASK (0x40000000U)ADC_SEQ_CTRL_MODE_SHIFT (30U)ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)ADC_SEQ_CTRL_COUNT (2U)ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)ADC_SEQ_GDAT_RESULT_SHIFT (4U)ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)ADC_SEQ_GDAT_CHN_SHIFT (26U)ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)ADC_SEQ_GDAT_COUNT (2U)ADC_DAT_RESULT_MASK (0xFFF0U)ADC_DAT_RESULT_SHIFT (4U)ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)ADC_DAT_THCMPRANGE_MASK (0x30000U)ADC_DAT_THCMPRANGE_SHIFT (16U)ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)ADC_DAT_THCMPCROSS_MASK (0xC0000U)ADC_DAT_THCMPCROSS_SHIFT (18U)ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)ADC_DAT_CHANNEL_MASK (0x3C000000U)ADC_DAT_CHANNEL_SHIFT (26U)ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)ADC_DAT_OVERRUN_MASK (0x40000000U)ADC_DAT_OVERRUN_SHIFT (30U)ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)ADC_DAT_DATAVALID_MASK (0x80000000U)ADC_DAT_DATAVALID_SHIFT (31U)ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)ADC_DAT_COUNT (12U)ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)ADC_THR0_LOW_THRLOW_SHIFT (4U)ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)ADC_THR1_LOW_THRLOW_SHIFT (4U)ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)ADC_THR0_HIGH_THRHIGH_SHIFT (4U)ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)ADC_THR1_HIGH_THRHIGH_SHIFT (4U)ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)ADC_INTEN_SEQA_INTEN_MASK (0x1U)ADC_INTEN_SEQA_INTEN_SHIFT (0U)ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)ADC_INTEN_SEQB_INTEN_MASK (0x2U)ADC_INTEN_SEQB_INTEN_SHIFT (1U)ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)ADC_INTEN_OVR_INTEN_MASK (0x4U)ADC_INTEN_OVR_INTEN_SHIFT (2U)ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)ADC_INTEN_ADCMPINTEN0_MASK (0x18U)ADC_INTEN_ADCMPINTEN0_SHIFT (3U)ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)ADC_INTEN_ADCMPINTEN1_MASK (0x60U)ADC_INTEN_ADCMPINTEN1_SHIFT (5U)ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)ADC_INTEN_ADCMPINTEN2_MASK (0x180U)ADC_INTEN_ADCMPINTEN2_SHIFT (7U)ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)ADC_INTEN_ADCMPINTEN3_MASK (0x600U)ADC_INTEN_ADCMPINTEN3_SHIFT (9U)ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)ADC_INTEN_ADCMPINTEN4_SHIFT (11U)ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)ADC_INTEN_ADCMPINTEN5_SHIFT (13U)ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)ADC_INTEN_ADCMPINTEN6_SHIFT (15U)ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)ADC_INTEN_ADCMPINTEN7_SHIFT (17U)ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)ADC_INTEN_ADCMPINTEN8_SHIFT (19U)ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)ADC_INTEN_ADCMPINTEN9_SHIFT (21U)ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)ADC_INTEN_ADCMPINTEN10_SHIFT (23U)ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)ADC_INTEN_ADCMPINTEN11_SHIFT (25U)ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)ADC_FLAGS_THCMP0_MASK (0x1U)ADC_FLAGS_THCMP0_SHIFT (0U)ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)ADC_FLAGS_THCMP1_MASK (0x2U)ADC_FLAGS_THCMP1_SHIFT (1U)ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)ADC_FLAGS_THCMP2_MASK (0x4U)ADC_FLAGS_THCMP2_SHIFT (2U)ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)ADC_FLAGS_THCMP3_MASK (0x8U)ADC_FLAGS_THCMP3_SHIFT (3U)ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)ADC_FLAGS_THCMP4_MASK (0x10U)ADC_FLAGS_THCMP4_SHIFT (4U)ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)ADC_FLAGS_THCMP5_MASK (0x20U)ADC_FLAGS_THCMP5_SHIFT (5U)ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)ADC_FLAGS_THCMP6_MASK (0x40U)ADC_FLAGS_THCMP6_SHIFT (6U)ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)ADC_FLAGS_THCMP7_MASK (0x80U)ADC_FLAGS_THCMP7_SHIFT (7U)ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)ADC_FLAGS_THCMP8_MASK (0x100U)ADC_FLAGS_THCMP8_SHIFT (8U)ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)ADC_FLAGS_THCMP9_MASK (0x200U)ADC_FLAGS_THCMP9_SHIFT (9U)ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)ADC_FLAGS_THCMP10_MASK (0x400U)ADC_FLAGS_THCMP10_SHIFT (10U)ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)ADC_FLAGS_THCMP11_MASK (0x800U)ADC_FLAGS_THCMP11_SHIFT (11U)ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)ADC_FLAGS_OVERRUN0_MASK (0x1000U)ADC_FLAGS_OVERRUN0_SHIFT (12U)ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)ADC_FLAGS_OVERRUN1_MASK (0x2000U)ADC_FLAGS_OVERRUN1_SHIFT (13U)ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)ADC_FLAGS_OVERRUN2_MASK (0x4000U)ADC_FLAGS_OVERRUN2_SHIFT (14U)ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)ADC_FLAGS_OVERRUN3_MASK (0x8000U)ADC_FLAGS_OVERRUN3_SHIFT (15U)ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)ADC_FLAGS_OVERRUN4_MASK (0x10000U)ADC_FLAGS_OVERRUN4_SHIFT (16U)ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)ADC_FLAGS_OVERRUN5_MASK (0x20000U)ADC_FLAGS_OVERRUN5_SHIFT (17U)ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)ADC_FLAGS_OVERRUN6_MASK (0x40000U)ADC_FLAGS_OVERRUN6_SHIFT (18U)ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)ADC_FLAGS_OVERRUN7_MASK (0x80000U)ADC_FLAGS_OVERRUN7_SHIFT (19U)ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)ADC_FLAGS_OVERRUN8_MASK (0x100000U)ADC_FLAGS_OVERRUN8_SHIFT (20U)ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)ADC_FLAGS_OVERRUN9_MASK (0x200000U)ADC_FLAGS_OVERRUN9_SHIFT (21U)ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)ADC_FLAGS_OVERRUN10_MASK (0x400000U)ADC_FLAGS_OVERRUN10_SHIFT (22U)ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)ADC_FLAGS_OVERRUN11_MASK (0x800000U)ADC_FLAGS_OVERRUN11_SHIFT (23U)ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)ADC_FLAGS_SEQA_OVR_SHIFT (24U)ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)ADC_FLAGS_SEQB_OVR_SHIFT (25U)ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)ADC_FLAGS_SEQA_INT_MASK (0x10000000U)ADC_FLAGS_SEQA_INT_SHIFT (28U)ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)ADC_FLAGS_SEQB_INT_MASK (0x20000000U)ADC_FLAGS_SEQB_INT_SHIFT (29U)ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)ADC_FLAGS_THCMP_INT_MASK (0x40000000U)ADC_FLAGS_THCMP_INT_SHIFT (30U)ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)ADC_FLAGS_OVR_INT_MASK (0x80000000U)ADC_FLAGS_OVR_INT_SHIFT (31U)ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)ADC_STARTUP_ADC_ENA_MASK (0x1U)ADC_STARTUP_ADC_ENA_SHIFT (0U)ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)ADC_STARTUP_ADC_INIT_MASK (0x2U)ADC_STARTUP_ADC_INIT_SHIFT (1U)ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)ADC_CALIB_CALIB_MASK (0x1U)ADC_CALIB_CALIB_SHIFT (0U)ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)ADC_CALIB_CALREQD_MASK (0x2U)ADC_CALIB_CALREQD_SHIFT (1U)ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)ADC_CALIB_CALVALUE_MASK (0x1FCU)ADC_CALIB_CALVALUE_SHIFT (2U)ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)ADC0_BASE (0x400A0000u)ADC0 ((ADC_Type *)ADC0_BASE)ADC_BASE_ADDRS { ADC0_BASE }ADC_BASE_PTRS { ADC0 }ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }ADC_THCMP_IRQS { ADC0_THCMP_IRQn }ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)ASYNC_SYSCON_BASE (0x40040000u)ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }CAN_TEST_LBCK_MASK (0x10U)CAN_TEST_LBCK_SHIFT (4U)CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)CAN_TEST_TX_MASK (0x60U)CAN_TEST_TX_SHIFT (5U)CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)CAN_TEST_RX_MASK (0x80U)CAN_TEST_RX_SHIFT (7U)CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)CAN_CCCR_INIT_MASK (0x1U)CAN_CCCR_INIT_SHIFT (0U)CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)CAN_CCCR_CCE_MASK (0x2U)CAN_CCCR_CCE_SHIFT (1U)CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)CAN_CCCR_ASM_MASK (0x4U)CAN_CCCR_ASM_SHIFT (2U)CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)CAN_CCCR_CSA_MASK (0x8U)CAN_CCCR_CSA_SHIFT (3U)CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)CAN_CCCR_CSR_MASK (0x10U)CAN_CCCR_CSR_SHIFT (4U)CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)CAN_CCCR_MON_MASK (0x20U)CAN_CCCR_MON_SHIFT (5U)CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)CAN_CCCR_DAR_MASK (0x40U)CAN_CCCR_DAR_SHIFT (6U)CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)CAN_CCCR_TEST_MASK (0x80U)CAN_CCCR_TEST_SHIFT (7U)CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)CAN_CCCR_PXHD_MASK (0x1000U)CAN_CCCR_PXHD_SHIFT (12U)CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)CAN_CCCR_EFBI_MASK (0x2000U)CAN_CCCR_EFBI_SHIFT (13U)CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)CAN_CCCR_TXP_MASK (0x4000U)CAN_CCCR_TXP_SHIFT (14U)CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)CAN_NBTP_NTSEG2_MASK (0x7FU)CAN_NBTP_NTSEG2_SHIFT (0U)CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)CAN_NBTP_NTSEG1_MASK (0xFF00U)CAN_NBTP_NTSEG1_SHIFT (8U)CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)CAN_NBTP_NBRP_MASK (0x1FF0000U)CAN_NBTP_NBRP_SHIFT (16U)CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)CAN_NBTP_NSJW_MASK (0xFE000000U)CAN_NBTP_NSJW_SHIFT (25U)CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)CAN_TSCC_TSS_MASK (0x3U)CAN_TSCC_TSS_SHIFT (0U)CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)CAN_TSCC_TCP_MASK (0xF0000U)CAN_TSCC_TCP_SHIFT (16U)CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)CAN_TSCV_TSC_MASK (0xFFFFU)CAN_TSCV_TSC_SHIFT (0U)CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)CAN_TOCC_ETOC_MASK (0x1U)CAN_TOCC_ETOC_SHIFT (0U)CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)CAN_TOCC_TOS_MASK (0x6U)CAN_TOCC_TOS_SHIFT (1U)CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)CAN_TOCC_TOP_MASK (0xFFFF0000U)CAN_TOCC_TOP_SHIFT (16U)CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)CAN_TOCV_TOC_MASK (0xFFFFU)CAN_TOCV_TOC_SHIFT (0U)CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)CAN_ECR_TEC_MASK (0xFFU)CAN_ECR_TEC_SHIFT (0U)CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)CAN_ECR_REC_MASK (0x7F00U)CAN_ECR_REC_SHIFT (8U)CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)CAN_ECR_RP_MASK (0x8000U)CAN_ECR_RP_SHIFT (15U)CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)CAN_ECR_CEL_MASK (0xFF0000U)CAN_ECR_CEL_SHIFT (16U)CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)CAN_PSR_LEC_MASK (0x7U)CAN_PSR_LEC_SHIFT (0U)CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)CAN_PSR_ACT_MASK (0x18U)CAN_PSR_ACT_SHIFT (3U)CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)CAN_PSR_EP_MASK (0x20U)CAN_PSR_EP_SHIFT (5U)CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)CAN_PSR_EW_MASK (0x40U)CAN_PSR_EW_SHIFT (6U)CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)CAN_PSR_BO_MASK (0x80U)CAN_PSR_BO_SHIFT (7U)CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)CAN_PSR_PXE_MASK (0x4000U)CAN_PSR_PXE_SHIFT (14U)CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)CAN_PSR_TDCV_MASK (0x7F0000U)CAN_PSR_TDCV_SHIFT (16U)CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)CAN_TDCR_TDCF_MASK (0x7FU)CAN_TDCR_TDCF_SHIFT (0U)CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)CAN_TDCR_TDCO_MASK (0x7F00U)CAN_TDCR_TDCO_SHIFT (8U)CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)CAN_IR_RF0N_MASK (0x1U)CAN_IR_RF0N_SHIFT (0U)CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)CAN_IR_RF0W_MASK (0x2U)CAN_IR_RF0W_SHIFT (1U)CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)CAN_IR_RF0F_MASK (0x4U)CAN_IR_RF0F_SHIFT (2U)CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)CAN_IR_RF0L_MASK (0x8U)CAN_IR_RF0L_SHIFT (3U)CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)CAN_IR_RF1N_MASK (0x10U)CAN_IR_RF1N_SHIFT (4U)CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)CAN_IR_RF1W_MASK (0x20U)CAN_IR_RF1W_SHIFT (5U)CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)CAN_IR_RF1F_MASK (0x40U)CAN_IR_RF1F_SHIFT (6U)CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)CAN_IR_RF1L_MASK (0x80U)CAN_IR_RF1L_SHIFT (7U)CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)CAN_IR_HPM_MASK (0x100U)CAN_IR_HPM_SHIFT (8U)CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)CAN_IR_TC_MASK (0x200U)CAN_IR_TC_SHIFT (9U)CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)CAN_IR_TCF_MASK (0x400U)CAN_IR_TCF_SHIFT (10U)CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)CAN_IR_TFE_MASK (0x800U)CAN_IR_TFE_SHIFT (11U)CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)CAN_IR_TEFN_MASK (0x1000U)CAN_IR_TEFN_SHIFT (12U)CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)CAN_IR_TEFW_MASK (0x2000U)CAN_IR_TEFW_SHIFT (13U)CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)CAN_IR_TEFF_MASK (0x4000U)CAN_IR_TEFF_SHIFT (14U)CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)CAN_IR_TEFL_MASK (0x8000U)CAN_IR_TEFL_SHIFT (15U)CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)CAN_IR_TSW_MASK (0x10000U)CAN_IR_TSW_SHIFT (16U)CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)CAN_IR_MRAF_MASK (0x20000U)CAN_IR_MRAF_SHIFT (17U)CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)CAN_IR_TOO_MASK (0x40000U)CAN_IR_TOO_SHIFT (18U)CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)CAN_IR_DRX_MASK (0x80000U)CAN_IR_DRX_SHIFT (19U)CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)CAN_IR_BEC_MASK (0x100000U)CAN_IR_BEC_SHIFT (20U)CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)CAN_IR_BEU_MASK (0x200000U)CAN_IR_BEU_SHIFT (21U)CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)CAN_IR_ELO_MASK (0x400000U)CAN_IR_ELO_SHIFT (22U)CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)CAN_IR_EP_MASK (0x800000U)CAN_IR_EP_SHIFT (23U)CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)CAN_IR_EW_MASK (0x1000000U)CAN_IR_EW_SHIFT (24U)CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)CAN_IR_BO_MASK (0x2000000U)CAN_IR_BO_SHIFT (25U)CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)CAN_IR_WDI_MASK (0x4000000U)CAN_IR_WDI_SHIFT (26U)CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)CAN_IR_PEA_MASK (0x8000000U)CAN_IR_PEA_SHIFT (27U)CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)CAN_IR_PED_MASK (0x10000000U)CAN_IR_PED_SHIFT (28U)CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)CAN_IR_ARA_MASK (0x20000000U)CAN_IR_ARA_SHIFT (29U)CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)CAN_IE_RF0NE_MASK (0x1U)CAN_IE_RF0NE_SHIFT (0U)CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)CAN_IE_RF0WE_MASK (0x2U)CAN_IE_RF0WE_SHIFT (1U)CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)CAN_IE_RF0FE_MASK (0x4U)CAN_IE_RF0FE_SHIFT (2U)CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)CAN_IE_RF0LE_MASK (0x8U)CAN_IE_RF0LE_SHIFT (3U)CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)CAN_IE_RF1NE_MASK (0x10U)CAN_IE_RF1NE_SHIFT (4U)CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)CAN_IE_RF1WE_MASK (0x20U)CAN_IE_RF1WE_SHIFT (5U)CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)CAN_IE_RF1FE_MASK (0x40U)CAN_IE_RF1FE_SHIFT (6U)CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)CAN_IE_RF1LE_MASK (0x80U)CAN_IE_RF1LE_SHIFT (7U)CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)CAN_IE_HPME_MASK (0x100U)CAN_IE_HPME_SHIFT (8U)CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)CAN_IE_TCE_MASK (0x200U)CAN_IE_TCE_SHIFT (9U)CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)CAN_IE_TCFE_MASK (0x400U)CAN_IE_TCFE_SHIFT (10U)CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)CAN_IE_TFEE_MASK (0x800U)CAN_IE_TFEE_SHIFT (11U)CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)CAN_IE_TEFNE_MASK (0x1000U)CAN_IE_TEFNE_SHIFT (12U)CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)CAN_IE_TEFWE_MASK (0x2000U)CAN_IE_TEFWE_SHIFT (13U)CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)CAN_IE_TEFFE_MASK (0x4000U)CAN_IE_TEFFE_SHIFT (14U)CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)CAN_IE_TEFLE_MASK (0x8000U)CAN_IE_TEFLE_SHIFT (15U)CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)CAN_IE_TSWE_MASK (0x10000U)CAN_IE_TSWE_SHIFT (16U)CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)CAN_IE_MRAFE_MASK (0x20000U)CAN_IE_MRAFE_SHIFT (17U)CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)CAN_IE_TOOE_MASK (0x40000U)CAN_IE_TOOE_SHIFT (18U)CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)CAN_IE_DRXE_MASK (0x80000U)CAN_IE_DRXE_SHIFT (19U)CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)CAN_IE_BECE_MASK (0x100000U)CAN_IE_BECE_SHIFT (20U)CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)CAN_IE_BEUE_MASK (0x200000U)CAN_IE_BEUE_SHIFT (21U)CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)CAN_IE_ELOE_MASK (0x400000U)CAN_IE_ELOE_SHIFT (22U)CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)CAN_IE_EPE_MASK (0x800000U)CAN_IE_EPE_SHIFT (23U)CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)CAN_IE_EWE_MASK (0x1000000U)CAN_IE_EWE_SHIFT (24U)CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)CAN_IE_BOE_MASK (0x2000000U)CAN_IE_BOE_SHIFT (25U)CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)CAN_IE_WDIE_MASK (0x4000000U)CAN_IE_WDIE_SHIFT (26U)CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)CAN_IE_PEAE_MASK (0x8000000U)CAN_IE_PEAE_SHIFT (27U)CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)CAN_IE_PEDE_MASK (0x10000000U)CAN_IE_PEDE_SHIFT (28U)CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)CAN_IE_ARAE_MASK (0x20000000U)CAN_IE_ARAE_SHIFT (29U)CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)CAN_ILS_RF0NL_MASK (0x1U)CAN_ILS_RF0NL_SHIFT (0U)CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)CAN_ILS_RF0WL_MASK (0x2U)CAN_ILS_RF0WL_SHIFT (1U)CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)CAN_ILS_RF0FL_MASK (0x4U)CAN_ILS_RF0FL_SHIFT (2U)CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)CAN_ILS_RF0LL_MASK (0x8U)CAN_ILS_RF0LL_SHIFT (3U)CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)CAN_ILS_RF1NL_MASK (0x10U)CAN_ILS_RF1NL_SHIFT (4U)CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)CAN_ILS_RF1WL_MASK (0x20U)CAN_ILS_RF1WL_SHIFT (5U)CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)CAN_ILS_RF1FL_MASK (0x40U)CAN_ILS_RF1FL_SHIFT (6U)CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)CAN_ILS_RF1LL_MASK (0x80U)CAN_ILS_RF1LL_SHIFT (7U)CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)CAN_ILS_HPML_MASK (0x100U)CAN_ILS_HPML_SHIFT (8U)CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)CAN_ILS_TCL_MASK (0x200U)CAN_ILS_TCL_SHIFT (9U)CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)CAN_ILS_TCFL_MASK (0x400U)CAN_ILS_TCFL_SHIFT (10U)CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)CAN_ILS_TFEL_MASK (0x800U)CAN_ILS_TFEL_SHIFT (11U)CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)CAN_ILS_TEFNL_MASK (0x1000U)CAN_ILS_TEFNL_SHIFT (12U)CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)CAN_ILS_TEFWL_MASK (0x2000U)CAN_ILS_TEFWL_SHIFT (13U)CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)CAN_ILS_TEFFL_MASK (0x4000U)CAN_ILS_TEFFL_SHIFT (14U)CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)CAN_ILS_TEFLL_MASK (0x8000U)CAN_ILS_TEFLL_SHIFT (15U)CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)CAN_ILS_TSWL_MASK (0x10000U)CAN_ILS_TSWL_SHIFT (16U)CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) CAN_ILS_MRAFL_MASK (0x20000U) CAN_ILS_MRAFL_SHIFT (17U) CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) CAN_ILS_TOOL_MASK (0x40000U) CAN_ILS_TOOL_SHIFT (18U) CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) CAN_ILS_DRXL_MASK (0x80000U) CAN_ILS_DRXL_SHIFT (19U) CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) CAN_ILS_BECL_MASK (0x100000U) CAN_ILS_BECL_SHIFT (20U) CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) CAN_ILS_BEUL_MASK (0x200000U) CAN_ILS_BEUL_SHIFT (21U) CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) CAN_ILS_ELOL_MASK (0x400000U) CAN_ILS_ELOL_SHIFT (22U) CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) CAN_ILS_EPL_MASK (0x800000U) CAN_ILS_EPL_SHIFT (23U) CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) CAN_ILS_EWL_MASK (0x1000000U) CAN_ILS_EWL_SHIFT (24U) CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) CAN_ILS_BOL_MASK (0x2000000U) CAN_ILS_BOL_SHIFT (25U) CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) CAN_ILS_WDIL_MASK (0x4000000U) CAN_ILS_WDIL_SHIFT (26U) CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) CAN_ILS_PEAL_MASK (0x8000000U) CAN_ILS_PEAL_SHIFT (27U) CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) CAN_ILS_PEDL_MASK (0x10000000U) CAN_ILS_PEDL_SHIFT (28U) CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) CAN_ILS_ARAL_MASK (0x20000000U) CAN_ILS_ARAL_SHIFT (29U) CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) CAN_ILE_EINT0_MASK (0x1U) CAN_ILE_EINT0_SHIFT (0U) CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) CAN_ILE_EINT1_MASK (0x2U) CAN_ILE_EINT1_SHIFT (1U) CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) CAN_GFC_RRFE_MASK (0x1U) CAN_GFC_RRFE_SHIFT (0U) CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) CAN_GFC_RRFS_MASK (0x2U) CAN_GFC_RRFS_SHIFT (1U) CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) CAN_GFC_ANFE_MASK (0xCU) CAN_GFC_ANFE_SHIFT (2U) CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) CAN_GFC_ANFS_MASK (0x30U) CAN_GFC_ANFS_SHIFT (4U) CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) CAN_SIDFC_FLSSA_MASK (0xFFFCU) CAN_SIDFC_FLSSA_SHIFT (2U) CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) CAN_SIDFC_LSS_MASK (0xFF0000U) CAN_SIDFC_LSS_SHIFT (16U) CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) CAN_XIDFC_FLESA_MASK (0xFFFCU) CAN_XIDFC_FLESA_SHIFT (2U) CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) CAN_XIDFC_LSE_MASK (0xFF0000U) CAN_XIDFC_LSE_SHIFT (16U) CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) CAN_XIDAM_EIDM_SHIFT (0U) CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) CAN_HPMS_BIDX_MASK (0x3FU) CAN_HPMS_BIDX_SHIFT (0U) CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) CAN_HPMS_MSI_MASK (0xC0U) CAN_HPMS_MSI_SHIFT (6U) CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) CAN_HPMS_FIDX_MASK (0x7F00U) CAN_HPMS_FIDX_SHIFT (8U) CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) CAN_HPMS_FLST_MASK (0x8000U) CAN_HPMS_FLST_SHIFT (15U) CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) CAN_NDAT1_ND_MASK (0xFFFFFFFFU) CAN_NDAT1_ND_SHIFT (0U) CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) CAN_NDAT2_ND_MASK (0xFFFFFFFFU) CAN_NDAT2_ND_SHIFT (0U) CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) CAN_RXF0C_F0SA_MASK (0xFFFCU) CAN_RXF0C_F0SA_SHIFT (2U) CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) CAN_RXF0C_F0S_MASK (0x7F0000U) CAN_RXF0C_F0S_SHIFT (16U) CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) CAN_RXF0C_F0WM_MASK (0x7F000000U) CAN_RXF0C_F0WM_SHIFT (24U) CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) CAN_RXF0C_F0OM_MASK (0x80000000U) CAN_RXF0C_F0OM_SHIFT (31U) CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) CAN_RXF0S_F0FL_MASK (0x7FU) CAN_RXF0S_F0FL_SHIFT (0U) CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) CAN_RXF0S_F0GI_MASK (0x3F00U) CAN_RXF0S_F0GI_SHIFT (8U) CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) CAN_RXF0S_F0PI_MASK (0x3F0000U) CAN_RXF0S_F0PI_SHIFT (16U) CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) CAN_RXF0S_F0F_MASK (0x1000000U) CAN_RXF0S_F0F_SHIFT (24U) CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) CAN_RXF0S_RF0L_MASK (0x2000000U) CAN_RXF0S_RF0L_SHIFT (25U) CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) CAN_RXF0A_F0AI_MASK (0x3FU) CAN_RXF0A_F0AI_SHIFT (0U) CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) CAN_RXBC_RBSA_MASK (0xFFFCU) CAN_RXBC_RBSA_SHIFT (2U) CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) CAN_RXF1C_F1SA_MASK (0xFFFCU) CAN_RXF1C_F1SA_SHIFT (2U) CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) CAN_RXF1C_F1S_MASK (0x7F0000U) CAN_RXF1C_F1S_SHIFT (16U) CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) CAN_RXF1C_F1WM_MASK (0x7F000000U) CAN_RXF1C_F1WM_SHIFT (24U) CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) CAN_RXF1C_F1OM_MASK (0x80000000U) CAN_RXF1C_F1OM_SHIFT (31U) CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) CAN_RXF1S_F1FL_MASK (0x7FU) CAN_RXF1S_F1FL_SHIFT (0U) CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) CAN_RXF1S_F1GI_MASK (0x3F00U) CAN_RXF1S_F1GI_SHIFT (8U) CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) CAN_RXF1S_F1PI_MASK (0x3F0000U) CAN_RXF1S_F1PI_SHIFT (16U) CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) CAN_RXF1S_F1F_MASK (0x1000000U) CAN_RXF1S_F1F_SHIFT (24U) CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) CAN_RXF1S_RF1L_MASK (0x2000000U) CAN_RXF1S_RF1L_SHIFT (25U) CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) CAN_RXF1A_F1AI_MASK (0x3FU) CAN_RXF1A_F1AI_SHIFT (0U) CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) CAN_RXESC_F0DS_MASK (0x7U) CAN_RXESC_F0DS_SHIFT (0U) CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) CAN_RXESC_F1DS_MASK (0x70U) CAN_RXESC_F1DS_SHIFT (4U) CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) CAN_RXESC_RBDS_MASK (0x700U) CAN_RXESC_RBDS_SHIFT (8U) CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) CAN_TXBC_TBSA_MASK (0xFFFCU) CAN_TXBC_TBSA_SHIFT (2U) CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) CAN_TXBC_NDTB_MASK (0x3F0000U) CAN_TXBC_NDTB_SHIFT (16U) CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) CAN_TXBC_TFQS_MASK (0x3F000000U) CAN_TXBC_TFQS_SHIFT (24U) CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) CAN_TXBC_TFQM_MASK (0x40000000U) CAN_TXBC_TFQM_SHIFT (30U) CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) CAN_TXFQS_TFGI_MASK (0x1F00U) CAN_TXFQS_TFGI_SHIFT (8U) CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) CAN_TXFQS_TFQPI_MASK (0x1F0000U) CAN_TXFQS_TFQPI_SHIFT (16U) CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) CAN_TXFQS_TFQF_MASK (0x200000U) CAN_TXFQS_TFQF_SHIFT (21U) CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) CAN_TXESC_TBDS_MASK (0x7U) CAN_TXESC_TBDS_SHIFT (0U) CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) CAN_TXBRP_TRP_SHIFT (0U) CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) CAN_TXBAR_AR_MASK (0xFFFFFFFFU) CAN_TXBAR_AR_SHIFT (0U) CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) CAN_TXBCR_CR_MASK (0xFFFFFFFFU) CAN_TXBCR_CR_SHIFT (0U) CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) CAN_TXBTO_TO_MASK (0xFFFFFFFFU) CAN_TXBTO_TO_SHIFT (0U) CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) CAN_TXBCF_TO_MASK (0xFFFFFFFFU) CAN_TXBCF_TO_SHIFT (0U) CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) CAN_TXBTIE_TIE_SHIFT (0U) CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) CAN_TXBCIE_CFIE_SHIFT (0U) CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) CAN_TXEFC_EFSA_MASK (0xFFFCU) CAN_TXEFC_EFSA_SHIFT (2U) CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) CAN_TXEFC_EFS_MASK (0x3F0000U) CAN_TXEFC_EFS_SHIFT (16U) CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) CAN_TXEFC_EFWM_MASK (0x3F000000U) CAN_TXEFC_EFWM_SHIFT (24U) CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) CAN_TXEFS_EFFL_MASK (0x3FU) CAN_TXEFS_EFFL_SHIFT (0U) CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) CAN_TXEFS_EFGI_MASK (0x1F00U) CAN_TXEFS_EFGI_SHIFT (8U) CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) CAN_TXEFS_EFPI_MASK (0x3F0000U) CAN_TXEFS_EFPI_SHIFT (16U) CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) CAN_TXEFS_EFF_MASK (0x1000000U) CAN_TXEFS_EFF_SHIFT (24U) CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) CAN_TXEFS_TEFL_MASK (0x2000000U) CAN_TXEFS_TEFL_SHIFT (25U) CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) CAN_TXEFA_EFAI_MASK (0x1FU) CAN_TXEFA_EFAI_SHIFT (0U) CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) CAN_MRBA_BA_MASK (0xFFFFFFFFU) CAN_MRBA_BA_SHIFT (0U) CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) CAN_ETSCC_ETCP_MASK (0x7FFU) CAN_ETSCC_ETCP_SHIFT (0U) CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) CAN_ETSCC_ETCE_MASK (0x80000000U) CAN_ETSCC_ETCE_SHIFT (31U) CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) CAN_ETSCV_ETSC_MASK (0xFFFFU) CAN_ETSCV_ETSC_SHIFT (0U) CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) CAN0_BASE (0x4009D000u) CAN0 ((CAN_Type *)CAN0_BASE) CAN1_BASE (0x4009E000u) CAN1 ((CAN_Type *)CAN1_BASE) CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } CAN_BASE_PTRS { CAN0, CAN1 } CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } } CRC_MODE_CRC_POLY_MASK (0x3U) CRC_MODE_CRC_POLY_SHIFT (0U) CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) CRC_MODE_BIT_RVS_WR_MASK (0x4U) CRC_MODE_BIT_RVS_WR_SHIFT (2U) CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) CRC_MODE_CMPL_WR_MASK (0x8U) CRC_MODE_CMPL_WR_SHIFT (3U) CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) CRC_MODE_BIT_RVS_SUM_MASK (0x10U) CRC_MODE_BIT_RVS_SUM_SHIFT (4U) CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) CRC_MODE_CMPL_SUM_MASK (0x20U) CRC_MODE_CMPL_SUM_SHIFT (5U) CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) CRC_SEED_CRC_SEED_SHIFT (0U) CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) CRC_SUM_CRC_SUM_SHIFT (0U) CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) CRC_ENGINE_BASE (0x40095000u) CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) CRC_BASE_ADDRS { CRC_ENGINE_BASE } CRC_BASE_PTRS { CRC_ENGINE } CTIMER_IR_MR0INT_MASK (0x1U) CTIMER_IR_MR0INT_SHIFT (0U) CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) CTIMER_IR_MR1INT_MASK (0x2U) CTIMER_IR_MR1INT_SHIFT (1U) CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) CTIMER_IR_MR2INT_MASK (0x4U) CTIMER_IR_MR2INT_SHIFT (2U) CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) CTIMER_IR_MR3INT_MASK (0x8U) CTIMER_IR_MR3INT_SHIFT (3U) CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) CTIMER_IR_CR0INT_MASK (0x10U) CTIMER_IR_CR0INT_SHIFT (4U) CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) CTIMER_IR_CR1INT_MASK (0x20U) CTIMER_IR_CR1INT_SHIFT (5U) CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) CTIMER_IR_CR2INT_MASK (0x40U) CTIMER_IR_CR2INT_SHIFT (6U) CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) CTIMER_IR_CR3INT_MASK (0x80U) CTIMER_IR_CR3INT_SHIFT (7U) CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) CTIMER_TCR_CEN_MASK (0x1U) CTIMER_TCR_CEN_SHIFT (0U) CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) CTIMER_TCR_CRST_MASK (0x2U) CTIMER_TCR_CRST_SHIFT (1U) CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) CTIMER_TC_TCVAL_SHIFT (0U) CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) CTIMER_PR_PRVAL_SHIFT (0U) CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) CTIMER_PC_PCVAL_SHIFT (0U) CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) CTIMER_MCR_MR0I_MASK (0x1U) CTIMER_MCR_MR0I_SHIFT (0U) CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) CTIMER_MCR_MR0R_MASK (0x2U) CTIMER_MCR_MR0R_SHIFT (1U) CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) CTIMER_MCR_MR0S_MASK (0x4U) CTIMER_MCR_MR0S_SHIFT (2U) CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) CTIMER_MCR_MR1I_MASK (0x8U) CTIMER_MCR_MR1I_SHIFT (3U) CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) CTIMER_MCR_MR1R_MASK (0x10U) CTIMER_MCR_MR1R_SHIFT (4U) CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) CTIMER_MCR_MR1S_MASK (0x20U) CTIMER_MCR_MR1S_SHIFT (5U) CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) CTIMER_MCR_MR2I_MASK (0x40U) CTIMER_MCR_MR2I_SHIFT (6U) CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) CTIMER_MCR_MR2R_MASK (0x80U) CTIMER_MCR_MR2R_SHIFT (7U) CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) CTIMER_MCR_MR2S_MASK (0x100U) CTIMER_MCR_MR2S_SHIFT (8U) CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) CTIMER_MCR_MR3I_MASK (0x200U) CTIMER_MCR_MR3I_SHIFT (9U) CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) CTIMER_MCR_MR3R_MASK (0x400U) CTIMER_MCR_MR3R_SHIFT (10U) CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) CTIMER_MCR_MR3S_MASK (0x800U) CTIMER_MCR_MR3S_SHIFT (11U) CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) CTIMER_MCR_MR0RL_MASK (0x1000000U) CTIMER_MCR_MR0RL_SHIFT (24U) CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) CTIMER_MCR_MR1RL_MASK (0x2000000U) CTIMER_MCR_MR1RL_SHIFT (25U) CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) CTIMER_MCR_MR2RL_MASK (0x4000000U) CTIMER_MCR_MR2RL_SHIFT (26U) CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) CTIMER_MCR_MR3RL_MASK (0x8000000U) CTIMER_MCR_MR3RL_SHIFT (27U) CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) CTIMER_MR_MATCH_SHIFT (0U) CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) CTIMER_MR_COUNT (4U) CTIMER_CCR_CAP0RE_MASK (0x1U) CTIMER_CCR_CAP0RE_SHIFT (0U) CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) CTIMER_CCR_CAP0FE_MASK (0x2U) CTIMER_CCR_CAP0FE_SHIFT (1U) CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) CTIMER_CCR_CAP0I_MASK (0x4U) CTIMER_CCR_CAP0I_SHIFT (2U) CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) CTIMER_CCR_CAP1RE_MASK (0x8U) CTIMER_CCR_CAP1RE_SHIFT (3U) CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) CTIMER_CCR_CAP1FE_MASK (0x10U) CTIMER_CCR_CAP1FE_SHIFT (4U) CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) CTIMER_CCR_CAP1I_MASK (0x20U) CTIMER_CCR_CAP1I_SHIFT (5U) CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) CTIMER_CCR_CAP2RE_MASK (0x40U) CTIMER_CCR_CAP2RE_SHIFT (6U) CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) CTIMER_CCR_CAP2FE_MASK (0x80U) CTIMER_CCR_CAP2FE_SHIFT (7U) CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) CTIMER_CCR_CAP2I_MASK (0x100U) CTIMER_CCR_CAP2I_SHIFT (8U) CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) CTIMER_CCR_CAP3RE_MASK (0x200U) CTIMER_CCR_CAP3RE_SHIFT (9U) CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) CTIMER_CCR_CAP3FE_MASK (0x400U) CTIMER_CCR_CAP3FE_SHIFT (10U) CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) CTIMER_CCR_CAP3I_MASK (0x800U) CTIMER_CCR_CAP3I_SHIFT (11U) CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) CTIMER_CR_CAP_MASK (0xFFFFFFFFU) CTIMER_CR_CAP_SHIFT (0U) CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) CTIMER_CR_COUNT (4U) CTIMER_EMR_EM0_MASK (0x1U) CTIMER_EMR_EM0_SHIFT (0U) CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) CTIMER_EMR_EM1_MASK (0x2U) CTIMER_EMR_EM1_SHIFT (1U) CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) CTIMER_EMR_EM2_MASK (0x4U) CTIMER_EMR_EM2_SHIFT (2U) CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) CTIMER_EMR_EM3_MASK (0x8U) CTIMER_EMR_EM3_SHIFT (3U) CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) CTIMER_EMR_EMC0_MASK (0x30U) CTIMER_EMR_EMC0_SHIFT (4U) CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) CTIMER_EMR_EMC1_MASK (0xC0U) CTIMER_EMR_EMC1_SHIFT (6U) CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) CTIMER_EMR_EMC2_MASK (0x300U) CTIMER_EMR_EMC2_SHIFT (8U) CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) CTIMER_EMR_EMC3_MASK (0xC00U) CTIMER_EMR_EMC3_SHIFT (10U) CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) CTIMER_CTCR_CTMODE_MASK (0x3U) CTIMER_CTCR_CTMODE_SHIFT (0U) CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) CTIMER_CTCR_CINSEL_MASK (0xCU) CTIMER_CTCR_CINSEL_SHIFT (2U)CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)CTIMER_CTCR_ENCC_MASK (0x10U)CTIMER_CTCR_ENCC_SHIFT (4U)CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)CTIMER_CTCR_SELCC_MASK (0xE0U)CTIMER_CTCR_SELCC_SHIFT (5U)CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)CTIMER_PWMC_PWMEN0_MASK (0x1U)CTIMER_PWMC_PWMEN0_SHIFT (0U)CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)CTIMER_PWMC_PWMEN1_MASK (0x2U)CTIMER_PWMC_PWMEN1_SHIFT (1U)CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)CTIMER_PWMC_PWMEN2_MASK (0x4U)CTIMER_PWMC_PWMEN2_SHIFT (2U)CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)CTIMER_PWMC_PWMEN3_MASK (0x8U)CTIMER_PWMC_PWMEN3_SHIFT (3U)CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)CTIMER_MSR_SHADOWW_SHIFT (0U)CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)CTIMER_MSR_COUNT (4U)CTIMER0_BASE (0x40008000u)CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)CTIMER1_BASE (0x40009000u)CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)CTIMER2_BASE (0x40028000u)CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)CTIMER3_BASE (0x40048000u)CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)CTIMER4_BASE (0x40049000u)CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }DMA_CTRL_ENABLE_MASK (0x1U)DMA_CTRL_ENABLE_SHIFT (0U)DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)DMA_INTSTAT_ACTIVEINT_MASK (0x2U)DMA_INTSTAT_ACTIVEINT_SHIFT (1U)DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)DMA_SRAMBASE_OFFSET_SHIFT (9U)DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)DMA_COMMON_ENABLESET_ENA_SHIFT (0U)DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)DMA_COMMON_ENABLESET_COUNT (1U)DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)DMA_COMMON_ENABLECLR_COUNT (1U)DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)DMA_COMMON_ACTIVE_ACT_SHIFT (0U)DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)DMA_COMMON_ACTIVE_COUNT (1U)DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)DMA_COMMON_BUSY_BSY_SHIFT (0U)DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)DMA_COMMON_BUSY_COUNT (1U)DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)DMA_COMMON_ERRINT_ERR_SHIFT (0U)DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)DMA_COMMON_ERRINT_COUNT (1U)DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)DMA_COMMON_INTENSET_INTEN_SHIFT (0U)DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)DMA_COMMON_INTENSET_COUNT (1U)DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)DMA_COMMON_INTENCLR_CLR_SHIFT (0U)DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)DMA_COMMON_INTENCLR_COUNT (1U)DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)DMA_COMMON_INTA_IA_SHIFT (0U)DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)DMA_COMMON_INTA_COUNT (1U)DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)DMA_COMMON_INTB_IB_SHIFT (0U)DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)DMA_COMMON_INTB_COUNT (1U)DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)DMA_COMMON_SETVALID_SV_SHIFT (0U)DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)DMA_COMMON_SETVALID_COUNT (1U)DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)DMA_COMMON_SETTRIG_COUNT (1U)DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)DMA_COMMON_ABORT_COUNT (1U)DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)DMA_CHANNEL_CFG_COUNT (30U)DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)DMA_CHANNEL_CTLSTAT_COUNT (30U)DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)DMA_CHANNEL_XFERCFG_COUNT (30U)DMA0_BASE (0x40082000u)DMA0 ((DMA_Type *)DMA0_BASE)DMA_BASE_ADDRS { DMA0_BASE }DMA_BASE_PTRS { DMA0 }DMA_IRQS { DMA0_IRQn }DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)DMIC_CHANNEL_OSR_OSR_SHIFT (0U)DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)DMIC_CHANNEL_OSR_COUNT (2U)DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)DMIC_CHANNEL_DIVHFCLK_COUNT (2U)DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)DMIC_CHANNEL_GAINSHIFT_COUNT (2U)DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)DMIC_CHANNEL_FIFO_DATA_COUNT (2U)DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)DMIC_CHANNEL_PHY_CTRL_COUNT (2U)DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)DMIC_CHANNEL_DC_CTRL_COUNT (2U)DMIC_CHANEN_EN_CH0_MASK (0x1U)DMIC_CHANEN_EN_CH0_SHIFT (0U)DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)DMIC_CHANEN_EN_CH1_MASK (0x2U)DMIC_CHANEN_EN_CH1_SHIFT (1U)DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)DMIC_USE2FS_USE2FS_MASK (0x1U)DMIC_USE2FS_USE2FS_SHIFT (0U)DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)DMIC_HWVADHPFS_HPFS_MASK (0x3U)DMIC_HWVADHPFS_HPFS_SHIFT (0U)DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)DMIC_HWVADST10_ST10_MASK (0x1U)DMIC_HWVADST10_ST10_SHIFT (0U)DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)DMIC_HWVADRSTT_RSTT_MASK (0x1U)DMIC_HWVADRSTT_RSTT_SHIFT (0U)DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)DMIC_HWVADTHGN_THGN_MASK (0xFU)DMIC_HWVADTHGN_THGN_SHIFT (0U)DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)DMIC_HWVADTHGS_THGS_MASK (0xFU)DMIC_HWVADTHGS_THGS_SHIFT (0U)DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)DMIC_ID_ID_MASK (0xFFFFFFFFU)DMIC_ID_ID_SHIFT (0U)DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)DMIC0_BASE (0x40090000u)DMIC0 ((DMIC_Type *)DMIC0_BASE)DMIC_BASE_ADDRS { DMIC0_BASE }DMIC_BASE_PTRS { DMIC0 }DMIC_IRQS { DMIC0_IRQn }DMIC_HWVAD_IRQS { HWVAD0_IRQn }EEPROM_CMD_CMD_MASK (0x7U)EEPROM_CMD_CMD_SHIFT (0U)EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)EEPROM_RWSTATE_RPHASE2_MASK (0xFFU)EEPROM_RWSTATE_RPHASE2_SHIFT (0U)EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK)EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U)EEPROM_RWSTATE_RPHASE1_SHIFT (8U)EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK)EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U)EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U)EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK)EEPROM_WSTATE_PHASE3_MASK (0xFFU)EEPROM_WSTATE_PHASE3_SHIFT (0U)EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK)EEPROM_WSTATE_PHASE2_MASK (0xFF00U)EEPROM_WSTATE_PHASE2_SHIFT (8U)EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK)EEPROM_WSTATE_PHASE1_MASK (0xFF0000U)EEPROM_WSTATE_PHASE1_SHIFT (16U)EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK)EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U)EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U)EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK)EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU)EEPROM_CLKDIV_CLKDIV_SHIFT (0U)EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK)EEPROM_PWRDWN_PWRDWN_MASK (0x1U)EEPROM_PWRDWN_PWRDWN_SHIFT (0U)EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK)EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U)EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U)EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK)EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U)EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U)EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK)EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U)EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U)EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK)EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U)EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U)EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK)EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U)EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U)EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK)EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U)EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U)EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK)EEPROM_BASE (0x40014000u)EEPROM ((EEPROM_Type *)EEPROM_BASE)EEPROM_BASE_ADDRS { EEPROM_BASE }EEPROM_BASE_PTRS { EEPROM }EEPROM_IRQS { EEPROM_IRQn }EMC_CONTROL_E_MASK (0x1U)EMC_CONTROL_E_SHIFT (0U)EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)EMC_CONTROL_M_MASK (0x2U)EMC_CONTROL_M_SHIFT (1U)EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)EMC_CONTROL_L_MASK (0x4U)EMC_CONTROL_L_SHIFT (2U)EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)EMC_STATUS_B_MASK (0x1U)EMC_STATUS_B_SHIFT (0U)EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)EMC_STATUS_S_MASK (0x2U)EMC_STATUS_S_SHIFT (1U)EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)EMC_STATUS_SA_MASK (0x4U)EMC_STATUS_SA_SHIFT (2U)EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)EMC_CONFIG_EM_MASK (0x1U)EMC_CONFIG_EM_SHIFT (0U)EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)EMC_CONFIG_CLKR_MASK (0x100U)EMC_CONFIG_CLKR_SHIFT (8U)EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)EMC_DYNAMICCONTROL_CE_MASK (0x1U)EMC_DYNAMICCONTROL_CE_SHIFT (0U)EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)EMC_DYNAMICCONTROL_CS_MASK (0x2U)EMC_DYNAMICCONTROL_CS_SHIFT (1U)EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)EMC_DYNAMICCONTROL_SR_MASK (0x4U)EMC_DYNAMICCONTROL_SR_SHIFT (2U)EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)EMC_DYNAMICCONTROL_MMC_MASK (0x20U)EMC_DYNAMICCONTROL_MMC_SHIFT (5U)EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)EMC_DYNAMICCONTROL_I_MASK (0x180U)EMC_DYNAMICCONTROL_I_SHIFT (7U)EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)EMC_DYNAMICRP_TRP_MASK (0xFU)EMC_DYNAMICRP_TRP_SHIFT (0U)EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)EMC_DYNAMICRAS_TRAS_MASK (0xFU)EMC_DYNAMICRAS_TRAS_SHIFT (0U)EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)EMC_DYNAMICSREX_TSREX_MASK (0xFU)EMC_DYNAMICSREX_TSREX_SHIFT (0U)EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)EMC_DYNAMICAPR_TAPR_MASK (0xFU)EMC_DYNAMICAPR_TAPR_SHIFT (0U)EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)EMC_DYNAMICDAL_TDAL_MASK (0xFU)EMC_DYNAMICDAL_TDAL_SHIFT (0U)EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)EMC_DYNAMICWR_TWR_MASK (0xFU)EMC_DYNAMICWR_TWR_SHIFT (0U)EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)EMC_DYNAMICRC_TRC_MASK (0x1FU)EMC_DYNAMICRC_TRC_SHIFT (0U)EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)EMC_DYNAMICRFC_TRFC_MASK (0x1FU)EMC_DYNAMICRFC_TRFC_SHIFT (0U)EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)EMC_DYNAMICXSR_TXSR_MASK (0x1FU)EMC_DYNAMICXSR_TXSR_SHIFT (0U)EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)EMC_DYNAMICRRD_TRRD_MASK (0xFU)EMC_DYNAMICRRD_TRRD_SHIFT (0U)EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)EMC_DYNAMICMRD_TMRD_MASK (0xFU)EMC_DYNAMICMRD_TMRD_SHIFT (0U)EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)EMC_STATIC_STATICCONFIG_B_SHIFT (19U)EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)EMC_STATIC_STATICCONFIG_P_SHIFT (20U)EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)EMC_STATIC_STATICCONFIG_COUNT (4U)EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)EMC_STATIC_STATICWAITWEN_COUNT (4U)EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)EMC_STATIC_STATICWAITOEN_COUNT (4U)EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)EMC_STATIC_STATICWAITRD_COUNT (4U)EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)EMC_STATIC_STATICWAITPAGE_COUNT (4U)EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)EMC_STATIC_STATICWAITWR_COUNT (4U)EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)EMC_STATIC_STATICWAITTURN_COUNT (4U)EMC_BASE (0x40081000u)EMC ((EMC_Type *)EMC_BASE)EMC_BASE_ADDRS { EMC_BASE }EMC_BASE_PTRS { EMC }ENET_MAC_CONFIG_RE_MASK (0x1U)ENET_MAC_CONFIG_RE_SHIFT (0U)ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)ENET_MAC_CONFIG_TE_MASK (0x2U)ENET_MAC_CONFIG_TE_SHIFT (1U)ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)ENET_MAC_CONFIG_PRELEN_MASK (0xCU)ENET_MAC_CONFIG_PRELEN_SHIFT (2U)ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)ENET_MAC_CONFIG_DC_MASK (0x10U)ENET_MAC_CONFIG_DC_SHIFT (4U)ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)ENET_MAC_CONFIG_BL_MASK (0x60U)ENET_MAC_CONFIG_BL_SHIFT (5U)ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)ENET_MAC_CONFIG_DR_MASK (0x100U)ENET_MAC_CONFIG_DR_SHIFT (8U)ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)ENET_MAC_CONFIG_DCRS_MASK (0x200U)ENET_MAC_CONFIG_DCRS_SHIFT (9U)ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)ENET_MAC_CONFIG_DO_MASK (0x400U)ENET_MAC_CONFIG_DO_SHIFT (10U)ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)ENET_MAC_CONFIG_LM_MASK (0x1000U)ENET_MAC_CONFIG_LM_SHIFT (12U)ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)ENET_MAC_CONFIG_DM_MASK (0x2000U)ENET_MAC_CONFIG_DM_SHIFT (13U)ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)ENET_MAC_CONFIG_FES_MASK (0x4000U)ENET_MAC_CONFIG_FES_SHIFT (14U)ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)ENET_MAC_CONFIG_PS_MASK (0x8000U)ENET_MAC_CONFIG_PS_SHIFT (15U)ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)ENET_MAC_CONFIG_JE_MASK (0x10000U)ENET_MAC_CONFIG_JE_SHIFT (16U)ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)ENET_MAC_CONFIG_JD_MASK (0x20000U)ENET_MAC_CONFIG_JD_SHIFT (17U)ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)ENET_MAC_CONFIG_BE_MASK (0x40000U)ENET_MAC_CONFIG_BE_SHIFT (18U)ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)ENET_MAC_CONFIG_WD_MASK (0x80000U)ENET_MAC_CONFIG_WD_SHIFT (19U)ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)ENET_MAC_CONFIG_ACS_MASK (0x100000U)ENET_MAC_CONFIG_ACS_SHIFT (20U)ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)ENET_MAC_CONFIG_CST_MASK (0x200000U)ENET_MAC_CONFIG_CST_SHIFT (21U)ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)ENET_MAC_CONFIG_S2KP_MASK (0x400000U)ENET_MAC_CONFIG_S2KP_SHIFT (22U)ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)ENET_MAC_CONFIG_IPG_MASK (0x7000000U)ENET_MAC_CONFIG_IPG_SHIFT (24U)ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)ENET_MAC_CONFIG_IPC_MASK (0x8000000U)ENET_MAC_CONFIG_IPC_SHIFT (27U)ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)ENET_MAC_VLAN_TAG_VL_SHIFT (0U)ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)ENET_MAC_RXQ_CTRL_COUNT (3U)ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)ENET_MAC_INTR_EN_TSIE_SHIFT (12U)ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)ENET_MAC_VERSION_SNPVER_MASK (0xFFU)ENET_MAC_VERSION_SNPVER_SHIFT (0U)ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)ENET_MAC_VERSION_USERVER_MASK (0xFF00U)ENET_MAC_VERSION_USERVER_SHIFT (8U)ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)ENET_MAC_DBG_REPESTS_MASK (0x1U)ENET_MAC_DBG_REPESTS_SHIFT (0U)ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)ENET_MAC_DBG_TPESTS_MASK (0x10000U)ENET_MAC_DBG_TPESTS_SHIFT (16U)ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)ENET_MAC_DBG_TFCSTS_MASK (0x60000U)ENET_MAC_DBG_TFCSTS_SHIFT (17U)ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)ENET_MAC_HW_FEAT_COUNT (3U)ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)ENET_MAC_MDIO_DATA_MD_SHIFT (0U)ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)ENET_MTL_OP_MODE_RAA_MASK (0x4U)ENET_MTL_OP_MODE_RAA_SHIFT (2U)ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)ENET_DMA_MODE_SWR_MASK (0x1U)ENET_DMA_MODE_SWR_SHIFT (0U)ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)ENET_DMA_MODE_DA_MASK (0x2U)ENET_DMA_MODE_DA_SHIFT (1U)ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)ENET_DMA_MODE_TAA_MASK (0x1CU)ENET_DMA_MODE_TAA_SHIFT (2U)ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)ENET_DMA_MODE_TXPR_MASK (0x800U)ENET_DMA_MODE_TXPR_SHIFT (11U)ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)ENET_DMA_MODE_PR_MASK (0x7000U)ENET_DMA_MODE_PR_SHIFT (12U)ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK) ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U) ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU) ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U) ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK) ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U) ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU) ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U) ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK) ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U) ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U) ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U) ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U) ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U) ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK) ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U) ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U) ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK) ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U) ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U) ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U) ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U) ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U) ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U) ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK) ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U) ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U) ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK) ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U) ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U) ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK) ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U) ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U) ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK) ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U) ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U) ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK) ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U) ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U) ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK) ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U) ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U) ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK) ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U) ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U) ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK) ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U) ENET_BASE (0x40092000u) ENET ((ENET_Type *)ENET_BASE) ENET_BASE_ADDRS { ENET_BASE } ENET_BASE_PTRS { ENET } ENET_IRQS { ETHERNET_IRQn } ENET_PMT_IRQS { ETHERNET_PMT_IRQn } ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } FLEXCOMM_PSELID_PERSEL_MASK (0x7U) FLEXCOMM_PSELID_PERSEL_SHIFT (0U) FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) FLEXCOMM_PSELID_LOCK_MASK (0x8U) FLEXCOMM_PSELID_LOCK_SHIFT (3U) FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)!FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)!FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)!FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)!FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)!FLEXCOMM_PSELID_ID_SHIFT (12U)!FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)!FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)!FLEXCOMM_PID_Minor_Rev_SHIFT (8U)!FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)!FLEXCOMM_PID_Major_Rev_MASK (0xF000U)!FLEXCOMM_PID_Major_Rev_SHIFT (12U)!FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)!FLEXCOMM_PID_ID_MASK (0xFFFF0000U)!FLEXCOMM_PID_ID_SHIFT (16U)!FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)!FLEXCOMM0_BASE (0x40086000u)!FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)!FLEXCOMM1_BASE (0x40087000u)!FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)!FLEXCOMM2_BASE (0x40088000u)!FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)!FLEXCOMM3_BASE (0x40089000u)!FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)!FLEXCOMM4_BASE (0x4008A000u)!FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)!FLEXCOMM5_BASE (0x40096000u)!FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)!FLEXCOMM6_BASE (0x40097000u)!FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)!FLEXCOMM7_BASE (0x40098000u)!FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)!FLEXCOMM8_BASE (0x40099000u)!FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)!FLEXCOMM9_BASE (0x4009A000u)!FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)!FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE }!FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 }!FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }!FMC_FCTR_FS_RD0_MASK (0x8U)!FMC_FCTR_FS_RD0_SHIFT (3U)!FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK)!FMC_FCTR_FS_RD1_MASK (0x10U)!FMC_FCTR_FS_RD1_SHIFT (4U)!FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK)!FMC_FBWST_WAITSTATES_MASK (0xFFU)!FMC_FBWST_WAITSTATES_SHIFT (0U)!FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK)!FMC_FMSSTART_START_MASK (0x1FFFFU)!FMC_FMSSTART_START_SHIFT (0U)!FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK)"FMC_FMSSTOP_STOP_MASK (0x1FFFFU)"FMC_FMSSTOP_STOP_SHIFT (0U)"FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK)"FMC_FMSSTOP_SIG_START_MASK (0x20000U)"FMC_FMSSTOP_SIG_START_SHIFT (17U)"FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK)"FMC_FMSW_SW_MASK (0xFFFFFFFFU)"FMC_FMSW_SW_SHIFT (0U)"FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK)"FMC_FMSW_COUNT (4U)"FMC_FMSTAT_SIG_DONE_MASK (0x4U)"FMC_FMSTAT_SIG_DONE_SHIFT (2U)"FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK)"FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U)"FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U)"FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK)"FMC_BASE (0x40034000u)"FMC ((FMC_Type *)FMC_BASE)"FMC_BASE_ADDRS { FMC_BASE }"FMC_BASE_PTRS { FMC }"GINT_CTRL_INT_MASK (0x1U)"GINT_CTRL_INT_SHIFT (0U)"GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)"GINT_CTRL_COMB_MASK (0x2U)"GINT_CTRL_COMB_SHIFT (1U)"GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)"GINT_CTRL_TRIG_MASK (0x4U)"GINT_CTRL_TRIG_SHIFT (2U)"GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)"GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)"GINT_PORT_POL_POL_SHIFT (0U)"GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)"GINT_PORT_POL_COUNT (2U)"GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)"GINT_PORT_ENA_ENA_SHIFT (0U)"GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)"GINT_PORT_ENA_COUNT (2U)"GINT0_BASE (0x40002000u)"GINT0 ((GINT_Type *)GINT0_BASE)"GINT1_BASE (0x40003000u)"GINT1 ((GINT_Type *)GINT1_BASE)"GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }"GINT_BASE_PTRS { GINT0, GINT1 }"GINT_IRQS { GINT0_IRQn, GINT1_IRQn }#GPIO_B_PBYTE_MASK (0x1U)#GPIO_B_PBYTE_SHIFT (0U)#GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)#GPIO_B_COUNT (6U)#GPIO_B_COUNT2 (32U)#GPIO_W_PWORD_MASK (0xFFFFFFFFU)#GPIO_W_PWORD_SHIFT (0U)#GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)#GPIO_W_COUNT (6U)#GPIO_W_COUNT2 (32U)#GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)#GPIO_DIR_DIRP_SHIFT (0U)#GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)#GPIO_DIR_COUNT (6U)#GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)#GPIO_MASK_MASKP_SHIFT (0U)#GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)#GPIO_MASK_COUNT (6U)#GPIO_PIN_PORT_MASK (0xFFFFFFFFU)#GPIO_PIN_PORT_SHIFT (0U)#GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)#GPIO_PIN_COUNT (6U)#GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)#GPIO_MPIN_MPORTP_SHIFT (0U)#GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)#GPIO_MPIN_COUNT (6U)#GPIO_SET_SETP_MASK (0xFFFFFFFFU)#GPIO_SET_SETP_SHIFT (0U)#GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)#GPIO_SET_COUNT (6U)#GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)#GPIO_CLR_CLRP_SHIFT (0U)#GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)#GPIO_CLR_COUNT (6U)#GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)#GPIO_NOT_NOTP_SHIFT (0U)#GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)#GPIO_NOT_COUNT (6U)#GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)#GPIO_DIRSET_DIRSETP_SHIFT (0U)#GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)$GPIO_DIRSET_COUNT (6U)$GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)$GPIO_DIRCLR_DIRCLRP_SHIFT (0U)$GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)$GPIO_DIRCLR_COUNT (6U)$GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)$GPIO_DIRNOT_DIRNOTP_SHIFT (0U)$GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)$GPIO_DIRNOT_COUNT (6U)$GPIO_BASE (0x4008C000u)$GPIO ((GPIO_Type *)GPIO_BASE)$GPIO_BASE_ADDRS { GPIO_BASE }$GPIO_BASE_PTRS { GPIO }$I2C_CFG_MSTEN_MASK (0x1U)$I2C_CFG_MSTEN_SHIFT (0U)$I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)$I2C_CFG_SLVEN_MASK (0x2U)$I2C_CFG_SLVEN_SHIFT (1U)$I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)$I2C_CFG_MONEN_MASK (0x4U)$I2C_CFG_MONEN_SHIFT (2U)$I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)$I2C_CFG_TIMEOUTEN_MASK (0x8U)$I2C_CFG_TIMEOUTEN_SHIFT (3U)$I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)$I2C_CFG_MONCLKSTR_MASK (0x10U)$I2C_CFG_MONCLKSTR_SHIFT (4U)$I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)$I2C_CFG_HSCAPABLE_MASK (0x20U)$I2C_CFG_HSCAPABLE_SHIFT (5U)$I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)$I2C_STAT_MSTPENDING_MASK (0x1U)$I2C_STAT_MSTPENDING_SHIFT (0U)$I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)$I2C_STAT_MSTSTATE_MASK (0xEU)$I2C_STAT_MSTSTATE_SHIFT (1U)$I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)$I2C_STAT_MSTARBLOSS_MASK (0x10U)$I2C_STAT_MSTARBLOSS_SHIFT (4U)$I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)$I2C_STAT_MSTSTSTPERR_MASK (0x40U)$I2C_STAT_MSTSTSTPERR_SHIFT (6U)$I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)$I2C_STAT_SLVPENDING_MASK (0x100U)$I2C_STAT_SLVPENDING_SHIFT (8U)$I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)$I2C_STAT_SLVSTATE_MASK (0x600U)$I2C_STAT_SLVSTATE_SHIFT (9U)$I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)$I2C_STAT_SLVNOTSTR_MASK (0x800U)$I2C_STAT_SLVNOTSTR_SHIFT (11U)$I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)$I2C_STAT_SLVIDX_MASK (0x3000U)$I2C_STAT_SLVIDX_SHIFT (12U)%I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)%I2C_STAT_SLVSEL_MASK (0x4000U)%I2C_STAT_SLVSEL_SHIFT (14U)%I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)%I2C_STAT_SLVDESEL_MASK (0x8000U)%I2C_STAT_SLVDESEL_SHIFT (15U)%I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)%I2C_STAT_MONRDY_MASK (0x10000U)%I2C_STAT_MONRDY_SHIFT (16U)%I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)%I2C_STAT_MONOV_MASK (0x20000U)%I2C_STAT_MONOV_SHIFT (17U)%I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)%I2C_STAT_MONACTIVE_MASK (0x40000U)%I2C_STAT_MONACTIVE_SHIFT (18U)%I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)%I2C_STAT_MONIDLE_MASK (0x80000U)%I2C_STAT_MONIDLE_SHIFT (19U)%I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)%I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)%I2C_STAT_EVENTTIMEOUT_SHIFT (24U)%I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)%I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)%I2C_STAT_SCLTIMEOUT_SHIFT (25U)%I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)%I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)%I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)%I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)%I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)%I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)%I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)%I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)%I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)%I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)%I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)%I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)%I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)%I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)%I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)%I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)%I2C_INTENSET_SLVDESELEN_MASK (0x8000U)%I2C_INTENSET_SLVDESELEN_SHIFT (15U)%I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)%I2C_INTENSET_MONRDYEN_MASK (0x10000U)%I2C_INTENSET_MONRDYEN_SHIFT (16U)%I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)%I2C_INTENSET_MONOVEN_MASK (0x20000U)%I2C_INTENSET_MONOVEN_SHIFT (17U)%I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)%I2C_INTENSET_MONIDLEEN_MASK (0x80000U)%I2C_INTENSET_MONIDLEEN_SHIFT (19U)%I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)%I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)%I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)%I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)%I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)%I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)%I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)%I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)%I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)%I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)%I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)%I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)%I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)%I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)%I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)%I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)%I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)%I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)%I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)%I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)%I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)%I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)%I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)%I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)%I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)%I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)%I2C_INTENCLR_MONRDYCLR_SHIFT (16U)%I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)%I2C_INTENCLR_MONOVCLR_MASK (0x20000U)%I2C_INTENCLR_MONOVCLR_SHIFT (17U)%I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)%I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)%I2C_INTENCLR_MONIDLECLR_SHIFT (19U)%I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)%I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)%I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)%I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)%I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)%I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)%I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)%I2C_TIMEOUT_TOMIN_MASK (0xFU)%I2C_TIMEOUT_TOMIN_SHIFT (0U)%I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)%I2C_TIMEOUT_TO_MASK (0xFFF0U)%I2C_TIMEOUT_TO_SHIFT (4U)%I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)%I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)%I2C_CLKDIV_DIVVAL_SHIFT (0U)%I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)%I2C_INTSTAT_MSTPENDING_MASK (0x1U)%I2C_INTSTAT_MSTPENDING_SHIFT (0U)%I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)%I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)%I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)%I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)%I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)%I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)%I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)%I2C_INTSTAT_SLVPENDING_MASK (0x100U)%I2C_INTSTAT_SLVPENDING_SHIFT (8U)%I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)%I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)%I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)%I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)%I2C_INTSTAT_SLVDESEL_MASK (0x8000U)%I2C_INTSTAT_SLVDESEL_SHIFT (15U)%I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)&I2C_INTSTAT_MONRDY_MASK (0x10000U)&I2C_INTSTAT_MONRDY_SHIFT (16U)&I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)&I2C_INTSTAT_MONOV_MASK (0x20000U)&I2C_INTSTAT_MONOV_SHIFT (17U)&I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)&I2C_INTSTAT_MONIDLE_MASK (0x80000U)&I2C_INTSTAT_MONIDLE_SHIFT (19U)&I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)&I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)&I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)&I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)&I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)&I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)&I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)&I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)&I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)&I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)&I2C_MSTCTL_MSTSTART_MASK (0x2U)&I2C_MSTCTL_MSTSTART_SHIFT (1U)&I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)&I2C_MSTCTL_MSTSTOP_MASK (0x4U)&I2C_MSTCTL_MSTSTOP_SHIFT (2U)&I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)&I2C_MSTCTL_MSTDMA_MASK (0x8U)&I2C_MSTCTL_MSTDMA_SHIFT (3U)&I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)&I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)&I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)&I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)&I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)&I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)&I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)&I2C_MSTDAT_DATA_MASK (0xFFU)&I2C_MSTDAT_DATA_SHIFT (0U)&I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)&I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)&I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)&I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)&I2C_SLVCTL_SLVNACK_MASK (0x2U)&I2C_SLVCTL_SLVNACK_SHIFT (1U)&I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)&I2C_SLVCTL_SLVDMA_MASK (0x8U)&I2C_SLVCTL_SLVDMA_SHIFT (3U)&I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)&I2C_SLVCTL_AUTOACK_MASK (0x100U)&I2C_SLVCTL_AUTOACK_SHIFT (8U)&I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)&I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)&I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)&I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)&I2C_SLVDAT_DATA_MASK (0xFFU)&I2C_SLVDAT_DATA_SHIFT (0U)&I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)&I2C_SLVADR_SADISABLE_MASK (0x1U)&I2C_SLVADR_SADISABLE_SHIFT (0U)&I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)&I2C_SLVADR_SLVADR_MASK (0xFEU)&I2C_SLVADR_SLVADR_SHIFT (1U)&I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)&I2C_SLVADR_AUTONACK_MASK (0x8000U)&I2C_SLVADR_AUTONACK_SHIFT (15U)&I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)&I2C_SLVADR_COUNT (4U)&I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)&I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)&I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)&I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)&I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)&I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)&I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)&I2C_MONRXDAT_MONRXDAT_SHIFT (0U)&I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)&I2C_MONRXDAT_MONSTART_MASK (0x100U)&I2C_MONRXDAT_MONSTART_SHIFT (8U)&I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)&I2C_MONRXDAT_MONRESTART_MASK (0x200U)&I2C_MONRXDAT_MONRESTART_SHIFT (9U)&I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)&I2C_MONRXDAT_MONNACK_MASK (0x400U)&I2C_MONRXDAT_MONNACK_SHIFT (10U)&I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)&I2C_ID_APERTURE_MASK (0xFFU)&I2C_ID_APERTURE_SHIFT (0U)&I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)&I2C_ID_MINOR_REV_MASK (0xF00U)&I2C_ID_MINOR_REV_SHIFT (8U)&I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)&I2C_ID_MAJOR_REV_MASK (0xF000U)&I2C_ID_MAJOR_REV_SHIFT (12U)&I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)&I2C_ID_ID_MASK (0xFFFF0000U)&I2C_ID_ID_SHIFT (16U)&I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)&I2C0_BASE (0x40086000u)&I2C0 ((I2C_Type *)I2C0_BASE)&I2C1_BASE (0x40087000u)'I2C1 ((I2C_Type *)I2C1_BASE)'I2C2_BASE (0x40088000u)'I2C2 ((I2C_Type *)I2C2_BASE)'I2C3_BASE (0x40089000u)'I2C3 ((I2C_Type *)I2C3_BASE)'I2C4_BASE (0x4008A000u)'I2C4 ((I2C_Type *)I2C4_BASE)'I2C5_BASE (0x40096000u)'I2C5 ((I2C_Type *)I2C5_BASE)'I2C6_BASE (0x40097000u)'I2C6 ((I2C_Type *)I2C6_BASE)'I2C7_BASE (0x40098000u)'I2C7 ((I2C_Type *)I2C7_BASE)'I2C8_BASE (0x40099000u)'I2C8 ((I2C_Type *)I2C8_BASE)'I2C9_BASE (0x4009A000u)'I2C9 ((I2C_Type *)I2C9_BASE)'I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }'I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }'I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }'I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U)'I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U)'I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)'I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U)'I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U)'I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)'I2S_SECCHANNEL_PCFG1_COUNT (3U)'I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U)'I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U)'I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)'I2S_SECCHANNEL_PCFG2_COUNT (3U)'I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U)'I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U)'I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)'I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U)'I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U)'I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)'I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U)'I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U)(I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)(I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U)(I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U)(I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)(I2S_SECCHANNEL_PSTAT_COUNT (3U)(I2S_CFG1_MAINENABLE_MASK (0x1U)(I2S_CFG1_MAINENABLE_SHIFT (0U)(I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)(I2S_CFG1_DATAPAUSE_MASK (0x2U)(I2S_CFG1_DATAPAUSE_SHIFT (1U)(I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)(I2S_CFG1_PAIRCOUNT_MASK (0xCU)(I2S_CFG1_PAIRCOUNT_SHIFT (2U)(I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)(I2S_CFG1_MSTSLVCFG_MASK (0x30U)(I2S_CFG1_MSTSLVCFG_SHIFT (4U)(I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)(I2S_CFG1_MODE_MASK (0xC0U)(I2S_CFG1_MODE_SHIFT (6U)(I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)(I2S_CFG1_RIGHTLOW_MASK (0x100U)(I2S_CFG1_RIGHTLOW_SHIFT (8U)(I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)(I2S_CFG1_LEFTJUST_MASK (0x200U)(I2S_CFG1_LEFTJUST_SHIFT (9U)(I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)(I2S_CFG1_ONECHANNEL_MASK (0x400U)(I2S_CFG1_ONECHANNEL_SHIFT (10U)(I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)(I2S_CFG1_PDMDATA_MASK (0x800U)(I2S_CFG1_PDMDATA_SHIFT (11U)(I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)(I2S_CFG1_SCK_POL_MASK (0x1000U)(I2S_CFG1_SCK_POL_SHIFT (12U)(I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)(I2S_CFG1_WS_POL_MASK (0x2000U)(I2S_CFG1_WS_POL_SHIFT (13U)(I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)(I2S_CFG1_DATALEN_MASK (0x1F0000U)(I2S_CFG1_DATALEN_SHIFT (16U)(I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)(I2S_CFG2_FRAMELEN_MASK (0x1FFU)(I2S_CFG2_FRAMELEN_SHIFT (0U)(I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)(I2S_CFG2_POSITION_MASK (0x1FF0000U)(I2S_CFG2_POSITION_SHIFT (16U)(I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)(I2S_STAT_BUSY_MASK (0x1U)(I2S_STAT_BUSY_SHIFT (0U)(I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)(I2S_STAT_SLVFRMERR_MASK (0x2U)(I2S_STAT_SLVFRMERR_SHIFT (1U)(I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)(I2S_STAT_LR_MASK (0x4U)(I2S_STAT_LR_SHIFT (2U)(I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)(I2S_STAT_DATAPAUSED_MASK (0x8U)(I2S_STAT_DATAPAUSED_SHIFT (3U)(I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)(I2S_DIV_DIV_MASK (0xFFFU)(I2S_DIV_DIV_SHIFT (0U)(I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)(I2S_FIFOCFG_ENABLETX_MASK (0x1U)(I2S_FIFOCFG_ENABLETX_SHIFT (0U)(I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)(I2S_FIFOCFG_ENABLERX_MASK (0x2U)(I2S_FIFOCFG_ENABLERX_SHIFT (1U)(I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)(I2S_FIFOCFG_TXI2SE0_MASK (0x4U)(I2S_FIFOCFG_TXI2SE0_SHIFT (2U)(I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)(I2S_FIFOCFG_PACK48_MASK (0x8U)(I2S_FIFOCFG_PACK48_SHIFT (3U)(I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)(I2S_FIFOCFG_SIZE_MASK (0x30U)(I2S_FIFOCFG_SIZE_SHIFT (4U)(I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)(I2S_FIFOCFG_DMATX_MASK (0x1000U)(I2S_FIFOCFG_DMATX_SHIFT (12U)(I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)(I2S_FIFOCFG_DMARX_MASK (0x2000U)(I2S_FIFOCFG_DMARX_SHIFT (13U)(I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)(I2S_FIFOCFG_WAKETX_MASK (0x4000U)(I2S_FIFOCFG_WAKETX_SHIFT (14U)(I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)(I2S_FIFOCFG_WAKERX_MASK (0x8000U)(I2S_FIFOCFG_WAKERX_SHIFT (15U)(I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)(I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)(I2S_FIFOCFG_EMPTYTX_SHIFT (16U)(I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)(I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)(I2S_FIFOCFG_EMPTYRX_SHIFT (17U)(I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)(I2S_FIFOCFG_POPDBG_MASK (0x40000U)(I2S_FIFOCFG_POPDBG_SHIFT (18U)(I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)(I2S_FIFOSTAT_TXERR_MASK (0x1U)(I2S_FIFOSTAT_TXERR_SHIFT (0U)(I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)(I2S_FIFOSTAT_RXERR_MASK (0x2U)(I2S_FIFOSTAT_RXERR_SHIFT (1U)(I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)(I2S_FIFOSTAT_PERINT_MASK (0x8U)(I2S_FIFOSTAT_PERINT_SHIFT (3U)(I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)(I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)(I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)(I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)(I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)(I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)(I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)(I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U))I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U))I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK))I2S_FIFOSTAT_RXFULL_MASK (0x80U))I2S_FIFOSTAT_RXFULL_SHIFT (7U))I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK))I2S_FIFOSTAT_TXLVL_MASK (0x1F00U))I2S_FIFOSTAT_TXLVL_SHIFT (8U))I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK))I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U))I2S_FIFOSTAT_RXLVL_SHIFT (16U))I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK))I2S_FIFOTRIG_TXLVLENA_MASK (0x1U))I2S_FIFOTRIG_TXLVLENA_SHIFT (0U))I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK))I2S_FIFOTRIG_RXLVLENA_MASK (0x2U))I2S_FIFOTRIG_RXLVLENA_SHIFT (1U))I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK))I2S_FIFOTRIG_TXLVL_MASK (0xF00U))I2S_FIFOTRIG_TXLVL_SHIFT (8U))I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK))I2S_FIFOTRIG_RXLVL_MASK (0xF0000U))I2S_FIFOTRIG_RXLVL_SHIFT (16U))I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK))I2S_FIFOINTENSET_TXERR_MASK (0x1U))I2S_FIFOINTENSET_TXERR_SHIFT (0U))I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK))I2S_FIFOINTENSET_RXERR_MASK (0x2U))I2S_FIFOINTENSET_RXERR_SHIFT (1U))I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK))I2S_FIFOINTENSET_TXLVL_MASK (0x4U))I2S_FIFOINTENSET_TXLVL_SHIFT (2U))I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK))I2S_FIFOINTENSET_RXLVL_MASK (0x8U))I2S_FIFOINTENSET_RXLVL_SHIFT (3U))I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK))I2S_FIFOINTENCLR_TXERR_MASK (0x1U))I2S_FIFOINTENCLR_TXERR_SHIFT (0U))I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK))I2S_FIFOINTENCLR_RXERR_MASK (0x2U))I2S_FIFOINTENCLR_RXERR_SHIFT (1U))I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK))I2S_FIFOINTENCLR_TXLVL_MASK (0x4U))I2S_FIFOINTENCLR_TXLVL_SHIFT (2U))I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK))I2S_FIFOINTENCLR_RXLVL_MASK (0x8U))I2S_FIFOINTENCLR_RXLVL_SHIFT (3U))I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK))I2S_FIFOINTSTAT_TXERR_MASK (0x1U))I2S_FIFOINTSTAT_TXERR_SHIFT (0U))I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK))I2S_FIFOINTSTAT_RXERR_MASK (0x2U))I2S_FIFOINTSTAT_RXERR_SHIFT (1U))I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK))I2S_FIFOINTSTAT_TXLVL_MASK (0x4U))I2S_FIFOINTSTAT_TXLVL_SHIFT (2U))I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK))I2S_FIFOINTSTAT_RXLVL_MASK (0x8U))I2S_FIFOINTSTAT_RXLVL_SHIFT (3U))I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK))I2S_FIFOINTSTAT_PERINT_MASK (0x10U))I2S_FIFOINTSTAT_PERINT_SHIFT (4U))I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK))I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU))I2S_FIFOWR_TXDATA_SHIFT (0U))I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK))I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU))I2S_FIFOWR48H_TXDATA_SHIFT (0U))I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK))I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU))I2S_FIFORD_RXDATA_SHIFT (0U))I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK))I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU))I2S_FIFORD48H_RXDATA_SHIFT (0U))I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK))I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU))I2S_FIFORDNOPOP_RXDATA_SHIFT (0U))I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK))I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU))I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U))I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK))I2S_ID_Aperture_MASK (0xFFU))I2S_ID_Aperture_SHIFT (0U))I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK))I2S_ID_Minor_Rev_MASK (0xF00U))I2S_ID_Minor_Rev_SHIFT (8U))I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK))I2S_ID_Major_Rev_MASK (0xF000U))I2S_ID_Major_Rev_SHIFT (12U))I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK))I2S_ID_ID_MASK (0xFFFF0000U))I2S_ID_ID_SHIFT (16U))I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK))I2S0_BASE (0x40097000u))I2S0 ((I2S_Type *)I2S0_BASE))I2S1_BASE (0x40098000u)*I2S1 ((I2S_Type *)I2S1_BASE)*I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }*I2S_BASE_PTRS { I2S0, I2S1 }*I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }*INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)*INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)*INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)*INPUTMUX_SCT0_INMUX_COUNT (7U)*INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU)*INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)*INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)*INPUTMUX_PINTSEL_COUNT (8U)*INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)*INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)*INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)*INPUTMUX_DMA_ITRIG_INMUX_COUNT (30U)*INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU)*INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U)*INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)*INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U)*INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)*INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)*INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)*INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)*INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)*INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)*INPUTMUX_BASE (0x40005000u)*INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)*INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }*INPUTMUX_BASE_PTRS { INPUTMUX }+IOCON_PIO_FUNC_MASK (0xFU)+IOCON_PIO_FUNC_SHIFT (0U)+IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)+IOCON_PIO_MODE_MASK (0x30U)+IOCON_PIO_MODE_SHIFT (4U)+IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)+IOCON_PIO_I2CSLEW_MASK (0x40U)+IOCON_PIO_I2CSLEW_SHIFT (6U)+IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)+IOCON_PIO_INVERT_MASK (0x80U)+IOCON_PIO_INVERT_SHIFT (7U)+IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)+IOCON_PIO_DIGIMODE_MASK (0x100U)+IOCON_PIO_DIGIMODE_SHIFT (8U)+IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)+IOCON_PIO_FILTEROFF_MASK (0x200U)+IOCON_PIO_FILTEROFF_SHIFT (9U)+IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)+IOCON_PIO_I2CDRIVE_MASK (0x400U)+IOCON_PIO_I2CDRIVE_SHIFT (10U)+IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)+IOCON_PIO_SLEW_MASK (0x400U)+IOCON_PIO_SLEW_SHIFT (10U)+IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)+IOCON_PIO_OD_MASK (0x800U)+IOCON_PIO_OD_SHIFT (11U)+IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)+IOCON_PIO_I2CFILTER_MASK (0x800U)+IOCON_PIO_I2CFILTER_SHIFT (11U)+IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)+IOCON_PIO_COUNT (6U)+IOCON_PIO_COUNT2 (32U)+IOCON_BASE (0x40001000u)+IOCON ((IOCON_Type *)IOCON_BASE)+IOCON_BASE_ADDRS { IOCON_BASE }+IOCON_BASE_PTRS { IOCON }+LCD_TIMH_PPL_MASK (0xFCU)+LCD_TIMH_PPL_SHIFT (2U)+LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)+LCD_TIMH_HSW_MASK (0xFF00U)+LCD_TIMH_HSW_SHIFT (8U)+LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)+LCD_TIMH_HFP_MASK (0xFF0000U)+LCD_TIMH_HFP_SHIFT (16U)+LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)+LCD_TIMH_HBP_MASK (0xFF000000U)+LCD_TIMH_HBP_SHIFT (24U)+LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)+LCD_TIMV_LPP_MASK (0x3FFU),LCD_TIMV_LPP_SHIFT (0U),LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK),LCD_TIMV_VSW_MASK (0xFC00U),LCD_TIMV_VSW_SHIFT (10U),LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK),LCD_TIMV_VFP_MASK (0xFF0000U),LCD_TIMV_VFP_SHIFT (16U),LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK),LCD_TIMV_VBP_MASK (0xFF000000U),LCD_TIMV_VBP_SHIFT (24U),LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK),LCD_POL_PCD_LO_MASK (0x1FU),LCD_POL_PCD_LO_SHIFT (0U),LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK),LCD_POL_ACB_MASK (0x7C0U),LCD_POL_ACB_SHIFT (6U),LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK),LCD_POL_IVS_MASK (0x800U),LCD_POL_IVS_SHIFT (11U),LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK),LCD_POL_IHS_MASK (0x1000U),LCD_POL_IHS_SHIFT (12U),LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK),LCD_POL_IPC_MASK (0x2000U),LCD_POL_IPC_SHIFT (13U),LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK),LCD_POL_IOE_MASK (0x4000U),LCD_POL_IOE_SHIFT (14U),LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK),LCD_POL_CPL_MASK (0x3FF0000U),LCD_POL_CPL_SHIFT (16U),LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK),LCD_POL_BCD_MASK (0x4000000U),LCD_POL_BCD_SHIFT (26U),LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK),LCD_POL_PCD_HI_MASK (0xF8000000U),LCD_POL_PCD_HI_SHIFT (27U),LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK),LCD_LE_LED_MASK (0x7FU),LCD_LE_LED_SHIFT (0U),LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK),LCD_LE_LEE_MASK (0x10000U),LCD_LE_LEE_SHIFT (16U),LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK),LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U),LCD_UPBASE_LCDUPBASE_SHIFT (3U),LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK),LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U),LCD_LPBASE_LCDLPBASE_SHIFT (3U),LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK),LCD_CTRL_LCDEN_MASK (0x1U),LCD_CTRL_LCDEN_SHIFT (0U),LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK),LCD_CTRL_LCDBPP_MASK (0xEU),LCD_CTRL_LCDBPP_SHIFT (1U),LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK),LCD_CTRL_LCDBW_MASK (0x10U),LCD_CTRL_LCDBW_SHIFT (4U),LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK),LCD_CTRL_LCDTFT_MASK (0x20U),LCD_CTRL_LCDTFT_SHIFT (5U),LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK),LCD_CTRL_LCDMONO8_MASK (0x40U),LCD_CTRL_LCDMONO8_SHIFT (6U),LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK),LCD_CTRL_LCDDUAL_MASK (0x80U),LCD_CTRL_LCDDUAL_SHIFT (7U),LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK),LCD_CTRL_BGR_MASK (0x100U),LCD_CTRL_BGR_SHIFT (8U),LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK),LCD_CTRL_BEBO_MASK (0x200U),LCD_CTRL_BEBO_SHIFT (9U),LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK),LCD_CTRL_BEPO_MASK (0x400U),LCD_CTRL_BEPO_SHIFT (10U),LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK),LCD_CTRL_LCDPWR_MASK (0x800U),LCD_CTRL_LCDPWR_SHIFT (11U),LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK),LCD_CTRL_LCDVCOMP_MASK (0x3000U),LCD_CTRL_LCDVCOMP_SHIFT (12U),LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK),LCD_CTRL_WATERMARK_MASK (0x10000U),LCD_CTRL_WATERMARK_SHIFT (16U),LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK),LCD_INTMSK_FUFIM_MASK (0x2U),LCD_INTMSK_FUFIM_SHIFT (1U),LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK),LCD_INTMSK_LNBUIM_MASK (0x4U),LCD_INTMSK_LNBUIM_SHIFT (2U),LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK),LCD_INTMSK_VCOMPIM_MASK (0x8U),LCD_INTMSK_VCOMPIM_SHIFT (3U),LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK),LCD_INTMSK_BERIM_MASK (0x10U),LCD_INTMSK_BERIM_SHIFT (4U),LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK),LCD_INTRAW_FUFRIS_MASK (0x2U),LCD_INTRAW_FUFRIS_SHIFT (1U),LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK),LCD_INTRAW_LNBURIS_MASK (0x4U),LCD_INTRAW_LNBURIS_SHIFT (2U),LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK),LCD_INTRAW_VCOMPRIS_MASK (0x8U),LCD_INTRAW_VCOMPRIS_SHIFT (3U),LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK),LCD_INTRAW_BERRAW_MASK (0x10U),LCD_INTRAW_BERRAW_SHIFT (4U),LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK),LCD_INTSTAT_FUFMIS_MASK (0x2U),LCD_INTSTAT_FUFMIS_SHIFT (1U)-LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)-LCD_INTSTAT_LNBUMIS_MASK (0x4U)-LCD_INTSTAT_LNBUMIS_SHIFT (2U)-LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)-LCD_INTSTAT_VCOMPMIS_MASK (0x8U)-LCD_INTSTAT_VCOMPMIS_SHIFT (3U)-LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)-LCD_INTSTAT_BERMIS_MASK (0x10U)-LCD_INTSTAT_BERMIS_SHIFT (4U)-LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)-LCD_INTCLR_FUFIC_MASK (0x2U)-LCD_INTCLR_FUFIC_SHIFT (1U)-LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)-LCD_INTCLR_LNBUIC_MASK (0x4U)-LCD_INTCLR_LNBUIC_SHIFT (2U)-LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)-LCD_INTCLR_VCOMPIC_MASK (0x8U)-LCD_INTCLR_VCOMPIC_SHIFT (3U)-LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)-LCD_INTCLR_BERIC_MASK (0x10U)-LCD_INTCLR_BERIC_SHIFT (4U)-LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)-LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU)-LCD_UPCURR_LCDUPCURR_SHIFT (0U)-LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)-LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU)-LCD_LPCURR_LCDLPCURR_SHIFT (0U)-LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)-LCD_PAL_R04_0_MASK (0x1FU)-LCD_PAL_R04_0_SHIFT (0U)-LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)-LCD_PAL_G04_0_MASK (0x3E0U)-LCD_PAL_G04_0_SHIFT (5U)-LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)-LCD_PAL_B04_0_MASK (0x7C00U)-LCD_PAL_B04_0_SHIFT (10U)-LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)-LCD_PAL_I0_MASK (0x8000U)-LCD_PAL_I0_SHIFT (15U)-LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)-LCD_PAL_R14_0_MASK (0x1F0000U)-LCD_PAL_R14_0_SHIFT (16U)-LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)-LCD_PAL_G14_0_MASK (0x3E00000U)-LCD_PAL_G14_0_SHIFT (21U)-LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)-LCD_PAL_B14_0_MASK (0x7C000000U)-LCD_PAL_B14_0_SHIFT (26U)-LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)-LCD_PAL_I1_MASK (0x80000000U)-LCD_PAL_I1_SHIFT (31U)-LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)-LCD_PAL_COUNT (128U)-LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU)-LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U)-LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)-LCD_CRSR_IMG_COUNT (256U)-LCD_CRSR_CTRL_CRSRON_MASK (0x1U)-LCD_CRSR_CTRL_CRSRON_SHIFT (0U)-LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)-LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U)-LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U)-LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)-LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U)-LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U)-LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)-LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U)-LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U)-LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)-LCD_CRSR_PAL0_RED_MASK (0xFFU)-LCD_CRSR_PAL0_RED_SHIFT (0U)-LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)-LCD_CRSR_PAL0_GREEN_MASK (0xFF00U)-LCD_CRSR_PAL0_GREEN_SHIFT (8U)-LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)-LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U)-LCD_CRSR_PAL0_BLUE_SHIFT (16U)-LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)-LCD_CRSR_PAL1_RED_MASK (0xFFU)-LCD_CRSR_PAL1_RED_SHIFT (0U)-LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)-LCD_CRSR_PAL1_GREEN_MASK (0xFF00U)-LCD_CRSR_PAL1_GREEN_SHIFT (8U)-LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)-LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U)-LCD_CRSR_PAL1_BLUE_SHIFT (16U)-LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)-LCD_CRSR_XY_CRSRX_MASK (0x3FFU)-LCD_CRSR_XY_CRSRX_SHIFT (0U)-LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)-LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U)-LCD_CRSR_XY_CRSRY_SHIFT (16U)-LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)-LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU)-LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U)-LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)-LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U)-LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U)-LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)-LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U).LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U).LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK).LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U).LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U).LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK).LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U).LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U).LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK).LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U).LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U).LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK).LCD_BASE (0x40083000u).LCD ((LCD_Type *)LCD_BASE).LCD_BASE_ADDRS { LCD_BASE }.LCD_BASE_PTRS { LCD }.LCD_IRQS { LCD_IRQn }.MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU).MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U).MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK).MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U).MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U).MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK).MRT_CHANNEL_INTVAL_COUNT (4U).MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU).MRT_CHANNEL_TIMER_VALUE_SHIFT (0U).MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK).MRT_CHANNEL_TIMER_COUNT (4U).MRT_CHANNEL_CTRL_INTEN_MASK (0x1U).MRT_CHANNEL_CTRL_INTEN_SHIFT (0U).MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK).MRT_CHANNEL_CTRL_MODE_MASK (0x6U).MRT_CHANNEL_CTRL_MODE_SHIFT (1U).MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK).MRT_CHANNEL_CTRL_COUNT (4U).MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U).MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U).MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK).MRT_CHANNEL_STAT_RUN_MASK (0x2U).MRT_CHANNEL_STAT_RUN_SHIFT (1U).MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK).MRT_CHANNEL_STAT_INUSE_MASK (0x4U).MRT_CHANNEL_STAT_INUSE_SHIFT (2U).MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK).MRT_CHANNEL_STAT_COUNT (4U).MRT_MODCFG_NOC_MASK (0xFU).MRT_MODCFG_NOC_SHIFT (0U).MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK).MRT_MODCFG_NOB_MASK (0x1F0U).MRT_MODCFG_NOB_SHIFT (4U).MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK).MRT_MODCFG_MULTITASK_MASK (0x80000000U).MRT_MODCFG_MULTITASK_SHIFT (31U).MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)/MRT_IDLE_CH_CHAN_MASK (0xF0U)/MRT_IDLE_CH_CHAN_SHIFT (4U)/MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)/MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)/MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)/MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)/MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)/MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)/MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)/MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)/MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)/MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)/MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)/MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)/MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)/MRT0_BASE (0x4000D000u)/MRT0 ((MRT_Type *)MRT0_BASE)/MRT_BASE_ADDRS { MRT0_BASE }/MRT_BASE_PTRS { MRT0 }/MRT_IRQS { MRT0_IRQn }/OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU)/OTPC_AESKEY_KEY_SHIFT (0U)/OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)/OTPC_AESKEY_COUNT (8U)/OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U)/OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U)/OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)/OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U)/OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U)/OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)/OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U)/OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U)/OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)/OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U)/OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U)/OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)/OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U)/OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U)/OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)/OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U)/OTPC_ECRP_JTAG_DISABLE_SHIFT (31U)/OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)/OTPC_USER0_USER0_MASK (0xFFFFFFFFU)/OTPC_USER0_USER0_SHIFT (0U)/OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)/OTPC_USER1_USER1_MASK (0xFFFFFFFFU)/OTPC_USER1_USER1_SHIFT (0U)/OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)/OTPC_BASE (0x40015000u)/OTPC ((OTPC_Type *)OTPC_BASE)/OTPC_BASE_ADDRS { OTPC_BASE }/OTPC_BASE_PTRS { OTPC }0PINT_ISEL_PMODE_MASK (0xFFU)0PINT_ISEL_PMODE_SHIFT (0U)0PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)0PINT_IENR_ENRL_MASK (0xFFU)0PINT_IENR_ENRL_SHIFT (0U)0PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)0PINT_SIENR_SETENRL_MASK (0xFFU)0PINT_SIENR_SETENRL_SHIFT (0U)0PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)0PINT_CIENR_CENRL_MASK (0xFFU)0PINT_CIENR_CENRL_SHIFT (0U)0PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)0PINT_IENF_ENAF_MASK (0xFFU)0PINT_IENF_ENAF_SHIFT (0U)0PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)0PINT_SIENF_SETENAF_MASK (0xFFU)0PINT_SIENF_SETENAF_SHIFT (0U)0PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)0PINT_CIENF_CENAF_MASK (0xFFU)0PINT_CIENF_CENAF_SHIFT (0U)0PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)0PINT_RISE_RDET_MASK (0xFFU)0PINT_RISE_RDET_SHIFT (0U)0PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)0PINT_FALL_FDET_MASK (0xFFU)0PINT_FALL_FDET_SHIFT (0U)0PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)0PINT_IST_PSTAT_MASK (0xFFU)0PINT_IST_PSTAT_SHIFT (0U)0PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)0PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)0PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)0PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)0PINT_PMCTRL_ENA_RXEV_MASK (0x2U)0PINT_PMCTRL_ENA_RXEV_SHIFT (1U)0PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)0PINT_PMCTRL_PMAT_MASK (0xFF000000U)0PINT_PMCTRL_PMAT_SHIFT (24U)0PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)0PINT_PMSRC_SRC0_MASK (0x700U)0PINT_PMSRC_SRC0_SHIFT (8U)0PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)0PINT_PMSRC_SRC1_MASK (0x3800U)0PINT_PMSRC_SRC1_SHIFT (11U)0PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)0PINT_PMSRC_SRC2_MASK (0x1C000U)0PINT_PMSRC_SRC2_SHIFT (14U)0PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)0PINT_PMSRC_SRC3_MASK (0xE0000U)0PINT_PMSRC_SRC3_SHIFT (17U)0PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)0PINT_PMSRC_SRC4_MASK (0x700000U)0PINT_PMSRC_SRC4_SHIFT (20U)0PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)0PINT_PMSRC_SRC5_MASK (0x3800000U)0PINT_PMSRC_SRC5_SHIFT (23U)0PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)0PINT_PMSRC_SRC6_MASK (0x1C000000U)0PINT_PMSRC_SRC6_SHIFT (26U)0PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)0PINT_PMSRC_SRC7_MASK (0xE0000000U)0PINT_PMSRC_SRC7_SHIFT (29U)0PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)0PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)0PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)0PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)0PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)1PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)1PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)1PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)1PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)1PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)1PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)1PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)1PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)1PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)1PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)1PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)1PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)1PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)1PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)1PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)1PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)1PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)1PINT_PMCFG_CFG0_MASK (0x700U)1PINT_PMCFG_CFG0_SHIFT (8U)1PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)1PINT_PMCFG_CFG1_MASK (0x3800U)1PINT_PMCFG_CFG1_SHIFT (11U)1PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)1PINT_PMCFG_CFG2_MASK (0x1C000U)1PINT_PMCFG_CFG2_SHIFT (14U)1PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)1PINT_PMCFG_CFG3_MASK (0xE0000U)1PINT_PMCFG_CFG3_SHIFT (17U)1PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)1PINT_PMCFG_CFG4_MASK (0x700000U)1PINT_PMCFG_CFG4_SHIFT (20U)1PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)1PINT_PMCFG_CFG5_MASK (0x3800000U)1PINT_PMCFG_CFG5_SHIFT (23U)1PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)1PINT_PMCFG_CFG6_MASK (0x1C000000U)1PINT_PMCFG_CFG6_SHIFT (26U)1PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)1PINT_PMCFG_CFG7_MASK (0xE0000000U)1PINT_PMCFG_CFG7_SHIFT (29U)1PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)1PINT_BASE (0x40004000u)1PINT ((PINT_Type *)PINT_BASE)1PINT_BASE_ADDRS { PINT_BASE }1PINT_BASE_PTRS { PINT }1PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }1RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU)1RIT_COMPVAL_RICOMP_SHIFT (0U)1RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)1RIT_MASK_RIMASK_MASK (0xFFFFFFFFU)1RIT_MASK_RIMASK_SHIFT (0U)1RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)1RIT_CTRL_RITINT_MASK (0x1U)1RIT_CTRL_RITINT_SHIFT (0U)1RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)1RIT_CTRL_RITENCLR_MASK (0x2U)1RIT_CTRL_RITENCLR_SHIFT (1U)1RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)1RIT_CTRL_RITENBR_MASK (0x4U)1RIT_CTRL_RITENBR_SHIFT (2U)1RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)1RIT_CTRL_RITEN_MASK (0x8U)1RIT_CTRL_RITEN_SHIFT (3U)1RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)1RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU)1RIT_COUNTER_RICOUNTER_SHIFT (0U)1RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)1RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU)1RIT_COMPVAL_H_RICOMP_SHIFT (0U)1RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)2RIT_MASK_H_RIMASK_MASK (0xFFFFU)2RIT_MASK_H_RIMASK_SHIFT (0U)2RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)2RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU)2RIT_COUNTER_H_RICOUNTER_SHIFT (0U)2RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)2RIT_BASE (0x4002D000u)2RIT ((RIT_Type *)RIT_BASE)2RIT_BASE_ADDRS { RIT_BASE }2RIT_BASE_PTRS { RIT }2RIT_IRQS { RIT_IRQn }2RTC_CTRL_SWRESET_MASK (0x1U)2RTC_CTRL_SWRESET_SHIFT (0U)2RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)2RTC_CTRL_ALARM1HZ_MASK (0x4U)2RTC_CTRL_ALARM1HZ_SHIFT (2U)2RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)2RTC_CTRL_WAKE1KHZ_MASK (0x8U)2RTC_CTRL_WAKE1KHZ_SHIFT (3U)2RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)2RTC_CTRL_ALARMDPD_EN_MASK (0x10U)2RTC_CTRL_ALARMDPD_EN_SHIFT (4U)2RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)2RTC_CTRL_WAKEDPD_EN_MASK (0x20U)2RTC_CTRL_WAKEDPD_EN_SHIFT (5U)2RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)2RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)2RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)2RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)2RTC_CTRL_RTC_EN_MASK (0x80U)2RTC_CTRL_RTC_EN_SHIFT (7U)2RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)2RTC_CTRL_RTC_OSC_PD_MASK (0x100U)2RTC_CTRL_RTC_OSC_PD_SHIFT (8U)2RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)2RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)2RTC_MATCH_MATVAL_SHIFT (0U)2RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)2RTC_COUNT_VAL_MASK (0xFFFFFFFFU)2RTC_COUNT_VAL_SHIFT (0U)2RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)2RTC_WAKE_VAL_MASK (0xFFFFU)2RTC_WAKE_VAL_SHIFT (0U)2RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)2RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)2RTC_GPREG_GPDATA_SHIFT (0U)2RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)2RTC_GPREG_COUNT (8U)2RTC_BASE (0x4002C000u)2RTC ((RTC_Type *)RTC_BASE)2RTC_BASE_ADDRS { RTC_BASE }2RTC_BASE_PTRS { RTC }2RTC_IRQS { RTC_IRQn }3SCT_CONFIG_UNIFY_MASK (0x1U)3SCT_CONFIG_UNIFY_SHIFT (0U)3SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)3SCT_CONFIG_CLKMODE_MASK (0x6U)3SCT_CONFIG_CLKMODE_SHIFT (1U)3SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)3SCT_CONFIG_CKSEL_MASK (0x78U)3SCT_CONFIG_CKSEL_SHIFT (3U)3SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)3SCT_CONFIG_NORELAOD_L_MASK (0x80U)3SCT_CONFIG_NORELAOD_L_SHIFT (7U)3SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)3SCT_CONFIG_NORELOAD_H_MASK (0x100U)3SCT_CONFIG_NORELOAD_H_SHIFT (8U)3SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)3SCT_CONFIG_INSYNC_MASK (0x1E00U)3SCT_CONFIG_INSYNC_SHIFT (9U)3SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)3SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)3SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)3SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)3SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)3SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)3SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)3SCT_CTRL_DOWN_L_MASK (0x1U)3SCT_CTRL_DOWN_L_SHIFT (0U)3SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)3SCT_CTRL_STOP_L_MASK (0x2U)3SCT_CTRL_STOP_L_SHIFT (1U)3SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)3SCT_CTRL_HALT_L_MASK (0x4U)3SCT_CTRL_HALT_L_SHIFT (2U)3SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)3SCT_CTRL_CLRCTR_L_MASK (0x8U)3SCT_CTRL_CLRCTR_L_SHIFT (3U)3SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)3SCT_CTRL_BIDIR_L_MASK (0x10U)3SCT_CTRL_BIDIR_L_SHIFT (4U)3SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)3SCT_CTRL_PRE_L_MASK (0x1FE0U)3SCT_CTRL_PRE_L_SHIFT (5U)3SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)3SCT_CTRL_DOWN_H_MASK (0x10000U)3SCT_CTRL_DOWN_H_SHIFT (16U)3SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)3SCT_CTRL_STOP_H_MASK (0x20000U)3SCT_CTRL_STOP_H_SHIFT (17U)3SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)3SCT_CTRL_HALT_H_MASK (0x40000U)3SCT_CTRL_HALT_H_SHIFT (18U)3SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)3SCT_CTRL_CLRCTR_H_MASK (0x80000U)3SCT_CTRL_CLRCTR_H_SHIFT (19U)3SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)3SCT_CTRL_BIDIR_H_MASK (0x100000U)3SCT_CTRL_BIDIR_H_SHIFT (20U)3SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)4SCT_CTRL_PRE_H_MASK (0x1FE00000U)4SCT_CTRL_PRE_H_SHIFT (21U)4SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)4SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)4SCT_LIMIT_LIMMSK_L_SHIFT (0U)4SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)4SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)4SCT_LIMIT_LIMMSK_H_SHIFT (16U)4SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)4SCT_HALT_HALTMSK_L_MASK (0xFFFFU)4SCT_HALT_HALTMSK_L_SHIFT (0U)4SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)4SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)4SCT_HALT_HALTMSK_H_SHIFT (16U)4SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)4SCT_STOP_STOPMSK_L_MASK (0xFFFFU)4SCT_STOP_STOPMSK_L_SHIFT (0U)4SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)4SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)4SCT_STOP_STOPMSK_H_SHIFT (16U)4SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)4SCT_START_STARTMSK_L_MASK (0xFFFFU)4SCT_START_STARTMSK_L_SHIFT (0U)4SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)4SCT_START_STARTMSK_H_MASK (0xFFFF0000U)4SCT_START_STARTMSK_H_SHIFT (16U)4SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)4SCT_COUNT_CTR_L_MASK (0xFFFFU)4SCT_COUNT_CTR_L_SHIFT (0U)4SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)4SCT_COUNT_CTR_H_MASK (0xFFFF0000U)4SCT_COUNT_CTR_H_SHIFT (16U)4SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)4SCT_STATE_STATE_L_MASK (0x1FU)4SCT_STATE_STATE_L_SHIFT (0U)4SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)4SCT_STATE_STATE_H_MASK (0x1F0000U)4SCT_STATE_STATE_H_SHIFT (16U)4SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)4SCT_INPUT_AIN0_MASK (0x1U)4SCT_INPUT_AIN0_SHIFT (0U)4SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)4SCT_INPUT_AIN1_MASK (0x2U)4SCT_INPUT_AIN1_SHIFT (1U)4SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)4SCT_INPUT_AIN2_MASK (0x4U)4SCT_INPUT_AIN2_SHIFT (2U)4SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)4SCT_INPUT_AIN3_MASK (0x8U)4SCT_INPUT_AIN3_SHIFT (3U)4SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)4SCT_INPUT_AIN4_MASK (0x10U)4SCT_INPUT_AIN4_SHIFT (4U)4SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)4SCT_INPUT_AIN5_MASK (0x20U)4SCT_INPUT_AIN5_SHIFT (5U)4SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)4SCT_INPUT_AIN6_MASK (0x40U)4SCT_INPUT_AIN6_SHIFT (6U)4SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)4SCT_INPUT_AIN7_MASK (0x80U)4SCT_INPUT_AIN7_SHIFT (7U)4SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)4SCT_INPUT_AIN8_MASK (0x100U)4SCT_INPUT_AIN8_SHIFT (8U)4SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)4SCT_INPUT_AIN9_MASK (0x200U)4SCT_INPUT_AIN9_SHIFT (9U)4SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)4SCT_INPUT_AIN10_MASK (0x400U)4SCT_INPUT_AIN10_SHIFT (10U)4SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)4SCT_INPUT_AIN11_MASK (0x800U)4SCT_INPUT_AIN11_SHIFT (11U)4SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)4SCT_INPUT_AIN12_MASK (0x1000U)4SCT_INPUT_AIN12_SHIFT (12U)4SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)4SCT_INPUT_AIN13_MASK (0x2000U)4SCT_INPUT_AIN13_SHIFT (13U)4SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)4SCT_INPUT_AIN14_MASK (0x4000U)4SCT_INPUT_AIN14_SHIFT (14U)4SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)4SCT_INPUT_AIN15_MASK (0x8000U)4SCT_INPUT_AIN15_SHIFT (15U)4SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)4SCT_INPUT_SIN0_MASK (0x10000U)4SCT_INPUT_SIN0_SHIFT (16U)4SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)4SCT_INPUT_SIN1_MASK (0x20000U)4SCT_INPUT_SIN1_SHIFT (17U)4SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)4SCT_INPUT_SIN2_MASK (0x40000U)4SCT_INPUT_SIN2_SHIFT (18U)4SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)4SCT_INPUT_SIN3_MASK (0x80000U)4SCT_INPUT_SIN3_SHIFT (19U)4SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)4SCT_INPUT_SIN4_MASK (0x100000U)4SCT_INPUT_SIN4_SHIFT (20U)4SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)4SCT_INPUT_SIN5_MASK (0x200000U)4SCT_INPUT_SIN5_SHIFT (21U)4SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)4SCT_INPUT_SIN6_MASK (0x400000U)4SCT_INPUT_SIN6_SHIFT (22U)4SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)4SCT_INPUT_SIN7_MASK (0x800000U)4SCT_INPUT_SIN7_SHIFT (23U)4SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)4SCT_INPUT_SIN8_MASK (0x1000000U)4SCT_INPUT_SIN8_SHIFT (24U)4SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)5SCT_INPUT_SIN9_MASK (0x2000000U)5SCT_INPUT_SIN9_SHIFT (25U)5SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)5SCT_INPUT_SIN10_MASK (0x4000000U)5SCT_INPUT_SIN10_SHIFT (26U)5SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)5SCT_INPUT_SIN11_MASK (0x8000000U)5SCT_INPUT_SIN11_SHIFT (27U)5SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)5SCT_INPUT_SIN12_MASK (0x10000000U)5SCT_INPUT_SIN12_SHIFT (28U)5SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)5SCT_INPUT_SIN13_MASK (0x20000000U)5SCT_INPUT_SIN13_SHIFT (29U)5SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)5SCT_INPUT_SIN14_MASK (0x40000000U)5SCT_INPUT_SIN14_SHIFT (30U)5SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)5SCT_INPUT_SIN15_MASK (0x80000000U)5SCT_INPUT_SIN15_SHIFT (31U)5SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)5SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)5SCT_REGMODE_REGMOD_L_SHIFT (0U)5SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)5SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)5SCT_REGMODE_REGMOD_H_SHIFT (16U)5SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)5SCT_OUTPUT_OUT_MASK (0xFFFFU)5SCT_OUTPUT_OUT_SHIFT (0U)5SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)5SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)5SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)5SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)5SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)5SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)5SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)5SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)5SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)5SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)5SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)5SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)5SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)5SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)5SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)5SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)5SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)5SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)5SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)5SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)5SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)5SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)5SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)5SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)5SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)5SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)5SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)5SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)5SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)5SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)5SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)5SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)5SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)5SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)5SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)5SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)5SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)5SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)5SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)5SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)5SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)5SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)5SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)5SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)5SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)5SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)5SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)5SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)5SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)5SCT_RES_O0RES_MASK (0x3U)5SCT_RES_O0RES_SHIFT (0U)5SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)5SCT_RES_O1RES_MASK (0xCU)5SCT_RES_O1RES_SHIFT (2U)5SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)5SCT_RES_O2RES_MASK (0x30U)5SCT_RES_O2RES_SHIFT (4U)5SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)5SCT_RES_O3RES_MASK (0xC0U)5SCT_RES_O3RES_SHIFT (6U)5SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)5SCT_RES_O4RES_MASK (0x300U)5SCT_RES_O4RES_SHIFT (8U)5SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)5SCT_RES_O5RES_MASK (0xC00U)5SCT_RES_O5RES_SHIFT (10U)5SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)5SCT_RES_O6RES_MASK (0x3000U)5SCT_RES_O6RES_SHIFT (12U)5SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)5SCT_RES_O7RES_MASK (0xC000U)5SCT_RES_O7RES_SHIFT (14U)5SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)5SCT_RES_O8RES_MASK (0x30000U)5SCT_RES_O8RES_SHIFT (16U)5SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)5SCT_RES_O9RES_MASK (0xC0000U)5SCT_RES_O9RES_SHIFT (18U)5SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)5SCT_RES_O10RES_MASK (0x300000U)5SCT_RES_O10RES_SHIFT (20U)5SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)5SCT_RES_O11RES_MASK (0xC00000U)5SCT_RES_O11RES_SHIFT (22U)5SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)5SCT_RES_O12RES_MASK (0x3000000U)5SCT_RES_O12RES_SHIFT (24U)5SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)5SCT_RES_O13RES_MASK (0xC000000U)5SCT_RES_O13RES_SHIFT (26U)5SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)6SCT_RES_O14RES_MASK (0x30000000U)6SCT_RES_O14RES_SHIFT (28U)6SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)6SCT_RES_O15RES_MASK (0xC0000000U)6SCT_RES_O15RES_SHIFT (30U)6SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)6SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU)6SCT_DMA0REQUEST_DEV_0_SHIFT (0U)6SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)6SCT_DMA0REQUEST_DRL0_MASK (0x40000000U)6SCT_DMA0REQUEST_DRL0_SHIFT (30U)6SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)6SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U)6SCT_DMA0REQUEST_DRQ0_SHIFT (31U)6SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)6SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU)6SCT_DMA1REQUEST_DEV_1_SHIFT (0U)6SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)6SCT_DMA1REQUEST_DRL1_MASK (0x40000000U)6SCT_DMA1REQUEST_DRL1_SHIFT (30U)6SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)6SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U)6SCT_DMA1REQUEST_DRQ1_SHIFT (31U)6SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)6SCT_EVEN_IEN_MASK (0xFFFFU)6SCT_EVEN_IEN_SHIFT (0U)6SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)6SCT_EVFLAG_FLAG_MASK (0xFFFFU)6SCT_EVFLAG_FLAG_SHIFT (0U)6SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)6SCT_CONEN_NCEN_MASK (0xFFFFU)6SCT_CONEN_NCEN_SHIFT (0U)6SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)6SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)6SCT_CONFLAG_NCFLAG_SHIFT (0U)6SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)6SCT_CONFLAG_BUSERRL_MASK (0x40000000U)6SCT_CONFLAG_BUSERRL_SHIFT (30U)6SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)6SCT_CONFLAG_BUSERRH_MASK (0x80000000U)6SCT_CONFLAG_BUSERRH_SHIFT (31U)6SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)6SCT_SCTCAP_CAPn_L_MASK (0xFFFFU)6SCT_SCTCAP_CAPn_L_SHIFT (0U)6SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)6SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U)6SCT_SCTCAP_CAPn_H_SHIFT (16U)6SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)6SCT_SCTCAP_COUNT (10U)6SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU)6SCT_SCTMATCH_MATCHn_L_SHIFT (0U)6SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)6SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U)6SCT_SCTMATCH_MATCHn_H_SHIFT (16U)6SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)6SCT_SCTMATCH_COUNT (10U)6SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU)6SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U)6SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)6SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)6SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U)6SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)6SCT_SCTCAPCTRL_COUNT (10U)6SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU)6SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U)6SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)6SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U)6SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U)6SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)6SCT_SCTMATCHREL_COUNT (10U)6SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU)6SCT_EVENT_STATE_STATEMSKn_SHIFT (0U)6SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)6SCT_EVENT_STATE_COUNT (10U)6SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU)6SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U)6SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)6SCT_EVENT_CTRL_HEVENT_MASK (0x10U)6SCT_EVENT_CTRL_HEVENT_SHIFT (4U)6SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)6SCT_EVENT_CTRL_OUTSEL_MASK (0x20U)6SCT_EVENT_CTRL_OUTSEL_SHIFT (5U)6SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)6SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U)6SCT_EVENT_CTRL_IOSEL_SHIFT (6U)6SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)6SCT_EVENT_CTRL_IOCOND_MASK (0xC00U)6SCT_EVENT_CTRL_IOCOND_SHIFT (10U)6SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)6SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U)6SCT_EVENT_CTRL_COMBMODE_SHIFT (12U)6SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)6SCT_EVENT_CTRL_STATELD_MASK (0x4000U)6SCT_EVENT_CTRL_STATELD_SHIFT (14U)7SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)7SCT_EVENT_CTRL_STATEV_MASK (0xF8000U)7SCT_EVENT_CTRL_STATEV_SHIFT (15U)7SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)7SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U)7SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U)7SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)7SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U)7SCT_EVENT_CTRL_DIRECTION_SHIFT (21U)7SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)7SCT_EVENT_CTRL_COUNT (10U)7SCT_OUT_SET_SET_MASK (0xFFFFU)7SCT_OUT_SET_SET_SHIFT (0U)7SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)7SCT_OUT_SET_COUNT (10U)7SCT_OUT_CLR_CLR_MASK (0xFFFFU)7SCT_OUT_CLR_CLR_SHIFT (0U)7SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)7SCT_OUT_CLR_COUNT (10U)7SCT0_BASE (0x40085000u)7SCT0 ((SCT_Type *)SCT0_BASE)7SCT_BASE_ADDRS { SCT0_BASE }7SCT_BASE_PTRS { SCT0 }7SCT_IRQS { SCT0_IRQn }7SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)7SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)7SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)7SDIF_CTRL_FIFO_RESET_MASK (0x2U)7SDIF_CTRL_FIFO_RESET_SHIFT (1U)7SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)7SDIF_CTRL_DMA_RESET_MASK (0x4U)7SDIF_CTRL_DMA_RESET_SHIFT (2U)7SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)7SDIF_CTRL_INT_ENABLE_MASK (0x10U)7SDIF_CTRL_INT_ENABLE_SHIFT (4U)7SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)7SDIF_CTRL_READ_WAIT_MASK (0x40U)7SDIF_CTRL_READ_WAIT_SHIFT (6U)8SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)8SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)8SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)8SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)8SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)8SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)8SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)8SDIF_CTRL_SEND_CCSD_MASK (0x200U)8SDIF_CTRL_SEND_CCSD_SHIFT (9U)8SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)8SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)8SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)8SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)8SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)8SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)8SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)8SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)8SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)8SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)8SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)8SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)8SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)8SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)8SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)8SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)8SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)8SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)8SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)8SDIF_PWREN_POWER_ENABLE_MASK (0x1U)8SDIF_PWREN_POWER_ENABLE_SHIFT (0U)8SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)8SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)8SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)8SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)8SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U)8SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U)8SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)8SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U)8SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U)8SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)8SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)8SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)8SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)8SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)8SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)8SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)8SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U)8SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U)8SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)8SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U)8SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U)8SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)8SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)8SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)8SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)8SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)8SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)8SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)8SDIF_INTMASK_CDET_MASK (0x1U)8SDIF_INTMASK_CDET_SHIFT (0U)8SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)8SDIF_INTMASK_RE_MASK (0x2U)8SDIF_INTMASK_RE_SHIFT (1U)8SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)8SDIF_INTMASK_CDONE_MASK (0x4U)8SDIF_INTMASK_CDONE_SHIFT (2U)8SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)8SDIF_INTMASK_DTO_MASK (0x8U)8SDIF_INTMASK_DTO_SHIFT (3U)8SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)8SDIF_INTMASK_TXDR_MASK (0x10U)8SDIF_INTMASK_TXDR_SHIFT (4U)8SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)8SDIF_INTMASK_RXDR_MASK (0x20U)8SDIF_INTMASK_RXDR_SHIFT (5U)8SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)8SDIF_INTMASK_RCRC_MASK (0x40U)8SDIF_INTMASK_RCRC_SHIFT (6U)8SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)8SDIF_INTMASK_DCRC_MASK (0x80U)8SDIF_INTMASK_DCRC_SHIFT (7U)8SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)8SDIF_INTMASK_RTO_MASK (0x100U)8SDIF_INTMASK_RTO_SHIFT (8U)8SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)8SDIF_INTMASK_DRTO_MASK (0x200U)8SDIF_INTMASK_DRTO_SHIFT (9U)8SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)8SDIF_INTMASK_HTO_MASK (0x400U)8SDIF_INTMASK_HTO_SHIFT (10U)8SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)8SDIF_INTMASK_FRUN_MASK (0x800U)8SDIF_INTMASK_FRUN_SHIFT (11U)8SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)8SDIF_INTMASK_HLE_MASK (0x1000U)8SDIF_INTMASK_HLE_SHIFT (12U)8SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)8SDIF_INTMASK_SBE_MASK (0x2000U)8SDIF_INTMASK_SBE_SHIFT (13U)8SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)8SDIF_INTMASK_ACD_MASK (0x4000U)8SDIF_INTMASK_ACD_SHIFT (14U)8SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)8SDIF_INTMASK_EBE_MASK (0x8000U)8SDIF_INTMASK_EBE_SHIFT (15U)8SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)8SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)8SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)8SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)8SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)9SDIF_CMDARG_CMD_ARG_SHIFT (0U)9SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)9SDIF_CMD_CMD_INDEX_MASK (0x3FU)9SDIF_CMD_CMD_INDEX_SHIFT (0U)9SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)9SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)9SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)9SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)9SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)9SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)9SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)9SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)9SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)9SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)9SDIF_CMD_DATA_EXPECTED_MASK (0x200U)9SDIF_CMD_DATA_EXPECTED_SHIFT (9U)9SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)9SDIF_CMD_READ_WRITE_MASK (0x400U)9SDIF_CMD_READ_WRITE_SHIFT (10U)9SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)9SDIF_CMD_TRANSFER_MODE_MASK (0x800U)9SDIF_CMD_TRANSFER_MODE_SHIFT (11U)9SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)9SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)9SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)9SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)9SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)9SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)9SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)9SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)9SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)9SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)9SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)9SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)9SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)9SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)9SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)9SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)9SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)9SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)9SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)9SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)9SDIF_CMD_CCS_EXPECTED_SHIFT (23U)9SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)9SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)9SDIF_CMD_ENABLE_BOOT_SHIFT (24U)9SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)9SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)9SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)9SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)9SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)9SDIF_CMD_DISABLE_BOOT_SHIFT (26U)9SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)9SDIF_CMD_BOOT_MODE_MASK (0x8000000U)9SDIF_CMD_BOOT_MODE_SHIFT (27U)9SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)9SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)9SDIF_CMD_VOLT_SWITCH_SHIFT (28U)9SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)9SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)9SDIF_CMD_USE_HOLD_REG_SHIFT (29U)9SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)9SDIF_CMD_START_CMD_MASK (0x80000000U)9SDIF_CMD_START_CMD_SHIFT (31U)9SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)9SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)9SDIF_RESP_RESPONSE_SHIFT (0U)9SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)9SDIF_RESP_COUNT (4U)9SDIF_MINTSTS_CDET_MASK (0x1U)9SDIF_MINTSTS_CDET_SHIFT (0U)9SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)9SDIF_MINTSTS_RE_MASK (0x2U)9SDIF_MINTSTS_RE_SHIFT (1U)9SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)9SDIF_MINTSTS_CDONE_MASK (0x4U)9SDIF_MINTSTS_CDONE_SHIFT (2U)9SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)9SDIF_MINTSTS_DTO_MASK (0x8U)9SDIF_MINTSTS_DTO_SHIFT (3U)9SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)9SDIF_MINTSTS_TXDR_MASK (0x10U)9SDIF_MINTSTS_TXDR_SHIFT (4U)9SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)9SDIF_MINTSTS_RXDR_MASK (0x20U)9SDIF_MINTSTS_RXDR_SHIFT (5U)9SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)9SDIF_MINTSTS_RCRC_MASK (0x40U)9SDIF_MINTSTS_RCRC_SHIFT (6U)9SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)9SDIF_MINTSTS_DCRC_MASK (0x80U)9SDIF_MINTSTS_DCRC_SHIFT (7U)9SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)9SDIF_MINTSTS_RTO_MASK (0x100U)9SDIF_MINTSTS_RTO_SHIFT (8U)9SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)9SDIF_MINTSTS_DRTO_MASK (0x200U)9SDIF_MINTSTS_DRTO_SHIFT (9U)9SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)9SDIF_MINTSTS_HTO_MASK (0x400U)9SDIF_MINTSTS_HTO_SHIFT (10U)9SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)9SDIF_MINTSTS_FRUN_MASK (0x800U)9SDIF_MINTSTS_FRUN_SHIFT (11U)9SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)9SDIF_MINTSTS_HLE_MASK (0x1000U)9SDIF_MINTSTS_HLE_SHIFT (12U)9SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)9SDIF_MINTSTS_SBE_MASK (0x2000U)9SDIF_MINTSTS_SBE_SHIFT (13U)9SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)9SDIF_MINTSTS_ACD_MASK (0x4000U)9SDIF_MINTSTS_ACD_SHIFT (14U)9SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)9SDIF_MINTSTS_EBE_MASK (0x8000U)9SDIF_MINTSTS_EBE_SHIFT (15U)9SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)9SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)9SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)9SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK):SDIF_RINTSTS_CDET_MASK (0x1U):SDIF_RINTSTS_CDET_SHIFT (0U):SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK):SDIF_RINTSTS_RE_MASK (0x2U):SDIF_RINTSTS_RE_SHIFT (1U):SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK):SDIF_RINTSTS_CDONE_MASK (0x4U):SDIF_RINTSTS_CDONE_SHIFT (2U):SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK):SDIF_RINTSTS_DTO_MASK (0x8U):SDIF_RINTSTS_DTO_SHIFT (3U):SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK):SDIF_RINTSTS_TXDR_MASK (0x10U):SDIF_RINTSTS_TXDR_SHIFT (4U):SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK):SDIF_RINTSTS_RXDR_MASK (0x20U):SDIF_RINTSTS_RXDR_SHIFT (5U):SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK):SDIF_RINTSTS_RCRC_MASK (0x40U):SDIF_RINTSTS_RCRC_SHIFT (6U):SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK):SDIF_RINTSTS_DCRC_MASK (0x80U):SDIF_RINTSTS_DCRC_SHIFT (7U):SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK):SDIF_RINTSTS_RTO_BAR_MASK (0x100U):SDIF_RINTSTS_RTO_BAR_SHIFT (8U):SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK):SDIF_RINTSTS_DRTO_BDS_MASK (0x200U):SDIF_RINTSTS_DRTO_BDS_SHIFT (9U):SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK):SDIF_RINTSTS_HTO_MASK (0x400U):SDIF_RINTSTS_HTO_SHIFT (10U):SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK):SDIF_RINTSTS_FRUN_MASK (0x800U):SDIF_RINTSTS_FRUN_SHIFT (11U):SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK):SDIF_RINTSTS_HLE_MASK (0x1000U):SDIF_RINTSTS_HLE_SHIFT (12U):SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK):SDIF_RINTSTS_SBE_MASK (0x2000U):SDIF_RINTSTS_SBE_SHIFT (13U):SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK):SDIF_RINTSTS_ACD_MASK (0x4000U):SDIF_RINTSTS_ACD_SHIFT (14U):SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK):SDIF_RINTSTS_EBE_MASK (0x8000U):SDIF_RINTSTS_EBE_SHIFT (15U):SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK):SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U):SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U):SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK):SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U):SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U):SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK):SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U):SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U):SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK):SDIF_STATUS_FIFO_EMPTY_MASK (0x4U):SDIF_STATUS_FIFO_EMPTY_SHIFT (2U):SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK):SDIF_STATUS_FIFO_FULL_MASK (0x8U):SDIF_STATUS_FIFO_FULL_SHIFT (3U):SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK):SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U):SDIF_STATUS_CMDFSMSTATES_SHIFT (4U):SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK):SDIF_STATUS_DATA_3_STATUS_MASK (0x100U):SDIF_STATUS_DATA_3_STATUS_SHIFT (8U):SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK):SDIF_STATUS_DATA_BUSY_MASK (0x200U):SDIF_STATUS_DATA_BUSY_SHIFT (9U):SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK):SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U):SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U):SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK):SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U):SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U):SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK):SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U):SDIF_STATUS_FIFO_COUNT_SHIFT (17U):SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK):SDIF_STATUS_DMA_ACK_MASK (0x40000000U):SDIF_STATUS_DMA_ACK_SHIFT (30U):SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK):SDIF_STATUS_DMA_REQ_MASK (0x80000000U):SDIF_STATUS_DMA_REQ_SHIFT (31U):SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK):SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU):SDIF_FIFOTH_TX_WMARK_SHIFT (0U):SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK):SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U):SDIF_FIFOTH_RX_WMARK_SHIFT (16U):SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK):SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U):SDIF_FIFOTH_DMA_MTS_SHIFT (28U):SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK):SDIF_CDETECT_CARD_DETECT_MASK (0x1U):SDIF_CDETECT_CARD_DETECT_SHIFT (0U):SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK):SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U):SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U):SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK):SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU):SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U):SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK):SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU):SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U):SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK):SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU):SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U):SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK);SDIF_RST_N_CARD_RESET_MASK (0x1U);SDIF_RST_N_CARD_RESET_SHIFT (0U);SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK);SDIF_BMOD_SWR_MASK (0x1U);SDIF_BMOD_SWR_SHIFT (0U);SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK);SDIF_BMOD_FB_MASK (0x2U);SDIF_BMOD_FB_SHIFT (1U);SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK);SDIF_BMOD_DSL_MASK (0x7CU);SDIF_BMOD_DSL_SHIFT (2U);SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK);SDIF_BMOD_DE_MASK (0x80U);SDIF_BMOD_DE_SHIFT (7U);SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK);SDIF_BMOD_PBL_MASK (0x700U);SDIF_BMOD_PBL_SHIFT (8U);SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK);SDIF_PLDMND_PD_MASK (0xFFFFFFFFU);SDIF_PLDMND_PD_SHIFT (0U);SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK);SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU);SDIF_DBADDR_SDL_SHIFT (0U);SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK);SDIF_IDSTS_TI_MASK (0x1U);SDIF_IDSTS_TI_SHIFT (0U);SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK);SDIF_IDSTS_RI_MASK (0x2U);SDIF_IDSTS_RI_SHIFT (1U);SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK);SDIF_IDSTS_FBE_MASK (0x4U);SDIF_IDSTS_FBE_SHIFT (2U);SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK);SDIF_IDSTS_DU_MASK (0x10U);SDIF_IDSTS_DU_SHIFT (4U);SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK);SDIF_IDSTS_CES_MASK (0x20U);SDIF_IDSTS_CES_SHIFT (5U);SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK);SDIF_IDSTS_NIS_MASK (0x100U);SDIF_IDSTS_NIS_SHIFT (8U);SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK);SDIF_IDSTS_AIS_MASK (0x200U);SDIF_IDSTS_AIS_SHIFT (9U);SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK);SDIF_IDSTS_EB_MASK (0x1C00U);SDIF_IDSTS_EB_SHIFT (10U);SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK);SDIF_IDSTS_FSM_MASK (0x1E000U);SDIF_IDSTS_FSM_SHIFT (13U);SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK);SDIF_IDINTEN_TI_MASK (0x1U);SDIF_IDINTEN_TI_SHIFT (0U);SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK);SDIF_IDINTEN_RI_MASK (0x2U);SDIF_IDINTEN_RI_SHIFT (1U);SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK);SDIF_IDINTEN_FBE_MASK (0x4U);SDIF_IDINTEN_FBE_SHIFT (2U);SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK);SDIF_IDINTEN_DU_MASK (0x10U);SDIF_IDINTEN_DU_SHIFT (4U);SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK);SDIF_IDINTEN_CES_MASK (0x20U);SDIF_IDINTEN_CES_SHIFT (5U);SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK);SDIF_IDINTEN_NIS_MASK (0x100U);SDIF_IDINTEN_NIS_SHIFT (8U);SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK);SDIF_IDINTEN_AIS_MASK (0x200U);SDIF_IDINTEN_AIS_SHIFT (9U);SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK);SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU);SDIF_DSCADDR_HDA_SHIFT (0U);SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK);SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU);SDIF_BUFADDR_HBA_SHIFT (0U);SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK);SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U);SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U);SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK);SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U);SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U);SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK);SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U);SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U);SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK);SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U);SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U);SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK);SDIF_FIFO_DATA_MASK (0xFFFFFFFFU);SDIF_FIFO_DATA_SHIFT (0U);SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK);SDIF_FIFO_COUNT (64U);SDIF_BASE (0x4009B000u)SPI_CFG_ENABLE_MASK (0x1U)>SPI_CFG_ENABLE_SHIFT (0U)>SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)>SPI_CFG_MASTER_MASK (0x4U)>SPI_CFG_MASTER_SHIFT (2U)>SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)>SPI_CFG_LSBF_MASK (0x8U)>SPI_CFG_LSBF_SHIFT (3U)>SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)>SPI_CFG_CPHA_MASK (0x10U)>SPI_CFG_CPHA_SHIFT (4U)>SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)>SPI_CFG_CPOL_MASK (0x20U)>SPI_CFG_CPOL_SHIFT (5U)>SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)>SPI_CFG_LOOP_MASK (0x80U)>SPI_CFG_LOOP_SHIFT (7U)>SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)>SPI_CFG_SPOL0_MASK (0x100U)>SPI_CFG_SPOL0_SHIFT (8U)>SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)>SPI_CFG_SPOL1_MASK (0x200U)>SPI_CFG_SPOL1_SHIFT (9U)>SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)>SPI_CFG_SPOL2_MASK (0x400U)>SPI_CFG_SPOL2_SHIFT (10U)>SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)>SPI_CFG_SPOL3_MASK (0x800U)>SPI_CFG_SPOL3_SHIFT (11U)>SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)>SPI_DLY_PRE_DELAY_MASK (0xFU)>SPI_DLY_PRE_DELAY_SHIFT (0U)>SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)>SPI_DLY_POST_DELAY_MASK (0xF0U)>SPI_DLY_POST_DELAY_SHIFT (4U)>SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)>SPI_DLY_FRAME_DELAY_MASK (0xF00U)>SPI_DLY_FRAME_DELAY_SHIFT (8U)>SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)>SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)>SPI_DLY_TRANSFER_DELAY_SHIFT (12U)>SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)>SPI_STAT_SSA_MASK (0x10U)>SPI_STAT_SSA_SHIFT (4U)>SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)>SPI_STAT_SSD_MASK (0x20U)>SPI_STAT_SSD_SHIFT (5U)>SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)>SPI_STAT_STALLED_MASK (0x40U)>SPI_STAT_STALLED_SHIFT (6U)>SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)>SPI_STAT_ENDTRANSFER_MASK (0x80U)>SPI_STAT_ENDTRANSFER_SHIFT (7U)>SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)>SPI_STAT_MSTIDLE_MASK (0x100U)>SPI_STAT_MSTIDLE_SHIFT (8U)>SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)>SPI_INTENSET_SSAEN_MASK (0x10U)>SPI_INTENSET_SSAEN_SHIFT (4U)>SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)>SPI_INTENSET_SSDEN_MASK (0x20U)>SPI_INTENSET_SSDEN_SHIFT (5U)>SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)>SPI_INTENSET_MSTIDLEEN_MASK (0x100U)>SPI_INTENSET_MSTIDLEEN_SHIFT (8U)>SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)>SPI_INTENCLR_SSAEN_MASK (0x10U)>SPI_INTENCLR_SSAEN_SHIFT (4U)>SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)>SPI_INTENCLR_SSDEN_MASK (0x20U)>SPI_INTENCLR_SSDEN_SHIFT (5U)>SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)>SPI_INTENCLR_MSTIDLE_MASK (0x100U)>SPI_INTENCLR_MSTIDLE_SHIFT (8U)>SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)>SPI_DIV_DIVVAL_MASK (0xFFFFU)>SPI_DIV_DIVVAL_SHIFT (0U)>SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)>SPI_INTSTAT_SSA_MASK (0x10U)>SPI_INTSTAT_SSA_SHIFT (4U)>SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)>SPI_INTSTAT_SSD_MASK (0x20U)>SPI_INTSTAT_SSD_SHIFT (5U)>SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)>SPI_INTSTAT_MSTIDLE_MASK (0x100U)>SPI_INTSTAT_MSTIDLE_SHIFT (8U)>SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)>SPI_FIFOCFG_ENABLETX_MASK (0x1U)>SPI_FIFOCFG_ENABLETX_SHIFT (0U)>SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)>SPI_FIFOCFG_ENABLERX_MASK (0x2U)>SPI_FIFOCFG_ENABLERX_SHIFT (1U)>SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)>SPI_FIFOCFG_SIZE_MASK (0x30U)>SPI_FIFOCFG_SIZE_SHIFT (4U)>SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)>SPI_FIFOCFG_DMATX_MASK (0x1000U)>SPI_FIFOCFG_DMATX_SHIFT (12U)>SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)>SPI_FIFOCFG_DMARX_MASK (0x2000U)>SPI_FIFOCFG_DMARX_SHIFT (13U)>SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)>SPI_FIFOCFG_WAKETX_MASK (0x4000U)>SPI_FIFOCFG_WAKETX_SHIFT (14U)>SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)>SPI_FIFOCFG_WAKERX_MASK (0x8000U)?SPI_FIFOCFG_WAKERX_SHIFT (15U)?SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)?SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)?SPI_FIFOCFG_EMPTYTX_SHIFT (16U)?SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)?SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)?SPI_FIFOCFG_EMPTYRX_SHIFT (17U)?SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)?SPI_FIFOCFG_POPDBG_MASK (0x40000U)?SPI_FIFOCFG_POPDBG_SHIFT (18U)?SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)?SPI_FIFOSTAT_TXERR_MASK (0x1U)?SPI_FIFOSTAT_TXERR_SHIFT (0U)?SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)?SPI_FIFOSTAT_RXERR_MASK (0x2U)?SPI_FIFOSTAT_RXERR_SHIFT (1U)?SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)?SPI_FIFOSTAT_PERINT_MASK (0x8U)?SPI_FIFOSTAT_PERINT_SHIFT (3U)?SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)?SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)?SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)?SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)?SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)?SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)?SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)?SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)?SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)?SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)?SPI_FIFOSTAT_RXFULL_MASK (0x80U)?SPI_FIFOSTAT_RXFULL_SHIFT (7U)?SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)?SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)?SPI_FIFOSTAT_TXLVL_SHIFT (8U)?SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)?SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)?SPI_FIFOSTAT_RXLVL_SHIFT (16U)?SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)?SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)?SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)?SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)?SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)?SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)?SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)?SPI_FIFOTRIG_TXLVL_MASK (0xF00U)?SPI_FIFOTRIG_TXLVL_SHIFT (8U)?SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)?SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)?SPI_FIFOTRIG_RXLVL_SHIFT (16U)?SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)?SPI_FIFOINTENSET_TXERR_MASK (0x1U)?SPI_FIFOINTENSET_TXERR_SHIFT (0U)?SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)?SPI_FIFOINTENSET_RXERR_MASK (0x2U)?SPI_FIFOINTENSET_RXERR_SHIFT (1U)?SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)?SPI_FIFOINTENSET_TXLVL_MASK (0x4U)?SPI_FIFOINTENSET_TXLVL_SHIFT (2U)?SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)?SPI_FIFOINTENSET_RXLVL_MASK (0x8U)?SPI_FIFOINTENSET_RXLVL_SHIFT (3U)?SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)?SPI_FIFOINTENCLR_TXERR_MASK (0x1U)?SPI_FIFOINTENCLR_TXERR_SHIFT (0U)?SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)?SPI_FIFOINTENCLR_RXERR_MASK (0x2U)?SPI_FIFOINTENCLR_RXERR_SHIFT (1U)?SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)?SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)?SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)?SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)?SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)?SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)?SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)?SPI_FIFOINTSTAT_TXERR_MASK (0x1U)?SPI_FIFOINTSTAT_TXERR_SHIFT (0U)?SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)?SPI_FIFOINTSTAT_RXERR_MASK (0x2U)?SPI_FIFOINTSTAT_RXERR_SHIFT (1U)?SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)?SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)?SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)?SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)?SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)?SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)?SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)?SPI_FIFOINTSTAT_PERINT_MASK (0x10U)?SPI_FIFOINTSTAT_PERINT_SHIFT (4U)?SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)?SPI_FIFOWR_TXDATA_MASK (0xFFFFU)?SPI_FIFOWR_TXDATA_SHIFT (0U)?SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)?SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)?SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)?SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)?SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)?SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)?SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)?SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)?SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)?SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)?SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)?SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)?SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)?SPI_FIFOWR_EOT_MASK (0x100000U)?SPI_FIFOWR_EOT_SHIFT (20U)?SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)?SPI_FIFOWR_EOF_MASK (0x200000U)?SPI_FIFOWR_EOF_SHIFT (21U)?SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)?SPI_FIFOWR_RXIGNORE_MASK (0x400000U)?SPI_FIFOWR_RXIGNORE_SHIFT (22U)?SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)?SPI_FIFOWR_LEN_MASK (0xF000000U)?SPI_FIFOWR_LEN_SHIFT (24U)?SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)@SPI_FIFORD_RXDATA_MASK (0xFFFFU)@SPI_FIFORD_RXDATA_SHIFT (0U)@SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)@SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)@SPI_FIFORD_RXSSEL0_N_SHIFT (16U)@SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)@SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)@SPI_FIFORD_RXSSEL1_N_SHIFT (17U)@SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)@SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)@SPI_FIFORD_RXSSEL2_N_SHIFT (18U)@SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)@SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)@SPI_FIFORD_RXSSEL3_N_SHIFT (19U)@SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)@SPI_FIFORD_SOT_MASK (0x100000U)@SPI_FIFORD_SOT_SHIFT (20U)@SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)@SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)@SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)@SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)@SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)@SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)@SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)@SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)@SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)@SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)@SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)@SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)@SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)@SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)@SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)@SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)@SPI_FIFORDNOPOP_SOT_MASK (0x100000U)@SPI_FIFORDNOPOP_SOT_SHIFT (20U)@SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)@SPI_ID_APERTURE_MASK (0xFFU)@SPI_ID_APERTURE_SHIFT (0U)@SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)@SPI_ID_MINOR_REV_MASK (0xF00U)@SPI_ID_MINOR_REV_SHIFT (8U)@SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)@SPI_ID_MAJOR_REV_MASK (0xF000U)@SPI_ID_MAJOR_REV_SHIFT (12U)@SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)@SPI_ID_ID_MASK (0xFFFF0000U)@SPI_ID_ID_SHIFT (16U)@SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)@SPI0_BASE (0x40086000u)@SPI0 ((SPI_Type *)SPI0_BASE)@SPI1_BASE (0x40087000u)@SPI1 ((SPI_Type *)SPI1_BASE)@SPI2_BASE (0x40088000u)@SPI2 ((SPI_Type *)SPI2_BASE)@SPI3_BASE (0x40089000u)@SPI3 ((SPI_Type *)SPI3_BASE)@SPI4_BASE (0x4008A000u)@SPI4 ((SPI_Type *)SPI4_BASE)@SPI5_BASE (0x40096000u)@SPI5 ((SPI_Type *)SPI5_BASE)@SPI6_BASE (0x40097000u)@SPI6 ((SPI_Type *)SPI6_BASE)@SPI7_BASE (0x40098000u)@SPI7 ((SPI_Type *)SPI7_BASE)@SPI8_BASE (0x40099000u)@SPI8 ((SPI_Type *)SPI8_BASE)@SPI9_BASE (0x4009A000u)@SPI9 ((SPI_Type *)SPI9_BASE)@SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE }@SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 }@SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }ASPIFI_CTRL_TIMEOUT_MASK (0xFFFFU)ASPIFI_CTRL_TIMEOUT_SHIFT (0U)ASPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)ASPIFI_CTRL_CSHIGH_MASK (0xF0000U)ASPIFI_CTRL_CSHIGH_SHIFT (16U)ASPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)ASPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U)ASPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U)ASPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)ASPIFI_CTRL_INTEN_MASK (0x400000U)ASPIFI_CTRL_INTEN_SHIFT (22U)ASPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)ASPIFI_CTRL_MODE3_MASK (0x800000U)ASPIFI_CTRL_MODE3_SHIFT (23U)ASPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)ASPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U)ASPIFI_CTRL_PRFTCH_DIS_SHIFT (27U)ASPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)ASPIFI_CTRL_DUAL_MASK (0x10000000U)ASPIFI_CTRL_DUAL_SHIFT (28U)ASPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)ASPIFI_CTRL_RFCLK_MASK (0x20000000U)ASPIFI_CTRL_RFCLK_SHIFT (29U)ASPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)ASPIFI_CTRL_FBCLK_MASK (0x40000000U)ASPIFI_CTRL_FBCLK_SHIFT (30U)ASPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)ASPIFI_CTRL_DMAEN_MASK (0x80000000U)ASPIFI_CTRL_DMAEN_SHIFT (31U)ASPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)ASPIFI_CMD_DATALEN_MASK (0x3FFFU)ASPIFI_CMD_DATALEN_SHIFT (0U)ASPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)ASPIFI_CMD_POLL_MASK (0x4000U)ASPIFI_CMD_POLL_SHIFT (14U)ASPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)ASPIFI_CMD_DOUT_MASK (0x8000U)ASPIFI_CMD_DOUT_SHIFT (15U)ASPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)ASPIFI_CMD_INTLEN_MASK (0x70000U)ASPIFI_CMD_INTLEN_SHIFT (16U)ASPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)ASPIFI_CMD_FIELDFORM_MASK (0x180000U)ASPIFI_CMD_FIELDFORM_SHIFT (19U)ASPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)ASPIFI_CMD_FRAMEFORM_MASK (0xE00000U)ASPIFI_CMD_FRAMEFORM_SHIFT (21U)ASPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)ASPIFI_CMD_OPCODE_MASK (0xFF000000U)ASPIFI_CMD_OPCODE_SHIFT (24U)ASPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)ASPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU)ASPIFI_ADDR_ADDRESS_SHIFT (0U)ASPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)ASPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU)ASPIFI_IDATA_IDATA_SHIFT (0U)ASPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)ASPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU)ASPIFI_CLIMIT_CLIMIT_SHIFT (0U)ASPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)ASPIFI_DATA_DATA_MASK (0xFFFFFFFFU)ASPIFI_DATA_DATA_SHIFT (0U)ASPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)ASPIFI_MCMD_POLL_MASK (0x4000U)ASPIFI_MCMD_POLL_SHIFT (14U)ASPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)ASPIFI_MCMD_DOUT_MASK (0x8000U)ASPIFI_MCMD_DOUT_SHIFT (15U)ASPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)ASPIFI_MCMD_INTLEN_MASK (0x70000U)ASPIFI_MCMD_INTLEN_SHIFT (16U)ASPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)ASPIFI_MCMD_FIELDFORM_MASK (0x180000U)ASPIFI_MCMD_FIELDFORM_SHIFT (19U)ASPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)ASPIFI_MCMD_FRAMEFORM_MASK (0xE00000U)ASPIFI_MCMD_FRAMEFORM_SHIFT (21U)ASPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)ASPIFI_MCMD_OPCODE_MASK (0xFF000000U)ASPIFI_MCMD_OPCODE_SHIFT (24U)ASPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)ASPIFI_STAT_MCINIT_MASK (0x1U)ASPIFI_STAT_MCINIT_SHIFT (0U)ASPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)ASPIFI_STAT_CMD_MASK (0x2U)ASPIFI_STAT_CMD_SHIFT (1U)ASPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)ASPIFI_STAT_RESET_MASK (0x10U)ASPIFI_STAT_RESET_SHIFT (4U)ASPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)ASPIFI_STAT_INTRQ_MASK (0x20U)ASPIFI_STAT_INTRQ_SHIFT (5U)ASPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)BSPIFI0_BASE (0x40080000u)BSPIFI0 ((SPIFI_Type *)SPIFI0_BASE)BSPIFI_BASE_ADDRS { SPIFI0_BASE }BSPIFI_BASE_PTRS { SPIFI0 }BSPIFI_IRQS { SPIFI0_IRQn }CSYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U)CSYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U)CSYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)CSYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU)CSYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U)CSYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)CSYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U)CSYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U)CSYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)CSYSCON_AHBMATPRIO_PRI_DMA_MASK (0x3C0U)CSYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U)CSYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)CSYSCON_AHBMATPRIO_PRI_ETH_MASK (0xC00U)CSYSCON_AHBMATPRIO_PRI_ETH_SHIFT (10U)CSYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)CSYSCON_AHBMATPRIO_PRI_LCD_MASK (0x3000U)CSYSCON_AHBMATPRIO_PRI_LCD_SHIFT (12U)CSYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)CSYSCON_AHBMATPRIO_PRI_USB0_MASK (0xC000U)CSYSCON_AHBMATPRIO_PRI_USB0_SHIFT (14U)CSYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)CSYSCON_AHBMATPRIO_PRI_USB1_MASK (0x30000U)CSYSCON_AHBMATPRIO_PRI_USB1_SHIFT (16U)CSYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)CSYSCON_AHBMATPRIO_PRI_SDIO_MASK (0xC0000U)CSYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (18U)CSYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)CSYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0x300000U)CSYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (20U)CSYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)CSYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0xC00000U)CSYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (22U)CSYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)CSYSCON_AHBMATPRIO_PRI_SHA_MASK (0x3000000U)CSYSCON_AHBMATPRIO_PRI_SHA_SHIFT (24U)CSYSCON_AHBMATPRIO_PRI_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK)CSYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU)CSYSCON_SYSTCKCAL_CAL_SHIFT (0U)CSYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)CSYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U)CSYSCON_SYSTCKCAL_SKEW_SHIFT (24U)CSYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)CSYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U)CSYSCON_SYSTCKCAL_NOREF_SHIFT (25U)CSYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)CSYSCON_NMISRC_IRQM4_MASK (0x3FU)CSYSCON_NMISRC_IRQM4_SHIFT (0U)CSYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)CSYSCON_NMISRC_NMIENM4_MASK (0x80000000U)CSYSCON_NMISRC_NMIENM4_SHIFT (31U)CSYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)CSYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U)CSYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U)CSYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)CSYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU)CSYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U)CSYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)CSYSCON_PIOPORCAP_COUNT (2U)CSYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU)CSYSCON_PIORESCAP_PIORESCAP_SHIFT (0U)CSYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)CSYSCON_PIORESCAP_COUNT (2U)DSYSCON_PRESETCTRL_MRT_RST_MASK (0x1U)DSYSCON_PRESETCTRL_MRT_RST_SHIFT (0U)DSYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)DSYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U)DSYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U)DSYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)DSYSCON_PRESETCTRL_LCD_RST_MASK (0x4U)DSYSCON_PRESETCTRL_LCD_RST_SHIFT (2U)DSYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)DSYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U)DSYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U)DSYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)DSYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U)DSYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U)DSYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)DSYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U)DSYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U)DSYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)DSYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U)DSYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U)DSYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)DSYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U)DSYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U)DSYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)DSYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U)DSYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U)DSYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK)DSYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U)DSYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U)DSYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)DSYSCON_PRESETCTRL_FMC_RST_MASK (0x100U)DSYSCON_PRESETCTRL_FMC_RST_SHIFT (8U)DSYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK)DSYSCON_PRESETCTRL_ETH_RST_MASK (0x100U)DSYSCON_PRESETCTRL_ETH_RST_SHIFT (8U)DSYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)DSYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U)DSYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U)DSYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)DSYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U)DSYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U)DSYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)DSYSCON_PRESETCTRL_EEPROM_RST_MASK (0x200U)DSYSCON_PRESETCTRL_EEPROM_RST_SHIFT (9U)DSYSCON_PRESETCTRL_EEPROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK)DSYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U)DSYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U)DSYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)DSYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U)DSYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U)DSYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)DSYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U)DSYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U)DSYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)DSYSCON_PRESETCTRL_AES_RST_MASK (0x800U)DSYSCON_PRESETCTRL_AES_RST_SHIFT (11U)DSYSCON_PRESETCTRL_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK)DSYSCON_PRESETCTRL_MUX_RST_MASK (0x800U)DSYSCON_PRESETCTRL_MUX_RST_SHIFT (11U)DSYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)DSYSCON_PRESETCTRL_FC0_RST_MASK (0x800U)DSYSCON_PRESETCTRL_FC0_RST_SHIFT (11U)DSYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)DSYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U)DSYSCON_PRESETCTRL_OTP_RST_SHIFT (12U)DSYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)DSYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U)DSYSCON_PRESETCTRL_FC1_RST_SHIFT (12U)DSYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)DSYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U)DSYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U)DSYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)DSYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U)DSYSCON_PRESETCTRL_RNG_RST_SHIFT (13U)DSYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)DSYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U)DSYSCON_PRESETCTRL_FC2_RST_SHIFT (13U)DSYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)DSYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U)DSYSCON_PRESETCTRL_FC8_RST_SHIFT (14U)DSYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)DSYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U)DSYSCON_PRESETCTRL_FC3_RST_SHIFT (14U)DSYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)DSYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U)DSYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U)DSYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)DSYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U)DSYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U)DSYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)DSYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U)DSYSCON_PRESETCTRL_FC9_RST_SHIFT (15U)DSYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)DSYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U)DSYSCON_PRESETCTRL_FC4_RST_SHIFT (15U)DSYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)DSYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U)DSYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U)DSYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)DSYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U)DSYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U)DSYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)DSYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U)DSYSCON_PRESETCTRL_FC5_RST_SHIFT (16U)DSYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)DSYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U)DSYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U)DSYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)DSYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U)DSYSCON_PRESETCTRL_FC6_RST_SHIFT (17U)DSYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)DSYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U)DSYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U)DSYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)DSYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U)DSYSCON_PRESETCTRL_FC7_RST_SHIFT (18U)DSYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)DSYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U)DSYSCON_PRESETCTRL_SHA_RST_SHIFT (18U)DSYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)DSYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U)DSYSCON_PRESETCTRL_PINT_RST_SHIFT (18U)DSYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)DSYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U)DSYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U)DSYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)DSYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U)DSYSCON_PRESETCTRL_SC0_RST_SHIFT (19U)ESYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)ESYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U)ESYSCON_PRESETCTRL_GINT_RST_SHIFT (19U)ESYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)ESYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U)ESYSCON_PRESETCTRL_SC1_RST_SHIFT (20U)ESYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)ESYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U)ESYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U)ESYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK)ESYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U)ESYSCON_PRESETCTRL_CRC_RST_SHIFT (21U)ESYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)ESYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U)ESYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U)ESYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)ESYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U)ESYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U)ESYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)ESYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U)ESYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U)ESYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)ESYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U)ESYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U)ESYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)ESYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U)ESYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U)ESYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)ESYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U)ESYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U)ESYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)ESYSCON_PRESETCTRL_COUNT (3U)ESYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU)ESYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U)ESYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)ESYSCON_PRESETCTRLSET_COUNT (3U)ESYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU)ESYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U)ESYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)ESYSCON_PRESETCTRLCLR_COUNT (3U)ESYSCON_SYSRSTSTAT_POR_MASK (0x1U)ESYSCON_SYSRSTSTAT_POR_SHIFT (0U)ESYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)ESYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U)ESYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U)ESYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)ESYSCON_SYSRSTSTAT_WDT_MASK (0x4U)ESYSCON_SYSRSTSTAT_WDT_SHIFT (2U)ESYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)ESYSCON_SYSRSTSTAT_BOD_MASK (0x8U)ESYSCON_SYSRSTSTAT_BOD_SHIFT (3U)ESYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)ESYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U)ESYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U)ESYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)ESYSCON_AHBCLKCTRL_MRT_MASK (0x1U)ESYSCON_AHBCLKCTRL_MRT_SHIFT (0U)ESYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)ESYSCON_AHBCLKCTRL_RIT_MASK (0x2U)ESYSCON_AHBCLKCTRL_RIT_SHIFT (1U)ESYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)ESYSCON_AHBCLKCTRL_ROM_MASK (0x2U)ESYSCON_AHBCLKCTRL_ROM_SHIFT (1U)ESYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)ESYSCON_AHBCLKCTRL_SCT0_MASK (0x4U)ESYSCON_AHBCLKCTRL_SCT0_SHIFT (2U)ESYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)ESYSCON_AHBCLKCTRL_LCD_MASK (0x4U)ESYSCON_AHBCLKCTRL_LCD_SHIFT (2U)ESYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)ESYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U)ESYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U)ESYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)ESYSCON_AHBCLKCTRL_SDIO_MASK (0x8U)ESYSCON_AHBCLKCTRL_SDIO_SHIFT (3U)ESYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)ESYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U)ESYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U)ESYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)ESYSCON_AHBCLKCTRL_USB1H_MASK (0x10U)ESYSCON_AHBCLKCTRL_USB1H_SHIFT (4U)ESYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)ESYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U)ESYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U)ESYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)ESYSCON_AHBCLKCTRL_USB1D_MASK (0x20U)ESYSCON_AHBCLKCTRL_USB1D_SHIFT (5U)ESYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)ESYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U)ESYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U)ESYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)ESYSCON_AHBCLKCTRL_FLASH_MASK (0x80U)ESYSCON_AHBCLKCTRL_FLASH_SHIFT (7U)ESYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK)ESYSCON_AHBCLKCTRL_EMC_MASK (0x80U)ESYSCON_AHBCLKCTRL_EMC_SHIFT (7U)ESYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)ESYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U)ESYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U)ESYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)ESYSCON_AHBCLKCTRL_FMC_MASK (0x100U)ESYSCON_AHBCLKCTRL_FMC_SHIFT (8U)ESYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK)ESYSCON_AHBCLKCTRL_ETH_MASK (0x100U)ESYSCON_AHBCLKCTRL_ETH_SHIFT (8U)ESYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)ESYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U)ESYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U)ESYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)ESYSCON_AHBCLKCTRL_EEPROM_MASK (0x200U)ESYSCON_AHBCLKCTRL_EEPROM_SHIFT (9U)ESYSCON_AHBCLKCTRL_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK)ESYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U)ESYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U)FSYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)FSYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U)FSYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U)FSYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)FSYSCON_AHBCLKCTRL_UTICK_MASK (0x400U)FSYSCON_AHBCLKCTRL_UTICK_SHIFT (10U)FSYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)FSYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U)FSYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U)FSYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)FSYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U)FSYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U)FSYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)FSYSCON_AHBCLKCTRL_AES_MASK (0x800U)FSYSCON_AHBCLKCTRL_AES_SHIFT (11U)FSYSCON_AHBCLKCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U)FSYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U)FSYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)FSYSCON_AHBCLKCTRL_OTP_MASK (0x1000U)FSYSCON_AHBCLKCTRL_OTP_SHIFT (12U)FSYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U)FSYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U)FSYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)FSYSCON_AHBCLKCTRL_RNG_MASK (0x2000U)FSYSCON_AHBCLKCTRL_RNG_SHIFT (13U)FSYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)FSYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U)FSYSCON_AHBCLKCTRL_IOCON_SHIFT (13U)FSYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U)FSYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U)FSYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)FSYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U)FSYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U)FSYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U)FSYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U)FSYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U)FSYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U)FSYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U)FSYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U)FSYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U)FSYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U)FSYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)FSYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U)FSYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U)FSYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)FSYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U)FSYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U)FSYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)FSYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U)FSYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U)FSYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U)FSYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U)FSYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U)FSYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U)FSYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)FSYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U)FSYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U)FSYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)FSYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U)FSYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U)FSYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)FSYSCON_AHBCLKCTRL_PINT_MASK (0x40000U)FSYSCON_AHBCLKCTRL_PINT_SHIFT (18U)FSYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)FSYSCON_AHBCLKCTRL_SHA0_MASK (0x40000U)FSYSCON_AHBCLKCTRL_SHA0_SHIFT (18U)FSYSCON_AHBCLKCTRL_SHA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK)FSYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U)FSYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U)FSYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)FSYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U)FSYSCON_AHBCLKCTRL_DMIC_SHIFT (19U)FSYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)FSYSCON_AHBCLKCTRL_GINT_MASK (0x80000U)FSYSCON_AHBCLKCTRL_GINT_SHIFT (19U)FSYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)FSYSCON_AHBCLKCTRL_SC0_MASK (0x80000U)FSYSCON_AHBCLKCTRL_SC0_SHIFT (19U)FSYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)FSYSCON_AHBCLKCTRL_SC1_MASK (0x100000U)FSYSCON_AHBCLKCTRL_SC1_SHIFT (20U)FSYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)FSYSCON_AHBCLKCTRL_DMA_MASK (0x100000U)FSYSCON_AHBCLKCTRL_DMA_SHIFT (20U)FSYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)FSYSCON_AHBCLKCTRL_CRC_MASK (0x200000U)FSYSCON_AHBCLKCTRL_CRC_SHIFT (21U)FSYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)FSYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U)FSYSCON_AHBCLKCTRL_WWDT_SHIFT (22U)FSYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)FSYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U)FSYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U)FSYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)FSYSCON_AHBCLKCTRL_RTC_MASK (0x800000U)FSYSCON_AHBCLKCTRL_RTC_SHIFT (23U)FSYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)FSYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U)FSYSCON_AHBCLKCTRL_USB0D_SHIFT (25U)FSYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)FSYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U)FSYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U)FSYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)FSYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U)FSYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U)FSYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)FSYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U)FSYSCON_AHBCLKCTRL_ADC0_SHIFT (27U)FSYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)FSYSCON_AHBCLKCTRL_COUNT (3U)FSYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU)FSYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U)FSYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)GSYSCON_AHBCLKCTRLSET_COUNT (3U)GSYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU)GSYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U)GSYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)GSYSCON_AHBCLKCTRLCLR_COUNT (3U)GSYSCON_MAINCLKSELA_SEL_MASK (0x3U)GSYSCON_MAINCLKSELA_SEL_SHIFT (0U)GSYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)GSYSCON_MAINCLKSELB_SEL_MASK (0x3U)GSYSCON_MAINCLKSELB_SEL_SHIFT (0U)GSYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)GSYSCON_CLKOUTSELA_SEL_MASK (0x7U)GSYSCON_CLKOUTSELA_SEL_SHIFT (0U)GSYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)GSYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U)GSYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U)GSYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)GSYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U)GSYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U)GSYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)GSYSCON_SPIFICLKSEL_SEL_MASK (0x7U)GSYSCON_SPIFICLKSEL_SEL_SHIFT (0U)GSYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)GSYSCON_ADCCLKSEL_SEL_MASK (0x7U)GSYSCON_ADCCLKSEL_SEL_SHIFT (0U)GSYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)GSYSCON_USB0CLKSEL_SEL_MASK (0x7U)GSYSCON_USB0CLKSEL_SEL_SHIFT (0U)GSYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)GSYSCON_USB1CLKSEL_SEL_MASK (0x7U)GSYSCON_USB1CLKSEL_SEL_SHIFT (0U)GSYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)GSYSCON_FCLKSEL_SEL_MASK (0x7U)GSYSCON_FCLKSEL_SEL_SHIFT (0U)GSYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)GSYSCON_FCLKSEL_COUNT (10U)GSYSCON_MCLKCLKSEL_SEL_MASK (0x7U)GSYSCON_MCLKCLKSEL_SEL_SHIFT (0U)GSYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)GSYSCON_FRGCLKSEL_SEL_MASK (0x7U)GSYSCON_FRGCLKSEL_SEL_SHIFT (0U)GSYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)GSYSCON_DMICCLKSEL_SEL_MASK (0x7U)GSYSCON_DMICCLKSEL_SEL_SHIFT (0U)GSYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)GSYSCON_SCTCLKSEL_SEL_MASK (0x7U)GSYSCON_SCTCLKSEL_SEL_SHIFT (0U)GSYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)GSYSCON_LCDCLKSEL_SEL_MASK (0x3U)GSYSCON_LCDCLKSEL_SEL_SHIFT (0U)GSYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)GSYSCON_SDIOCLKSEL_SEL_MASK (0x7U)GSYSCON_SDIOCLKSEL_SEL_SHIFT (0U)GSYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)GSYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU)GSYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U)GSYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)GSYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U)GSYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U)GSYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)GSYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U)GSYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U)GSYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)GSYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U)GSYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U)GSYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)GSYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU)GSYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U)GSYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)GSYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U)GSYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U)GSYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)GSYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U)GSYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U)GSYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)GSYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U)GSYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U)GSYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)GSYSCON_CAN0CLKDIV_DIV_MASK (0xFFU)GSYSCON_CAN0CLKDIV_DIV_SHIFT (0U)GSYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)GSYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U)GSYSCON_CAN0CLKDIV_RESET_SHIFT (29U)GSYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)HSYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U)HSYSCON_CAN0CLKDIV_HALT_SHIFT (30U)HSYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)HSYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U)HSYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)HSYSCON_CAN1CLKDIV_DIV_MASK (0xFFU)HSYSCON_CAN1CLKDIV_DIV_SHIFT (0U)HSYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)HSYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U)HSYSCON_CAN1CLKDIV_RESET_SHIFT (29U)HSYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)HSYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U)HSYSCON_CAN1CLKDIV_HALT_SHIFT (30U)HSYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)HSYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U)HSYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)HSYSCON_SC0CLKDIV_DIV_MASK (0xFFU)HSYSCON_SC0CLKDIV_DIV_SHIFT (0U)HSYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)HSYSCON_SC0CLKDIV_RESET_MASK (0x20000000U)HSYSCON_SC0CLKDIV_RESET_SHIFT (29U)HSYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)HSYSCON_SC0CLKDIV_HALT_MASK (0x40000000U)HSYSCON_SC0CLKDIV_HALT_SHIFT (30U)HSYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)HSYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U)HSYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)HSYSCON_SC1CLKDIV_DIV_MASK (0xFFU)HSYSCON_SC1CLKDIV_DIV_SHIFT (0U)HSYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)HSYSCON_SC1CLKDIV_RESET_MASK (0x20000000U)HSYSCON_SC1CLKDIV_RESET_SHIFT (29U)HSYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)HSYSCON_SC1CLKDIV_HALT_MASK (0x40000000U)HSYSCON_SC1CLKDIV_HALT_SHIFT (30U)HSYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)HSYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U)HSYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)HSYSCON_AHBCLKDIV_DIV_MASK (0xFFU)HSYSCON_AHBCLKDIV_DIV_SHIFT (0U)HSYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)HSYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)HSYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)HSYSCON_CLKOUTDIV_DIV_MASK (0xFFU)HSYSCON_CLKOUTDIV_DIV_SHIFT (0U)HSYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)HSYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)HSYSCON_CLKOUTDIV_RESET_SHIFT (29U)HSYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)HSYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)HSYSCON_CLKOUTDIV_HALT_SHIFT (30U)HSYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)HSYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)HSYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)HSYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)HSYSCON_FROHFCLKDIV_DIV_MASK (0xFFU)HSYSCON_FROHFCLKDIV_DIV_SHIFT (0U)HSYSCON_FROHFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK)HSYSCON_FROHFCLKDIV_RESET_MASK (0x20000000U)HSYSCON_FROHFCLKDIV_RESET_SHIFT (29U)HSYSCON_FROHFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK)HSYSCON_FROHFCLKDIV_HALT_MASK (0x40000000U)HSYSCON_FROHFCLKDIV_HALT_SHIFT (30U)HSYSCON_FROHFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK)HSYSCON_FROHFCLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_FROHFCLKDIV_REQFLAG_SHIFT (31U)HSYSCON_FROHFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK)HSYSCON_SPIFICLKDIV_DIV_MASK (0xFFU)HSYSCON_SPIFICLKDIV_DIV_SHIFT (0U)HSYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)HSYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U)HSYSCON_SPIFICLKDIV_RESET_SHIFT (29U)HSYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)HSYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U)HSYSCON_SPIFICLKDIV_HALT_SHIFT (30U)HSYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)HSYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U)HSYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)HSYSCON_ADCCLKDIV_DIV_MASK (0xFFU)HSYSCON_ADCCLKDIV_DIV_SHIFT (0U)HSYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)HSYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)HSYSCON_ADCCLKDIV_RESET_SHIFT (29U)HSYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)HSYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)HSYSCON_ADCCLKDIV_HALT_SHIFT (30U)HSYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)HSYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)HSYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)HSYSCON_USB0CLKDIV_DIV_MASK (0xFFU)HSYSCON_USB0CLKDIV_DIV_SHIFT (0U)HSYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)HSYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)HSYSCON_USB0CLKDIV_RESET_SHIFT (29U)HSYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)HSYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)HSYSCON_USB0CLKDIV_HALT_SHIFT (30U)HSYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)HSYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)HSYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)HSYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)ISYSCON_USB1CLKDIV_DIV_MASK (0xFFU)ISYSCON_USB1CLKDIV_DIV_SHIFT (0U)ISYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)ISYSCON_USB1CLKDIV_RESET_MASK (0x20000000U)ISYSCON_USB1CLKDIV_RESET_SHIFT (29U)ISYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)ISYSCON_USB1CLKDIV_HALT_MASK (0x40000000U)ISYSCON_USB1CLKDIV_HALT_SHIFT (30U)ISYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)ISYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U)ISYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U)ISYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)ISYSCON_FRGCTRL_DIV_MASK (0xFFU)ISYSCON_FRGCTRL_DIV_SHIFT (0U)ISYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)ISYSCON_FRGCTRL_MULT_MASK (0xFF00U)ISYSCON_FRGCTRL_MULT_SHIFT (8U)ISYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)ISYSCON_DMICCLKDIV_DIV_MASK (0xFFU)ISYSCON_DMICCLKDIV_DIV_SHIFT (0U)ISYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)ISYSCON_DMICCLKDIV_RESET_MASK (0x20000000U)ISYSCON_DMICCLKDIV_RESET_SHIFT (29U)ISYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)ISYSCON_DMICCLKDIV_HALT_MASK (0x40000000U)ISYSCON_DMICCLKDIV_HALT_SHIFT (30U)ISYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)ISYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U)ISYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U)ISYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)ISYSCON_MCLKDIV_DIV_MASK (0xFFU)ISYSCON_MCLKDIV_DIV_SHIFT (0U)ISYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)ISYSCON_MCLKDIV_RESET_MASK (0x20000000U)ISYSCON_MCLKDIV_RESET_SHIFT (29U)ISYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)ISYSCON_MCLKDIV_HALT_MASK (0x40000000U)ISYSCON_MCLKDIV_HALT_SHIFT (30U)ISYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)ISYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)ISYSCON_MCLKDIV_REQFLAG_SHIFT (31U)ISYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)ISYSCON_LCDCLKDIV_DIV_MASK (0xFFU)ISYSCON_LCDCLKDIV_DIV_SHIFT (0U)ISYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)ISYSCON_LCDCLKDIV_RESET_MASK (0x20000000U)ISYSCON_LCDCLKDIV_RESET_SHIFT (29U)ISYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)ISYSCON_LCDCLKDIV_HALT_MASK (0x40000000U)ISYSCON_LCDCLKDIV_HALT_SHIFT (30U)ISYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)ISYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U)ISYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U)ISYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)ISYSCON_SCTCLKDIV_DIV_MASK (0xFFU)ISYSCON_SCTCLKDIV_DIV_SHIFT (0U)ISYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)ISYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)ISYSCON_SCTCLKDIV_RESET_SHIFT (29U)ISYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)ISYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)ISYSCON_SCTCLKDIV_HALT_SHIFT (30U)ISYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)ISYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)ISYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)ISYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)ISYSCON_EMCCLKDIV_DIV_MASK (0xFFU)ISYSCON_EMCCLKDIV_DIV_SHIFT (0U)ISYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)ISYSCON_EMCCLKDIV_RESET_MASK (0x20000000U)ISYSCON_EMCCLKDIV_RESET_SHIFT (29U)ISYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)ISYSCON_EMCCLKDIV_HALT_MASK (0x40000000U)ISYSCON_EMCCLKDIV_HALT_SHIFT (30U)ISYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)ISYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U)ISYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U)ISYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)ISYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)ISYSCON_SDIOCLKDIV_DIV_SHIFT (0U)ISYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)ISYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)ISYSCON_SDIOCLKDIV_RESET_SHIFT (29U)ISYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)ISYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)ISYSCON_SDIOCLKDIV_HALT_SHIFT (30U)ISYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)ISYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)ISYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)ISYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)ISYSCON_FLASHCFG_FETCHCFG_MASK (0x3U)ISYSCON_FLASHCFG_FETCHCFG_SHIFT (0U)ISYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK)ISYSCON_FLASHCFG_DATACFG_MASK (0xCU)ISYSCON_FLASHCFG_DATACFG_SHIFT (2U)ISYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK)ISYSCON_FLASHCFG_ACCEL_MASK (0x10U)ISYSCON_FLASHCFG_ACCEL_SHIFT (4U)ISYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK)ISYSCON_FLASHCFG_PREFEN_MASK (0x20U)ISYSCON_FLASHCFG_PREFEN_SHIFT (5U)ISYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK)ISYSCON_FLASHCFG_PREFOVR_MASK (0x40U)ISYSCON_FLASHCFG_PREFOVR_SHIFT (6U)ISYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK)ISYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U)ISYSCON_FLASHCFG_FLASHTIM_SHIFT (12U)ISYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK)ISYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)ISYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)JSYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)JSYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)JSYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)JSYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)JSYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)JSYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)JSYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)JSYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)JSYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)JSYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)JSYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U)JSYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U)JSYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)JSYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)JSYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)JSYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)JSYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)JSYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)JSYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)JSYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU)JSYSCON_FREQMECTRL_CAPVAL_SHIFT (0U)JSYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)JSYSCON_FREQMECTRL_PROG_MASK (0x80000000U)JSYSCON_FREQMECTRL_PROG_SHIFT (31U)JSYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)JSYSCON_MCLKIO_DIR_MASK (0x1U)JSYSCON_MCLKIO_DIR_SHIFT (0U)JSYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)JSYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)JSYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)JSYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)JSYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)JSYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)JSYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)JSYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)JSYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)JSYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)JSYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)JSYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)JSYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)JSYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)JSYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)JSYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)JSYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)JSYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)JSYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)JSYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)JSYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)JSYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)JSYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U)JSYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U)JSYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)JSYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U)JSYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U)JSYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)JSYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U)JSYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U)JSYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)JSYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U)JSYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U)JSYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)JSYSCON_EMCDLYCTRL_CMD_DELAY_MASK (0x1FU)JSYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT (0U)JSYSCON_EMCDLYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK)JSYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK (0x1F00U)JSYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT (8U)JSYSCON_EMCDLYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK)JSYSCON_EMCDLYCAL_CALVALUE_MASK (0xFFU)JSYSCON_EMCDLYCAL_CALVALUE_SHIFT (0U)JSYSCON_EMCDLYCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK)JSYSCON_EMCDLYCAL_START_MASK (0x4000U)JSYSCON_EMCDLYCAL_START_SHIFT (14U)JSYSCON_EMCDLYCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK)JSYSCON_EMCDLYCAL_DONE_MASK (0x8000U)JSYSCON_EMCDLYCAL_DONE_SHIFT (15U)JSYSCON_EMCDLYCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK)JSYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U)JSYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U)JSYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)JSYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U)JSYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U)JSYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)JSYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)JSYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)JSYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)JSYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)JSYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)JSYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)JSYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)JSYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)JSYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)JSYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)JSYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)JSYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)JSYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)JSYSCON_FROCTRL_TRIM_MASK (0x3FFFU)KSYSCON_FROCTRL_TRIM_SHIFT (0U)KSYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK)KSYSCON_FROCTRL_SEL_MASK (0x4000U)KSYSCON_FROCTRL_SEL_SHIFT (14U)KSYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)KSYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U)KSYSCON_FROCTRL_FREQTRIM_SHIFT (16U)KSYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)KSYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U)KSYSCON_FROCTRL_USBCLKADJ_SHIFT (24U)KSYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)KSYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U)KSYSCON_FROCTRL_USBMODCHG_SHIFT (25U)KSYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)KSYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U)KSYSCON_FROCTRL_HSPDCLK_SHIFT (30U)KSYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)KSYSCON_FROCTRL_WRTRIM_MASK (0x80000000U)KSYSCON_FROCTRL_WRTRIM_SHIFT (31U)KSYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK)KSYSCON_SYSOSCCTRL_BYPASS_MASK (0x1U)KSYSCON_SYSOSCCTRL_BYPASS_SHIFT (0U)KSYSCON_SYSOSCCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK)KSYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U)KSYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U)KSYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)KSYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU)KSYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U)KSYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)KSYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U)KSYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U)KSYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)KSYSCON_RTCOSCCTRL_EN_MASK (0x1U)KSYSCON_RTCOSCCTRL_EN_SHIFT (0U)KSYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)KSYSCON_USBPLLCTRL_MSEL_MASK (0xFFU)KSYSCON_USBPLLCTRL_MSEL_SHIFT (0U)KSYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)KSYSCON_USBPLLCTRL_PSEL_MASK (0x300U)KSYSCON_USBPLLCTRL_PSEL_SHIFT (8U)KSYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)KSYSCON_USBPLLCTRL_NSEL_MASK (0xC00U)KSYSCON_USBPLLCTRL_NSEL_SHIFT (10U)KSYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)KSYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U)KSYSCON_USBPLLCTRL_DIRECT_SHIFT (12U)KSYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)KSYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U)KSYSCON_USBPLLCTRL_BYPASS_SHIFT (13U)KSYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)KSYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U)KSYSCON_USBPLLCTRL_FBSEL_SHIFT (14U)KSYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)KSYSCON_USBPLLSTAT_LOCK_MASK (0x1U)KSYSCON_USBPLLSTAT_LOCK_SHIFT (0U)KSYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)KSYSCON_SYSPLLCTRL_SELR_MASK (0xFU)KSYSCON_SYSPLLCTRL_SELR_SHIFT (0U)KSYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)KSYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U)KSYSCON_SYSPLLCTRL_SELI_SHIFT (4U)KSYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)KSYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U)KSYSCON_SYSPLLCTRL_SELP_SHIFT (10U)KSYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)KSYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U)KSYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U)KSYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)KSYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U)KSYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U)KSYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)KSYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U)KSYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U)KSYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)KSYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U)KSYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U)KSYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)KSYSCON_SYSPLLSTAT_LOCK_MASK (0x1U)KSYSCON_SYSPLLSTAT_LOCK_SHIFT (0U)KSYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)KSYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU)KSYSCON_SYSPLLNDEC_NDEC_SHIFT (0U)KSYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)KSYSCON_SYSPLLNDEC_NREQ_MASK (0x400U)KSYSCON_SYSPLLNDEC_NREQ_SHIFT (10U)KSYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)KSYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU)KSYSCON_SYSPLLPDEC_PDEC_SHIFT (0U)KSYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)KSYSCON_SYSPLLPDEC_PREQ_MASK (0x80U)KSYSCON_SYSPLLPDEC_PREQ_SHIFT (7U)KSYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)KSYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU)KSYSCON_SYSPLLMDEC_MDEC_SHIFT (0U)KSYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)KSYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U)KSYSCON_SYSPLLMDEC_MREQ_SHIFT (17U)KSYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)KSYSCON_AUDPLLCTRL_SELR_MASK (0xFU)KSYSCON_AUDPLLCTRL_SELR_SHIFT (0U)KSYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)KSYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U)KSYSCON_AUDPLLCTRL_SELI_SHIFT (4U)KSYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)KSYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U)KSYSCON_AUDPLLCTRL_SELP_SHIFT (10U)LSYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)LSYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U)LSYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U)LSYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)LSYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U)LSYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U)LSYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)LSYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U)LSYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U)LSYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)LSYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U)LSYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U)LSYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)LSYSCON_AUDPLLSTAT_LOCK_MASK (0x1U)LSYSCON_AUDPLLSTAT_LOCK_SHIFT (0U)LSYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)LSYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU)LSYSCON_AUDPLLNDEC_NDEC_SHIFT (0U)LSYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)LSYSCON_AUDPLLNDEC_NREQ_MASK (0x400U)LSYSCON_AUDPLLNDEC_NREQ_SHIFT (10U)LSYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)LSYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU)LSYSCON_AUDPLLPDEC_PDEC_SHIFT (0U)LSYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)LSYSCON_AUDPLLPDEC_PREQ_MASK (0x80U)LSYSCON_AUDPLLPDEC_PREQ_SHIFT (7U)LSYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)LSYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU)LSYSCON_AUDPLLMDEC_MDEC_SHIFT (0U)LSYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)LSYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U)LSYSCON_AUDPLLMDEC_MREQ_SHIFT (17U)LSYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)LSYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU)LSYSCON_AUDPLLFRAC_CTRL_SHIFT (0U)LSYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)LSYSCON_AUDPLLFRAC_REQ_MASK (0x400000U)LSYSCON_AUDPLLFRAC_REQ_SHIFT (22U)LSYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)LSYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U)LSYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U)LSYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)LSYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U)LSYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U)LSYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)LSYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U)LSYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U)LSYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)LSYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U)LSYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U)LSYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)LSYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U)LSYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U)LSYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)LSYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U)LSYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U)LSYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)LSYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK (0x20U)LSYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT (5U)LSYSCON_PDSLEEPCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK)LSYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U)LSYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U)LSYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)LSYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U)LSYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U)LSYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)LSYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U)LSYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U)LSYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)LSYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U)LSYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U)LSYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)LSYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U)LSYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U)LSYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)LSYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U)LSYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U)LSYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)LSYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U)LSYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U)LSYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)LSYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U)LSYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U)LSYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)LSYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U)LSYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U)LSYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)LSYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U)LSYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U)LSYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)LSYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U)LSYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U)LSYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)LSYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U)LSYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U)LSYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)LSYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U)LSYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U)LSYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)LSYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U)LSYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U)LSYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)LSYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U)LSYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U)LSYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)LSYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U)LSYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U)LSYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)LSYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U)LSYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U)LSYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)LSYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U)LSYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U)LSYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)LSYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U)MSYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U)MSYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)MSYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U)MSYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U)MSYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)MSYSCON_PDSLEEPCFG_COUNT (2U)MSYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U)MSYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U)MSYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)MSYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U)MSYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U)MSYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)MSYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U)MSYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U)MSYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)MSYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U)MSYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U)MSYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)MSYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U)MSYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U)MSYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)MSYSCON_PDRUNCFG_PDEN_EEPROM_MASK (0x20U)MSYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT (5U)MSYSCON_PDRUNCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK)MSYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U)MSYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U)MSYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)MSYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U)MSYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U)MSYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)MSYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U)MSYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U)MSYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)MSYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U)MSYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U)MSYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)MSYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U)MSYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U)MSYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)MSYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U)MSYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U)MSYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)MSYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U)MSYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U)MSYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)MSYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U)MSYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U)MSYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)MSYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U)MSYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U)MSYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)MSYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U)MSYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U)MSYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)MSYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U)MSYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U)MSYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)MSYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U)MSYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U)MSYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)MSYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U)MSYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U)MSYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)MSYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U)MSYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U)MSYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)MSYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U)MSYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U)MSYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)MSYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U)MSYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U)MSYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)MSYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U)MSYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U)MSYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)MSYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U)MSYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U)MSYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)MSYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U)MSYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U)MSYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)MSYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U)MSYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U)MSYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)MSYSCON_PDRUNCFG_COUNT (2U)MSYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U)MSYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U)MSYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)MSYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U)MSYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U)MSYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)MSYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U)MSYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U)MSYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)MSYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U)MSYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U)MSYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)MSYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U)MSYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U)MSYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)MSYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK (0x20U)MSYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT (5U)MSYSCON_PDRUNCFGSET_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK)MSYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U)MSYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U)MSYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)MSYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U)MSYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U)MSYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)MSYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U)MSYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U)MSYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)MSYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U)MSYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U)MSYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)MSYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U)MSYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U)MSYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)MSYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U)MSYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U)NSYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)NSYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U)NSYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U)NSYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)NSYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U)NSYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U)NSYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)NSYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U)NSYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U)NSYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)NSYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U)NSYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U)NSYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)NSYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U)NSYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U)NSYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)NSYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U)NSYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U)NSYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)NSYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U)NSYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U)NSYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)NSYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U)NSYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U)NSYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)NSYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U)NSYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U)NSYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)NSYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U)NSYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U)NSYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)NSYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U)NSYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U)NSYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)NSYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U)NSYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U)NSYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)NSYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U)NSYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U)NSYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)NSYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U)NSYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U)NSYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)NSYSCON_PDRUNCFGSET_COUNT (2U)NSYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U)NSYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U)NSYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)NSYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U)NSYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U)NSYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)NSYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U)NSYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U)NSYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)NSYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U)NSYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U)NSYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)NSYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U)NSYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U)NSYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)NSYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK (0x20U)NSYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT (5U)NSYSCON_PDRUNCFGCLR_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK)NSYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U)NSYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U)NSYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)NSYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U)NSYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U)NSYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)NSYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U)NSYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U)NSYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)NSYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U)NSYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U)NSYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)NSYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U)NSYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U)NSYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)NSYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U)NSYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U)NSYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)NSYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U)NSYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U)NSYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)NSYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U)NSYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U)NSYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)NSYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U)NSYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U)NSYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)NSYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U)NSYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U)NSYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)NSYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U)NSYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U)NSYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)NSYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U)NSYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U)NSYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)NSYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U)NSYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U)NSYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)NSYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U)NSYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U)NSYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)NSYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U)NSYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U)NSYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)NSYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U)NSYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U)NSYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)NSYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U)NSYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U)NSYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)NSYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U)NSYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U)NSYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)NSYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U)NSYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U)NSYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)NSYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U)NSYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U)NSYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)OSYSCON_PDRUNCFGCLR_COUNT (2U)OSYSCON_STARTER_WDT_BOD_MASK (0x1U)OSYSCON_STARTER_WDT_BOD_SHIFT (0U)OSYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)OSYSCON_STARTER_PINT4_MASK (0x1U)OSYSCON_STARTER_PINT4_SHIFT (0U)OSYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)OSYSCON_STARTER_PINT5_MASK (0x2U)OSYSCON_STARTER_PINT5_SHIFT (1U)OSYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)OSYSCON_STARTER_DMA_MASK (0x2U)OSYSCON_STARTER_DMA_SHIFT (1U)OSYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)OSYSCON_STARTER_GINT0_MASK (0x4U)OSYSCON_STARTER_GINT0_SHIFT (2U)OSYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)OSYSCON_STARTER_PINT6_MASK (0x4U)OSYSCON_STARTER_PINT6_SHIFT (2U)OSYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)OSYSCON_STARTER_GINT1_MASK (0x8U)OSYSCON_STARTER_GINT1_SHIFT (3U)OSYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)OSYSCON_STARTER_PINT7_MASK (0x8U)OSYSCON_STARTER_PINT7_SHIFT (3U)OSYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)OSYSCON_STARTER_CTIMER2_MASK (0x10U)OSYSCON_STARTER_CTIMER2_SHIFT (4U)OSYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)OSYSCON_STARTER_PIN_INT0_MASK (0x10U)OSYSCON_STARTER_PIN_INT0_SHIFT (4U)OSYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)OSYSCON_STARTER_CTIMER4_MASK (0x20U)OSYSCON_STARTER_CTIMER4_SHIFT (5U)OSYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)OSYSCON_STARTER_PIN_INT1_MASK (0x20U)OSYSCON_STARTER_PIN_INT1_SHIFT (5U)OSYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)OSYSCON_STARTER_PIN_INT2_MASK (0x40U)OSYSCON_STARTER_PIN_INT2_SHIFT (6U)OSYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)OSYSCON_STARTER_PIN_INT3_MASK (0x80U)OSYSCON_STARTER_PIN_INT3_SHIFT (7U)OSYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)OSYSCON_STARTER_SPIFI_MASK (0x80U)OSYSCON_STARTER_SPIFI_SHIFT (7U)OSYSCON_STARTER_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK)OSYSCON_STARTER_FLEXCOMM8_MASK (0x100U)OSYSCON_STARTER_FLEXCOMM8_SHIFT (8U)OSYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)OSYSCON_STARTER_UTICK_MASK (0x100U)OSYSCON_STARTER_UTICK_SHIFT (8U)OSYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)OSYSCON_STARTER_MRT_MASK (0x200U)OSYSCON_STARTER_MRT_SHIFT (9U)OSYSCON_STARTER_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK)OSYSCON_STARTER_FLEXCOMM9_MASK (0x200U)OSYSCON_STARTER_FLEXCOMM9_SHIFT (9U)OSYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)OSYSCON_STARTER_CTIMER0_MASK (0x400U)OSYSCON_STARTER_CTIMER0_SHIFT (10U)OSYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)OSYSCON_STARTER_CTIMER1_MASK (0x800U)OSYSCON_STARTER_CTIMER1_SHIFT (11U)OSYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)OSYSCON_STARTER_SCT0_MASK (0x1000U)OSYSCON_STARTER_SCT0_SHIFT (12U)OSYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)OSYSCON_STARTER_CTIMER3_MASK (0x2000U)OSYSCON_STARTER_CTIMER3_SHIFT (13U)OSYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)OSYSCON_STARTER_FLEXCOMM0_MASK (0x4000U)OSYSCON_STARTER_FLEXCOMM0_SHIFT (14U)OSYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)OSYSCON_STARTER_FLEXCOMM1_MASK (0x8000U)OSYSCON_STARTER_FLEXCOMM1_SHIFT (15U)OSYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)OSYSCON_STARTER_USB1_MASK (0x8000U)OSYSCON_STARTER_USB1_SHIFT (15U)OSYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)OSYSCON_STARTER_FLEXCOMM2_MASK (0x10000U)OSYSCON_STARTER_FLEXCOMM2_SHIFT (16U)OSYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)OSYSCON_STARTER_USB1_ACT_MASK (0x10000U)OSYSCON_STARTER_USB1_ACT_SHIFT (16U)OSYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)OSYSCON_STARTER_ENET_INT1_MASK (0x20000U)OSYSCON_STARTER_ENET_INT1_SHIFT (17U)OSYSCON_STARTER_ENET_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK)OSYSCON_STARTER_FLEXCOMM3_MASK (0x20000U)OSYSCON_STARTER_FLEXCOMM3_SHIFT (17U)OSYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)OSYSCON_STARTER_ENET_INT2_MASK (0x40000U)OSYSCON_STARTER_ENET_INT2_SHIFT (18U)OSYSCON_STARTER_ENET_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK)OSYSCON_STARTER_FLEXCOMM4_MASK (0x40000U)OSYSCON_STARTER_FLEXCOMM4_SHIFT (18U)OSYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)OSYSCON_STARTER_ENET_INT0_MASK (0x80000U)OSYSCON_STARTER_ENET_INT0_SHIFT (19U)OSYSCON_STARTER_ENET_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK)OSYSCON_STARTER_FLEXCOMM5_MASK (0x80000U)OSYSCON_STARTER_FLEXCOMM5_SHIFT (19U)OSYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)OSYSCON_STARTER_FLEXCOMM6_MASK (0x100000U)OSYSCON_STARTER_FLEXCOMM6_SHIFT (20U)OSYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)OSYSCON_STARTER_FLEXCOMM7_MASK (0x200000U)OSYSCON_STARTER_FLEXCOMM7_SHIFT (21U)OSYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)OSYSCON_STARTER_ADC0_SEQA_MASK (0x400000U)OSYSCON_STARTER_ADC0_SEQA_SHIFT (22U)OSYSCON_STARTER_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK)OSYSCON_STARTER_SMARTCARD0_MASK (0x800000U)OSYSCON_STARTER_SMARTCARD0_SHIFT (23U)OSYSCON_STARTER_SMARTCARD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK)OSYSCON_STARTER_ADC0_SEQB_MASK (0x800000U)OSYSCON_STARTER_ADC0_SEQB_SHIFT (23U)OSYSCON_STARTER_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK)OSYSCON_STARTER_ADC0_THCMP_MASK (0x1000000U)OSYSCON_STARTER_ADC0_THCMP_SHIFT (24U)OSYSCON_STARTER_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK)OSYSCON_STARTER_SMARTCARD1_MASK (0x1000000U)OSYSCON_STARTER_SMARTCARD1_SHIFT (24U)OSYSCON_STARTER_SMARTCARD1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK)OSYSCON_STARTER_DMIC_MASK (0x2000000U)OSYSCON_STARTER_DMIC_SHIFT (25U)PSYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)PSYSCON_STARTER_HWVAD_MASK (0x4000000U)PSYSCON_STARTER_HWVAD_SHIFT (26U)PSYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)PSYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U)PSYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U)PSYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)PSYSCON_STARTER_USB0_MASK (0x10000000U)PSYSCON_STARTER_USB0_SHIFT (28U)PSYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)PSYSCON_STARTER_RTC_MASK (0x20000000U)PSYSCON_STARTER_RTC_SHIFT (29U)PSYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)PSYSCON_STARTER_COUNT (2U)PSYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU)PSYSCON_STARTERSET_START_SET_SHIFT (0U)PSYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)PSYSCON_STARTERSET_COUNT (2U)PSYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU)PSYSCON_STARTERCLR_START_CLR_SHIFT (0U)PSYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)PSYSCON_STARTERCLR_COUNT (2U)PSYSCON_HWWAKE_FORCEWAKE_MASK (0x1U)PSYSCON_HWWAKE_FORCEWAKE_SHIFT (0U)PSYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)PSYSCON_HWWAKE_FCWAKE_MASK (0x2U)PSYSCON_HWWAKE_FCWAKE_SHIFT (1U)PSYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)PSYSCON_HWWAKE_WAKEDMIC_MASK (0x4U)PSYSCON_HWWAKE_WAKEDMIC_SHIFT (2U)PSYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)PSYSCON_HWWAKE_WAKEDMA_MASK (0x8U)PSYSCON_HWWAKE_WAKEDMA_SHIFT (3U)PSYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)PSYSCON_AUTOCGOR_RAM0X_MASK (0x2U)PSYSCON_AUTOCGOR_RAM0X_SHIFT (1U)PSYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)PSYSCON_AUTOCGOR_RAM1_MASK (0x4U)PSYSCON_AUTOCGOR_RAM1_SHIFT (2U)PSYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)PSYSCON_AUTOCGOR_RAM2_MASK (0x8U)PSYSCON_AUTOCGOR_RAM2_SHIFT (3U)PSYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)PSYSCON_AUTOCGOR_RAM3_MASK (0x10U)PSYSCON_AUTOCGOR_RAM3_SHIFT (4U)PSYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)PSYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU)PSYSCON_JTAGIDCODE_JTAGID_SHIFT (0U)PSYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)PSYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU)PSYSCON_DEVICE_ID0_PARTID_SHIFT (0U)PSYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)PSYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU)PSYSCON_DEVICE_ID1_REVID_SHIFT (0U)PSYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)PSYSCON_BODCTRL_BODRSTLEV_MASK (0x3U)PSYSCON_BODCTRL_BODRSTLEV_SHIFT (0U)PSYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)PSYSCON_BODCTRL_BODRSTENA_MASK (0x4U)PSYSCON_BODCTRL_BODRSTENA_SHIFT (2U)PSYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)PSYSCON_BODCTRL_BODINTLEV_MASK (0x18U)PSYSCON_BODCTRL_BODINTLEV_SHIFT (3U)PSYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)PSYSCON_BODCTRL_BODINTENA_MASK (0x20U)PSYSCON_BODCTRL_BODINTENA_SHIFT (5U)PSYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)PSYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U)PSYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U)PSYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)PSYSCON_BODCTRL_BODINTSTAT_MASK (0x80U)PSYSCON_BODCTRL_BODINTSTAT_SHIFT (7U)PSYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)PSYSCON_BASE (0x40000000u)PSYSCON ((SYSCON_Type *)SYSCON_BASE)PSYSCON_BASE_ADDRS { SYSCON_BASE }PSYSCON_BASE_PTRS { SYSCON }QUSART_CFG_ENABLE_MASK (0x1U)QUSART_CFG_ENABLE_SHIFT (0U)QUSART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)QUSART_CFG_DATALEN_MASK (0xCU)QUSART_CFG_DATALEN_SHIFT (2U)QUSART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)QUSART_CFG_PARITYSEL_MASK (0x30U)QUSART_CFG_PARITYSEL_SHIFT (4U)QUSART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)QUSART_CFG_STOPLEN_MASK (0x40U)QUSART_CFG_STOPLEN_SHIFT (6U)QUSART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)QUSART_CFG_MODE32K_MASK (0x80U)QUSART_CFG_MODE32K_SHIFT (7U)QUSART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)QUSART_CFG_LINMODE_MASK (0x100U)QUSART_CFG_LINMODE_SHIFT (8U)QUSART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)QUSART_CFG_CTSEN_MASK (0x200U)QUSART_CFG_CTSEN_SHIFT (9U)QUSART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)QUSART_CFG_SYNCEN_MASK (0x800U)QUSART_CFG_SYNCEN_SHIFT (11U)QUSART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)QUSART_CFG_CLKPOL_MASK (0x1000U)QUSART_CFG_CLKPOL_SHIFT (12U)QUSART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)QUSART_CFG_SYNCMST_MASK (0x4000U)QUSART_CFG_SYNCMST_SHIFT (14U)QUSART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)QUSART_CFG_LOOP_MASK (0x8000U)QUSART_CFG_LOOP_SHIFT (15U)QUSART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)QUSART_CFG_OETA_MASK (0x40000U)QUSART_CFG_OETA_SHIFT (18U)QUSART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)QUSART_CFG_AUTOADDR_MASK (0x80000U)QUSART_CFG_AUTOADDR_SHIFT (19U)QUSART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)QUSART_CFG_OESEL_MASK (0x100000U)QUSART_CFG_OESEL_SHIFT (20U)QUSART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)QUSART_CFG_OEPOL_MASK (0x200000U)QUSART_CFG_OEPOL_SHIFT (21U)QUSART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)QUSART_CFG_RXPOL_MASK (0x400000U)QUSART_CFG_RXPOL_SHIFT (22U)QUSART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)QUSART_CFG_TXPOL_MASK (0x800000U)QUSART_CFG_TXPOL_SHIFT (23U)QUSART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)QUSART_CTL_TXBRKEN_MASK (0x2U)QUSART_CTL_TXBRKEN_SHIFT (1U)QUSART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)QUSART_CTL_ADDRDET_MASK (0x4U)QUSART_CTL_ADDRDET_SHIFT (2U)QUSART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)QUSART_CTL_TXDIS_MASK (0x40U)QUSART_CTL_TXDIS_SHIFT (6U)QUSART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)QUSART_CTL_CC_MASK (0x100U)QUSART_CTL_CC_SHIFT (8U)QUSART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)QUSART_CTL_CLRCCONRX_MASK (0x200U)QUSART_CTL_CLRCCONRX_SHIFT (9U)QUSART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)QUSART_CTL_AUTOBAUD_MASK (0x10000U)QUSART_CTL_AUTOBAUD_SHIFT (16U)QUSART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)QUSART_STAT_RXIDLE_MASK (0x2U)QUSART_STAT_RXIDLE_SHIFT (1U)QUSART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)QUSART_STAT_TXIDLE_MASK (0x8U)QUSART_STAT_TXIDLE_SHIFT (3U)QUSART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)QUSART_STAT_CTS_MASK (0x10U)QUSART_STAT_CTS_SHIFT (4U)QUSART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)QUSART_STAT_DELTACTS_MASK (0x20U)QUSART_STAT_DELTACTS_SHIFT (5U)QUSART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)QUSART_STAT_TXDISSTAT_MASK (0x40U)QUSART_STAT_TXDISSTAT_SHIFT (6U)QUSART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)QUSART_STAT_RXBRK_MASK (0x400U)QUSART_STAT_RXBRK_SHIFT (10U)RUSART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)RUSART_STAT_DELTARXBRK_MASK (0x800U)RUSART_STAT_DELTARXBRK_SHIFT (11U)RUSART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)RUSART_STAT_START_MASK (0x1000U)RUSART_STAT_START_SHIFT (12U)RUSART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)RUSART_STAT_FRAMERRINT_MASK (0x2000U)RUSART_STAT_FRAMERRINT_SHIFT (13U)RUSART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)RUSART_STAT_PARITYERRINT_MASK (0x4000U)RUSART_STAT_PARITYERRINT_SHIFT (14U)RUSART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)RUSART_STAT_RXNOISEINT_MASK (0x8000U)RUSART_STAT_RXNOISEINT_SHIFT (15U)RUSART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)RUSART_STAT_ABERR_MASK (0x10000U)RUSART_STAT_ABERR_SHIFT (16U)RUSART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)RUSART_INTENSET_TXIDLEEN_MASK (0x8U)RUSART_INTENSET_TXIDLEEN_SHIFT (3U)RUSART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)RUSART_INTENSET_DELTACTSEN_MASK (0x20U)RUSART_INTENSET_DELTACTSEN_SHIFT (5U)RUSART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)RUSART_INTENSET_TXDISEN_MASK (0x40U)RUSART_INTENSET_TXDISEN_SHIFT (6U)RUSART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)RUSART_INTENSET_DELTARXBRKEN_MASK (0x800U)RUSART_INTENSET_DELTARXBRKEN_SHIFT (11U)RUSART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)RUSART_INTENSET_STARTEN_MASK (0x1000U)RUSART_INTENSET_STARTEN_SHIFT (12U)RUSART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)RUSART_INTENSET_FRAMERREN_MASK (0x2000U)RUSART_INTENSET_FRAMERREN_SHIFT (13U)RUSART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)RUSART_INTENSET_PARITYERREN_MASK (0x4000U)RUSART_INTENSET_PARITYERREN_SHIFT (14U)RUSART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)RUSART_INTENSET_RXNOISEEN_MASK (0x8000U)RUSART_INTENSET_RXNOISEEN_SHIFT (15U)RUSART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)RUSART_INTENSET_ABERREN_MASK (0x10000U)RUSART_INTENSET_ABERREN_SHIFT (16U)RUSART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)RUSART_INTENCLR_TXIDLECLR_MASK (0x8U)RUSART_INTENCLR_TXIDLECLR_SHIFT (3U)RUSART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)RUSART_INTENCLR_DELTACTSCLR_MASK (0x20U)RUSART_INTENCLR_DELTACTSCLR_SHIFT (5U)RUSART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)RUSART_INTENCLR_TXDISCLR_MASK (0x40U)RUSART_INTENCLR_TXDISCLR_SHIFT (6U)RUSART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)RUSART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)RUSART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)RUSART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)RUSART_INTENCLR_STARTCLR_MASK (0x1000U)RUSART_INTENCLR_STARTCLR_SHIFT (12U)RUSART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)RUSART_INTENCLR_FRAMERRCLR_MASK (0x2000U)RUSART_INTENCLR_FRAMERRCLR_SHIFT (13U)RUSART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)RUSART_INTENCLR_PARITYERRCLR_MASK (0x4000U)RUSART_INTENCLR_PARITYERRCLR_SHIFT (14U)RUSART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)RUSART_INTENCLR_RXNOISECLR_MASK (0x8000U)RUSART_INTENCLR_RXNOISECLR_SHIFT (15U)RUSART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)RUSART_INTENCLR_ABERRCLR_MASK (0x10000U)RUSART_INTENCLR_ABERRCLR_SHIFT (16U)RUSART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)RUSART_BRG_BRGVAL_MASK (0xFFFFU)RUSART_BRG_BRGVAL_SHIFT (0U)RUSART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)RUSART_INTSTAT_TXIDLE_MASK (0x8U)RUSART_INTSTAT_TXIDLE_SHIFT (3U)RUSART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)RUSART_INTSTAT_DELTACTS_MASK (0x20U)RUSART_INTSTAT_DELTACTS_SHIFT (5U)RUSART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)RUSART_INTSTAT_TXDISINT_MASK (0x40U)RUSART_INTSTAT_TXDISINT_SHIFT (6U)RUSART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)RUSART_INTSTAT_DELTARXBRK_MASK (0x800U)RUSART_INTSTAT_DELTARXBRK_SHIFT (11U)RUSART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)RUSART_INTSTAT_START_MASK (0x1000U)RUSART_INTSTAT_START_SHIFT (12U)RUSART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)RUSART_INTSTAT_FRAMERRINT_MASK (0x2000U)RUSART_INTSTAT_FRAMERRINT_SHIFT (13U)RUSART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)RUSART_INTSTAT_PARITYERRINT_MASK (0x4000U)RUSART_INTSTAT_PARITYERRINT_SHIFT (14U)RUSART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)RUSART_INTSTAT_RXNOISEINT_MASK (0x8000U)RUSART_INTSTAT_RXNOISEINT_SHIFT (15U)RUSART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)RUSART_INTSTAT_ABERRINT_MASK (0x10000U)RUSART_INTSTAT_ABERRINT_SHIFT (16U)RUSART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)RUSART_OSR_OSRVAL_MASK (0xFU)RUSART_OSR_OSRVAL_SHIFT (0U)RUSART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)RUSART_ADDR_ADDRESS_MASK (0xFFU)RUSART_ADDR_ADDRESS_SHIFT (0U)RUSART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)RUSART_FIFOCFG_ENABLETX_MASK (0x1U)RUSART_FIFOCFG_ENABLETX_SHIFT (0U)RUSART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)RUSART_FIFOCFG_ENABLERX_MASK (0x2U)RUSART_FIFOCFG_ENABLERX_SHIFT (1U)SUSART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)SUSART_FIFOCFG_SIZE_MASK (0x30U)SUSART_FIFOCFG_SIZE_SHIFT (4U)SUSART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)SUSART_FIFOCFG_DMATX_MASK (0x1000U)SUSART_FIFOCFG_DMATX_SHIFT (12U)SUSART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)SUSART_FIFOCFG_DMARX_MASK (0x2000U)SUSART_FIFOCFG_DMARX_SHIFT (13U)SUSART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)SUSART_FIFOCFG_WAKETX_MASK (0x4000U)SUSART_FIFOCFG_WAKETX_SHIFT (14U)SUSART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)SUSART_FIFOCFG_WAKERX_MASK (0x8000U)SUSART_FIFOCFG_WAKERX_SHIFT (15U)SUSART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)SUSART_FIFOCFG_EMPTYTX_MASK (0x10000U)SUSART_FIFOCFG_EMPTYTX_SHIFT (16U)SUSART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)SUSART_FIFOCFG_EMPTYRX_MASK (0x20000U)SUSART_FIFOCFG_EMPTYRX_SHIFT (17U)SUSART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)SUSART_FIFOCFG_POPDBG_MASK (0x40000U)SUSART_FIFOCFG_POPDBG_SHIFT (18U)SUSART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)SUSART_FIFOSTAT_TXERR_MASK (0x1U)SUSART_FIFOSTAT_TXERR_SHIFT (0U)SUSART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)SUSART_FIFOSTAT_RXERR_MASK (0x2U)SUSART_FIFOSTAT_RXERR_SHIFT (1U)SUSART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)SUSART_FIFOSTAT_PERINT_MASK (0x8U)SUSART_FIFOSTAT_PERINT_SHIFT (3U)SUSART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)SUSART_FIFOSTAT_TXEMPTY_MASK (0x10U)SUSART_FIFOSTAT_TXEMPTY_SHIFT (4U)SUSART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)SUSART_FIFOSTAT_TXNOTFULL_MASK (0x20U)SUSART_FIFOSTAT_TXNOTFULL_SHIFT (5U)SUSART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)SUSART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)SUSART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)SUSART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)SUSART_FIFOSTAT_RXFULL_MASK (0x80U)SUSART_FIFOSTAT_RXFULL_SHIFT (7U)SUSART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)SUSART_FIFOSTAT_TXLVL_MASK (0x1F00U)SUSART_FIFOSTAT_TXLVL_SHIFT (8U)SUSART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)SUSART_FIFOSTAT_RXLVL_MASK (0x1F0000U)SUSART_FIFOSTAT_RXLVL_SHIFT (16U)SUSART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)SUSART_FIFOTRIG_TXLVLENA_MASK (0x1U)SUSART_FIFOTRIG_TXLVLENA_SHIFT (0U)SUSART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)SUSART_FIFOTRIG_RXLVLENA_MASK (0x2U)SUSART_FIFOTRIG_RXLVLENA_SHIFT (1U)SUSART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)SUSART_FIFOTRIG_TXLVL_MASK (0xF00U)SUSART_FIFOTRIG_TXLVL_SHIFT (8U)SUSART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)SUSART_FIFOTRIG_RXLVL_MASK (0xF0000U)SUSART_FIFOTRIG_RXLVL_SHIFT (16U)SUSART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)SUSART_FIFOINTENSET_TXERR_MASK (0x1U)SUSART_FIFOINTENSET_TXERR_SHIFT (0U)SUSART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)SUSART_FIFOINTENSET_RXERR_MASK (0x2U)SUSART_FIFOINTENSET_RXERR_SHIFT (1U)SUSART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)SUSART_FIFOINTENSET_TXLVL_MASK (0x4U)SUSART_FIFOINTENSET_TXLVL_SHIFT (2U)SUSART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)SUSART_FIFOINTENSET_RXLVL_MASK (0x8U)SUSART_FIFOINTENSET_RXLVL_SHIFT (3U)SUSART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)SUSART_FIFOINTENCLR_TXERR_MASK (0x1U)SUSART_FIFOINTENCLR_TXERR_SHIFT (0U)SUSART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)SUSART_FIFOINTENCLR_RXERR_MASK (0x2U)SUSART_FIFOINTENCLR_RXERR_SHIFT (1U)SUSART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)SUSART_FIFOINTENCLR_TXLVL_MASK (0x4U)SUSART_FIFOINTENCLR_TXLVL_SHIFT (2U)SUSART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)SUSART_FIFOINTENCLR_RXLVL_MASK (0x8U)SUSART_FIFOINTENCLR_RXLVL_SHIFT (3U)SUSART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)SUSART_FIFOINTSTAT_TXERR_MASK (0x1U)SUSART_FIFOINTSTAT_TXERR_SHIFT (0U)SUSART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)SUSART_FIFOINTSTAT_RXERR_MASK (0x2U)SUSART_FIFOINTSTAT_RXERR_SHIFT (1U)SUSART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)SUSART_FIFOINTSTAT_TXLVL_MASK (0x4U)SUSART_FIFOINTSTAT_TXLVL_SHIFT (2U)SUSART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)SUSART_FIFOINTSTAT_RXLVL_MASK (0x8U)SUSART_FIFOINTSTAT_RXLVL_SHIFT (3U)SUSART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)SUSART_FIFOINTSTAT_PERINT_MASK (0x10U)SUSART_FIFOINTSTAT_PERINT_SHIFT (4U)SUSART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)SUSART_FIFOWR_TXDATA_MASK (0x1FFU)SUSART_FIFOWR_TXDATA_SHIFT (0U)SUSART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)SUSART_FIFORD_RXDATA_MASK (0x1FFU)SUSART_FIFORD_RXDATA_SHIFT (0U)SUSART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)SUSART_FIFORD_FRAMERR_MASK (0x2000U)SUSART_FIFORD_FRAMERR_SHIFT (13U)SUSART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)SUSART_FIFORD_PARITYERR_MASK (0x4000U)SUSART_FIFORD_PARITYERR_SHIFT (14U)TUSART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)TUSART_FIFORD_RXNOISE_MASK (0x8000U)TUSART_FIFORD_RXNOISE_SHIFT (15U)TUSART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)TUSART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)TUSART_FIFORDNOPOP_RXDATA_SHIFT (0U)TUSART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)TUSART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)TUSART_FIFORDNOPOP_FRAMERR_SHIFT (13U)TUSART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)TUSART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)TUSART_FIFORDNOPOP_PARITYERR_SHIFT (14U)TUSART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)TUSART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)TUSART_FIFORDNOPOP_RXNOISE_SHIFT (15U)TUSART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)TUSART_ID_APERTURE_MASK (0xFFU)TUSART_ID_APERTURE_SHIFT (0U)TUSART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)TUSART_ID_MINOR_REV_MASK (0xF00U)TUSART_ID_MINOR_REV_SHIFT (8U)TUSART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)TUSART_ID_MAJOR_REV_MASK (0xF000U)TUSART_ID_MAJOR_REV_SHIFT (12U)TUSART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)TUSART_ID_ID_MASK (0xFFFF0000U)TUSART_ID_ID_SHIFT (16U)TUSART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)TUSART0_BASE (0x40086000u)TUSART0 ((USART_Type *)USART0_BASE)TUSART1_BASE (0x40087000u)TUSART1 ((USART_Type *)USART1_BASE)TUSART2_BASE (0x40088000u)TUSART2 ((USART_Type *)USART2_BASE)TUSART3_BASE (0x40089000u)TUSART3 ((USART_Type *)USART3_BASE)TUSART4_BASE (0x4008A000u)TUSART4 ((USART_Type *)USART4_BASE)TUSART5_BASE (0x40096000u)TUSART5 ((USART_Type *)USART5_BASE)TUSART6_BASE (0x40097000u)TUSART6 ((USART_Type *)USART6_BASE)TUSART7_BASE (0x40098000u)TUSART7 ((USART_Type *)USART7_BASE)TUSART8_BASE (0x40099000u)TUSART8 ((USART_Type *)USART8_BASE)TUSART9_BASE (0x4009A000u)TUSART9 ((USART_Type *)USART9_BASE)TUSART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }TUSART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }TUSART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }UUSB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)UUSB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)UUSB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)UUSB_DEVCMDSTAT_DEV_EN_MASK (0x80U)UUSB_DEVCMDSTAT_DEV_EN_SHIFT (7U)UUSB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)UUSB_DEVCMDSTAT_SETUP_MASK (0x100U)UUSB_DEVCMDSTAT_SETUP_SHIFT (8U)UUSB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)UUSB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)UUSB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)UUSB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)UUSB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)UUSB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)UUSB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)UUSB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)UUSB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)UUSB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)UUSB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)UUSB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)UUSB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)UUSB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)UUSB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)UUSB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)UUSB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)UUSB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)UUSB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)UUSB_DEVCMDSTAT_DCON_MASK (0x10000U)UUSB_DEVCMDSTAT_DCON_SHIFT (16U)UUSB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)UUSB_DEVCMDSTAT_DSUS_MASK (0x20000U)UUSB_DEVCMDSTAT_DSUS_SHIFT (17U)UUSB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)UUSB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)UUSB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)UUSB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)UUSB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)UUSB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)UUSB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)UUSB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)UUSB_DEVCMDSTAT_DCON_C_SHIFT (24U)UUSB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)UUSB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)UUSB_DEVCMDSTAT_DSUS_C_SHIFT (25U)UUSB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)UUSB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)UUSB_DEVCMDSTAT_DRES_C_SHIFT (26U)UUSB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)UUSB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)UUSB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)UUSB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)UUSB_INFO_FRAME_NR_MASK (0x7FFU)UUSB_INFO_FRAME_NR_SHIFT (0U)UUSB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)UUSB_INFO_ERR_CODE_MASK (0x7800U)UUSB_INFO_ERR_CODE_SHIFT (11U)UUSB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)UUSB_INFO_MINREV_MASK (0xFF0000U)UUSB_INFO_MINREV_SHIFT (16U)UUSB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)UUSB_INFO_MAJREV_MASK (0xFF000000U)UUSB_INFO_MAJREV_SHIFT (24U)UUSB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)UUSB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)UUSB_EPLISTSTART_EP_LIST_SHIFT (8U)UUSB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)UUSB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)UUSB_DATABUFSTART_DA_BUF_SHIFT (22U)UUSB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)UUSB_LPM_HIRD_HW_MASK (0xFU)UUSB_LPM_HIRD_HW_SHIFT (0U)UUSB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)UUSB_LPM_HIRD_SW_MASK (0xF0U)UUSB_LPM_HIRD_SW_SHIFT (4U)UUSB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)UUSB_LPM_DATA_PENDING_MASK (0x100U)UUSB_LPM_DATA_PENDING_SHIFT (8U)UUSB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)UUSB_EPSKIP_SKIP_MASK (0x3FFU)UUSB_EPSKIP_SKIP_SHIFT (0U)UUSB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)UUSB_EPINUSE_BUF_MASK (0x3FCU)UUSB_EPINUSE_BUF_SHIFT (2U)UUSB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)UUSB_EPBUFCFG_BUF_SB_MASK (0x3FCU)UUSB_EPBUFCFG_BUF_SB_SHIFT (2U)UUSB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)UUSB_INTSTAT_EP0OUT_MASK (0x1U)UUSB_INTSTAT_EP0OUT_SHIFT (0U)UUSB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)UUSB_INTSTAT_EP0IN_MASK (0x2U)UUSB_INTSTAT_EP0IN_SHIFT (1U)UUSB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)UUSB_INTSTAT_EP1OUT_MASK (0x4U)UUSB_INTSTAT_EP1OUT_SHIFT (2U)UUSB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)UUSB_INTSTAT_EP1IN_MASK (0x8U)UUSB_INTSTAT_EP1IN_SHIFT (3U)UUSB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)UUSB_INTSTAT_EP2OUT_MASK (0x10U)UUSB_INTSTAT_EP2OUT_SHIFT (4U)UUSB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)UUSB_INTSTAT_EP2IN_MASK (0x20U)UUSB_INTSTAT_EP2IN_SHIFT (5U)UUSB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)UUSB_INTSTAT_EP3OUT_MASK (0x40U)UUSB_INTSTAT_EP3OUT_SHIFT (6U)UUSB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)UUSB_INTSTAT_EP3IN_MASK (0x80U)UUSB_INTSTAT_EP3IN_SHIFT (7U)UUSB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)UUSB_INTSTAT_EP4OUT_MASK (0x100U)VUSB_INTSTAT_EP4OUT_SHIFT (8U)VUSB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)VUSB_INTSTAT_EP4IN_MASK (0x200U)VUSB_INTSTAT_EP4IN_SHIFT (9U)VUSB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)VUSB_INTSTAT_FRAME_INT_MASK (0x40000000U)VUSB_INTSTAT_FRAME_INT_SHIFT (30U)VUSB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)VUSB_INTSTAT_DEV_INT_MASK (0x80000000U)VUSB_INTSTAT_DEV_INT_SHIFT (31U)VUSB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)VUSB_INTEN_EP_INT_EN_MASK (0x3FFU)VUSB_INTEN_EP_INT_EN_SHIFT (0U)VUSB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)VUSB_INTEN_FRAME_INT_EN_MASK (0x40000000U)VUSB_INTEN_FRAME_INT_EN_SHIFT (30U)VUSB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)VUSB_INTEN_DEV_INT_EN_MASK (0x80000000U)VUSB_INTEN_DEV_INT_EN_SHIFT (31U)VUSB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)VUSB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)VUSB_INTSETSTAT_EP_SET_INT_SHIFT (0U)VUSB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)VUSB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)VUSB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)VUSB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)VUSB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)VUSB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)VUSB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)VUSB_EPTOGGLE_TOGGLE_MASK (0x3FFU)VUSB_EPTOGGLE_TOGGLE_SHIFT (0U)VUSB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)VUSB0_BASE (0x40084000u)VUSB0 ((USB_Type *)USB0_BASE)VUSB_BASE_ADDRS { USB0_BASE }VUSB_BASE_PTRS { USB0 }VUSB_IRQS { USB0_IRQn }VUSB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }VUSBFSH_HCREVISION_REV_MASK (0xFFU)VUSBFSH_HCREVISION_REV_SHIFT (0U)VUSBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)VUSBFSH_HCCONTROL_CBSR_MASK (0x3U)VUSBFSH_HCCONTROL_CBSR_SHIFT (0U)VUSBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)VUSBFSH_HCCONTROL_PLE_MASK (0x4U)VUSBFSH_HCCONTROL_PLE_SHIFT (2U)VUSBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)VUSBFSH_HCCONTROL_IE_MASK (0x8U)VUSBFSH_HCCONTROL_IE_SHIFT (3U)VUSBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)VUSBFSH_HCCONTROL_CLE_MASK (0x10U)VUSBFSH_HCCONTROL_CLE_SHIFT (4U)VUSBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)VUSBFSH_HCCONTROL_BLE_MASK (0x20U)WUSBFSH_HCCONTROL_BLE_SHIFT (5U)WUSBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)WUSBFSH_HCCONTROL_HCFS_MASK (0xC0U)WUSBFSH_HCCONTROL_HCFS_SHIFT (6U)WUSBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)WUSBFSH_HCCONTROL_IR_MASK (0x100U)WUSBFSH_HCCONTROL_IR_SHIFT (8U)WUSBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)WUSBFSH_HCCONTROL_RWC_MASK (0x200U)WUSBFSH_HCCONTROL_RWC_SHIFT (9U)WUSBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)WUSBFSH_HCCONTROL_RWE_MASK (0x400U)WUSBFSH_HCCONTROL_RWE_SHIFT (10U)WUSBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)WUSBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)WUSBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)WUSBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)WUSBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)WUSBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)WUSBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)WUSBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)WUSBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)WUSBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)WUSBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)WUSBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)WUSBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)WUSBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)WUSBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)WUSBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)WUSBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)WUSBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)WUSBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)WUSBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)WUSBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)WUSBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)WUSBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)WUSBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)WUSBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)WUSBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)WUSBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)WUSBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)WUSBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)WUSBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)WUSBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)WUSBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)WUSBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)WUSBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)WUSBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)WUSBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)WUSBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)WUSBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)WUSBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)WUSBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)WUSBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)WUSBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)WUSBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)WUSBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)WUSBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)WUSBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)WUSBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)WUSBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)WUSBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)WUSBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)WUSBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)WUSBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)WUSBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)WUSBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)WUSBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)WUSBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)WUSBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)WUSBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)WUSBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)WUSBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)WUSBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)WUSBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)WUSBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)WUSBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)WUSBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)WUSBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)WUSBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)WUSBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)WUSBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)WUSBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)WUSBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)WUSBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)WUSBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)WUSBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)WUSBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)WUSBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)WUSBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)WUSBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)WUSBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)WUSBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)WUSBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)WUSBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)WUSBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)WUSBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)WUSBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)WUSBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)WUSBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)WUSBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)WUSBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)WUSBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)WUSBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)WUSBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)WUSBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)WUSBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)WUSBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)WUSBFSH_HCHCCA_HCCA_SHIFT (8U)WUSBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)WUSBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)WUSBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)WUSBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)WUSBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)XUSBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)XUSBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)XUSBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)XUSBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)XUSBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)XUSBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)XUSBFSH_HCBULKHEADED_BHED_SHIFT (4U)XUSBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)XUSBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)XUSBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)XUSBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)XUSBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)XUSBFSH_HCDONEHEAD_DH_SHIFT (4U)XUSBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)XUSBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)XUSBFSH_HCFMINTERVAL_FI_SHIFT (0U)XUSBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)XUSBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)XUSBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)XUSBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)XUSBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)XUSBFSH_HCFMINTERVAL_FIT_SHIFT (31U)XUSBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)XUSBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)XUSBFSH_HCFMREMAINING_FR_SHIFT (0U)XUSBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)XUSBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)XUSBFSH_HCFMREMAINING_FRT_SHIFT (31U)XUSBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)XUSBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)XUSBFSH_HCFMNUMBER_FN_SHIFT (0U)XUSBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)XUSBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)XUSBFSH_HCPERIODICSTART_PS_SHIFT (0U)XUSBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)XUSBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)XUSBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)XUSBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)XUSBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)XUSBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)XUSBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)XUSBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)XUSBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)XUSBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)XUSBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)XUSBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)XUSBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)XUSBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)XUSBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)XUSBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)XUSBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)XUSBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)XUSBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)XUSBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)XUSBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)XUSBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)XUSBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)XUSBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)XUSBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)XUSBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)XUSBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)XUSBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)XUSBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)XUSBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)XUSBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)XUSBFSH_HCRHSTATUS_LPS_MASK (0x1U)XUSBFSH_HCRHSTATUS_LPS_SHIFT (0U)XUSBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)XUSBFSH_HCRHSTATUS_OCI_MASK (0x2U)XUSBFSH_HCRHSTATUS_OCI_SHIFT (1U)XUSBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)XUSBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)XUSBFSH_HCRHSTATUS_DRWE_SHIFT (15U)XUSBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)XUSBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)XUSBFSH_HCRHSTATUS_LPSC_SHIFT (16U)XUSBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)XUSBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)XUSBFSH_HCRHSTATUS_OCIC_SHIFT (17U)XUSBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)XUSBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)XUSBFSH_HCRHSTATUS_CRWE_SHIFT (31U)XUSBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)XUSBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)XUSBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)XUSBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)XUSBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)XUSBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)XUSBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)XUSBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)XUSBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)XUSBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)XUSBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)XUSBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)XUSBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)XUSBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)XUSBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)XUSBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)XUSBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)XUSBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)XUSBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)XUSBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)YUSBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)YUSBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)YUSBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)YUSBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)YUSBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)YUSBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)YUSBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)YUSBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)YUSBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)YUSBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)YUSBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)YUSBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)YUSBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)YUSBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)YUSBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)YUSBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)YUSBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)YUSBFSH_PORTMODE_ID_MASK (0x1U)YUSBFSH_PORTMODE_ID_SHIFT (0U)YUSBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)YUSBFSH_PORTMODE_ID_EN_MASK (0x100U)YUSBFSH_PORTMODE_ID_EN_SHIFT (8U)YUSBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)YUSBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)YUSBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)YUSBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)YUSBFSH_BASE (0x400A2000u)YUSBFSH ((USBFSH_Type *)USBFSH_BASE)YUSBFSH_BASE_ADDRS { USBFSH_BASE }YUSBFSH_BASE_PTRS { USBFSH }YUSBFSH_IRQS { USB0_IRQn }YUSBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }YUSBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)YUSBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)YUSBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)YUSBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)YUSBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)YUSBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)YUSBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)YUSBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)YUSBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)YUSBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)YUSBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)YUSBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)YUSBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U)YUSBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U)YUSBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)YUSBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)YUSBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)YUSBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)YUSBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)YUSBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)YUSBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)YUSBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)YUSBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)YUSBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)YUSBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)YUSBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)YUSBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)YUSBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)YUSBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)YUSBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)YUSBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)YUSBHSD_DEVCMDSTAT_DCON_SHIFT (16U)YUSBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)YUSBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)YUSBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)YUSBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)YUSBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)ZUSBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)ZUSBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)ZUSBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)ZUSBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)ZUSBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)ZUSBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)ZUSBHSD_DEVCMDSTAT_Speed_SHIFT (22U)ZUSBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)ZUSBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)ZUSBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)ZUSBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)ZUSBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)ZUSBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)ZUSBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)ZUSBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)ZUSBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)ZUSBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)ZUSBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)ZUSBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)ZUSBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)ZUSBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)ZUSBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)ZUSBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)ZUSBHSD_INFO_FRAME_NR_MASK (0x7FFU)ZUSBHSD_INFO_FRAME_NR_SHIFT (0U)ZUSBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)ZUSBHSD_INFO_ERR_CODE_MASK (0x7800U)ZUSBHSD_INFO_ERR_CODE_SHIFT (11U)ZUSBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)ZUSBHSD_INFO_Minrev_MASK (0xFF0000U)ZUSBHSD_INFO_Minrev_SHIFT (16U)ZUSBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)ZUSBHSD_INFO_Majrev_MASK (0xFF000000U)ZUSBHSD_INFO_Majrev_SHIFT (24U)ZUSBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)ZUSBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)ZUSBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)ZUSBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)ZUSBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)ZUSBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)ZUSBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)ZUSBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU)ZUSBHSD_DATABUFSTART_DA_BUF_SHIFT (0U)ZUSBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)ZUSBHSD_LPM_HIRD_HW_MASK (0xFU)ZUSBHSD_LPM_HIRD_HW_SHIFT (0U)ZUSBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)ZUSBHSD_LPM_HIRD_SW_MASK (0xF0U)ZUSBHSD_LPM_HIRD_SW_SHIFT (4U)ZUSBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)ZUSBHSD_LPM_DATA_PENDING_MASK (0x100U)ZUSBHSD_LPM_DATA_PENDING_SHIFT (8U)ZUSBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)ZUSBHSD_EPSKIP_SKIP_MASK (0xFFFU)ZUSBHSD_EPSKIP_SKIP_SHIFT (0U)ZUSBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)ZUSBHSD_EPINUSE_BUF_MASK (0xFFCU)ZUSBHSD_EPINUSE_BUF_SHIFT (2U)ZUSBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)ZUSBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)ZUSBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)ZUSBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)ZUSBHSD_INTSTAT_EP0OUT_MASK (0x1U)ZUSBHSD_INTSTAT_EP0OUT_SHIFT (0U)ZUSBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)ZUSBHSD_INTSTAT_EP0IN_MASK (0x2U)ZUSBHSD_INTSTAT_EP0IN_SHIFT (1U)ZUSBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)ZUSBHSD_INTSTAT_EP1OUT_MASK (0x4U)ZUSBHSD_INTSTAT_EP1OUT_SHIFT (2U)ZUSBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)ZUSBHSD_INTSTAT_EP1IN_MASK (0x8U)ZUSBHSD_INTSTAT_EP1IN_SHIFT (3U)ZUSBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)ZUSBHSD_INTSTAT_EP2OUT_MASK (0x10U)ZUSBHSD_INTSTAT_EP2OUT_SHIFT (4U)ZUSBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)ZUSBHSD_INTSTAT_EP2IN_MASK (0x20U)ZUSBHSD_INTSTAT_EP2IN_SHIFT (5U)ZUSBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)ZUSBHSD_INTSTAT_EP3OUT_MASK (0x40U)ZUSBHSD_INTSTAT_EP3OUT_SHIFT (6U)ZUSBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)ZUSBHSD_INTSTAT_EP3IN_MASK (0x80U)ZUSBHSD_INTSTAT_EP3IN_SHIFT (7U)ZUSBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)ZUSBHSD_INTSTAT_EP4OUT_MASK (0x100U)ZUSBHSD_INTSTAT_EP4OUT_SHIFT (8U)ZUSBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)ZUSBHSD_INTSTAT_EP4IN_MASK (0x200U)ZUSBHSD_INTSTAT_EP4IN_SHIFT (9U)ZUSBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)ZUSBHSD_INTSTAT_EP5OUT_MASK (0x400U)ZUSBHSD_INTSTAT_EP5OUT_SHIFT (10U)ZUSBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)ZUSBHSD_INTSTAT_EP5IN_MASK (0x800U)ZUSBHSD_INTSTAT_EP5IN_SHIFT (11U)ZUSBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)ZUSBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)ZUSBHSD_INTSTAT_FRAME_INT_SHIFT (30U)ZUSBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)ZUSBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)ZUSBHSD_INTSTAT_DEV_INT_SHIFT (31U)ZUSBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)ZUSBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)ZUSBHSD_INTEN_EP_INT_EN_SHIFT (0U)ZUSBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)ZUSBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)ZUSBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)ZUSBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)[USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)[USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)[USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)[USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)[USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)[USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)[USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)[USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)[USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)[USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)[USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)[USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)[USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)[USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)[USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)[USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU)[USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U)[USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK)[USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U)[USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U)[USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK)[USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U)[USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U)[USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK)[USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U)[USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U)[USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK)[USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U)[USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U)[USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK)[USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U)[USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U)[USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK)[USBHSD_BASE (0x40094000u)[USBHSD ((USBHSD_Type *)USBHSD_BASE)[USBHSD_BASE_ADDRS { USBHSD_BASE }[USBHSD_BASE_PTRS { USBHSD }[USBHSD_IRQS { USB1_IRQn }[USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }[USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)[USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)[USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)[USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)[USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)[USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)[USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)[USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)[USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)[USBHSH_HCSPARAMS_PPC_MASK (0x10U)[USBHSH_HCSPARAMS_PPC_SHIFT (4U)[USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)[USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)[USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)[USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)[USBHSH_HCCPARAMS_LPMC_MASK (0x20000U)\USBHSH_HCCPARAMS_LPMC_SHIFT (17U)\USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)\USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)\USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)\USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)\USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)\USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)\USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)\USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U)\USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U)\USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)\USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U)\USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U)\USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)\USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U)\USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)\USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)\USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U)\USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U)\USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)\USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U)\USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)\USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)\USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U)\USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U)\USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)\USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)\USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)\USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)\USBHSH_USBCMD_RS_MASK (0x1U)\USBHSH_USBCMD_RS_SHIFT (0U)\USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)\USBHSH_USBCMD_HCRESET_MASK (0x2U)\USBHSH_USBCMD_HCRESET_SHIFT (1U)\USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)\USBHSH_USBCMD_FLS_MASK (0xCU)\USBHSH_USBCMD_FLS_SHIFT (2U)\USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)\USBHSH_USBCMD_LHCR_MASK (0x80U)\USBHSH_USBCMD_LHCR_SHIFT (7U)\USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)\USBHSH_USBCMD_ATL_EN_MASK (0x100U)\USBHSH_USBCMD_ATL_EN_SHIFT (8U)\USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)\USBHSH_USBCMD_ISO_EN_MASK (0x200U)\USBHSH_USBCMD_ISO_EN_SHIFT (9U)\USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)\USBHSH_USBCMD_INT_EN_MASK (0x400U)\USBHSH_USBCMD_INT_EN_SHIFT (10U)\USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)\USBHSH_USBCMD_HIRD_MASK (0xF000000U)\USBHSH_USBCMD_HIRD_SHIFT (24U)\USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)\USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U)\USBHSH_USBCMD_LPM_RWU_SHIFT (28U)\USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK)\USBHSH_USBSTS_PCD_MASK (0x4U)\USBHSH_USBSTS_PCD_SHIFT (2U)\USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)\USBHSH_USBSTS_FLR_MASK (0x8U)\USBHSH_USBSTS_FLR_SHIFT (3U)\USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)\USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)\USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)\USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)\USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)\USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)\USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)\USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)\USBHSH_USBSTS_INT_IRQ_SHIFT (18U)\USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)\USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)\USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)\USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)\USBHSH_USBINTR_PCDE_MASK (0x4U)\USBHSH_USBINTR_PCDE_SHIFT (2U)\USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)\USBHSH_USBINTR_FLRE_MASK (0x8U)\USBHSH_USBINTR_FLRE_SHIFT (3U)\USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)\USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)\USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)\USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)\USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)\USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)\USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)\USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)\USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)\USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)\USBHSH_USBINTR_SOF_E_MASK (0x80000U)\USBHSH_USBINTR_SOF_E_SHIFT (19U)\USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)\USBHSH_PORTSC1_CCS_MASK (0x1U)\USBHSH_PORTSC1_CCS_SHIFT (0U)\USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)\USBHSH_PORTSC1_CSC_MASK (0x2U)\USBHSH_PORTSC1_CSC_SHIFT (1U)\USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)\USBHSH_PORTSC1_PED_MASK (0x4U)\USBHSH_PORTSC1_PED_SHIFT (2U)\USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)\USBHSH_PORTSC1_PEDC_MASK (0x8U)\USBHSH_PORTSC1_PEDC_SHIFT (3U)\USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)\USBHSH_PORTSC1_OCA_MASK (0x10U)\USBHSH_PORTSC1_OCA_SHIFT (4U)\USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)\USBHSH_PORTSC1_OCC_MASK (0x20U)\USBHSH_PORTSC1_OCC_SHIFT (5U)\USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)]USBHSH_PORTSC1_FPR_MASK (0x40U)]USBHSH_PORTSC1_FPR_SHIFT (6U)]USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)]USBHSH_PORTSC1_SUSP_MASK (0x80U)]USBHSH_PORTSC1_SUSP_SHIFT (7U)]USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)]USBHSH_PORTSC1_PR_MASK (0x100U)]USBHSH_PORTSC1_PR_SHIFT (8U)]USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)]USBHSH_PORTSC1_SUS_L1_MASK (0x200U)]USBHSH_PORTSC1_SUS_L1_SHIFT (9U)]USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)]USBHSH_PORTSC1_LS_MASK (0xC00U)]USBHSH_PORTSC1_LS_SHIFT (10U)]USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)]USBHSH_PORTSC1_PP_MASK (0x1000U)]USBHSH_PORTSC1_PP_SHIFT (12U)]USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)]USBHSH_PORTSC1_PIC_MASK (0xC000U)]USBHSH_PORTSC1_PIC_SHIFT (14U)]USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)]USBHSH_PORTSC1_PTC_MASK (0xF0000U)]USBHSH_PORTSC1_PTC_SHIFT (16U)]USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)]USBHSH_PORTSC1_PSPD_MASK (0x300000U)]USBHSH_PORTSC1_PSPD_SHIFT (20U)]USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)]USBHSH_PORTSC1_WOO_MASK (0x400000U)]USBHSH_PORTSC1_WOO_SHIFT (22U)]USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)]USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U)]USBHSH_PORTSC1_SUS_STAT_SHIFT (23U)]USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)]USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U)]USBHSH_PORTSC1_DEV_ADD_SHIFT (25U)]USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)]USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU)]USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U)]USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)]USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU)]USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U)]USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)]USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU)]USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U)]USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)]USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU)]USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U)]USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)]USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU)]USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U)]USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)]USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU)]USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U)]USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)]USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU)]USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U)]USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK)]USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U)]USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U)]USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK)]USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U)]USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U)]USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U)]USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK)]USBHSH_PORTMODE_ID0_MASK (0x1U)]USBHSH_PORTMODE_ID0_SHIFT (0U)]USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)]USBHSH_PORTMODE_ID0_EN_MASK (0x100U)]USBHSH_PORTMODE_ID0_EN_SHIFT (8U)]USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)]USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)]USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)]USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)]USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)]USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)]USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)]USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)]USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)]USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)]USBHSH_BASE (0x400A3000u)]USBHSH ((USBHSH_Type *)USBHSH_BASE)]USBHSH_BASE_ADDRS { USBHSH_BASE }^USBHSH_BASE_PTRS { USBHSH }^USBHSH_IRQS { USB1_IRQn }^USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }^UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)^UTICK_CTRL_DELAYVAL_SHIFT (0U)^UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)^UTICK_CTRL_REPEAT_MASK (0x80000000U)^UTICK_CTRL_REPEAT_SHIFT (31U)^UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)^UTICK_STAT_INTR_MASK (0x1U)^UTICK_STAT_INTR_SHIFT (0U)^UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)^UTICK_STAT_ACTIVE_MASK (0x2U)^UTICK_STAT_ACTIVE_SHIFT (1U)^UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)^UTICK_CFG_CAPEN0_MASK (0x1U)^UTICK_CFG_CAPEN0_SHIFT (0U)^UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)^UTICK_CFG_CAPEN1_MASK (0x2U)^UTICK_CFG_CAPEN1_SHIFT (1U)^UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)^UTICK_CFG_CAPEN2_MASK (0x4U)^UTICK_CFG_CAPEN2_SHIFT (2U)^UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)^UTICK_CFG_CAPEN3_MASK (0x8U)^UTICK_CFG_CAPEN3_SHIFT (3U)^UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)^UTICK_CFG_CAPPOL0_MASK (0x100U)^UTICK_CFG_CAPPOL0_SHIFT (8U)^UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)^UTICK_CFG_CAPPOL1_MASK (0x200U)^UTICK_CFG_CAPPOL1_SHIFT (9U)^UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)^UTICK_CFG_CAPPOL2_MASK (0x400U)^UTICK_CFG_CAPPOL2_SHIFT (10U)^UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)^UTICK_CFG_CAPPOL3_MASK (0x800U)^UTICK_CFG_CAPPOL3_SHIFT (11U)^UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)^UTICK_CAPCLR_CAPCLR0_MASK (0x1U)^UTICK_CAPCLR_CAPCLR0_SHIFT (0U)^UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)^UTICK_CAPCLR_CAPCLR1_MASK (0x2U)^UTICK_CAPCLR_CAPCLR1_SHIFT (1U)^UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)^UTICK_CAPCLR_CAPCLR2_MASK (0x4U)^UTICK_CAPCLR_CAPCLR2_SHIFT (2U)^UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)^UTICK_CAPCLR_CAPCLR3_MASK (0x8U)^UTICK_CAPCLR_CAPCLR3_SHIFT (3U)^UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)^UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)^UTICK_CAP_CAP_VALUE_SHIFT (0U)^UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)^UTICK_CAP_VALID_MASK (0x80000000U)^UTICK_CAP_VALID_SHIFT (31U)^UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)^UTICK_CAP_COUNT (4U)^UTICK0_BASE (0x4000E000u)^UTICK0 ((UTICK_Type *)UTICK0_BASE)^UTICK_BASE_ADDRS { UTICK0_BASE }^UTICK_BASE_PTRS { UTICK0 }^UTICK_IRQS { UTICK0_IRQn }_WWDT_MOD_WDEN_MASK (0x1U)_WWDT_MOD_WDEN_SHIFT (0U)_WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)_WWDT_MOD_WDRESET_MASK (0x2U)_WWDT_MOD_WDRESET_SHIFT (1U)_WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)_WWDT_MOD_WDTOF_MASK (0x4U)_WWDT_MOD_WDTOF_SHIFT (2U)_WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)_WWDT_MOD_WDINT_MASK (0x8U)_WWDT_MOD_WDINT_SHIFT (3U)_WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)_WWDT_MOD_WDPROTECT_MASK (0x10U)_WWDT_MOD_WDPROTECT_SHIFT (4U)_WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)_WWDT_MOD_LOCK_MASK (0x20U)_WWDT_MOD_LOCK_SHIFT (5U)_WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)_WWDT_TC_COUNT_MASK (0xFFFFFFU)_WWDT_TC_COUNT_SHIFT (0U)_WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)_WWDT_FEED_FEED_MASK (0xFFU)_WWDT_FEED_FEED_SHIFT (0U)_WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)_WWDT_TV_COUNT_MASK (0xFFFFFFU)_WWDT_TV_COUNT_SHIFT (0U)_WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)_WWDT_WARNINT_WARNINT_MASK (0x3FFU)_WWDT_WARNINT_WARNINT_SHIFT (0U)_WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)_WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)_WWDT_WINDOW_WINDOW_SHIFT (0U)_WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)_WWDT_BASE (0x4000C000u)_WWDT ((WWDT_Type *)WWDT_BASE)_WWDT_BASE_ADDRS { WWDT_BASE }_WWDT_BASE_PTRS { WWDT }_WWDT_IRQS { WDT_BOD_IRQn }`NXP_VAL2FLD(field,value) (((value) << (field ## _SHIFT)) & (field ## _MASK))`NXP_FLD2VAL(field,value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))`EMC_CS0_BASE (0x80000000u)`EMC_CS1_BASE (0x90000000u)`EMC_CS2_BASE (0x98000000u)`EMC_CS3_BASE (0x9C000000u)`EMC_DYCS0_BASE (0xA0000000u)`EMC_DYCS1_BASE (0xB0000000u)`EMC_DYCS2_BASE (0xC0000000u)`EMC_DYCS3_BASE (0xD0000000u)`EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}`EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}`ROM_API_BASE (0x03000200u)`ROM_API (*(ROM_API_Type**) ROM_API_BASE)`OTP_API (ROM_API->otpApiBase)__string_h __ARMCLIB_VERSION 5060034_ARMABI __declspec(__nothrow)__STRING_DECLS __CLIBNS$__CLIBNS 7NULL8NULL 0 __stdint_h  __ARMCLIB_VERSION 5060034__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS sINT8_MIN -128tINT16_MIN -32768uINT32_MIN (~0x7fffffff)vINT64_MIN __INT64_C(~0x7fffffffffffffff)yINT8_MAX 127zINT16_MAX 32767{INT32_MAX 2147483647|INT64_MAX __INT64_C(9223372036854775807)UINT8_MAX 255UINT16_MAX 65535UINT32_MAX 4294967295uUINT64_MAX __UINT64_C(18446744073709551615)INT_LEAST8_MIN -128INT_LEAST16_MIN -32768INT_LEAST32_MIN (~0x7fffffff)INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_LEAST8_MAX 127INT_LEAST16_MAX 32767INT_LEAST32_MAX 2147483647INT_LEAST64_MAX __INT64_C(9223372036854775807)UINT_LEAST8_MAX 255UINT_LEAST16_MAX 65535UINT_LEAST32_MAX 4294967295uUINT_LEAST64_MAX __UINT64_C(18446744073709551615)INT_FAST8_MIN (~0x7fffffff)INT_FAST16_MIN (~0x7fffffff)INT_FAST32_MIN (~0x7fffffff)INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_FAST8_MAX 2147483647INT_FAST16_MAX 2147483647INT_FAST32_MAX 2147483647INT_FAST64_MAX __INT64_C(9223372036854775807)UINT_FAST8_MAX 4294967295uUINT_FAST16_MAX 4294967295uUINT_FAST32_MAX 4294967295uUINT_FAST64_MAX __UINT64_C(18446744073709551615)INTPTR_MIN INT32_MININTPTR_MAX INT32_MAXUINTPTR_MAX UINT32_MAXINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)INTMAX_MAX __ESCAPE__(9223372036854775807ll)UINTMAX_MAX __ESCAPE__(18446744073709551615ull)PTRDIFF_MIN INT32_MINPTRDIFF_MAX INT32_MAXSIG_ATOMIC_MIN (~0x7fffffff)SIG_ATOMIC_MAX 2147483647SIZE_MAX UINT32_MAXWCHAR_MINWCHAR_MAXWCHAR_MIN 0WCHAR_MAX 65535WINT_MIN (~0x7fffffff)WINT_MAX 2147483647INT8_C(x) (x)INT16_C(x) (x)INT32_C(x) (x)INT64_C(x) __INT64_C(x)UINT8_C(x) (x ## u)UINT16_C(x) (x ## u)UINT32_C(x) (x ## u)UINT64_C(x) __UINT64_C(x)INTMAX_C(x) __ESCAPE__(x ## ll)UINTMAX_C(x) __ESCAPE__(x ## ull)__INT64__LONGLONG VERS 1"UNKNOWN 0#ONCHIP 1$EXT8BIT 2%EXT16BIT 3&EXT32BIT 4'EXTSPI 5)SECTOR_NUM 512*PAGE_MAX 655361SECTOR_END 0xFFFFFFFF, 0xFFFFFFFFCFLASH_DRV_VERS (0x0100+VERS))DCLOCK_SetupFROClocking$@SPIFI_GetInstancey4SPIFI_GetDefaultConfig)SPIFI_InitSPIFI_DeinitSPIFI_SetCommandYSPIFI_SetMemoryCommandFlashDevice(SPIFI_CheckIfFinishedh SPIFI_EnableQuadModeQSPIFI_InitPinstSPIFI_InitCommandsInitUnInit)EraseChipuEraseSectorBlankCheckEProgramPage2commandconfigbase_adr.@$dlt* 6<"N ^tBcpitt*6tddh*6@386I6`6`q6q6`6`6``6$I6X````````+S|  57&J]XYl=^qx:>j"2D &A^%+5 BVo %4Y ptt8 $t$d$d.realdataFlashPrg.c.rev16_text.revsh_text.textCLOCK_EnableClockIOCON_PinMuxSet.bss.dataFlashDev.c.constdatadevices\\LPC54608\\drivers\\fsl_spifi.cdevices\LPC54608\drivers\fsl_spifi.cs_spifiClocks_spifiBasesdevices\\LPC54608\\drivers\\fsl_clock.cdevices\LPC54608\drivers\fsl_clock.cdc.s../clib/stdlib.c../clib/angel/sysapp.c../clib/signal.c../clib/angel/sys.s../clib/angel/rt.s../clib/signal.sBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$RWPI$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2__asm___10_FlashPrg_c_21f264b4____REV16__asm___11_fsl_spifi_c_d2a84ddf____REV16__asm___11_fsl_clock_c_d9f3d481____REV16__asm___10_FlashPrg_c_21f264b4____REVSH__asm___11_fsl_spifi_c_d2a84ddf____REVSH__asm___11_fsl_clock_c_d9f3d481____REVSHSPIFI_CheckIfFinishedSPIFI_EnableQuadModeSPIFI_InitPinsSPIFI_InitCommandsInitUnInitEraseChipEraseSectorBlankCheckProgramPageSPIFI_GetInstanceSPIFI_GetDefaultConfigSPIFI_InitSPIFI_DeinitSPIFI_SetCommandSPIFI_SetMemoryCommandCLOCK_SetupFROClockingabort_sys_exit__rt_SIGABRT__I$use$semihosting__use_no_semihosting_swi__semihosting_library_function__sig_exit__rt_SIGABRT_inner__default_signal_display_ttywrchbase_adrFlashDevicecommandconfig@ARMComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armlink [4d35e2]ArmLink --strict --load_addr_map_info --map --symbols --diag_suppress=9931,L6305 --cpu=Cortex-M0 --list=.\Out\LPC5460x_MT25QL128.map --output=.\Out\LPC5460x_MT25QL128.axf --scatter=.\Target.lin --info=summarysizes,sizes,totals,unused,veneers C:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\c_pe.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\fz_ps.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\h_pe.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\m_ps.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\vfpsupport.lInput Comments:flashprg.oComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armlink [4d35e2]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,66,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\out\flashprg.o --vfemode=force Input Comments:p2d44-3Component: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]armasm --debug --diag_suppress=9931,9931,66,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide flashprg.oComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621]ArmCC --c99 --debug -c -o.\out\flashprg.o --depend=.\out\flashprg.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931,66 -I.\ -I.\devices\LPC54608 -I.\devices\LPC54608\drivers -I.\RTE\_LPC5460x_MT25QL128 -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\Device\ARM\ARMCM0\Include -D__UVISION_VERSION=524 -D_RTE_ -DARMCM0 -DMT25QL128 -DCPU_LPC54608J512ET180=1 --omf_browse=.\out\flashprg.crf FlashPrg.cflashdev.oComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621]ArmCC --c99 --debug -c -o.\out\flashdev.o --depend=.\out\flashdev.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931,66 -I.\ -I.\devices\LPC54608 -I.\devices\LPC54608\drivers -I.\RTE\_LPC5460x_MT25QL128 -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\Device\ARM\ARMCM0\Include -D__UVISION_VERSION=524 -D_RTE_ -DARMCM0 -DMT25QL128 -DCPU_LPC54608J512ET180=1 --omf_browse=.\out\flashdev.crf FlashDev.cfsl_spifi.oComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armlink [4d35e2]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,66,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\out\fsl_spifi.o --vfemode=force Input Comments:p1520-3Component: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]armasm --debug --diag_suppress=9931,9931,66,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide fsl_spifi.oComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621]ArmCC --c99 --debug -c -o.\out\fsl_spifi.o --depend=.\out\fsl_spifi.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931,66 -I.\ -I.\devices\LPC54608 -I.\devices\LPC54608\drivers -I.\RTE\_LPC5460x_MT25QL128 -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\Device\ARM\ARMCM0\Include -D__UVISION_VERSION=524 -D_RTE_ -DARMCM0 -DMT25QL128 -DCPU_LPC54608J512ET180=1 --omf_browse=.\out\fsl_spifi.crf devices\LPC54608\drivers\fsl_spifi.cfsl_clock.oComponent: ARM Compiler 5.06 update 5 (build 528) Tool: armlink [4d35e2]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,66,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\out\fsl_clock.o --vfemode=force Input Comments:p88-3Component: ARM Compiler 5.06 update 5 (build 528) Tool: armasm [4d35e1]armasm --debug --diag_suppress=9931,9931,66,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide fsl_clock.oComponent: ARM Compiler 5.06 update 5 (build 528) Tool: ArmCC [4d3621]ArmCC --c99 --debug -c -o.\out\fsl_clock.o --depend=.\out\fsl_clock.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931,66 -I.\ -I.\devices\LPC54608 -I.\devices\LPC54608\drivers -I.\RTE\_LPC5460x_MT25QL128 -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\Device\ARM\ARMCM0\Include -D__UVISION_VERSION=524 -D_RTE_ -DARMCM0 -DMT25QL128 -DCPU_LPC54608J512ET180=1 --omf_browse=.\out\fsl_clock.crf devices\LPC54608\drivers\fsl_clock.cPrgCodePrgDataDevDscr.debug_abbrev.debug_frame.debug_info.debug_line.debug_loc.debug_macinfo.debug_pubnames.symtab.strtab.note.comment.shstrtab4t0tt 4l l tDtH' 4@@LPWf v  F~" t' ' l8