ELF( 84 (pF FF>..>.6!x)pdmvp@pG@pG@pG@pG@pG@pG@pGpGpGpGpGpGpGpGuH@@sIsH@@qIoH!@(lHCjIjH!@(gHCfIfHh!@( dHbIH`cH`Fh!C !C]I`_Hi(\Hi@@ZIaZH@i! @BUFFFSHjFSIID F, NIID ( F pGFIID }(  F @$#"F=IID (  pFFF @$+F"F3IID ( p #*L4c`O%K[i$$C"LcaOK3hK@Y K@KL#@#CLccFR+ FI+Oo @ @ @ (?@HIID`Hk! CIcHk(HhI@0ICI` IaHi(нHi! CIaH@8kI@#0ICI@9c IaHIID`$d!FHHDhIBذH@iI@a "@Ca "@CIHaF@j HbFiC@IaFiI@!CIaFiI@Q@!C@IaHk! CIcFi! CIaI1 h"CJ2`pGI1 h"CJ2`pG FF&' "IyD"IyD1hF--HrH@8k tHi!CF#-kF,4 ,$`\ `@x C @!@CjHh!ChI` ZH@8kBWH@8cZHiBXHa ]Hh!C[I`𵅰 FF$ OHHDh---.IHHDh,EH@i! @ G9F2F?Hi:H@8kDH$!HC7Hi!@ @F 4`F +)*1L `/L ` $HHDhpG H@i! @ D!FHHDhF FF!IF !8FA()F F*F#dAFX@Y@C6n @ @#@x DM*@8 @B FYNZH7F5F FW(&nngnn m(`m(O`m(!OHcOHc m(!KHdKHd!HHeHHe!FHAeFHEeDHeDHeBHeBHe@Hf@HfE ](IcpG Hk! @B:HkC9Ic9Hh!I@B"J 2"4U2Hh(/Hh!C-I`,HDh%8F1FMA C!A (F!dAF!H@h!*F AH@h!A+Hk!@()HpG)HHDh@ @..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.c0U != delay_usDWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)@ @6npF F%!F0FF- #"F2!0F`|( t(Fp𵉰F FFF!hFp  hFt!F1B!8F iF8Fz F F%,= 0]( !F0FF-. 0]( F0kBkkk F0FlKl llcCccc!F0FF 0]( F000-(F FFF'3F*F!F F/!hFp  hFt!F1B! A iF F8F F F%,# 0]( F0iBiii F0FjKj jjaCaaa!F0FF-, 0]( F00(F FF,-e 0]( (X@! l@ B- 0]( 0]2Fs!F- 0](!K 0]( F ]2FZ!F 0](!2!.@!@ !HC8F( FF&F0F"!F ;F!F F-L iFr  G ]( 0]( 0] 0]iFv 0Y!F1B! ?  F-;F!F F- 0](;F!F F "!F (F󵍰F' $5F!hFq  hFuG @]( 0@]( 0@] 0@]"1F /FP7 + ("1F 'F, 1F1B!   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".(""?#@1K;C##C#Q?#@#[C#[C#Q?#@#C#Q?#@KC##CC#Q?#@K[C}#[#CC#QFCFBV )Nr%r $  3$ ?#@#CC#Q?#@#CC#Q?#@#C#Q?#@KC##CC"2Q?#@#[C##C"2Q?#@K3Co#[#CC#Q?#@#[C#Q?#@#C###C"2Q?#@#[C#3Q?#@#[C##CC"12Q.@#"lC"d"#3U! FFN "IyD,(h( (h(hFF .jF!F&=F. s d sP d!E U!F&EF.(h(#F&& (h(#"F&!E U"&@F. F(P d sI1 QI Q (h((( (Z((T#"mB ! !Ҳ#'?;@C#"QҲ#;@C#"2Qʲ#;@C##"2QG#Q*VK"QVK"QUK"QTK"Q##["12Q#"2UKKNI QNI QHI QLI QII9 QGI!9 0Q;!I 10QBI9 0QBIQ(h(!hFp!p!Ap t `t a!au u`4I Q3I9 Q2I Q! 0U0F) FH;>h ( FP"$IyD' &!E U>h%> d%(8hF; ;((jF!F<;;()N $  3'  6!E U s%(!E U s %( s!E U. &---З%(-&-!E U-!E U.@! lC d@! lC d!F<;;(s $.%(( $ $ $%(( $ $ $$'B#F<l &<;;(< F sI QI Q/F. " . , . ) .!(!(! @ !C!@@9"@CC!Q@!C?"@C!@ "@CC!Q(@ !CI@A8@CC!Q(@!C!@@9@CC 0Q(@!CI@@9@CC 0Q@!C?"@C!1Q(! @`!C!@!11Q--%(! @!C!@ @ "@CC!Q(@!C!@!Q! 0U a-iiCa-!iCa.!iCa! lC d!y UI QI Q t- `t `t!au u` iFq.-A Hq-с iFHq iFHq-B iFHq-т iFHq iFHq iFq ;;?F FF&,-^!I Fr!F U eZH `ZH`` `ss 0U(h $%,-4*F!F8FF'"!F8FeF "!F8F^F*F!F8FF*F!F8FaF *F!F8FF&. F(x F U!D U0F F',p 0YEB @@@B!1 YIB@FB 0]( 0Y(*F!FF/8F 0YEBB? 0Y(FC( p( 0YB*F!FZF/ 8F$q FCFBV 0YE *F!FF/8F 0YEB8FFF /,--F iFs  wHB(FF  ( - h"C`h)pGIa!apGIa!apGF"l@( pG F "l@( pG Fl( pG F"l@( pG F"l@( pG F@"l@( pG F )ъK{DXpG󵍰 F F -, {( {(((( F(  ( 0~ ! m I BӀ! l@( (y d ^A Fx0@xA Fx0@\(;A Fx0G\d!OC/' F} |( ѝH@}!HCK!xF Hr}!HCK!jF K!8FdFK pCBv?'B>Fp?!I@!1CPP@((h!@(  ((h!C(` m(`m( AQm(m( AQ ((h!C(` FFF .(-]HhCF8FFd FHChCB4` F FOH0FF-, p!0FjF!0F{#CI#?IC- A +C4eFvF/6 >C- A+C4eFvF/6 >C- A+C$eFvF>CAӕ+CeFvFv>CmAӒ[AdvFeFIAA `FAFF%@iAR*C[drFcF FFF*F#FFFF; F850F2/lF r r 4 !(Fw01Fd!p- F*** assertion failed: , file , line F C* B!B  C*R x x@Ix x@IђF )ҋppG) p@I)Ӄ""" B, B#FNF C<"CB1 B BӔF? BRA BӋRAC BKRA B RABRABӋRACBKRAAFRAFpG]IB@BS@"F B- B" B ӉBӉBӉ:В BRA BӋRAC BKRA B RABRABӋRACBKRAAFcFRA[F@B+IBpGcF[@B FF FF Fd x(iFp I & pG(! SIGABRT: Abnormal terminationpF F m-(x(d, x( p FXC!&F^C7 6yAFnC7 6yA&FnC0tFd%xdBc][0GF"  !"3DUfwZ0$Z 1%Z 2&$` '` Z0$Z Z0$Z &Z 'ZZ *@@ܳMIMXRT1015 16mB QuadSPI NOR Flash`d!/!I$ > %%%% %C %C % % %%%C%C&I  ((      1 1 1 1 I8  I I8 4 ! I8 "I#7I$I%I&I 'I(I) * +,-./4  04 14 24 34 44 5.:;9? I6.:;9? 7.:;9G8.:;9? I 9.:;9? :.:;9G ;.:;9? I<.:;9? =.:;9G>.:;9? I@?.:;9? @@.:;9G@A.:;9? I@ B.:;9? @ C.:;9G@ D1E1F1XYWG1XYWH.1I.1@J.1@ K.1L.< 4 I? M.< 4 ? NIOPI:;9QI4 R S TUVW1X4I ,Y4I Z4I[4I,\4I]4I 4 ^4I ,4 _4I4 `4I,4 a4I4 b41 ,c41d41,e41f1g1hI iIjIkI 4 lI ,4 mI4 n1 o1p4I ? q4I? < r4I,s4It5Iu;v=w%x<%%.,armcc+|    (armcc+|  (armcc+|  (armcc+|  (armcc+|   8 T0pA~0<Ax \D0JA~0b&A~0(A|0A~ < X0| A~   0AxAle{ 0A{AvE{0$(A~ L0TA~0rHAz @ \0Az 0": \\ \f D ` 0tAxV A|A 0A|0 A|0 A~0 JA~ \   \0  \> 0L A~N0 NA~0" A~0@ A|0 4A~0L LA~ 0 Z0 ZA| \L 0h \ \0 A} \ 0lA~ \ 06A| 006A| 00,Az 0 H d0:A| 0DA{Ar_{ 0AwArH{ 0bAwAnn{ 0 |AwAr{{ 0AxAtp{ 0lAwAlo{ 0P6AyAl{ 0AxAnk{ 0bAxAnk{ 0>FA{Ap`{ 0AwAh{ 0@A{AlK{$0 AxA`{ 0AwAo{$0RAwAj{ 0$8AxA^{ 0 &A{AR^{ 0&8A{ApY{(0'fA{ApX{A$0l'A{Atu{$0\*AxAd{$0p,"AxAZ{$01jAxAR2{$036AxA{028Az$0 9AwAtj A{A 0:AwAj~{ L h 0: 0: 0: : : \: : ; ; 0.; 0@;AyAl{ 0=XAwAti{ 0h=~AxN A|A 0= 0> 0> 0<> 0F>AyAt{0b?fA{0?:A|$0@rAyAp6{ 0tBAwArD{ 0CzA{Apz{0|CTAz 0ChAwAd{ 08EAxAna{ 0FPAyAve{$0PFAxAlJ A{A 0fGPAyAve{ 0GAyAv{0FI(A|0nI A|0I<A| P l 0I0IA~0pJ^Ax 0Kv0DLA~(0 MAxw {AA 0$NRA|0NZB~ 8 0N 0O 02O 06O :ONOF>~0PA~0PA~0P A~ 0P0P A~ P0P A~0PA~0 Q4A|0QA~I AA 0TQ0AzC:\Keil_v525\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] HDsigned charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_t8 Pint16_t9 Pint32_t: Pint64_t; Puint8_t> Puint16_t? Puint32_t@ Puint64_tA Pint_least8_tG Pint_least16_tH Pint_least32_tI Pint_least64_tJ Puint_least8_tM Puint_least16_tN Puint_least32_tO Puint_least64_tP Pint_fast8_tU Pint_fast16_tV Pint_fast32_tW Pint_fast64_tX Puint_fast8_t[ Puint_fast16_t\ Puint_fast32_t] Puint_fast64_t^ Pintptr_te Puintptr_tf Pintmax_tj!Puintmax_tk!X .\middleware\flexspi/fsl_flexspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash\A_Bool"[Pflexspi_serial_clk_freq_tQcPflexspi_read_sample_clk_tsPflexspi_ipcmd_error_tdPflexspi_lut_seq_tPflexspi_dll_time_t Pflexspi_mem_config_t Pflexspi_operation_tPflexspi_xfer_tkFlexSpiClock_CoreClock kFlexSpiClock_AhbClock kFlexSpiClock_SerialRootClock kFlexSpiClock_IpgClock Pflexspi_clock_type_t_FlexSpiSerialClockFreqkFlexSpiSerialClk_30MHz kFlexSpiSerialClk_50MHz kFlexSpiSerialClk_60MHz kFlexSpiSerialClk_75MHz kFlexSpiSerialClk_80MHz kFlexSpiSerialClk_100MHz kFlexSpiSerialClk_133MHz kFlexSpiSerialClk_166MHz kFlexSpiSerialClk_200MHz kFlexSpiClk_SDR kFlexSpiClk_DDR _FlashReadSampleClkSourcekFlexSPIReadSampleClk_LoopbackInternally kFlexSPIReadSampleClk_LoopbackFromDqsPad kFlexSPIReadSampleClk_LoopbackFromSckPad kFlexSPIReadSampleClk_ExternalInputFromDqsPad  _FlexSpiIpCmdErrorkFlexSpiIpCmdError_NoError kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode kFlexSpiIpCmdError_JumpOnCsInIpCmd kFlexSpiIpCmdError_UnknownOpCode kFlexSpiIpCmdError_SdrDummyInDdrSequence kFlexSpiIpCmdError_DDRDummyInSdrSequence kFlexSpiIpCmdError_InvalidAddress kFlexSpiIpCmdError_SequenceExecutionTimeout kFlexSpiIpCmdError_FlashBoundaryAcrosss  _flexspi_statuskStatus_FLEXSPI_SequenceExecutionTimeoutXkStatus_FLEXSPI_InvalidSequenceYkStatus_FLEXSPI_DeviceTimeoutZkFlexSpiMiscOffset_DiffClkEnable kFlexSpiMiscOffset_Ck2Enable kFlexSpiMiscOffset_ParallelEnable kFlexSpiMiscOffset_WordAddressableEnable kFlexSpiMiscOffset_SafeConfigFreqEnable kFlexSpiMiscOffset_PadSettingOverrideEnable kFlexSpiMiscOffset_DdrModeEnable kFlexSpiMiscOffset_UseValidTimeForAllFreq kFlexSpiDeviceType_SerialNOR kFlexSpiDeviceType_SerialNAND kFlexSpiDeviceType_SerialRAM kFlexSpiDeviceType_MCP_NOR_NAND kFlexSpiDeviceType_MCP_NOR_RAM kSerialFlash_1Pad kSerialFlash_2Pads kSerialFlash_4Pads kSerialFlash_8Pads )_lut_sequenceseqNum<#seqId<#reservedK#kDeviceConfigCmdType_Generic kDeviceConfigCmdType_QuadEnable kDeviceConfigCmdType_Spi2Xpi kDeviceConfigCmdType_Xpi2Spi kDeviceConfigCmdType_Spi2NoCmd kDeviceConfigCmdType_Reset *time_100ps<#delay_cells<#)_FlexSPIConfigtag[#version[#reserved0[#readSampleClkSrc<# dataHoldTime<# dataSetupTime<#columnAddressWidth<#deviceModeCfgEnable<#deviceModeType<#waitTimeCfgCommandsK#deviceModeSeq:#deviceModeArg[#configCmdEnable<#<configModeType? #:configCmdSeqs` # reserved1[#,[configCmdArgs #0reserved2[#<controllerMiscOption[#@deviceType<#DsflashPadType<#EserialClkFreq<#FlutCustomSeqEnable<#G[reserved3@ #HsflashA1Size[#PsflashA2Size[#TsflashB1Size[#XsflashB2Size[#\csPadSettingOverride[#`sclkPadSettingOverride[#ddataPadSettingOverride[#hdqsPadSettingOverride[#ltimeoutInMs[#pcommandInterval[#tTdataValidTime_ #xbusyOffsetK#|busyBitPolarityK#~[?lookupTable #: lutCustomSeq #[reserved4 #_FlexSPIOperationTypekFlexSpiOperation_Command kFlexSpiOperation_Config kFlexSpiOperation_Write kFlexSpiOperation_Read kFlexSpiOperation_End )_FlexSpiXfer$operation#baseAddress[#seqId[#seqNum[# isParallelModeEnable#txBuffer#txSize[#rxBuffer#rxSize[# 8 ..\..\..\..\devices\MIMXRT1015\MIMXRT1015.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash8CIRQnNotAvail_IRQnNonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnDMA0_DMA16_IRQnDMA1_DMA17_IRQnDMA2_DMA18_IRQnDMA3_DMA19_IRQnDMA4_DMA20_IRQnDMA5_DMA21_IRQnDMA6_DMA22_IRQnDMA7_DMA23_IRQnDMA8_DMA24_IRQnDMA9_DMA25_IRQn DMA10_DMA26_IRQn DMA11_DMA27_IRQn DMA12_DMA28_IRQn DMA13_DMA29_IRQn DMA14_DMA30_IRQnDMA15_DMA31_IRQnDMA_ERROR_IRQnCTI0_ERROR_IRQnCTI1_ERROR_IRQnCORE_IRQnLPUART1_IRQnLPUART2_IRQnLPUART3_IRQnLPUART4_IRQnReserved40_IRQnReserved41_IRQnReserved42_IRQnReserved43_IRQnLPI2C1_IRQnLPI2C2_IRQnReserved46_IRQnReserved47_IRQnLPSPI1_IRQn LPSPI2_IRQn!Reserved50_IRQn"Reserved51_IRQn#Reserved52_IRQn$Reserved53_IRQn%FLEXRAM_IRQn&KPP_IRQn'Reserved56_IRQn(GPR_IRQ_IRQn)Reserved58_IRQn*Reserved59_IRQn+Reserved60_IRQn,WDOG2_IRQn-SNVS_HP_WRAPPER_IRQn.SNVS_HP_WRAPPER_TZ_IRQn/SNVS_LP_WRAPPER_IRQn0CSU_IRQn1DCP_IRQn2DCP_VMI_IRQn3Reserved68_IRQn4TRNG_IRQn5Reserved70_IRQn6BEE_IRQn7SAI1_IRQn8SAI2_IRQn9SAI3_RX_IRQn:SAI3_TX_IRQn;SPDIF_IRQn<PMU_IRQn=Reserved78_IRQn>TEMP_LOW_HIGH_IRQn?TEMP_PANIC_IRQnUSB_PHY_IRQnReserved82_IRQnADC1_IRQnReserved84_IRQnDCDC_IRQnReserved86_IRQnReserved87_IRQnGPIO1_INT0_IRQnGPIO1_INT1_IRQnGPIO1_INT2_IRQnGPIO1_INT3_IRQnGPIO1_INT4_IRQnGPIO1_INT5_IRQnGPIO1_INT6_IRQnGPIO1_INT7_IRQnGPIO1_Combined_0_15_IRQnGPIO1_Combined_16_31_IRQnGPIO2_Combined_0_15_IRQnGPIO2_Combined_16_31_IRQnGPIO3_Combined_0_15_IRQnGPIO3_Combined_16_31_IRQnReserved102_IRQnReserved103_IRQnGPIO5_Combined_0_15_IRQnGPIO5_Combined_16_31_IRQnFLEXIO1_IRQnReserved107_IRQnWDOG1_IRQnRTWDOG_IRQnEWM_IRQnCCM_1_IRQnCCM_2_IRQnGPC_IRQnSRC_IRQnReserved115_IRQnGPT1_IRQnGPT2_IRQnPWM1_0_IRQnPWM1_1_IRQnPWM1_2_IRQnPWM1_3_IRQnPWM1_FAULT_IRQnReserved123_IRQnFLEXSPI_IRQnReserved125_IRQnReserved126_IRQnReserved127_IRQnReserved128_IRQnUSB_OTG1_IRQnReserved130_IRQnReserved131_IRQnXBAR1_IRQ_0_1_IRQnXBAR1_IRQ_2_3_IRQnADC_ETC_IRQ0_IRQnADC_ETC_IRQ1_IRQnADC_ETC_IRQ2_IRQnADC_ETC_ERROR_IRQ_IRQnPIT_IRQnReserved139_IRQnReserved140_IRQnReserved141_IRQnReserved142_IRQnReserved143_IRQnReserved144_IRQnENC1_IRQnReserved146_IRQnReserved147_IRQnReserved148_IRQnTMR1_IRQnPIRQn_Type"_dma_request_sourcekDmaRequestMuxFlexIO1Request0Request1kDmaRequestMuxFlexIO1Request4Request5kDmaRequestMuxLPUART1TxkDmaRequestMuxLPUART1RxkDmaRequestMuxLPUART3TxkDmaRequestMuxLPUART3RxkDmaRequestMuxLPSPI1Rx kDmaRequestMuxLPSPI1TxkDmaRequestMuxLPI2C1kDmaRequestMuxSai1RxkDmaRequestMuxSai1TxkDmaRequestMuxSai2RxkDmaRequestMuxSai2TxkDmaRequestMuxADC_ETCkDmaRequestMuxADC1kDmaRequestMuxFlexSPIRxkDmaRequestMuxFlexSPITxkDmaRequestMuxXBAR1Request0kDmaRequestMuxXBAR1Request1kDmaRequestMuxFlexPWM1CaptureSub0 kDmaRequestMuxFlexPWM1CaptureSub1!kDmaRequestMuxFlexPWM1CaptureSub2"kDmaRequestMuxFlexPWM1CaptureSub3#kDmaRequestMuxFlexPWM1ValueSub0$kDmaRequestMuxFlexPWM1ValueSub1%kDmaRequestMuxFlexPWM1ValueSub2&kDmaRequestMuxFlexPWM1ValueSub3'kDmaRequestMuxQTIMER1CaptTimer00kDmaRequestMuxQTIMER1CaptTimer11kDmaRequestMuxQTIMER1CaptTimer22kDmaRequestMuxQTIMER1CaptTimer33kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer14kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer05kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer36kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer27kDmaRequestMuxFlexIO1Request2Request3@kDmaRequestMuxFlexIO1Request6Request7AkDmaRequestMuxLPUART2TxBkDmaRequestMuxLPUART2RxCkDmaRequestMuxLPUART4TxDkDmaRequestMuxLPUART4RxEkDmaRequestMuxLPSPI2RxMkDmaRequestMuxLPSPI2TxNkDmaRequestMuxLPI2C2QkDmaRequestMuxSai3RxSkDmaRequestMuxSai3TxTkDmaRequestMuxSpdifRxUkDmaRequestMuxSpdifTxVkDmaRequestMuxXBAR1Request2^kDmaRequestMuxXBAR1Request3_Pdma_request_source_t 4_iomuxc_sw_mux_ctl_padkIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 &kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 'kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 (kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 )kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 *kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 +kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 ,kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 -kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 .kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 /kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 0kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 1kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 2kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 3kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 4kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 5kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 @kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 AkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 BkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 CkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 DkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 EkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 MkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 NkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 OkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 PkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 QkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 RkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 SkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 TkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 UkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 VkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 WkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 XPiomuxc_sw_mux_ctl_pad_tF_iomuxc_sw_pad_ctl_padkIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 &kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 'kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 (kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 )kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 *kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 +kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 ,kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 -kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 .kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 /kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 0kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 1kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 2kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 3kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 4kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 5kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 @kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 AkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 BkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 CkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 DkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 EkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 MkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 NkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 OkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 PkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 QkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 RkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 SkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 TkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 UkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 VkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 WkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 XPiomuxc_sw_pad_ctl_pad_taa_iomuxc_select_inputkIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT kIOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_0 kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_1 kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_2 kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_3 kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_0 kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_1 kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_2 kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_3 kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT0_SELECT_INPUT kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT1_SELECT_INPUT kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT2_SELECT_INPUT kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT3_SELECT_INPUT kIOMUXC_FLEXSPI_IPP_IND_SCK_FA_SELECT_INPUT kIOMUXC_LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT kIOMUXC_LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT !kIOMUXC_LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT "kIOMUXC_LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT #kIOMUXC_LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 (kIOMUXC_LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT )kIOMUXC_LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT *kIOMUXC_LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT +kIOMUXC_LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 ,kIOMUXC_LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT -kIOMUXC_LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT .kIOMUXC_LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT /kIOMUXC_LPUART2_IPP_IND_LPUART_CTS_B_SELECT_INPUT 4kIOMUXC_LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT 5kIOMUXC_LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT 6kIOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT 7kIOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT 8kIOMUXC_LPUART4_IPP_IND_LPUART_CTS_B_SELECT_INPUT 9kIOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT :kIOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT ;kIOMUXC_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT DkIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT EkIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT FkIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT GkIOMUXC_QTIMER1_TMR3_INPUT_SELECT_INPUT HkIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 MkIOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT NkIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 OkIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 PkIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_2 QkIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_3 RkIOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT SkIOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT TkIOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT UkIOMUXC_SAI2_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 VkIOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT WkIOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 XkIOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT YkIOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT ZkIOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT [kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 \kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT ]kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 ^kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT _kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT `kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT akIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT ckIOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT dkIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_14 ikIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_15 jkIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_16 kkIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_17 lkIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_10 mkIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_12 nkIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_13 okIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_18 pkIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_19 qPiomuxc_select_input_t1#ނ_xbar_input_signalkXBARA1_InputLogicLowkXBARA1_InputLogicHighkXBARA1_InputRESERVED2kXBARA1_InputRESERVED3kXBARA1_InputIomuxXbarInout04kXBARA1_InputIomuxXbarInout05kXBARA1_InputIomuxXbarInout06kXBARA1_InputIomuxXbarInout07kXBARA1_InputIomuxXbarInout08kXBARA1_InputIomuxXbarInout09 kXBARA1_InputIomuxXbarInout10 kXBARA1_InputRESERVED11 kXBARA1_InputRESERVED12 kXBARA1_InputRESERVED13 kXBARA1_InputRESERVED14kXBARA1_InputRESERVED15kXBARA1_InputIomuxXbarInout16kXBARA1_InputIomuxXbarInout17kXBARA1_InputRESERVED18kXBARA1_InputRESERVED19kXBARA1_InputRESERVED20kXBARA1_InputRESERVED21kXBARA1_InputRESERVED22kXBARA1_InputRESERVED23kXBARA1_InputRESERVED24kXBARA1_InputRESERVED25kXBARA1_InputRESERVED26kXBARA1_InputRESERVED27kXBARA1_InputRESERVED28kXBARA1_InputRESERVED29kXBARA1_InputRESERVED30kXBARA1_InputRESERVED31kXBARA1_InputQtimer1Tmr0 kXBARA1_InputQtimer1Tmr1!kXBARA1_InputQtimer1Tmr2"kXBARA1_InputQtimer1Tmr3#kXBARA1_InputRESERVED36$kXBARA1_InputRESERVED37%kXBARA1_InputRESERVED38&kXBARA1_InputRESERVED39'kXBARA1_InputFlexpwm1Pwm1OutTrig01(kXBARA1_InputFlexpwm1Pwm2OutTrig01)kXBARA1_InputFlexpwm1Pwm3OutTrig01*kXBARA1_InputFlexpwm1Pwm4OutTrig01+kXBARA1_InputRESERVED44,kXBARA1_InputRESERVED45-kXBARA1_InputRESERVED46.kXBARA1_InputRESERVED47/kXBARA1_InputRESERVED480kXBARA1_InputRESERVED491kXBARA1_InputRESERVED502kXBARA1_InputRESERVED513kXBARA1_InputRESERVED524kXBARA1_InputRESERVED535kXBARA1_InputRESERVED546kXBARA1_InputRESERVED557kXBARA1_InputPitTrigger08kXBARA1_InputPitTrigger19kXBARA1_InputPitTrigger2:kXBARA1_InputPitTrigger3;kXBARA1_InputEnc1PosMatch<kXBARA1_InputRESERVED61=kXBARA1_InputRESERVED62>kXBARA1_InputRESERVED63?kXBARA1_InputDmaDone0@kXBARA1_InputDmaDone1AkXBARA1_InputDmaDone2BkXBARA1_InputDmaDone3CkXBARA1_InputDmaDone4DkXBARA1_InputDmaDone5EkXBARA1_InputDmaDone6FkXBARA1_InputDmaDone7GkXBARA1_InputAoi1Out0HkXBARA1_InputAoi1Out1IkXBARA1_InputAoi1Out2JkXBARA1_InputAoi1Out3KkXBARA1_InputRESERVED76LkXBARA1_InputRESERVED77MkXBARA1_InputRESERVED78NkXBARA1_InputRESERVED79OkXBARA1_InputAdcEtc0Coco0PkXBARA1_InputAdcEtc0Coco1QkXBARA1_InputAdcEtc0Coco2RkXBARA1_InputAdcEtc0Coco3SkXBARA1_InputAdcEtc1Coco0TkXBARA1_InputAdcEtc1Coco1UkXBARA1_InputAdcEtc1Coco2VkXBARA1_InputAdcEtc1Coco3WkXBARB2_InputLogicLowkXBARB2_InputLogicHighkXBARB2_InputRESERVED2kXBARB2_InputRESERVED3kXBARB2_InputRESERVED4kXBARB2_InputRESERVED5kXBARB2_InputRESERVED6kXBARB2_InputRESERVED7kXBARB2_InputRESERVED8kXBARB2_InputRESERVED9 kXBARB2_InputRESERVED10 kXBARB2_InputRESERVED11 kXBARB2_InputQtimer1Tmr0 kXBARB2_InputQtimer1Tmr1 kXBARB2_InputQtimer1Tmr2kXBARB2_InputQtimer1Tmr3kXBARB2_InputRESERVED16kXBARB2_InputRESERVED17kXBARB2_InputRESERVED18kXBARB2_InputRESERVED19kXBARB2_InputFlexpwm1Pwm1OutTrig01kXBARB2_InputFlexpwm1Pwm2OutTrig01kXBARB2_InputFlexpwm1Pwm3OutTrig01kXBARB2_InputFlexpwm1Pwm4OutTrig01kXBARB2_InputRESERVED24kXBARB2_InputRESERVED25kXBARB2_InputRESERVED26kXBARB2_InputRESERVED27kXBARB2_InputRESERVED28kXBARB2_InputRESERVED29kXBARB2_InputRESERVED30kXBARB2_InputRESERVED31kXBARB2_InputRESERVED32 kXBARB2_InputRESERVED33!kXBARB2_InputRESERVED34"kXBARB2_InputRESERVED35#kXBARB2_InputPitTrigger0$kXBARB2_InputPitTrigger1%kXBARB2_InputAdcEtc0Coco0&kXBARB2_InputAdcEtc0Coco1'kXBARB2_InputAdcEtc0Coco2(kXBARB2_InputAdcEtc0Coco3)kXBARB2_InputAdcEtc1Coco0*kXBARB2_InputAdcEtc1Coco1+kXBARB2_InputAdcEtc1Coco2,kXBARB2_InputAdcEtc1Coco3-kXBARB2_InputEnc1PosMatch.kXBARB2_InputRESERVED47/kXBARB2_InputRESERVED480kXBARB2_InputRESERVED491kXBARB2_InputDmaDone02kXBARB2_InputDmaDone13kXBARB2_InputDmaDone24kXBARB2_InputDmaDone35kXBARB2_InputDmaDone46kXBARB2_InputDmaDone57kXBARB2_InputDmaDone68kXBARB2_InputDmaDone79Pxbar_input_signal_t0ť_xbar_output_signalkXBARA1_OutputRESERVED0kXBARA1_OutputRESERVED1kXBARA1_OutputRESERVED2kXBARA1_OutputRESERVED3kXBARA1_OutputRESERVED4kXBARA1_OutputRESERVED5kXBARA1_OutputRESERVED6kXBARA1_OutputRESERVED7kXBARA1_OutputRESERVED8kXBARA1_OutputRESERVED9 kXBARA1_OutputRESERVED10 kXBARA1_OutputRESERVED11 kXBARA1_OutputRESERVED12 kXBARA1_OutputRESERVED13 kXBARA1_OutputRESERVED14kXBARA1_OutputRESERVED15kXBARA1_OutputRESERVED16kXBARA1_OutputRESERVED17kXBARA1_OutputRESERVED18kXBARA1_OutputRESERVED19kXBARA1_OutputRESERVED20kXBARA1_OutputRESERVED21kXBARA1_OutputRESERVED22kXBARA1_OutputRESERVED23kXBARA1_OutputRESERVED24kXBARA1_OutputRESERVED25kXBARA1_OutputFlexpwm1Exta0kXBARA1_OutputFlexpwm1Exta1kXBARA1_OutputFlexpwm1Exta2kXBARA1_OutputFlexpwm1Exta3kXBARA1_OutputFlexpwm1ExtSync0kXBARA1_OutputFlexpwm1ExtSync1kXBARA1_OutputFlexpwm1ExtSync2 kXBARA1_OutputFlexpwm1ExtSync3!kXBARA1_OutputFlexpwm1ExtClk"kXBARA1_OutputFlexpwm1Fault0#kXBARA1_OutputFlexpwm1Fault1$kXBARA1_OutputFlexpwm1Fault2%kXBARA1_OutputFlexpwm1Fault3&kXBARA1_OutputFlexpwm1ExtForce'kXBARA1_OutputRESERVED40(kXBARA1_OutputRESERVED41)kXBARA1_OutputRESERVED42*kXBARA1_OutputRESERVED43+kXBARA1_OutputRESERVED44,kXBARA1_OutputRESERVED45-kXBARA1_OutputRESERVED46.kXBARA1_OutputRESERVED47/kXBARA1_OutputRESERVED480kXBARA1_OutputRESERVED491kXBARA1_OutputRESERVED502kXBARA1_OutputRESERVED513kXBARA1_OutputRESERVED524kXBARA1_OutputRESERVED535kXBARA1_OutputRESERVED546kXBARA1_OutputRESERVED557kXBARA1_OutputRESERVED568kXBARA1_OutputRESERVED579kXBARA1_OutputRESERVED58:kXBARA1_OutputRESERVED59;kXBARA1_OutputRESERVED60<kXBARA1_OutputRESERVED61=kXBARA1_OutputRESERVED62>kXBARA1_OutputRESERVED63?kXBARA1_OutputRESERVED64@kXBARA1_OutputRESERVED65AkXBARA1_OutputEnc1PhaseAInputBkXBARA1_OutputEnc1PhaseBInputCkXBARA1_OutputEnc1IndexDkXBARA1_OutputEnc1HomeEkXBARA1_OutputEnc1TriggerFkXBARA1_OutputRESERVED71GkXBARA1_OutputRESERVED72HkXBARA1_OutputRESERVED73IkXBARA1_OutputRESERVED74JkXBARA1_OutputRESERVED75KkXBARA1_OutputRESERVED76LkXBARA1_OutputRESERVED77MkXBARA1_OutputRESERVED78NkXBARA1_OutputRESERVED79OkXBARA1_OutputRESERVED80PkXBARA1_OutputRESERVED81QkXBARA1_OutputRESERVED82RkXBARA1_OutputRESERVED83SkXBARA1_OutputRESERVED84TkXBARA1_OutputRESERVED85UkXBARA1_OutputQtimer1Tmr0VkXBARA1_OutputQtimer1Tmr1WkXBARA1_OutputQtimer1Tmr2XkXBARA1_OutputQtimer1Tmr3YkXBARA1_OutputRESERVED90ZkXBARA1_OutputRESERVED91[kXBARA1_OutputRESERVED92\kXBARA1_OutputRESERVED93]kXBARA1_OutputRESERVED94^kXBARA1_OutputRESERVED95_kXBARA1_OutputRESERVED96`kXBARA1_OutputRESERVED97akXBARA1_OutputRESERVED98bkXBARA1_OutputRESERVED99ckXBARA1_OutputRESERVED100dkXBARA1_OutputRESERVED101ekXBARA1_OutputEwmEwmInfkXBARA1_OutputAdcEtcTrig00gkXBARA1_OutputAdcEtcTrig01hkXBARA1_OutputAdcEtcTrig02ikXBARA1_OutputAdcEtcTrig03jkXBARA1_OutputAdcEtcTrig10kkXBARA1_OutputAdcEtcTrig11lkXBARA1_OutputAdcEtcTrig12mkXBARA1_OutputAdcEtcTrig13nkXBARA1_OutputLpi2c1TrgInputokXBARA1_OutputLpi2c2TrgInputpkXBARA1_OutputRESERVED113qkXBARA1_OutputRESERVED114rkXBARA1_OutputLpspi1TrgInputskXBARA1_OutputLpspi2TrgInputtkXBARA1_OutputRESERVED117ukXBARA1_OutputRESERVED118vkXBARA1_OutputLpuart1TrgInputwkXBARA1_OutputLpuart2TrgInputxkXBARA1_OutputLpuart3TrgInputykXBARA1_OutputLpuart4TrgInputzkXBARA1_OutputRESERVED123{kXBARA1_OutputRESERVED124|kXBARA1_OutputRESERVED125}kXBARA1_OutputRESERVED126~kXBARA1_OutputFlexio1TriggerIn0kXBARA1_OutputFlexio1TriggerIn1kXBARA1_OutputRESERVED129kXBARA1_OutputRESERVED130kXBARA1_OutputRESERVED131kXBARB2_OutputAoi1In00kXBARB2_OutputAoi1In01kXBARB2_OutputAoi1In02kXBARB2_OutputAoi1In03kXBARB2_OutputAoi1In04kXBARB2_OutputAoi1In05kXBARB2_OutputAoi1In06kXBARB2_OutputAoi1In07kXBARB2_OutputAoi1In08kXBARB2_OutputAoi1In09 kXBARB2_OutputAoi1In10 kXBARB2_OutputAoi1In11 kXBARB2_OutputAoi1In12 kXBARB2_OutputAoi1In13 kXBARB2_OutputAoi1In14kXBARB2_OutputAoi1In15Pxbar_output_signal_tzA*ئ\XSHCR#HSdS# dSRS#$CFGXS#DGCXS#HGSXS#LCVXS#POFSXS#TCALXS#Xt[[t^SPADC_TypeR*(TRIGn_CTRLXS#TRIGn_COUNTERXS#TRIGn_CHAIN_1_0XS#TRIGn_CHAIN_3_2XS# TRIGn_CHAIN_5_4XS#TRIGn_CHAIN_7_6XS#TRIGn_RESULT_1_0dS#TRIGn_RESULT_3_2dS#TRIGn_RESULT_5_4dS# TRIGn_RESULT_7_6dS#$*éCTRLXS#DONE0_1_IRQXS#DONE2_ERR_IRQXS#DMA_CTRLXS# ySTRIGT#PADC_ETC_TypebT *̪TMPRXS#<;RESERVED_0T#OPACRXS#@OPACR1XS#DOPACR2XS#HOPACR3XS#LOPACR4XS#PPAIPSTZ_TypeT *BFCRT01U#BFCRT23U#tK*`UBFCRTU#PAOI_TypeU*HCTRLXS#ADDR_OFFSET0XS#ADDR_OFFSET1XS#AES_KEY0_W0XS# AES_KEY0_W1XS#AES_KEY0_W2XS#AES_KEY0_W3XS#STATUSXS#CTR_NONCE0_W0XS# CTR_NONCE0_W1XS#$CTR_NONCE0_W2XS#(CTR_NONCE0_W3XS#,CTR_NONCE1_W0XS#0CTR_NONCE1_W1XS#4CTR_NONCE1_W2XS#8CTR_NONCE1_W3XS#<REGION1_TOPXS#@REGION1_BOTXS#DPBEE_TypeU*CCRXS#Ȯ<RESERVED_0#CFG2XS#< RESERVED_11k#CFG3XS#< RESERVED_12#CFG4XS#ч< RESERVED_13Ń#CFG5XS#< RESERVED_14#CFG6XS#< RESERVED_15#MEM0XS# ؈< RESERVED_16L# MEM1XS# < RESERVED_17y# MEM2XS# < RESERVED_18# MEM3XS# ߉< RESERVED_19ӄ# MEM4XS# < RESERVED_20# ANA0XS# < RESERVED_21-# ANA1XS# < RESERVED_22Z# ANA2XS# <RESERVED_23# SRK0XS# < RESERVED_24# SRK1XS# < RESERVED_25# SRK2XS# < RESERVED_26# SRK3XS# Ȍ< RESERVED_27<# SRK4XS# < RESERVED_28i# SRK5XS# < RESERVED_29# SRK6XS# ύ< RESERVED_30Æ# SRK7XS# < RESERVED_31# SJC_RESP0XS# < RESERVED_32"# SJC_RESP1XS# < RESERVED_33T# MAC0XS# < RESERVED_34# MAC1XS# < RESERVED_35# GP3XS# <RESERVED_36ڇ# GP1XS# < RESERVED_37# GP2XS# < RESERVED_382# SW_GP1XS# < RESERVED_39a# SW_GP20XS# < RESERVED_40# SW_GP21XS# ͑< RESERVED_41# SW_GP22XS# < RESERVED_42# SW_GP23XS# < RESERVED_43!# MISC_CONF0XS# < RESERVED_44T# MISC_CONF1XS# < RESERVED_45# SRK_REVOKEXS# POCOTP_Typeќ*<RESERVED_0Չ#MEGA_CTRLXS#MEGA_PUPSCRXS#MEGA_PDNSCRXS#MEGA_SRXS#ʔ<oRESERVED_1>#CPU_CTRLXS#CPU_PUPSCRXS#CPU_PDNSCRXS#CPU_SRXS#PPGC_Typeω*LDVALXS#CVALdS#TCTRLXS#TFLGXS# *MCRXS#<RESERVED_0#LTMR64HdS#LTMR64LdS#ʖ<RESERVED_1>#CHANNEL]#PPIT_Type*<RESERVED_0#REG_1P1XS#REG_1P1_SETXS#REG_1P1_CLRXS#REG_1P1_TOGXS#REG_3P0XS#REG_3P0_SETXS#REG_3P0_CLRXS#REG_3P0_TOGXS#REG_2P5XS#REG_2P5_SETXS#REG_2P5_CLRXS#REG_2P5_TOGXS#REG_COREXS#REG_CORE_SETXS#REG_CORE_CLRXS#REG_CORE_TOGXS#MISC0XS#MISC0_SETXS#MISC0_CLRXS#MISC0_TOGXS#MISC1XS#MISC1_SETXS#MISC1_CLRXS#MISC1_TOGXS#MISC2XS#MISC2_SETXS#MISC2_CLRXS#MISC2_TOGXS#PPMU_Type£*`CNTl#INITU#CTRL2U#CTRLU#<RESERVED_0#VAL0U# FRACVAL1U# VAL1U#FRACVAL2U#VAL2U#FRACVAL3U#VAL3U#FRACVAL4U#VAL4U#FRACVAL5U#VAL5U#FRCTRLU# OCTRLU#"STSU#$INTENU#&DMAENU#(TCTRLU#*UDISMAP#,DTCNT0U#0DTCNT1U#2CAPTCTRLAU#4CAPTCOMPAU#6CAPTCTRLBU#8CAPTCOMPBU#:CAPTCTRLXU#<CAPTCOMPXU#>CVAL0l#@CVAL0CYCl#BCVAL1l#DCVAL1CYCl#FCVAL2l#HCVAL2CYCl#JCVAL3l#LCVAL3CYCl#NCVAL4l#PCVAL4CYCl#RCVAL5l#TCVAL5CYCl#VΠ<RESERVED_1B#X*SMg#OUTENU#MASKU#SWCOUTU#DTSRCSELU#MCTRLU#MCTRL2U#FCTRLU#FSTSU#FFILTU#FTSTU#FCTRL2U#PPWM_Typea*<RESERVED_01#ڢXSROMPATCHDP#ROMPATCHCNTLXS#ROMPATCHENH[#ROMPATCHENLXS#XSROMPATCHA#ԣ<RESERVED_1Ǒ#ROMPATCHSRXS#PROMC_Type+*CSXS#CNTXS#TOVALXS#WINXS# PRTWDOG_Type۾*HPLRXS#HPCOMRXS#HPCRXS#HPSICRXS# HPSVCRXS#HPSRXS#HPSVSRXS#HPHACIVRXS#HPHACRdS# HPRTCMRXS#$HPRTCLRXS#(HPTAMRXS#,HPTALRXS#0LPLRXS#4LPCRXS#8LPMKCRXS#<LPSVCRXS#@Ц<RESERVED_0D#DLPTDCRXS#HLPSRXS#LLPSRTCMRXS#PLPSRTCLRXS#TLPTARXS#XLPSMCMRdS#\LPSMCLRdS#`LPPGDRXS#dLPGPR0_LEGACY_ALIASXS#hXSLPZMKR#l<RESERVED_1#XSLPGPR_ALIAS'#Ѩ<_RESERVED_2E#XSLPGPRd#<RESERVED_3|#HPVIDR1dS#HPVIDR2dS#PSNVS_TypeVSSICXSSISdS*TSCRXS#SRCDXS#SRPCXS#SIEXS# Д#SRLdS#SRRdS#SRCSHdS#SRCSLdS# SRUdS#$SRQdS#(STLXS#,STRXS#0STCSCHXS#4STCSCLXS#8<RESERVED_0#<SRFMdS#Dϫ<RESERVED_1Õ#HSTCXS#PPSPDIF_Type*HSCRXS#SBMR1dS#SRSRXS#<RESERVED_0*# SBMR2dS#߬XS GPRU# PSRC_Type*˯<RESERVED_0#TEMPSENSE0XS#TEMPSENSE0_SETXS#TEMPSENSE0_CLRXS#TEMPSENSE0_TOGXS#TEMPSENSE1XS#TEMPSENSE1_SETXS#TEMPSENSE1_CLRXS#TEMPSENSE1_TOGXS#߮<RESERVED_1R#TEMPSENSE2XS#TEMPSENSE2_SETXS#TEMPSENSE2_CLRXS#TEMPSENSE2_TOGXS#PTEMPMON_Type}* COMP1U#COMP2U#CAPTU#LOADU#HOLDU#CNTRU# CTRLU# SCTRLU#CMPLD1U#CMPLD2U#CSCTRLU#FILTU#DMAU#<RESERVED_0#ENBLU#*ձűCHANNEL#PTMR_TypeSPKRMAXXSPKRSQdSSSBLIMXSTOTSAMdSSFRQCNTdSFRQMAXXSSѲSCMCdSSCMLXSSSCR1CdSSCR1LXSSSCR2CdSSCR2LXSSSCR3CdSSCR3LXSSSCR4CdSSCR4LXSSӳSCR5CdSSCR5LXSSSCR6PCdSSCR6PLXS*MCTLXS#SCMISCXS#PKRRNGXS## SDCTLXS##FRQMINXS##9# Q#$k#(#,#0#4ә#8STATUSdS#<dSENT#@PKRCNT10dS#PKRCNT32dS#PKRCNT54dS#PKRCNT76dS#PKRCNT98dS#PKRCNTBAdS#PKRCNTDCdS#PKRCNTFEdS#SEC_CFGXS#INT_CTRLXS#INT_MASKXS#INT_STATUSdS#<?RESERVED_0x#VID1dS#VID2dS#PTRNG_TypeSDEVICEADDRXSPERIODICLISTBASEXSSASYNCLISTADDRXSENDPTLISTADDRXS*IDdS#HWGENERALdS#HWHOSTdS#HWDEVICEdS# HWTXBUFdS#HWRXBUFdS#<gRESERVED_0v#GPTIMER0LDXS#GPTIMER0CTRLXS#GPTIMER1LDXS#GPTIMER1CTRLXS#SBUSCFGXS#<kRESERVED_1#CAPLENGTH#<RESERVED_2%#HCIVERSIONl#HCSPARAMSdS#HCCPARAMSdS#<RESERVED_3{#DCIVERSIONl#<RESERVED_4#DCCPARAMSdS#<RESERVED_5ޝ#USBCMDXS#USBSTSXS#USBINTRXS#FRINDEXXS#Ǽ<RESERVED_6;#ś##<RESERVED_7l#BURSTSIZEXS#TXFILLTUNINGXS#<RESERVED_8#ENDPTNAKXS#ENDPTNAKENXS#CONFIGFLAGdS#PORTSC1XS#<RESERVED_9#OTGSCXS#USBMODEXS#ENDPTSETUPSTATXS#ENDPTPRIMEXS#ENDPTFLUSHXS#ENDPTSTATdS#ENDPTCOMPLETEXS#ENDPTCTRL0XS#׿XSENDPTCTRL͟#<tPUSB_Type*<RESERVED_0 #USB_OTGn_CTRLXS#<RESERVED_1A#USB_OTGn_PHY_CTRL_0XS#PUSBNC_Type*PWDXS#PWD_SETXS#PWD_CLRXS#PWD_TOGXS# TXXS#TX_SETXS#TX_CLRXS#TX_TOGXS#RXXS# RX_SETXS#$RX_CLRXS#(RX_TOGXS#,CTRLXS#0CTRL_SETXS#4CTRL_CLRXS#8CTRL_TOGXS#<STATUSXS#@< RESERVED_0#DDEBUGrXS#PDEBUG_SETXS#TDEBUG_CLRXS#XDEBUG_TOGXS#\DEBUG0_STATUSdS#`< RESERVED_1#dDEBUG1XS#pDEBUG1_SETXS#tDEBUG1_CLRXS#xDEBUG1_TOGXS#|VERSIONdS#PUSBPHY_Type*`VBUS_DETECTXS#VBUS_DETECT_SETXS#VBUS_DETECT_CLRXS#VBUS_DETECT_TOGXS# CHRG_DETECTXS#CHRG_DETECT_SETXS#CHRG_DETECT_CLRXS#CHRG_DETECT_TOGXS#VBUS_DETECT_STATdS# < RESERVED_0J#$CHRG_DETECT_STATdS#0< RESERVED_1#4LOOPBACKXS#@LOOPBACK_SETXS#DLOOPBACK_CLRXS#HLOOPBACK_TOGXS#LMISCXS#PMISC_SETXS#TMISC_CLRXS#XMISC_TOGXS#\*<RESERVED_0-#}INSTANCEL#<_RESERVED_1g#DIGPROGdS#PUSB_ANALOG_Type'* WCRU#WSRU#WRSRl#WICRU#WMCRU#PWDOG_Type*SEL0U#SEL1U#SEL2U#SEL3U#SEL4U#SEL5U# SEL6U# SEL7U#SEL8U#SEL9U#SEL10U#SEL11U#SEL12U#SEL13U#SEL14U#SEL15U#SEL16U# SEL17U#"SEL18U#$SEL19U#&SEL20U#(SEL21U#*SEL22U#,SEL23U#.SEL24U#0SEL25U#2SEL26U#4SEL27U#6SEL28U#8SEL29U#:SEL30U#<SEL31U#>SEL32U#@SEL33U#BSEL34U#DSEL35U#FSEL36U#HSEL37U#JSEL38U#LSEL39U#NSEL40U#PSEL41U#RSEL42U#TSEL43U#VSEL44U#XSEL45U#ZSEL46U#\SEL47U#^SEL48U#`SEL49U#bSEL50U#dSEL51U#fSEL52U#hSEL53U#jSEL54U#lSEL55U#nSEL56U#pSEL57U#rSEL58U#tSEL59U#vSEL60U#xSEL61U#zSEL62U#|SEL63U#~SEL64U#SEL65U#CTRL0U#CTRL1U#PXBARA_Type*SEL0U#SEL1U#SEL2U#SEL3U#SEL4U#SEL5U# SEL6U# SEL7U#PXBARB_Type*<RESERVED_0 #MISC0XS#MISC0_SETXS#MISC0_CLRXS#MISC0_TOGXS#<RESERVED_1o#LOWPWR_CTRLXS#LOWPWR_CTRL_SETXS#LOWPWR_CTRL_CLRXS#LOWPWR_CTRL_TOGXS#<RESERVED_2#OSC_CONFIG0XS#OSC_CONFIG0_SETXS#OSC_CONFIG0_CLRXS#OSC_CONFIG0_TOGXS#OSC_CONFIG1XS#OSC_CONFIG1_SETXS#OSC_CONFIG1_CLRXS#OSC_CONFIG1_TOGXS#OSC_CONFIG2XS#OSC_CONFIG2_SETXS#OSC_CONFIG2_CLRXS#OSC_CONFIG2_TOGXS#PXTALOSC24M_TypeX middleware\flexspi\fsl_flexspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash\p_Bool"[Pflexspi_serial_clk_freq_tOcPflexspi_read_sample_clk_tsPflexspi_ipcmd_error_tbPflexspi_lut_seq_tPflexspi_dll_time_t Pflexspi_mem_config_t Pflexspi_operation_tPflexspi_xfer_tkFlexSpiClock_CoreClock kFlexSpiClock_AhbClock kFlexSpiClock_SerialRootClock kFlexSpiClock_IpgClock Pflexspi_clock_type_t_FlexSpiSerialClockFreqkFlexSpiSerialClk_30MHz kFlexSpiSerialClk_50MHz kFlexSpiSerialClk_60MHz kFlexSpiSerialClk_75MHz kFlexSpiSerialClk_80MHz kFlexSpiSerialClk_100MHz kFlexSpiSerialClk_133MHz kFlexSpiSerialClk_166MHz kFlexSpiSerialClk_200MHz kFlexSpiClk_SDR kFlexSpiClk_DDR _FlashReadSampleClkSourcekFlexSPIReadSampleClk_LoopbackInternally kFlexSPIReadSampleClk_LoopbackFromDqsPad kFlexSPIReadSampleClk_LoopbackFromSckPad kFlexSPIReadSampleClk_ExternalInputFromDqsPad  _FlexSpiIpCmdErrorkFlexSpiIpCmdError_NoError kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode kFlexSpiIpCmdError_JumpOnCsInIpCmd kFlexSpiIpCmdError_UnknownOpCode kFlexSpiIpCmdError_SdrDummyInDdrSequence kFlexSpiIpCmdError_DDRDummyInSdrSequence kFlexSpiIpCmdError_InvalidAddress kFlexSpiIpCmdError_SequenceExecutionTimeout kFlexSpiIpCmdError_FlashBoundaryAcrosss  _flexspi_statuskStatus_FLEXSPI_SequenceExecutionTimeoutXkStatus_FLEXSPI_InvalidSequenceYkStatus_FLEXSPI_DeviceTimeoutZkFlexSpiMiscOffset_DiffClkEnable kFlexSpiMiscOffset_Ck2Enable kFlexSpiMiscOffset_ParallelEnable kFlexSpiMiscOffset_WordAddressableEnable kFlexSpiMiscOffset_SafeConfigFreqEnable kFlexSpiMiscOffset_PadSettingOverrideEnable kFlexSpiMiscOffset_DdrModeEnable kFlexSpiMiscOffset_UseValidTimeForAllFreq kFlexSpiDeviceType_SerialNOR kFlexSpiDeviceType_SerialNAND kFlexSpiDeviceType_SerialRAM kFlexSpiDeviceType_MCP_NOR_NAND kFlexSpiDeviceType_MCP_NOR_RAM kSerialFlash_1Pad kSerialFlash_2Pads kSerialFlash_4Pads kSerialFlash_8Pads )_lut_sequenceseqNum<#seqId<#reservedK#kDeviceConfigCmdType_Generic kDeviceConfigCmdType_QuadEnable kDeviceConfigCmdType_Spi2Xpi kDeviceConfigCmdType_Xpi2Spi kDeviceConfigCmdType_Spi2NoCmd kDeviceConfigCmdType_Reset *time_100ps<#delay_cells<#)_FlexSPIConfigtag[#version[#reserved0[#readSampleClkSrc<# dataHoldTime<# dataSetupTime<#columnAddressWidth<#deviceModeCfgEnable<#deviceModeType<#waitTimeCfgCommandsK#deviceModeSeq8#deviceModeArg[#configCmdEnable<#<configModeType= #8configCmdSeqs^ # reserved1[#,[configCmdArgs #0reserved2[#<controllerMiscOption[#@deviceType<#DsflashPadType<#EserialClkFreq<#FlutCustomSeqEnable<#G[reserved3> #HsflashA1Size[#PsflashA2Size[#TsflashB1Size[#XsflashB2Size[#\csPadSettingOverride[#`sclkPadSettingOverride[#ddataPadSettingOverride[#hdqsPadSettingOverride[#ltimeoutInMs[#pcommandInterval[#tRdataValidTime] #xbusyOffsetK#|busyBitPolarityK#~[?lookupTable #8 lutCustomSeq #[reserved4 #_FlexSPIOperationTypekFlexSpiOperation_Command kFlexSpiOperation_Config kFlexSpiOperation_Write kFlexSpiOperation_Read kFlexSpiOperation_End )_FlexSpiXfer$operation#baseAddress[#seqId[#seqNum[# isParallelModeEnable#txBuffer#txSize[#rxBuffer#rxSize[#  middleware\flexspi_nor\flexspi_nor_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashDv_flexspi_nor_statuskStatusGroup_FLEXSPINOR kStatus_FLEXSPINOR_ProgramFail NkStatus_FLEXSPINOR_EraseSectorFail!NkStatus_FLEXSPINOR_EraseAllFail"NkStatus_FLEXSPINOR_WaitTimeout#NkStatus_FlexSPINOR_NotSupported$NkStatus_FlexSPINOR_WriteAlignmentError%NkStatus_FlexSPINOR_CommandFailure&NkStatus_FlexSPINOR_SFDP_NotFound'NkStatus_FLEXSPINOR_Unsupported_SFDP_Version(NkStatus_FLEXSPINOR_Flash_NotFound)NkStatus_FLEXSPINOR_DTRRead_DummyProbeFailed*N kSerialNorCfgOption_Tag kSerialNorCfgOption_DeviceType_ReadSFDP_SDR kSerialNorCfgOption_DeviceType_ReadSFDP_DDR kSerialNorCfgOption_DeviceType_HyperFLASH1V8 kSerialNorCfgOption_DeviceType_HyperFLASH3V0 kSerialNorCfgOption_DeviceType_MacronixOctalDDR kSerialNorCfgOption_DeviceType_MacronixOctalSDR kSerialNorCfgOption_DeviceType_MicronOctalDDR kSerialNorCfgOption_DeviceType_MicronOctalSDR kSerialNorCfgOption_DeviceType_AdestoOctalDDR kSerialNorCfgOption_DeviceType_AdestoOctalSDR  kSerialNorQuadMode_NotConfig kSerialNorQuadMode_StatusReg1_Bit6 kSerialNorQuadMode_StatusReg2_Bit1 kSerialNorQuadMode_StatusReg2_Bit7 kSerialNorQuadMode_StatusReg2_Bit1_0x31  kSerialNorEnhanceMode_Disabled kSerialNorEnhanceMode_0_4_4_Mode kSerialNorEnhanceMode_0_8_8_Mode kSerialNorEnhanceMode_DataOrderSwapped kSerialNorEnhanceMode_2ndPinMux * !max_freq[#!misc_mode[#!quad_mode_setting[#!cmd_pads[#!query_pads[# !device_type[#!option_size[#!tag[#SB>U[*!dummy_cycles[#!status_override[#!reserved[#SB U[)_serial_nor_config_optionoption0#option1Z#Pserial_nor_config_option_tm*por_mode<#current_mode<#exit_no_cmd_sequence<#restore_sequence<#SBU[Pflash_run_context_t2kRestoreSequence_None kRestoreSequence_HW_Reset kRestoreSequence_4QPI_FF kRestoreSequence_5QPI_FF kRestoreSequence_8QPI_FF kRestoreSequence_Send_F0 kRestoreSequence_Send_66_99 kRestoreSequence_Send_6699_9966 kRestoreSequence_Send_06_FF kFlashInstMode_ExtendedSpi kFlashInstMode_0_4_4_SDR kFlashInstMode_0_4_4_DDR kFlashInstMode_QPI_SDR AkFlashInstMode_QPI_DDR BkFlashInstMode_OPI_SDR kFlashInstMode_OPI_DDR )_flexspi_nor_configmemConfig{#pageSize[#sectorSize[#ipcmdSerialClkFreq<#isUniformBlockSize<#isDataOrderSwapped<#<reserved0 #serialNorType<#needExitNoCmdMode<#halfClkForNonReadCmd<#needRestoreNoCmdMode<#blockSize[#[ reserve2~ #Pflexspi_nor_config_t0  ..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashy01_BoolPclock_name_tPclock_ip_name_tPclock_osc_t Pclock_gate_value_t0 Pclock_mode_t Pclock_mux_t Pclock_div_ttPclock_usb_src_t^Pclock_usb_phy_src_tPclock_usb_pll_config_t Pclock_sys_pll_config_tHPclock_audio_pll_config_tPclock_enet_pll_config_t^_clock_pllkCLOCK_PllSys 0kCLOCK_PllUsb1 kCLOCK_PllAudio pkCLOCK_PllEnet500MPclock_pll_t0_clock_pfdkCLOCK_Pfd0 kCLOCK_Pfd1 kCLOCK_Pfd2 kCLOCK_Pfd3 Pclock_pfd_t<CLOCK_SetMux$Umux$[value\busyShift[;CLOCK_GetMux[$Umuxa__result[<CLOCK_SetDiv$idivider$[value\busyShift[;CLOCK_GetDiv[$idividera__result[<CLOCK_ControlGate$name$%value\index[\shift[\regBt["<<CLOCK_EnableClock$name< CLOCK_DisableClock$name< CLOCK_SetMode$@mode; CLOCK_GetCpuClkFreq[a__result[< CLOCK_SetXtalFreq$[freq< CLOCK_SetRtcXtalFreq$[freq< CLOCK_SetPllBypass$hbase$pll$bypass"o< CLOCK_SetPllBypassRefClkSrc$hbase$pll$[src8 CLOCK_GetOscFreq[a__result[8 CLOCK_GetRtcFreq[a__result[8 CLOCK_IsPllBypassed$hbase$plla__result8 CLOCK_IsPllEnabled$hbase$plla__result8 CLOCK_GetPllBypassRefClk[$hbase$plla__result[_clock_namekCLOCK_CpuClk kCLOCK_AhbClk kCLOCK_SemcClk kCLOCK_IpgClk kCLOCK_PerClk kCLOCK_OscClk kCLOCK_RtcClk kCLOCK_Usb1PllClk kCLOCK_Usb1PllPfd0Clk kCLOCK_Usb1PllPfd1Clk kCLOCK_Usb1PllPfd2Clk kCLOCK_Usb1PllPfd3Clk kCLOCK_SysPllClk kCLOCK_SysPllPfd0Clk kCLOCK_SysPllPfd1Clk kCLOCK_SysPllPfd2Clk kCLOCK_SysPllPfd3Clk kCLOCK_EnetPllClk kCLOCK_EnetPll25MClk kCLOCK_EnetPll500MClk kCLOCK_AudioPllClk _clock_ip_namekCLOCK_IpInvalidkCLOCK_Aips_tz1kCLOCK_Aips_tz2kCLOCK_MqskCLOCK_Sim_m_clk_rkCLOCK_Dcp kCLOCK_Lpuart3 kCLOCK_TracekCLOCK_Gpt2kCLOCK_Gpt2SkCLOCK_Lpuart2kCLOCK_Gpio2kCLOCK_Lpspi1kCLOCK_Lpspi2kCLOCK_PitkCLOCK_Adc1kCLOCK_Gpt1kCLOCK_Gpt1SkCLOCK_Lpuart4kCLOCK_Gpio1kCLOCK_CsukCLOCK_Gpio5kCLOCK_OcramExsckCLOCK_IomuxcSnvskCLOCK_Lpi2c1kCLOCK_Lpi2c2kCLOCK_OcotpkCLOCK_Xbar1kCLOCK_Xbar2kCLOCK_Gpio3kCLOCK_AoikCLOCK_Ewm0kCLOCK_Wdog1kCLOCK_FlexRamkCLOCK_IomuxcSnvsGprkCLOCK_Sim_m7_clk_rkCLOCK_IomuxckCLOCK_IomuxcGprkCLOCK_BeekCLOCK_SimM7kCLOCK_SimMkCLOCK_SimEmskCLOCK_Pwm1kCLOCK_Enc1kCLOCK_Rom kCLOCK_Flexio1 kCLOCK_Wdog3 kCLOCK_Dma kCLOCK_Kpp kCLOCK_Wdog2 kCLOCK_Aips_tz4 kCLOCK_Spdif kCLOCK_Sai1 kCLOCK_Sai2 kCLOCK_Sai3 kCLOCK_Lpuart1 kCLOCK_SnvsHp kCLOCK_SnvsLp kCLOCK_UsbOh3 kCLOCK_Dcdc kCLOCK_FlexSpi kCLOCK_Trng kCLOCK_Aips_tz3 kCLOCK_SimPer kCLOCK_Anadig kCLOCK_Timer1 _clock_osckCLOCK_RcOsc kCLOCK_XtalOsc _clock_gate_valuekCLOCK_ClockNotNeeded kCLOCK_ClockNeededRun kCLOCK_ClockNeededRunWait _clock_mode_tkCLOCK_ModeRun kCLOCK_ModeWait kCLOCK_ModeStop _clock_muxkCLOCK_Pll3SwMuxxkCLOCK_PeriphMuxkCLOCK_SemcAltMux΀xkCLOCK_SemcMux̀xkCLOCK_PrePeriphMux䁀xkCLOCK_TraceMux܁xkCLOCK_PeriphClk2Mux؁xkCLOCK_LpspiMuxȁxkCLOCK_FlexspiMuxxkCLOCK_Sai3Mux܁xkCLOCK_Sai2Mux؁xkCLOCK_Sai1MuxԁxkCLOCK_PerclkMux̀xkCLOCK_Flexio1Mux恀xkCLOCK_UartMux̀xkCLOCK_SpdifMux聀xkCLOCK_Lpi2cMux䀀x"_clock_divkCLOCK_ArmDivkCLOCK_PeriphClk2DivxkCLOCK_SemcDivkCLOCK_AhbDivԃ kCLOCK_IpgDivЁxkCLOCK_LpspiDivxkCLOCK_FlexspiDivxkCLOCK_PerclkDivxkCLOCK_TraceDivxkCLOCK_UartDivxkCLOCK_Flexio1DivxkCLOCK_Sai3PreDiv샀xkCLOCK_Sai3DivxkCLOCK_Flexio1PreDiv҃xkCLOCK_Sai1PreDiṽxkCLOCK_Sai1DivxkCLOCK_Sai2PreDiṽxkCLOCK_Sai2DivxkCLOCK_Spdif0PreDivxkCLOCK_Spdif0Div샀xkCLOCK_Lpi2cDiv柀x#_clock_usb_srckCLOCK_Usb480MkCLOCK_UsbSrcUnused#_clock_usb_phy_srckCLOCK_Usbphy480M $_clock_pll_clk_srckCLOCK_PllClkSrc24M kCLOCK_PllSrcClkPN )$_clock_usb_pll_configloopDivider<#src<#)%_clock_sys_pll_configloopDivider<#numerator[#denominator[#src<# ss_stopK#ss_enable<#ss_stepK#)&_clock_audio_pll_configloopDivider<#postDivider<#numerator[#denominator[#src<# )'_clock_enet_pll_configenableClkOutput#enableClkOutput500M#enableClkOutput25M#loopDivider<#src<# FlashOS.HComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashDunsigned longunsigned shortcharunsigned char)FlashDevice!Vers#DevName #DevType#DevAdr#szDev#szPage#Res#valEmpty#toProg#toErase#sectors#)FlashSectorsszSector#AddrSector# ..\..\..\..\CMSIS\Include\core_cm7.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash*!_reserved0[#!GE[# !_reserved1[#!Q[#!V[#!C[#!Z[#!N[#Sbw[PAPSR_TypeU*!ISR[# !_reserved0[#Sbzw[PIPSR_Type*!ISR[# !_reserved0[#!ICI_IT_1[#!GE[# !_reserved1[#!T[#!ICI_IT_2[#!Q[#!V[#!C[#!Z[#!N[#Sbw[PxPSR_Type*!nPRIV[#!SPSEL[#!FPCA[#!_reserved0[#Sbw[PCONTROL_Type*{ISER>#[RESERVED0S# {ICERo#[RSERVED1#{ISPR#[RESERVED2#{ICPR#[RESERVED3#{IABR#[7RESERVED4#IP:#[RESERVED5O#STIR{#t[t<PNVIC_Type9*CPUID#ICSR{#VTOR{#AIRCR{# SCR{#CCR{#  SHPR#SHCSR{#$CFSR{#(HFSR{#,DFSR{#0MMFAR{#4BFAR{#8AFSR{#< ID_PFRQ#@ID_DFR#HID_AFR#L ID_MFR#P ID_ISAR#` [RESERVED0#tCLIDR#xCTR#|CCSIDR#CSSELR{#CPACR{# [\RESERVED3#STIR{# [RESERVED4=#MVFR0#MVFR1#MVFR2# [RESERVED5#ICIALLU{# [RESERVED6#ICIMVAU{#DCIMVAC{#DCISW{#DCCMVAU{#DCCMVAC{#DCCSW{#DCCIMVAC{#DCCISW{#[RESERVED7J#ITCMCR{#DTCMCR{#AHBPCR{#CACR{#AHBSCR{#[RESERVED8#ABFSR{#[tPSCB_Type* [RESERVED0#ICTR#ACTLR{#PSCnSCB_Type*CTRL{#LOAD{#VAL{#CALIB# PSysTick_TypeESu8u16u32{tK* x PORT#[RESERVED0#TER{#[RESERVED1#TPR{#[RESERVED2 #TCR{#[RESERVED3G #IWR{#IRR#IMCR{#[*RESERVED4 #LAR{#LSR#[RESERVED5 #PID4#PID5#PID6#PID7#PID0#PID1#PID2#PID3#CID0#CID1#CID2#CID3#tPITM_Type*CTRL{#CYCCNT{#CPICNT{#EXCCNT{# SLEEPCNT{#LSUCNT{#FOLDCNT{#PCSR#COMP0{# MASK0{#$FUNCTION0{#([RESERVED0, #,COMP1{#0MASK1{#4FUNCTION1{#8[RESERVED1s #<COMP2{#@MASK2{#DFUNCTION2{#H[RESERVED2 #LCOMP3{#PMASK3{#TFUNCTION3{#X[RESERVED3 #\LAR{#LSR#PDWT_Type *SSPSR{#CSPSR{#[RESERVED0g #ACPR{#[6RESERVED1 #SPPR{#[RESERVED2 #FFSR#FFCR{#FSCR#[RESERVED3 #TRIGGER#FIFO0#ITATBCTR2#[RESERVED4K #ITATBCTR0#FIFO1#ITCTRL{#[&RESERVED5 #CLAIMSET{#CLAIMCLR{#[RESERVED7 #DEVID#DEVTYPE#PTPI_TypeH  *,TYPE#CTRL{#RNR{#RBAR{# RASR{#RBAR_A1{#RASR_A1{#RBAR_A2{#RASR_A2{# RBAR_A3{#$RASR_A3{#(PMPU_Type# *[RESERVED0#FPCCR{#FPCAR{#FPDSCR{# MVFR0#MVFR1#MVFR2#PFPU_Type *DHCSR{#DCRSR{#DCRDR{#DEMCR{# PCoreDebug_TypeO tqITM_RxBuffer< __NVIC_SetPriorityGrouping$[PriorityGroup\reg_value[\PriorityGroupTmp[; __NVIC_GetPriorityGrouping[a__result[< __NVIC_EnableIRQ$XIRQn;!__NVIC_GetEnableIRQ[$XIRQna__result[kStatusGroup_CAAM ?kStatusGroup_ECSPI @kStatusGroup_USDHC AkStatusGroup_LPC_I2C BkStatusGroup_DCP CkStatusGroup_MSCAN DkStatusGroup_ESAI EkStatusGroup_FLEXSPI FkStatusGroup_MMDC GkStatusGroup_PDM HkStatusGroup_SDMA IkStatusGroup_ICS JkStatusGroup_SPDIF KkStatusGroup_LPC_MINISPI LkStatusGroup_HASHCRYPT MkStatusGroup_LPC_SPI_SSP NkStatusGroup_I3C OkStatusGroup_LPC_I2C_1 akStatusGroup_NOTIFIER bkStatusGroup_DebugConsole ckStatusGroup_SEMC dkStatusGroup_ApplicationRangeStart ekStatusGroup_IAP fkStatusGroup_HAL_GPIO ykStatusGroup_HAL_UART zkStatusGroup_HAL_TIMER {kStatusGroup_HAL_SPI |kStatusGroup_HAL_I2C }kStatusGroup_HAL_FLASH ~kStatusGroup_HAL_PWM kStatusGroup_HAL_RNG kStatusGroup_TIMERMANAGER kStatusGroup_SERIALMANAGER kStatusGroup_LED kStatusGroup_BUTTON kStatusGroup_EXTERN_EEPROM kStatusGroup_SHELL kStatusGroup_MEM_MANAGER kStatusGroup_LIST kStatusGroup_OSA kStatusGroup_COMMON_TASK kStatusGroup_MSG kStatusGroup_SDK_OCOTP kStatusGroup_SDK_FLEXSPINOR kStatusGroup_CODEC kStatus_Success kStatus_Fail kStatus_ReadOnly kStatus_OutOfRange kStatus_InvalidArgument kStatus_Timeout kStatus_NoTransferInProgress Pstatus_t;EnableIRQ> $Xinterrupta__result> ;DisableIRQ> $Xinterrupta__result> ;DisableGlobalIRQ[a__result[\regPrimask[<EnableGlobalIRQ$[primask middleware\flexspi_nor\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashu_BoolPlut_seq_tJPsfdp_header_tuPsfdp_parameter_header_t* Pjedec_flash_param_table_tPjedec_4byte_addressing_inst_table_tPjedec_info_table_t-"[""{"["p""""D"<"Et[kSerialNorCmd_BasicRead_3B kSerialNorCmd_BasicRead_4B kSerialNorCmd_PageProgram_1_1_1_3B kSerialNorCmd_PageProgram_1_1_1_4B kSerialNorCmd_PageProgram_1_4_4_4B >kSerialNorCmd_PageProgram_1_1_4_4B 4kSerialNorCmd_Read_SDR_1_4_4_3B kSerialNorCmd_Read_DDR_1_4_4_3B kSerialNorCmd_Read_SDR_1_4_4_4B kSerialNorCmd_Read_SDR_1_1_4_4B lkSerialNorCmd_Read_DDR_1_4_4_4B kSerialNorCmd_ChipErase `kSerialNorCmd_WriteEnable kSerialNorCmd_WriteStatusReg1 kSerialNorCmd_ReadStatusReg1 kSerialNorCmd_WriteStatusReg2 >kSerialNorCmd_ReadStatusReg2 ?kSerialNorCmd_ReadFlagReg p kSerialNorCmd_SE4K_3B kSerialNorCmd_SE4K_4B !kSerialNorCmd_SE64K_3B kSerialNorCmd_SE64K_4B  kSerialNorQpiMode_NotConfig kSerialNorQpiMode_Cmd_0x38 kSerialNorQpiMode_Cmd_0x38_QE kSerialNorQpiMode_Cmd_0x35 kSerialNorQpiMode_Cmd_0x71 kSerialNorQpiMode_Cmd_0x61  kSerialNorType_StandardSPI kSerialNorType_HyperBus kSerialNorType_XPI kSerialNorType_NoCmd ) _lut_seq [lut# kSerialNOR_IndividualMode kSerialNOR_ParallelMode  kFlexSpiSerialClk_Update kFlexSpiSerialClk_Restore  kSerialFlash_ReadSFDP ZkSerialFlash_ReadManufacturerId kSfdp_Version_Major_1_0 kSfdp_Version_Minor_0 kSfdp_Version_Minor_A kSfdp_Version_Minor_B kSfdp_Version_Minor_C kSfdp_BasicProtocolTableSize_Rev0 $kSfdp_BasicProtocolTableSize_RevA @kSfdp_BasicProtocolTableSize_RevB @kSfdp_BasicProtocolTableSize_RevC P)_sfdp_headersignature[#minor_rev<#major_rev<#param_hdr_num<#sfdp_access_protocol<#kParameterID_BasicSpiProtocolkParameterID_SectorMapkParameterID_4ByteAddressInstructionTablekParameterID_xSpiProfile1_0kParameterID_xSpiOrofile2_0kParameterID_StaCtrlCfgRegMapkParameterID_OpiEnableSeq )_sfdp_parameter_headerparameter_id_lsb<#minor_rev<#major_rev<#table_length_in_32bit<#<parameter_table_pointer #parameter_id_msb<#*!erase_size[#!write_granularity[#!reserved0[#!unused0[#!erase4k_inst[#!support_1_1_2_fast_read[#!address_bits[# !support_ddr_clocking[# !support_1_2_2_fast_read[# !supports_1_4_4_fast_read[# !support_1_1_4_fast_read[# !unused1[# *!dummy_clocks_1_4_4_read[#!mode_clocks_1_4_4_read[#!inst_1_4_4_read[#!dummy_clocks_1_1_4_read[# !mode_clocks_1_1_4_read[#!inst_1_1_4_read[#*!dummy_clocks_1_2_2_read[#!mode_clocks_1_2_2_read[#!inst_1_2_2_read[#!dummy_clocks_1_1_2_read[# !mode_clocks_1_1_2_read[#!inst_1_1_2_read[#*!support_2_2_2_fast_read[#!reserved0[#!support_4_4_4_fast_read[#!reserved1[#*!reserved0[#!dummy_clocks_2_2_2_read[# !mode_clocks_2_2_2_read[#!inst_2_2_2_read[#*!reserved0[#!dummy_clocks_4_4_4_read[# !mode_clocks_4_4_4_read[#!inst_4_4_4_read[#*size<#inst<#*!reserved0[#!page_size[#!reserved1[#*suspend_resume_spec[#suspend_resume_inst[#*!reserved0[#!busy_status_polling[#!reserved1[#* !mode_4_4_4_disable_seq[#!mode_4_4_4_enable_seq[#!support_mode_0_4_4[#!mode_0_4_4_exit_method[#!mode_0_4_4_entry_method[# !quad_enable_requirement[# !hold_reset_disable[#!reserved0[#*!!status_reg_write_enable[#!reserved0[#!soft_reset_rescue_support[#!exit_4_byte_addressing[# !enter_4_byte_addrssing[#*#!dummy_clocks_1_8_8_read[#!mode_clocks_1_8_8_read[#!inst_1_8_8_read[#!dummy_clocks_1_1_8_read[# !mode_clocks_1_1_8_read[#!inst_1_1_8_read[#*%!reserved[#!output_driver_strength[# !jedec_spi_protocol_reset[#!dqs_waveform_type_sdr[#!dqs_support_in_qpi_sdr[#!dqs_support_in_qpi_ddr[#!dqs_support_in_opi_str[#!cmd_and_extension_in_opi_ddr[#!byte_order_in_opi_ddr[#*'!opi_sdr_disable_seq[#!opi_sdr_enable_deq[#!support_mode_0_8_8[#!mode_0_8_8_exit_method[#!mode_0_8_8_entry_method[# !octal_enable_requirement[# !reserved[# *)!qpi_sdr_no_dqs[#!qpi_sdr_with_dqs[#!qpi_ddr_no_dqs[#!qpi_ddr_with_dqs[#!opi_sdr_no_dqs[# !opi_sdr_with_dqs[#!opi_ddr_no_dqs[#!opi_ddr_with_dqs[#),_jedec_flash_param_tablePmisc #flash_density[#read_1_4_infoE #read_1_2_info # read_22_44_check #read_2_2_infoT #read_4_4_info #*Perase_infot#erase_timing[#$chip_erase_progrm_infoq#(suspend_resume_info#,busy_status_info#4mode_4_4_infoH#8mode_config_infoQ#<read_1_8_info#@xpi_misc_info#Dmode_octal_info#Hmax_speed_info_xpi#L*3!support_1_1_1_read[#!support_1_1_1_fast_read[#!support_1_1_2_fast_read[#!support_1_2_2_fast_read[#!support_1_1_4_fast_read[#!support_1_4_4_fast_read[#!support_1_1_1_page_program[#!support_1_1_4_page_program[#!support_1_4_4_page_program[#!support_erase_type1_size[#!support_erase_type2_size[#!support_erase_type3_size[#!support_erase_type4_size[#!support_1_1_1_dtr_read[#!support_1_2_2_dtr_read[#!support_1_4_4_dtr_read[#!support_volatile_sector_lock_read_cmd[#!support_volatile_sector_lock_write_cmd[#!support_nonvolatile_sector_lock_read_cmd[# !support_nonvolatile_sector_lock_write_cmd[# !reserved[# *33<erase_inst#)4_jedec_4byte_addressing_inst_tablecmd_4byte_support_info#erase_inst_info#)5_jdec_query_tabledstandard_version[#flash_param_tbl_size[#flash_param_tbl"#has_4b_addressing_inst_table#Xflash_4b_inst_tblD#\( ..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashyl0_Boolm""""Pclock_64b_tk,t[ bsp\src\hardware_init_MIMXRT1015.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash0l8"{["[ bsp\src\clock_config_MIMXRT1015.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashP;kMaxAHBClockD"[t[ ..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash<_BoolPclock_name_tPclock_ip_name_tPclock_osc_t Pclock_gate_value_tQ Pclock_mode_t Pclock_mux_tPclock_div_tPclock_usb_src_tPclock_usb_phy_src_tPclock_usb_pll_config_t,Pclock_sys_pll_config_tiPclock_audio_pll_config_tPclock_enet_pll_config_t_clock_pllkCLOCK_PllSys 0kCLOCK_PllUsb1 kCLOCK_PllAudio pkCLOCK_PllEnet500MPclock_pll_t0_clock_pfdkCLOCK_Pfd0 kCLOCK_Pfd1 kCLOCK_Pfd2 kCLOCK_Pfd3 Pclock_pfd_tt[qg_xtalFreq qg_rtcXtalFreq <CLOCK_SetMux$Umux$[value\busyShift[;CLOCK_GetMux[$Umuxa__result[<CLOCK_SetDiv$idivider$[value\busyShift[;CLOCK_GetDiv[$idividera__result[<CLOCK_ControlGate$name$%value\index[\shift[\regg" < CLOCK_EnableClock$name< CLOCK_DisableClock$name< CLOCK_SetMode$@mode; CLOCK_GetOscFreq[a__result[; CLOCK_GetCpuClkFreq[a__result[; CLOCK_GetRtcFreq[a__result[< CLOCK_SetRtcXtalFreq$[freq< CLOCK_SetPllBypass$base$pll$bypass"o; CLOCK_IsPllBypassed$base$plla__result; CLOCK_IsPllEnabled$base$plla__result< CLOCK_SetPllBypassRefClkSrc$base$pll$[src; CLOCK_GetPllBypassRefClk[$base$plla__result[9 CLOCK_SetXtalFreq$[freq_clock_namekCLOCK_CpuClk kCLOCK_AhbClk kCLOCK_SemcClk kCLOCK_IpgClk kCLOCK_PerClk kCLOCK_OscClk kCLOCK_RtcClk kCLOCK_Usb1PllClk kCLOCK_Usb1PllPfd0Clk kCLOCK_Usb1PllPfd1Clk kCLOCK_Usb1PllPfd2Clk kCLOCK_Usb1PllPfd3Clk kCLOCK_SysPllClk kCLOCK_SysPllPfd0Clk kCLOCK_SysPllPfd1Clk kCLOCK_SysPllPfd2Clk kCLOCK_SysPllPfd3Clk kCLOCK_EnetPllClk kCLOCK_EnetPll25MClk kCLOCK_EnetPll500MClk kCLOCK_AudioPllClk _clock_ip_namekCLOCK_IpInvalidkCLOCK_Aips_tz1kCLOCK_Aips_tz2kCLOCK_MqskCLOCK_Sim_m_clk_rkCLOCK_Dcp kCLOCK_Lpuart3 kCLOCK_TracekCLOCK_Gpt2kCLOCK_Gpt2SkCLOCK_Lpuart2kCLOCK_Gpio2kCLOCK_Lpspi1kCLOCK_Lpspi2kCLOCK_PitkCLOCK_Adc1kCLOCK_Gpt1kCLOCK_Gpt1SkCLOCK_Lpuart4kCLOCK_Gpio1kCLOCK_CsukCLOCK_Gpio5kCLOCK_OcramExsckCLOCK_IomuxcSnvskCLOCK_Lpi2c1kCLOCK_Lpi2c2kCLOCK_OcotpkCLOCK_Xbar1kCLOCK_Xbar2kCLOCK_Gpio3kCLOCK_AoikCLOCK_Ewm0kCLOCK_Wdog1kCLOCK_FlexRamkCLOCK_IomuxcSnvsGprkCLOCK_Sim_m7_clk_rkCLOCK_IomuxckCLOCK_IomuxcGprkCLOCK_BeekCLOCK_SimM7kCLOCK_SimMkCLOCK_SimEmskCLOCK_Pwm1kCLOCK_Enc1kCLOCK_Rom kCLOCK_Flexio1 kCLOCK_Wdog3 kCLOCK_Dma kCLOCK_Kpp kCLOCK_Wdog2 kCLOCK_Aips_tz4 kCLOCK_Spdif kCLOCK_Sai1 kCLOCK_Sai2 kCLOCK_Sai3 kCLOCK_Lpuart1 kCLOCK_SnvsHp kCLOCK_SnvsLp kCLOCK_UsbOh3 kCLOCK_Dcdc kCLOCK_FlexSpi kCLOCK_Trng kCLOCK_Aips_tz3 kCLOCK_SimPer kCLOCK_Anadig kCLOCK_Timer1 _clock_osckCLOCK_RcOsc kCLOCK_XtalOsc _clock_gate_valuekCLOCK_ClockNotNeeded kCLOCK_ClockNeededRun kCLOCK_ClockNeededRunWait _clock_mode_tkCLOCK_ModeRun kCLOCK_ModeWait kCLOCK_ModeStop _clock_muxkCLOCK_Pll3SwMuxxkCLOCK_PeriphMuxkCLOCK_SemcAltMux΀xkCLOCK_SemcMux̀xkCLOCK_PrePeriphMux䁀xkCLOCK_TraceMux܁xkCLOCK_PeriphClk2Mux؁xkCLOCK_LpspiMuxȁxkCLOCK_FlexspiMuxxkCLOCK_Sai3Mux܁xkCLOCK_Sai2Mux؁xkCLOCK_Sai1MuxԁxkCLOCK_PerclkMux̀xkCLOCK_Flexio1Mux恀xkCLOCK_UartMux̀xkCLOCK_SpdifMux聀xkCLOCK_Lpi2cMux䀀x"_clock_divkCLOCK_ArmDivkCLOCK_PeriphClk2DivxkCLOCK_SemcDivkCLOCK_AhbDivԃ kCLOCK_IpgDivЁxkCLOCK_LpspiDivxkCLOCK_FlexspiDivxkCLOCK_PerclkDivxkCLOCK_TraceDivxkCLOCK_UartDivxkCLOCK_Flexio1DivxkCLOCK_Sai3PreDiv샀xkCLOCK_Sai3DivxkCLOCK_Flexio1PreDiv҃xkCLOCK_Sai1PreDiṽxkCLOCK_Sai1DivxkCLOCK_Sai2PreDiṽxkCLOCK_Sai2DivxkCLOCK_Spdif0PreDivxkCLOCK_Spdif0Div샀xkCLOCK_Lpi2cDiv柀x#_clock_usb_srckCLOCK_Usb480MkCLOCK_UsbSrcUnused#_clock_usb_phy_srckCLOCK_Usbphy480M $_clock_pll_clk_srckCLOCK_PllClkSrc24M kCLOCK_PllSrcClkPN )$_clock_usb_pll_configloopDivider<#src<#)&_clock_sys_pll_configloopDivider<#numerator[#denominator[#src<# ss_stopK#ss_enable<#ss_stepK#)&_clock_audio_pll_configloopDivider<#postDivider<#numerator[#denominator[#src<# )(_clock_enet_pll_configenableClkOutput#enableClkOutput500M#enableClkOutput25M#loopDivider<#src<# FlashDev.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashP@ ..\..\..\..\CMSIS\Include\core_cm7.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash{C*!_reserved0[#!GE[# !_reserved1[#!Q[#!V[#!C[#!Z[#!N[#Sbw[PAPSR_TypeU*!ISR[# !_reserved0[#Sbzw[PIPSR_Type*!ISR[# !_reserved0[#!ICI_IT_1[#!GE[# !_reserved1[#!T[#!ICI_IT_2[#!Q[#!V[#!C[#!Z[#!N[#Sbw[PxPSR_Type*!nPRIV[#!SPSEL[#!FPCA[#!_reserved0[#Sbw[PCONTROL_Type*{ISER>#[RESERVED0S# {ICERo#[RSERVED1#{ISPR#[RESERVED2#{ICPR#[RESERVED3#{IABR#[7RESERVED4#IP:#[RESERVED5O#STIR{#t[t<PNVIC_Type9*CPUID#ICSR{#VTOR{#AIRCR{# SCR{#CCR{#  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#TRIGGER#FIFO0#ITATBCTR2#[RESERVED4K #ITATBCTR0#FIFO1#ITCTRL{#[&RESERVED5 #CLAIMSET{#CLAIMCLR{#[RESERVED7 #DEVID#DEVTYPE#PTPI_TypeH  *,TYPE#CTRL{#RNR{#RBAR{# RASR{#RBAR_A1{#RASR_A1{#RBAR_A2{#RASR_A2{# RBAR_A3{#$RASR_A3{#(PMPU_Type# *[RESERVED0#FPCCR{#FPCAR{#FPDSCR{# MVFR0#MVFR1#MVFR2#PFPU_Type *DHCSR{#DCRSR{#DCRDR{#DEMCR{# PCoreDebug_TypeO tqITM_RxBuffer< __NVIC_SetPriorityGrouping$[PriorityGroup\reg_value[\PriorityGroupTmp[; __NVIC_GetPriorityGrouping[a__result[< __NVIC_EnableIRQ$XIRQn;!__NVIC_GetEnableIRQ[$XIRQna__result[_flexspi_is_parallel_mode::HiconfigZY___resultF>kflexspi_is_padsetting_override_enable::4iconfigZ(___result>wflexspi_is_differential_clock_enable:: iconfigZ___result>flexspi_is_word_addressable:; iconfigZ___result>flexspi_is_ck2_enabled;;iconfigZ___result>flexspi_is_ddr_mode_enable;.;iconfigZd___resultQ>flexspi_get_module_base.;@;iinstance[3^__resultPXbaseAddrP>  flexspi_configure_dll@;=iinstance[iconfigZ^__resultPXstatus` ZmdisConfigRequired @; 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Zwatermark[ Zburst_rx_size[ @`AZrx_fifo_regv @ AZburst_rx_round[ @`AYbuf[HZsrc Zdst @HAXindex[QnAjBZxferRemainingSizev ZxferBufferPtr`c Ztx_fifo_size[O Zwatermark[; Zburst_tx_size[' Zis_transfer_started A"BZtx_fifo_regv A"BZburst_tx_round[ > flexspi_update_luttBCiinstance[ iseqIndex[ ilutBasel iseqNumber[t ^__resultPXstatusXBBZbasea Zstart_index[M Zend_index[9 ZflexspiLutPtrv% > flexspi_device_write_enableC|Ciinstance[ iconfigZ iisParallelMode ibaseAddr[ ^__resultPvXstatushCxCYflashXferJD> flexspi_extract_parallel_data|CCidst0` idst1`| isrc`i ilength[V ^__resultPRXstatushCCZdst0Byte8 Zdst1Byte ZsrcByte >" flexspi_device_wait_busyC8E\iinstance[ iconfigZ iisParallelMode ibaseAddr[ ^__resultPXstatusX "C4E![YstatusDataBufferPZbusyMask[Z ZbusyPolarity[F ZisBusym Ystatus0[DYstatus1[@YflashXferJZenableTimeoutCheck1 ZremainingMsk >$ flexspi_device_workmode_config8EF#iinstance[iconfigZibaseAddr[^__resultPXstatusV $DEEZbaseZread_cmd_pads[YflashXferJ>& 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[4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashhlP__asm___13_fsl_flexspi_c_c729c902____REVSHhlmiddleware\\flexspi\\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashLP__asm___13_fsl_flexspi_c_c729c902____REV16LPmiddleware\flexspi_nor\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash:_Bool> flexspi_nor_flash_initiinstance[Z)iconfig<)^__resultP8XstatusU> flexspi_nor_exit_no_cmd_modeuiinstance[)iconfig)iisParallelMode(ibaseAddr[(^__resultP@YflashXferH> flexspi_nor_write_enable=iinstance[(iconfig(iisParallelModei(ibaseAddr[J(^__resultPXstatusU [Ylut_tmpL>flexspi_nor_restore_no_cmd_mode iinstance[+(iconfig (iisParallelMode'ibaseAddr['^__resultP^XstatusW YflashXfer> flexspi_nor_wait_busy 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___resultZaligned_start[Zaligned_end[Zstatus=x9:Zis_addr_block_alignedZremaining_size[>? flexspi_nor_flash_read::iinstance[xiconfigZidst<istart[ibytes[ ^__resultP~XstatusX?::YflashXferZisParallelModeZmemCfg?@:|:ZreadLength[middleware\\flexspi_nor\\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashdh/__asm___19_flexspi_nor_flash_c_93f2e184____REVSHdhmiddleware\\flexspi_nor\\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashHL 0__asm___19_flexspi_nor_flash_c_93f2e184____REV16HL ..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash1_Bool> CLOCK_GetPllFreq[,ipllT0___result[0Zfreq[E0ZdivSelect[0ZfreqTmp.0F o)0o20e:FIopl0oyX0eFo20o0e> CLOCK_GetSysPfdFreq[ ~,ipfd/^__result[PXfreq[U > CLOCK_GetUsb1PfdFreq[  ^,ipfd/^__result[PXfreq[U>GCLOCK_GetPeriphClkFreq[ >,^__result[PZfreq[p/?CLOCK_InitExternalClk  ,ibypassXtalOscR/?CLOCK_DeinitExternalClk  ,?CLOCK_SwitchOsc 0 +iosc?/?CLOCK_InitRcOsc24M0 > +?CLOCK_DeinitRcOsc24M> L +> CLOCK_GetAhbFreq[L +^__result[P> CLOCK_GetSemcFreq[ " +^__result[PLXfreq[T4>  CLOCK_GetIpgFreq[" @ b+^__result[P>  CLOCK_GetFreq[@  B+iname!/^__result[PZfreq[S.F  e>  CLOCK_GetPerClkFreq[ L "+^__result[P2Xfreq[T> CLOCK_EnableUsbhs0ClockL +isrc95.ifreq[".^__resultPJ L Yi.x? CLOCK_InitUsb1Pll *iconfig..> CLOCK_EnableUsbhs0PhyPllClock L*isrcQ-ifreq[-^__resultPXYg_ccmConfigUsbPll.p? CLOCK_DisableUsbhs0PhyPllClockLh*?CLOCK_InitSysPllh*iconfig.-?CLOCK_DeinitSysPll*?CLOCK_DeinitUsb1Pll~*?CLOCK_InitAudioPll^*iconfig.-XpllAudio[PZXmisc2[R?CLOCK_DeinitAudioPllJ*?CLOCK_InitEnetPll**iconfig.-Xenet_pll[Q?CLOCK_DeinitEnetPll*?CLOCK_InitSysPfd)ipfd|-ipfdFrac<^-XpfdIndex[QXpfd528[S?CLOCK_DeinitSysPfd)ipfdK-?CLOCK_InitUsb1Pfd)ipfd8-ipfdFrac<-XpfdIndex[QXpfd480[S?CLOCK_DeinitUsb1Pfd,)ipfd-?SDK_DelayAtLeastUs,)idelay_us[,XcountkTlXperiod[WIjx)c, ..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashpg_xtalFreq. y"pg_rtcXtalFreq. y"..\\..\\..\\..\\devices\\MIMXRT1015\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash`d7__asm___11_fsl_clock_c_07a918fd____REVSH`d..\\..\\..\\..\\devices\\MIMXRT1015\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashDH 8__asm___11_fsl_clock_c_07a918fd____REV16DHbsp\src\hardware_init_MIMXRT1015.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashr89?Yflexspi_iomux_config"41iinstance[2iconfig/1ZcsPadCtlValue[1ZdqsPadCtlValue[1ZsclkPadCtlValue[1ZdataPadCtlValue[1> flexspi_set_failsafe_setting"\ 1iconfig/1^__resultP8XstatusP> flexspi_nor_write_persistent\f 1idata/r1^__resultP> flexspi_nor_read_persistentfr0idata/T1^__resultP bsp\\src\\hardware_init_MIMXRT1015.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash\`:__asm___26_hardware_init_MIMXRT1015_c_753bbbb7____REVSH\`bsp\\src\\hardware_init_MIMXRT1015.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash@DL;__asm___26_hardware_init_MIMXRT1015_c_753bbbb7____REV16@Dbsp\src\clock_config_MIMXRT1015.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash|=?'clock_init|G3Xahb_divider[TF7)o74?flexspi_clock_gate_enable33iinstance[4?flexspi_clock_gate_disable3iinstance[4?yflexspi_clock_config2iinstance[4ifreq4isampleClkMode[t4)_flexspi_clock_paramfrac<#podf<#Pflexspi_clock_param_tXpfd480[V Xcscmr1[W Xfrac[\Xpodf[X< Yk_sdr_clock_configD Yk_ddr_clock_configZflexspi_config_array a4"> flexspi_get_clock$2iinstance[B4itype@$4ifreq04^__resultPXclockFrequency[T XstatushXahbBusDivider[WZseralRootClkDivider[3Xarm_clock[` ZpfdFrac[3ZpfdClk[3\flexspi_clk_src[>  flexspi_get_max_supported_freq$L2iinstance[3ifreq03iclkMode[z3^__resultP&XstatusP>  get_core_clock[LTz2^__result[P>  get_bus_clock[TrZ2^__result[PXahbBusDivider[T? flexspi_sw_delay_usr82iuskg3XticksPerUs[W YticksCount0hbsp\\src\\clock_config_MIMXRT1015.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashX\?__asm___25_clock_config_MIMXRT1015_c_efd8dd31____REVSHX\bsp\\src\\clock_config_MIMXRT1015.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash<@ @__asm___25_clock_config_MIMXRT1015_c_efd8dd31____REV16<@FlashDev.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashpFlashDeviceE y"FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashpFDintunsigned longunsigned char"?disableWatchdogp5>=InitD5iadr7iclk6ifnc6___result6Zstatus6Yoption8e`>QUnInitDJ5ifnc6^__resultP>\EraseChipJbi5___result{6>gEraseSectorbI5iadr]6___resultJ6>vProgramPage)5iadr,6isz6ibuf5___result5IH]F5bc]P>bp]QDb{]RFlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashpconfig)i y"FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flashTXF__asm___10_FlashPrg_c_config____REVSHTXFlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\repo1\mcu-sdk-2.0\boards\evkmimxrt1015\cmsis_pack_flash_algo\qspi_flash8<F__asm___10_FlashPrg_c_config____REV168< ..\..\..\..\CMSIS\Include\C:\Keil_v525\ARM\ARMCC\Bin\..\include\core_cm7.hstdint.hcmsis_version.hcmsis_compiler.hmpu_armv7.hPs ..\..\..\..\devices\MIMXRT1015\..\..\..\..\CMSIS\Include\system_MIMXRT1015.ccore_cm7.hI~ ,0 -' -'; -0 2 2# 3j+p!j -l+r# 3k q TkVP>mW2)   @   -\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hl\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hP middleware\flexspi\C:\Keil_v525\ARM\ARMCC\Bin\..\include\..\..\..\..\devices\MIMXRT1015\middleware\flexspi\fsl_flexspi.cfsl_flexspi.hassert.hstdbool.hfsl_device_registers.hxm middleware\flexspi\..\..\..\..\platform\drivers\common\fsl_flexspi.hfsl_common.h$ 8 middleware\flexspi\fsl_flexspi.c:  ( ' ~ ' ~ ' ~ ' ~ ' ~ ' ~ "~      F't  '  ' ! -2,21 )![W&!!-QI& 2 '   "%  %    " ~& !/  '2 ~ 0 o! n&&23 ! !9, ., . . .!"    "  ,.> 9' &- '"/98G 8] & S/     "'  "  @~C  d     8~I x |!  2 (     1 $ 4,96' ~#!.}&-M~C2' T* >0 !$ 4& 96' ~#! w , ' T*   . ':}  ~~& ! 6 9  2 {  f|,   + '  !D' j .@ C     |  u     ;V + '  "!Q9@!  &-_OG <%/P2 z       ,0  -D&  0 ;3 Z(  "  ,$v k        (488',&'2 cE&&'3 3[$x/ G;  "  ,$v l !   ?!:& ? !   0 G "  ! &" %' *"""" &  &  !G!2I  " ~    / x      { !   /( r\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hh\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hL C:\Keil_v525\ARM\ARMCC\Bin\..\include\.\middleware\middleware\flexspi_nor\middleware\flexspi_nor\flexspi_nor_flash.cstring.hstdlib.hstdbool.hflexspi/fsl_flexspi.hflexspi_nor_flash.hflexspi_nor_flash.c middleware\flexspi_nor\..\..\..\..\platform\drivers\common\.\middleware\flexspi_nor_flash.hfsl_common.hflexspi/fsl_flexspi.hB middleware\flexspi_nor\flexspi_nor_flash.c &  4  t0E )     )2  '> M4 ' -  _#& 2  E& n4     '> M2  p '.  " $I%P   " '3 !' *'. !' &  %( 8 ~$ D=""$' 2  + '  !!E&  2   '4 Z('"' ' $(   2 E&  i    2'2 $k '"##' 2  + '  "E&  2   '2 Y)'"##' 2  + '  "E&  2   '2 Y)'-    ' u &) * Ls  ' @x  -& 2%' $@'  '!'! '! ` " &  ,&  "Q! p  ) 9E& # ,J  !3   2 E& 2 & 3%  , &' h,& 3`,+    7  (4  ! /,8%># )- 2 7! )q ! !)" ' !&5L} L}  2: ;  '  ( - '   2 ' ''  #'-!"-!$''!  ke).% #' '! & ,   '!' '--''   "    (  (8' '!/%''2& .%(!)3%(!$    ~y #$#     "}   2   ! * "AF   9  ! # F&!$5}+)%-(8!8 1T &#%  ' &   (!2 K,  13 -'-'&   !  &  '.&+ 2  2  + ' 2  % ) 2  !!!!!!    ~     ! E  E  !4DDDD +\!o &  ,)( 7 M~C w#F   ",  .  .    ,   - ! ,   # &     ?&    !  ; 3&! " !-)*!   '#)!0/9!/;!/;!/:!/; {{Gw{<0 WcG{{AG !   } # ?  ( ,    &   '3 '5 ,  -  # @% '  )'e_i"(   #))'(! !~ #E) & ! !,4      ,J  .       ) "&   .z  .z  @,  .-9-9-8-9 }eR, F # '  ( 0     # $!# ~  "  & R,,, , , ,k   ' O3   ,F,% ',"`y  ,J/-,9), !j S/& "3 (  !3; &  q  c\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hd\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hH ..\..\..\..\devices\MIMXRT1015\drivers\..\..\..\..\devices\MIMXRT1015\..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.cfsl_clock.hdrivers\fsl_clock.c ..\..\..\..\devices\MIMXRT1015\drivers\..\..\..\..\platform\drivers\common\..\..\..\..\devices\MIMXRT1015\fsl_clock.hfsl_common.hdrivers\fsl_clock.ha ..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.cdrivers\fsl_clock.h|a  Q||7  kp- \+b .pXy  Ly  ! @>JJJp ' @>JJJpy 3k&  r Tk   m'  4 4    !,,VU . -* %KV% d  z            F= -$"?8, ~#$?j_ 024 35,-3,2 jZ,"q 02   v,_ @nF 6,  v F 6> &;48 D ;48 D& 3)1. -/-+ '1 .N+[\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.h`\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hD ..\..\..\..\devices\MIMXRT1015\.\middleware\bsp\src\hardware_init_MIMXRT1015.cfsl_device_registers.hflexspi/fsl_flexspi.hflexspi_nor/flexspi_nor_flash.h9 bsp\src\hardware_init_MIMXRT1015.c '!      "    '!         '#!  n\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.h\\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.h@ ..\..\..\..\devices\MIMXRT1015\..\..\..\..\devices\MIMXRT1015\drivers\.\middleware\bsp\src\clock_config_MIMXRT1015.cfsl_device_registers.hfsl_clock.hflexspi/fsl_flexspi.h ..\..\..\..\devices\MIMXRT1015\drivers\..\..\..\..\platform\drivers\common\fsl_clock.hfsl_common.ho ..\..\..\..\devices\MIMXRT1015\drivers\bsp\src\clock_config_MIMXRT1015.cfsl_clock.h|'x3  +=! .1I"  ~=w/4AT22>> R 4  &;0     ! 3,' ! + N3 ! 42 '& ,39 ' d !     r2,2& ' ~) x I\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hX\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.h<8. FlashDev.cFlashOS.H .\middleware\..\..\..\..\platform\drivers\common\flexspi_nor/flexspi_nor_flash.hfsl_common.hflexspi/fsl_flexspi.hxo .\middleware\..\..\..\..\platform\drivers\common\flexspi/fsl_flexspi.hfsl_common.h( ..\..\..\..\platform\drivers\common\C:\Keil_v525\ARM\ARMCC\Bin\..\include\..\..\..\..\devices\MIMXRT1015\..\..\..\..\devices\MIMXRT1015\drivers\fsl_common.hassert.hstdbool.hstdint.hstring.hstdlib.hfsl_device_registers.hfsl_clock.h ..\..\..\..\devices\MIMXRT1015\..\..\..\..\CMSIS\Include\MIMXRT1015.hcore_cm7.hsystem_MIMXRT1015.h ..\..\..\..\CMSIS\Include\C:\Keil_v525\ARM\ARMCC\Bin\..\include\core_cm7.hstdint.hcmsis_version.hcmsis_compiler.hmpu_armv7.hPF C:\Keil_v525\ARM\ARMCC\Bin\..\include\stdint.h,  FlashOS.HJ ..\..\..\..\CMSIS\Include\FlashPrg.ccore_cm7.hp,. -' -' -; -. 2 "2 1 1 C~  = 2  @  !\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.hT\E ..\\..\\..\\..\\CMSIS\\Include\\cmsis_armcc.h8xz}z }x}}} }}}LRTVrTTTTT}>}}}}}* , }, . }. }(} } } ( }(( * } } } ^ }^ ` }` }t v }v x }x }( } } } r }r t }D F }F H }$H } }}D }vx}xz}z}}}}$t}8tv}vx}xz}z}}<>}>v}}<}}}}0}}}v}Zv}}} }Z} }}$}0}}}}}}}z}fz}Rf}>R}*>} *} }}8T Q >UP>VTPUTPUn `< T0 V V* 2 Q2 U* . P. d V \ U W Q * T P * d\ ` P  U \ V R W Q T P ` V \ U Wt | Q| Tt x Px d j \ j W R t U Q t T P t ` U h Lb WZ HD L SL hD L RL dD L QL TD H PH \  P < P V < V U < UD SD RD QPD TvSVvRUv~Q~Tv|P|WDlL&lP$lTlWSvURvVQvTPv\.Q PHLPTWV@DRvQLP"LPT W VX\v~Q~UvzPzdJpU<BPBvV T<TQ<UP<SVPWU\\QTPdPPvPZvPPXUQXTPXVTTSURdQWPVvj@2 HzXzUzWVVzV\4\QTPdPQPPQPz~P~QtvPfjPjxQ`bPRZPZdQLNP>BPBPQ8:P*.P.<Q *P PPp'r'}r't'}$t''}''}x&z&}z&|&}$|&&}0&&}&p'}0%%}%x&}h!j!}j!l!} l!%}%%}}} f!}f!h!}}} }}}} }}}}}0}rt}tv}v}}}:<}<>}>p}pr}xz}z|}|8}8:}@B}BD} Dv}vx} } }$ >}>@}R T }T V }$V } }H J }J L } L P }P R }}}F }F H }}}$}}}}}}}} }}}} }}}}}}}}$}}}} }0}vx}xz}$z}8}}}$t}tv}~}}$}8}:<}<>}>|}8|~}}:}''V''''z''Up'x'Sx''hp'x'Rx''Tp'v'Qv''Wp't'Pt''\&b'T&b'X&&P&n'W~&n'V~&n'Ux&&S&n'hx&&R&n'dx&&Q&n'Tx&|&P|&n'\%%R%x&U%%Q%x&T%%P%x&Wp#%}d#%}X#%~L#%~@#%~>#%~<#%~<#%W"%!%U!%!%h!p!Rp!%hh!p!Qp!%Th!l!Pl!%`0 Q( P^!~Rh!UQh!TPh!`~~~QPV.~~UWRhQTP`WVRUQTP`RVQTPWrSVr|R|UrzQzTrxPxW:HSHrV:DRDrU:BQBrT:@P@rWxR:UxQ:Tx~P~:Wb~Pb~nUnnT@HRHxh@HQHxT@DPDx`PPp&6d 6B 6> 6: 6H 6P 6T 6U V8V6V S @W R @d Q @T P @\ S * PZ L LR ^ S^ hR RR ^ Q^ UR X PX T B V B  B  B H P RP R hH P QP R TH L PL R `SH  RH WQH TPH VWSURVQTP\SVRTQUPWRWQVP`RWQVP`QVPdShRWQTP\W(V\RUQTP`vShvRdvQTv|P|V S vVRvUQvTPv\~Sh~Rd~QT~PV:HSH~V:DRD~U:BQB~T:@P@~WQ:TP:VR j } } R } }X Z }Z }B X }  } B } }} }}}} x}nx}n}}jl}l}j}}}}}}}}}LN}N}}}L}}}}}@B}B}}@}}}tv}v}}0} 02}2t} ` b P P R V PX ^ Q^ RX PB X P  Q B R B P PPQnPjrQrUjnPnTjPQPRTTTTT TT "T*,T46T>@THJTRTT\^TfhTprTz|TTPUP@FPFTTTTTT&(T0@TPTtzPzTU6U\tW\rP\rT8Xh4Xd.2P .P(hlrlPrW^j}T^}T}}}^bPbjQTXPX^QPTQU W hVQTP}>}}}}}}}}}(}HJ}JL} L}}4H} 4}} }>TRQPS|Xn\ ^dd"R"VQUPSHRRRUHNQNTHLPL`4HP 4PP@B}B}}@}}}}}}}} }}:<P$R$>UQ>VP>TPPTPPQPTRWQVPU __CORE_CM7_H_GENERIC "?B__CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)C__CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB)D__CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB )G__CORTEX_M (7U)U__FPU_USED 0U__CORE_CM7_H_DEPENDANT __I volatile const__O volatile__IO volatile__IM volatile const__OM volatile__IOM volatileAPSR_N_Pos 31UAPSR_N_Msk (1UL << APSR_N_Pos)APSR_Z_Pos 30UAPSR_Z_Msk (1UL << APSR_Z_Pos)APSR_C_Pos 29UAPSR_C_Msk (1UL << APSR_C_Pos)APSR_V_Pos 28UAPSR_V_Msk (1UL << APSR_V_Pos)APSR_Q_Pos 27UAPSR_Q_Msk (1UL << APSR_Q_Pos)APSR_GE_Pos 16UAPSR_GE_Msk (0xFUL << APSR_GE_Pos)IPSR_ISR_Pos 0UIPSR_ISR_Msk (0x1FFUL )xPSR_N_Pos 31UxPSR_N_Msk (1UL << xPSR_N_Pos)xPSR_Z_Pos 30UxPSR_Z_Msk (1UL << xPSR_Z_Pos)xPSR_C_Pos 29UxPSR_C_Msk (1UL << xPSR_C_Pos)xPSR_V_Pos 28UxPSR_V_Msk (1UL << xPSR_V_Pos)xPSR_Q_Pos 27UxPSR_Q_Msk (1UL << xPSR_Q_Pos)xPSR_ICI_IT_2_Pos 25UxPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)xPSR_T_Pos 24UxPSR_T_Msk (1UL << xPSR_T_Pos)xPSR_GE_Pos 16UxPSR_GE_Msk (0xFUL << xPSR_GE_Pos)xPSR_ICI_IT_1_Pos 10UxPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)xPSR_ISR_Pos 0UxPSR_ISR_Msk (0x1FFUL )CONTROL_FPCA_Pos 2UCONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)CONTROL_SPSEL_Pos 1UCONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)CONTROL_nPRIV_Pos 0UCONTROL_nPRIV_Msk (1UL )NVIC_STIR_INTID_Pos 0UNVIC_STIR_INTID_Msk (0x1FFUL )SCB_CPUID_IMPLEMENTER_Pos 24USCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)SCB_CPUID_VARIANT_Pos 20USCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)SCB_CPUID_ARCHITECTURE_Pos 16USCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)SCB_CPUID_PARTNO_Pos 4USCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)SCB_CPUID_REVISION_Pos 0USCB_CPUID_REVISION_Msk (0xFUL )SCB_ICSR_NMIPENDSET_Pos 31USCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)SCB_ICSR_PENDSVSET_Pos 28USCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)SCB_ICSR_PENDSVCLR_Pos 27USCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)SCB_ICSR_PENDSTSET_Pos 26USCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)SCB_ICSR_PENDSTCLR_Pos 25USCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)SCB_ICSR_ISRPREEMPT_Pos 23USCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)SCB_ICSR_ISRPENDING_Pos 22USCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)SCB_ICSR_VECTPENDING_Pos 12USCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)SCB_ICSR_RETTOBASE_Pos 11USCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)SCB_ICSR_VECTACTIVE_Pos 0USCB_ICSR_VECTACTIVE_Msk (0x1FFUL )SCB_VTOR_TBLOFF_Pos 7USCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)SCB_AIRCR_VECTKEY_Pos 16USCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)SCB_AIRCR_VECTKEYSTAT_Pos 16USCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)SCB_AIRCR_ENDIANESS_Pos 15USCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)SCB_AIRCR_PRIGROUP_Pos 8USCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)SCB_AIRCR_SYSRESETREQ_Pos 2USCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)SCB_AIRCR_VECTCLRACTIVE_Pos 1USCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)SCB_AIRCR_VECTRESET_Pos 0USCB_AIRCR_VECTRESET_Msk (1UL )SCB_SCR_SEVONPEND_Pos 4USCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)SCB_SCR_SLEEPDEEP_Pos 2USCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)SCB_SCR_SLEEPONEXIT_Pos 1USCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)SCB_CCR_BP_Pos 18USCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)SCB_CCR_IC_Pos 17USCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)SCB_CCR_DC_Pos 16USCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)SCB_CCR_STKALIGN_Pos 9USCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)SCB_CCR_BFHFNMIGN_Pos 8USCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)SCB_CCR_DIV_0_TRP_Pos 4USCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)SCB_CCR_UNALIGN_TRP_Pos 3USCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)SCB_CCR_USERSETMPEND_Pos 1USCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)SCB_CCR_NONBASETHRDENA_Pos 0USCB_CCR_NONBASETHRDENA_Msk (1UL )SCB_SHCSR_USGFAULTENA_Pos 18USCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)SCB_SHCSR_BUSFAULTENA_Pos 17USCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)SCB_SHCSR_MEMFAULTENA_Pos 16USCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)SCB_SHCSR_SVCALLPENDED_Pos 15USCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)SCB_SHCSR_BUSFAULTPENDED_Pos 14USCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)SCB_SHCSR_MEMFAULTPENDED_Pos 13USCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)SCB_SHCSR_USGFAULTPENDED_Pos 12USCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)SCB_SHCSR_SYSTICKACT_Pos 11USCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)SCB_SHCSR_PENDSVACT_Pos 10USCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)SCB_SHCSR_MONITORACT_Pos 8USCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)SCB_SHCSR_SVCALLACT_Pos 7USCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)SCB_SHCSR_USGFAULTACT_Pos 3USCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)SCB_SHCSR_BUSFAULTACT_Pos 1USCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)SCB_SHCSR_MEMFAULTACT_Pos 0USCB_SHCSR_MEMFAULTACT_Msk (1UL )SCB_CFSR_USGFAULTSR_Pos 16USCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)SCB_CFSR_BUSFAULTSR_Pos 8USCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)SCB_CFSR_MEMFAULTSR_Pos 0USCB_CFSR_MEMFAULTSR_Msk (0xFFUL )SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)SCB_CFSR_IACCVIOL_Msk (1UL )SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)SCB_HFSR_DEBUGEVT_Pos 31USCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)SCB_HFSR_FORCED_Pos 30USCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)SCB_HFSR_VECTTBL_Pos 1USCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)SCB_DFSR_EXTERNAL_Pos 4USCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)SCB_DFSR_VCATCH_Pos 3USCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)SCB_DFSR_DWTTRAP_Pos 2USCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)SCB_DFSR_BKPT_Pos 1USCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)SCB_DFSR_HALTED_Pos 0USCB_DFSR_HALTED_Msk (1UL )SCB_CLIDR_LOUU_Pos 27USCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)SCB_CLIDR_LOC_Pos 24USCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)SCB_CTR_FORMAT_Pos 29USCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)SCB_CTR_CWG_Pos 24USCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)SCB_CTR_ERG_Pos 20USCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)SCB_CTR_DMINLINE_Pos 16USCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)SCB_CTR_IMINLINE_Pos 0USCB_CTR_IMINLINE_Msk (0xFUL )SCB_CCSIDR_WT_Pos 31USCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)SCB_CCSIDR_WB_Pos 30USCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)SCB_CCSIDR_RA_Pos 29USCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)SCB_CCSIDR_WA_Pos 28USCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)SCB_CCSIDR_NUMSETS_Pos 13USCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)SCB_CCSIDR_ASSOCIATIVITY_Pos 3USCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)SCB_CCSIDR_LINESIZE_Pos 0USCB_CCSIDR_LINESIZE_Msk (7UL )SCB_CSSELR_LEVEL_Pos 1USCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)SCB_CSSELR_IND_Pos 0USCB_CSSELR_IND_Msk (1UL )SCB_STIR_INTID_Pos 0USCB_STIR_INTID_Msk (0x1FFUL )SCB_DCISW_WAY_Pos 30USCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)SCB_DCISW_SET_Pos 5USCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)SCB_DCCSW_WAY_Pos 30USCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)SCB_DCCSW_SET_Pos 5USCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)SCB_DCCISW_WAY_Pos 30USCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)SCB_DCCISW_SET_Pos 5USCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)SCB_ITCMCR_SZ_Pos 3USCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)SCB_ITCMCR_RETEN_Pos 2USCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)SCB_ITCMCR_RMW_Pos 1USCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)SCB_ITCMCR_EN_Pos 0USCB_ITCMCR_EN_Msk (1UL )SCB_DTCMCR_SZ_Pos 3USCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)SCB_DTCMCR_RETEN_Pos 2USCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)SCB_DTCMCR_RMW_Pos 1USCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)SCB_DTCMCR_EN_Pos 0USCB_DTCMCR_EN_Msk (1UL )SCB_AHBPCR_SZ_Pos 1USCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)SCB_AHBPCR_EN_Pos 0USCB_AHBPCR_EN_Msk (1UL )SCB_CACR_FORCEWT_Pos 2USCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)SCB_CACR_ECCEN_Pos 1USCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)SCB_CACR_SIWT_Pos 0USCB_CACR_SIWT_Msk (1UL )SCB_AHBSCR_INITCOUNT_Pos 11USCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)SCB_AHBSCR_TPRI_Pos 2USCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)SCB_AHBSCR_CTL_Pos 0USCB_AHBSCR_CTL_Msk (3UL )SCB_ABFSR_AXIMTYPE_Pos 8USCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)SCB_ABFSR_EPPB_Pos 4USCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)SCB_ABFSR_AXIM_Pos 3USCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)SCB_ABFSR_AHBP_Pos 2USCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)SCB_ABFSR_DTCM_Pos 1USCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)SCB_ABFSR_ITCM_Pos 0USCB_ABFSR_ITCM_Msk (1UL )SCnSCB_ICTR_INTLINESNUM_Pos 0USCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12USCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)SCnSCB_ACTLR_DISRAMODE_Pos 11USCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)SCnSCB_ACTLR_FPEXCODIS_Pos 10USCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)SCnSCB_ACTLR_DISFOLD_Pos 2USCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)SCnSCB_ACTLR_DISMCYCINT_Pos 0USCnSCB_ACTLR_DISMCYCINT_Msk (1UL )SysTick_CTRL_COUNTFLAG_Pos 16USysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)SysTick_CTRL_CLKSOURCE_Pos 2USysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)SysTick_CTRL_TICKINT_Pos 1USysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)SysTick_CTRL_ENABLE_Pos 0USysTick_CTRL_ENABLE_Msk (1UL )SysTick_LOAD_RELOAD_Pos 0USysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )SysTick_VAL_CURRENT_Pos 0USysTick_VAL_CURRENT_Msk (0xFFFFFFUL )SysTick_CALIB_NOREF_Pos 31USysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)SysTick_CALIB_SKEW_Pos 30USysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)SysTick_CALIB_TENMS_Pos 0USysTick_CALIB_TENMS_Msk (0xFFFFFFUL )ITM_TPR_PRIVMASK_Pos 0UITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL )ITM_TCR_BUSY_Pos 23UITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)ITM_TCR_TraceBusID_Pos 16UITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)ITM_TCR_GTSFREQ_Pos 10UITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)ITM_TCR_TSPrescale_Pos 8UITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)ITM_TCR_SWOENA_Pos 4UITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)ITM_TCR_DWTENA_Pos 3UITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)ITM_TCR_SYNCENA_Pos 2UITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)ITM_TCR_TSENA_Pos 1UITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)ITM_TCR_ITMENA_Pos 0UITM_TCR_ITMENA_Msk (1UL )ITM_IWR_ATVALIDM_Pos 0UITM_IWR_ATVALIDM_Msk (1UL )ITM_IRR_ATREADYM_Pos 0UITM_IRR_ATREADYM_Msk (1UL )ITM_IMCR_INTEGRATION_Pos 0UITM_IMCR_INTEGRATION_Msk (1UL )ITM_LSR_ByteAcc_Pos 2UITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)ITM_LSR_Access_Pos 1UITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)ITM_LSR_Present_Pos 0UITM_LSR_Present_Msk (1UL )DWT_CTRL_NUMCOMP_Pos 28UDWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)DWT_CTRL_NOTRCPKT_Pos 27UDWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) DWT_CTRL_NOEXTTRIG_Pos 26U DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) DWT_CTRL_NOCYCCNT_Pos 25U DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) DWT_CTRL_NOPRFCNT_Pos 24U DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) DWT_CTRL_CYCEVTENA_Pos 22U DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) DWT_CTRL_FOLDEVTENA_Pos 21U DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) DWT_CTRL_LSUEVTENA_Pos 20U DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) DWT_CTRL_SLEEPEVTENA_Pos 19U DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) DWT_CTRL_EXCEVTENA_Pos 18U DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) DWT_CTRL_CPIEVTENA_Pos 17U DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) DWT_CTRL_EXCTRCENA_Pos 16U DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) DWT_CTRL_PCSAMPLENA_Pos 12U DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) DWT_CTRL_SYNCTAP_Pos 10U DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) DWT_CTRL_CYCTAP_Pos 9U DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) DWT_CTRL_POSTINIT_Pos 5U DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) DWT_CTRL_POSTPRESET_Pos 1U DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) DWT_CTRL_CYCCNTENA_Pos 0U DWT_CTRL_CYCCNTENA_Msk (0x1UL ) DWT_CPICNT_CPICNT_Pos 0U DWT_CPICNT_CPICNT_Msk (0xFFUL ) DWT_EXCCNT_EXCCNT_Pos 0U DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) DWT_SLEEPCNT_SLEEPCNT_Pos 0U DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) DWT_LSUCNT_LSUCNT_Pos 0U DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) DWT_FOLDCNT_FOLDCNT_Pos 0U DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) DWT_MASK_MASK_Pos 0U DWT_MASK_MASK_Msk (0x1FUL ) DWT_FUNCTION_MATCHED_Pos 24U DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) DWT_FUNCTION_DATAVADDR1_Pos 16U DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) DWT_FUNCTION_DATAVADDR0_Pos 12U DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) DWT_FUNCTION_DATAVSIZE_Pos 10U DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) DWT_FUNCTION_LNK1ENA_Pos 9U DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) DWT_FUNCTION_DATAVMATCH_Pos 8U DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) DWT_FUNCTION_CYCMATCH_Pos 7U DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) DWT_FUNCTION_EMITRANGE_Pos 5U DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) DWT_FUNCTION_FUNCTION_Pos 0U DWT_FUNCTION_FUNCTION_Msk (0xFUL ) TPI_ACPR_PRESCALER_Pos 0U TPI_ACPR_PRESCALER_Msk (0x1FFFUL ) TPI_ACPR_SWOSCALER_Pos 0U TPI_ACPR_SWOSCALER_Msk (0xFFFFUL ) TPI_SPPR_TXMODE_Pos 0U TPI_SPPR_TXMODE_Msk (0x3UL ) TPI_FFSR_FtNonStop_Pos 3U TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) TPI_FFSR_TCPresent_Pos 2U TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) TPI_FFSR_FtStopped_Pos 1U TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) TPI_FFSR_FlInProg_Pos 0U TPI_FFSR_FlInProg_Msk (0x1UL ) TPI_FFCR_TrigIn_Pos 8U TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) TPI_FFCR_EnFCont_Pos 1U TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) TPI_TRIGGER_TRIGGER_Pos 0U TPI_TRIGGER_TRIGGER_Msk (0x1UL ) TPI_FIFO0_ITM_ATVALID_Pos 29U TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) TPI_FIFO0_ITM_bytecount_Pos 27U TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) TPI_FIFO0_ETM_ATVALID_Pos 26U TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) TPI_FIFO0_ETM_bytecount_Pos 24U TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) TPI_FIFO0_ETM2_Pos 16U TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) TPI_FIFO0_ETM1_Pos 8U TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) TPI_FIFO0_ETM0_Pos 0U TPI_FIFO0_ETM0_Msk (0xFFUL ) TPI_ITATBCTR2_ATREADY_Pos 0U TPI_ITATBCTR2_ATREADY_Msk (0x1UL ) TPI_FIFO1_ITM_ATVALID_Pos 29U TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) TPI_FIFO1_ITM_bytecount_Pos 27U TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) TPI_FIFO1_ETM_ATVALID_Pos 26U TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) TPI_FIFO1_ETM_bytecount_Pos 24U TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) TPI_FIFO1_ITM2_Pos 16U TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) TPI_FIFO1_ITM1_Pos 8U TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) TPI_FIFO1_ITM0_Pos 0U TPI_FIFO1_ITM0_Msk (0xFFUL ) TPI_ITATBCTR0_ATREADY_Pos 0U TPI_ITATBCTR0_ATREADY_Msk (0x1UL ) TPI_ITCTRL_Mode_Pos 0U TPI_ITCTRL_Mode_Msk (0x1UL ) TPI_DEVID_NRZVALID_Pos 11U TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) TPI_DEVID_MANCVALID_Pos 10U TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) TPI_DEVID_PTINVALID_Pos 9U TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) TPI_DEVID_MinBufSz_Pos 6U TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) TPI_DEVID_AsynClkIn_Pos 5U TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) TPI_DEVID_NrTraceInput_Pos 0U TPI_DEVID_NrTraceInput_Msk (0x1FUL ) TPI_DEVTYPE_MajorType_Pos 4U TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) TPI_DEVTYPE_SubType_Pos 0U TPI_DEVTYPE_SubType_Msk (0xFUL ) MPU_TYPE_RALIASES 4U MPU_TYPE_IREGION_Pos 16U MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) MPU_TYPE_DREGION_Pos 8U MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) MPU_TYPE_SEPARATE_Pos 0U MPU_TYPE_SEPARATE_Msk (1UL ) MPU_CTRL_PRIVDEFENA_Pos 2U MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) MPU_CTRL_HFNMIENA_Pos 1U MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) MPU_CTRL_ENABLE_Pos 0U MPU_CTRL_ENABLE_Msk (1UL ) MPU_RNR_REGION_Pos 0U MPU_RNR_REGION_Msk (0xFFUL ) MPU_RBAR_ADDR_Pos 5U MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) MPU_RBAR_VALID_Pos 4U MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) MPU_RBAR_REGION_Pos 0U MPU_RBAR_REGION_Msk (0xFUL ) MPU_RASR_ATTRS_Pos 16U MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) MPU_RASR_XN_Pos 28U MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) MPU_RASR_AP_Pos 24U MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) MPU_RASR_TEX_Pos 19U MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) MPU_RASR_S_Pos 18U MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) MPU_RASR_C_Pos 17U MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) MPU_RASR_B_Pos 16U MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) MPU_RASR_SRD_Pos 8U MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) MPU_RASR_SIZE_Pos 1U MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) MPU_RASR_ENABLE_Pos 0U MPU_RASR_ENABLE_Msk (1UL ) FPU_FPCCR_ASPEN_Pos 31U FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) FPU_FPCCR_LSPEN_Pos 30U FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) FPU_FPCCR_MONRDY_Pos 8U FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) FPU_FPCCR_BFRDY_Pos 6U FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) FPU_FPCCR_MMRDY_Pos 5U FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) FPU_FPCCR_HFRDY_Pos 4U FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) FPU_FPCCR_THREAD_Pos 3U FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) FPU_FPCCR_USER_Pos 1U FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) FPU_FPCCR_LSPACT_Pos 0U FPU_FPCCR_LSPACT_Msk (1UL ) FPU_FPCAR_ADDRESS_Pos 3U FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) FPU_FPDSCR_AHP_Pos 26U FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) FPU_FPDSCR_DN_Pos 25U FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) FPU_FPDSCR_FZ_Pos 24U FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) FPU_FPDSCR_RMode_Pos 22U FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) FPU_MVFR0_FP_rounding_modes_Pos 28U FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) FPU_MVFR0_Short_vectors_Pos 24U FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) FPU_MVFR0_Square_root_Pos 20U FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) FPU_MVFR0_Divide_Pos 16U FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) FPU_MVFR0_FP_excep_trapping_Pos 12U FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) FPU_MVFR0_Double_precision_Pos 8U FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) FPU_MVFR0_Single_precision_Pos 4U FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) FPU_MVFR0_A_SIMD_registers_Pos 0U FPU_MVFR0_A_SIMD_registers_Msk (0xFUL ) FPU_MVFR1_FP_fused_MAC_Pos 28U FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) FPU_MVFR1_FP_HPFP_Pos 24U FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) FPU_MVFR1_D_NaN_mode_Pos 4U FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) FPU_MVFR1_FtZ_mode_Pos 0U FPU_MVFR1_FtZ_mode_Msk (0xFUL ) CoreDebug_DHCSR_DBGKEY_Pos 16U CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) CoreDebug_DHCSR_S_RESET_ST_Pos 25U CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) CoreDebug_DHCSR_S_LOCKUP_Pos 19U CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) CoreDebug_DHCSR_S_SLEEP_Pos 18U CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) CoreDebug_DHCSR_S_HALT_Pos 17U CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) CoreDebug_DHCSR_S_REGRDY_Pos 16U CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) CoreDebug_DHCSR_C_MASKINTS_Pos 3U CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) CoreDebug_DHCSR_C_STEP_Pos 2U CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) CoreDebug_DHCSR_C_HALT_Pos 1U CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) CoreDebug_DHCSR_C_DEBUGEN_Pos 0U CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) CoreDebug_DCRSR_REGWnR_Pos 16U CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) CoreDebug_DCRSR_REGSEL_Pos 0U CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) CoreDebug_DEMCR_TRCENA_Pos 24U CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) CoreDebug_DEMCR_MON_REQ_Pos 19U CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) CoreDebug_DEMCR_MON_STEP_Pos 18U CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) CoreDebug_DEMCR_MON_PEND_Pos 17U CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) CoreDebug_DEMCR_MON_EN_Pos 16U CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) CoreDebug_DEMCR_VC_HARDERR_Pos 10U CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) CoreDebug_DEMCR_VC_INTERR_Pos 9U CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) CoreDebug_DEMCR_VC_BUSERR_Pos 8U CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) CoreDebug_DEMCR_VC_STATERR_Pos 7U CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) CoreDebug_DEMCR_VC_CHKERR_Pos 6U CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) CoreDebug_DEMCR_VC_NOCPERR_Pos 5U CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) CoreDebug_DEMCR_VC_MMERR_Pos 4U CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) CoreDebug_DEMCR_VC_CORERESET_Pos 0U CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) _VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) _FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) SCS_BASE (0xE000E000UL) ITM_BASE (0xE0000000UL) DWT_BASE (0xE0001000UL) TPI_BASE (0xE0040000UL) CoreDebug_BASE (0xE000EDF0UL) SysTick_BASE (SCS_BASE + 0x0010UL) NVIC_BASE (SCS_BASE + 0x0100UL) SCB_BASE (SCS_BASE + 0x0D00UL) SCnSCB ((SCnSCB_Type *) SCS_BASE ) SCB ((SCB_Type *) SCB_BASE ) SysTick ((SysTick_Type *) SysTick_BASE ) NVIC ((NVIC_Type *) NVIC_BASE ) ITM ((ITM_Type *) ITM_BASE ) DWT ((DWT_Type *) DWT_BASE ) TPI ((TPI_Type *) TPI_BASE ) CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) MPU_BASE (SCS_BASE + 0x0D90UL) MPU ((MPU_Type *) MPU_BASE ) FPU_BASE (SCS_BASE + 0x0F30UL) FPU ((FPU_Type *) FPU_BASE )NVIC_SetPriorityGrouping __NVIC_SetPriorityGroupingNVIC_GetPriorityGrouping __NVIC_GetPriorityGroupingNVIC_EnableIRQ __NVIC_EnableIRQNVIC_GetEnableIRQ __NVIC_GetEnableIRQNVIC_DisableIRQ __NVIC_DisableIRQNVIC_GetPendingIRQ __NVIC_GetPendingIRQNVIC_SetPendingIRQ __NVIC_SetPendingIRQNVIC_ClearPendingIRQ __NVIC_ClearPendingIRQNVIC_GetActive __NVIC_GetActiveNVIC_SetPriority __NVIC_SetPriorityNVIC_GetPriority __NVIC_GetPriorityNVIC_SystemReset __NVIC_SystemResetNVIC_SetVector __NVIC_SetVectorNVIC_GetVector __NVIC_GetVectorNVIC_USER_IRQ_OFFSET 16CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) FLEXSPI_LUT_KEY_VAL (0x5AF05AF0ul)FLEXSPI_WAIT_TIMEOUT_NS (500000000UL)FLEXSPI_FREQ_1GHz (1000000000UL)FREQ_1MHz (1000000UL)FLEXSPI_DLLCR_DEFAULT (0x100UL)FLEXSPI0_CLK_GATE_OFFSET 13UFLEXSPI1_CLK_GATE_OFFSET 15UCMD_LUT_FOR_IP_CMD 1 FLEXSPI_PINMUX_VAL 0x08__FSL_FLEXSPI_H__  FlexSPI_LUT_COUNT (64)FlexSPI_AHB_RX_BUF_COUNT (4U)FlexSPI_AHB_RX_BUF_DEPTH (512U)FlexSPI_AHB_TX_BUF_DEPTH (32U)FlexSPI_IP_RX_BUF_DEPTH (256U)FlexSPI_IP_TX_BUF_DEPTH (256U)FLEXSPI_CFG_BLK_TAG (0x42464346UL) FLEXSPI_CFG_BLK_VERSION (0x56010400UL)!FLEXSPI_CFG_BLK_SIZE (512)$FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1'CMD_INDEX_READ 0(CMD_INDEX_READSTATUS 1)CMD_INDEX_WRITEENABLE 2*CMD_INDEX_WRITE 4,CMD_LUT_SEQ_IDX_READ 0-CMD_LUT_SEQ_IDX_READSTATUS 1.CMD_LUT_SEQ_IDX_WRITEENABLE 3/CMD_LUT_SEQ_IDX_WRITE 91CMD_SDR 0x012CMD_DDR 0x213RADDR_SDR 0x024RADDR_DDR 0x225CADDR_SDR 0x036CADDR_DDR 0x237MODE1_SDR 0x048MODE1_DDR 0x249MODE2_SDR 0x05:MODE2_DDR 0x25;MODE4_SDR 0x06MODE8_DDR 0x27?WRITE_SDR 0x08@WRITE_DDR 0x28AREAD_SDR 0x09BREAD_DDR 0x29CLEARN_SDR 0x0ADLEARN_DDR 0x2AEDATSZ_SDR 0x0BFDATSZ_DDR 0x2BGDUMMY_SDR 0x0CHDUMMY_DDR 0x2CIDUMMY_RWDS_SDR 0x0DJDUMMY_RWDS_DDR 0x2DKJMP_ON_CS 0x1FLSTOP 0NFLEXSPI_1PAD 0OFLEXSPI_2PAD 1PFLEXSPI_4PAD 2QFLEXSPI_8PAD 3SFLEXSPI_LUT_SEQ(cmd0,pad0,op0,cmd1,pad1,op1) (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset))   MAX_24BIT_ADDRESSING_SIZE (16UL * 1024 * 1024)NOR_CMD_LUT_FOR_IP_CMD 1_SFDP_SIGNATURE 0x50444653__FLEXSPI_NOR_FLASH_H__   NOR_CMD_INDEX_READ CMD_INDEX_READNOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUSNOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLENOR_CMD_INDEX_ERASESECTOR 3NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITENOR_CMD_INDEX_CHIPERASE 5NOR_CMD_INDEX_DUMMY 6NOR_CMD_INDEX_ERASEBLOCK 7NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READNOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUSNOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLENOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5!NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8"NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE$NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11%NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13&NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14(NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 FSL_COMPONENT_ID "platform.drivers.clock" _FSL_CLOCK_H_  !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0+FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)).CCM_ANALOG_PLL_BYPASS_SHIFT (16U)/CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)0CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)4SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)CBCMR_OFFSET 0x18?CSCMR1_OFFSET 0x1C@CSCMR2_OFFSET 0x20ACSCDR1_OFFSET 0x24BCDCDR_OFFSET 0x30CCSCDR2_OFFSET 0x38DCACRR_OFFSET 0x10ECS1CDR_OFFSET 0x28FCS2CDR_OFFSET 0x2CKPLL_SYS_OFFSET 0x30LPLL_USB1_OFFSET 0x10MPLL_AUDIO_OFFSET 0x70NPLL_ENET_OFFSET 0xE0PCCM_TUPLE(reg,shift,mask,busyShift) (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))RCCM_TUPLE_REG(base,tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))SCCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)TCCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))UCCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)WCCM_NO_BUSY_WAIT (0x20U)\CCM_ANALOG_TUPLE(reg,shift) (((reg & 0xFFFU) << 16U) | (shift))]CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)^CCM_ANALOG_TUPLE_REG_OFF(base,tuple,off) (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))`CCM_ANALOG_TUPLE_REG(base,tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)bCCM_ANALOG_PLL_BYPASS_SHIFT (16U)cCCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)dCCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)iCLKPN_FREQ 0UCLOCK_SetXtal0Freq CLOCK_SetXtalFreqCLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreqADC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Adc1 }AOI_CLOCKS { kCLOCK_Aoi }BEE_CLOCKS { kCLOCK_Bee }DCDC_CLOCKS { kCLOCK_Dcdc }DCP_CLOCKS { kCLOCK_Dcp }DMAMUX_CLOCKS { kCLOCK_Dma }EDMA_CLOCKS { kCLOCK_Dma }ENC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Enc1 }EWM_CLOCKS { kCLOCK_Ewm0 }FLEXIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Flexio1 }FLEXRAM_CLOCKS { kCLOCK_FlexRam }FLEXSPI_CLOCKS { kCLOCK_FlexSpi }GPIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 }GPT_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 }KPP_CLOCKS { kCLOCK_Kpp }LPI2C_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2 }LPSPI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2 }LPUART_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 }OCRAM_EXSC_CLOCKS { kCLOCK_OcramExsc }PIT_CLOCKS { kCLOCK_Pit }PWM_CLOCKS { {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, { kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 } }RTWDOG_CLOCKS { kCLOCK_Wdog3 }SAI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 }TMR_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Timer1 }TRNG_CLOCKS { kCLOCK_Trng }WDOG_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 }SPDIF_CLOCKS { kCLOCK_Spdif }XBARA_CLOCKS { kCLOCK_Xbar1 }XBARB_CLOCKS { kCLOCK_Xbar2 }kCLOCK_CoreSysClk kCLOCK_CpuClkCLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq FREQ_396MHz (396000000U)FREQ_480MHz (480000000U)FREQ_528MHz (528000000U)FREQ_24MHz (24000000U)SW_MUX_CTL_PAD_FLEXSPIB_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00SW_MUX_CTL_PAD_FLEXSPIB_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01SW_MUX_CTL_PAD_FLEXSPIB_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02SW_MUX_CTL_PAD_FLEXSPIB_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03SW_MUX_CTL_PAD_FLEXSPIB_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04SW_MUX_CTL_PAD_FLEXSPIB_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04SW_MUX_CTL_PAD_FLEXSPIA_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05SW_MUX_CTL_PAD_FLEXSPIA_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06SW_MUX_CTL_PAD_FLEXSPIA_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW_MUX_CTL_PAD_FLEXSPIA_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07!SW_MUX_CTL_PAD_FLEXSPIA_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08"SW_MUX_CTL_PAD_FLEXSPIA_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09#SW_MUX_CTL_PAD_FLEXSPIA_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10$SW_MUX_CTL_PAD_FLEXSPIA_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11%SW_MUX_CTL_PAD_FLEXSPIA_SCLK_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04(SW_PAD_CTL_PAD_FLEXSPIB_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00)SW_PAD_CTL_PAD_FLEXSPIB_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01*SW_PAD_CTL_PAD_FLEXSPIB_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02+SW_PAD_CTL_PAD_FLEXSPIB_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03,SW_PAD_CTL_PAD_FLEXSPIB_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05.SW_PAD_CTL_PAD_FLEXSPIB_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_040SW_PAD_CTL_PAD_FLEXSPIA_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_051SW_PAD_CTL_PAD_FLEXSPIA_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_062SW_PAD_CTL_PAD_FLEXSPIA_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_013SW_PAD_CTL_PAD_FLEXSPIA_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_074SW_PAD_CTL_PAD_FLEXSPIA_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_085SW_PAD_CTL_PAD_FLEXSPIA_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_096SW_PAD_CTL_PAD_FLEXSPIA_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_107SW_PAD_CTL_PAD_FLEXSPIA_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_118SW_PAD_CTL_PAD_FLEXSPIA_SCLK_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04:FLEXSPIA_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1);FLEXSPIB_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1)FLEXSPIB_SS0_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4)?FLEXSPIB_DQS_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4)FFLEXSPI_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(0) | IOMUXC_SW_PAD_CTL_PAD_PUS(0))PFLEXSPI_DQS_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | IOMUXC_SW_PAD_CTL_PAD_HYS(1)) FREQ_396MHz (396UL * 1000 * 1000)FREQ_528MHz (528UL * 1000 * 1000)FREQ_24MHz (24UL * 1000 * 1000)FREQ_480MHz (480UL * 1000 * 1000) _FSL_CLOCK_H_  !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0+FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)).CCM_ANALOG_PLL_BYPASS_SHIFT (16U)/CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)0CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)4SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)CBCMR_OFFSET 0x18?CSCMR1_OFFSET 0x1C@CSCMR2_OFFSET 0x20ACSCDR1_OFFSET 0x24BCDCDR_OFFSET 0x30CCSCDR2_OFFSET 0x38DCACRR_OFFSET 0x10ECS1CDR_OFFSET 0x28FCS2CDR_OFFSET 0x2CKPLL_SYS_OFFSET 0x30LPLL_USB1_OFFSET 0x10MPLL_AUDIO_OFFSET 0x70NPLL_ENET_OFFSET 0xE0PCCM_TUPLE(reg,shift,mask,busyShift) (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))RCCM_TUPLE_REG(base,tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))SCCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)TCCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))UCCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)WCCM_NO_BUSY_WAIT (0x20U)\CCM_ANALOG_TUPLE(reg,shift) (((reg & 0xFFFU) << 16U) | (shift))]CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)^CCM_ANALOG_TUPLE_REG_OFF(base,tuple,off) (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))`CCM_ANALOG_TUPLE_REG(base,tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)bCCM_ANALOG_PLL_BYPASS_SHIFT (16U)cCCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)dCCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)iCLKPN_FREQ 0UCLOCK_SetXtal0Freq CLOCK_SetXtalFreqCLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreqADC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Adc1 }AOI_CLOCKS { kCLOCK_Aoi }BEE_CLOCKS { kCLOCK_Bee }DCDC_CLOCKS { kCLOCK_Dcdc }DCP_CLOCKS { kCLOCK_Dcp }DMAMUX_CLOCKS { kCLOCK_Dma }EDMA_CLOCKS { kCLOCK_Dma }ENC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Enc1 }EWM_CLOCKS { kCLOCK_Ewm0 }FLEXIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Flexio1 }FLEXRAM_CLOCKS { kCLOCK_FlexRam }FLEXSPI_CLOCKS { kCLOCK_FlexSpi }GPIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 }GPT_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 }KPP_CLOCKS { kCLOCK_Kpp }LPI2C_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2 }LPSPI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2 }LPUART_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 }OCRAM_EXSC_CLOCKS { kCLOCK_OcramExsc }PIT_CLOCKS { kCLOCK_Pit }PWM_CLOCKS { {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, { kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 } }RTWDOG_CLOCKS { kCLOCK_Wdog3 }SAI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 }TMR_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Timer1 }TRNG_CLOCKS { kCLOCK_Trng }WDOG_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 }SPDIF_CLOCKS { kCLOCK_Spdif }XBARA_CLOCKS { kCLOCK_Xbar1 }XBARB_CLOCKS { kCLOCK_Xbar2 }kCLOCK_CoreSysClk kCLOCK_CpuClkCLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq __FLEXSPI_NOR_FLASH_H__   NOR_CMD_INDEX_READ CMD_INDEX_READNOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUSNOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLENOR_CMD_INDEX_ERASESECTOR 3NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITENOR_CMD_INDEX_CHIPERASE 5NOR_CMD_INDEX_DUMMY 6NOR_CMD_INDEX_ERASEBLOCK 7NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READNOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUSNOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLENOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5!NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8"NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE$NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11%NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13&NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14(NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15__FSL_FLEXSPI_H__  FlexSPI_LUT_COUNT (64)FlexSPI_AHB_RX_BUF_COUNT (4U)FlexSPI_AHB_RX_BUF_DEPTH (512U)FlexSPI_AHB_TX_BUF_DEPTH (32U)FlexSPI_IP_RX_BUF_DEPTH (256U)FlexSPI_IP_TX_BUF_DEPTH (256U)FLEXSPI_CFG_BLK_TAG (0x42464346UL) FLEXSPI_CFG_BLK_VERSION (0x56010400UL)!FLEXSPI_CFG_BLK_SIZE (512)$FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1'CMD_INDEX_READ 0(CMD_INDEX_READSTATUS 1)CMD_INDEX_WRITEENABLE 2*CMD_INDEX_WRITE 4,CMD_LUT_SEQ_IDX_READ 0-CMD_LUT_SEQ_IDX_READSTATUS 1.CMD_LUT_SEQ_IDX_WRITEENABLE 3/CMD_LUT_SEQ_IDX_WRITE 91CMD_SDR 0x012CMD_DDR 0x213RADDR_SDR 0x024RADDR_DDR 0x225CADDR_SDR 0x036CADDR_DDR 0x237MODE1_SDR 0x048MODE1_DDR 0x249MODE2_SDR 0x05:MODE2_DDR 0x25;MODE4_SDR 0x06MODE8_DDR 0x27?WRITE_SDR 0x08@WRITE_DDR 0x28AREAD_SDR 0x09BREAD_DDR 0x29CLEARN_SDR 0x0ADLEARN_DDR 0x2AEDATSZ_SDR 0x0BFDATSZ_DDR 0x2BGDUMMY_SDR 0x0CHDUMMY_DDR 0x2CIDUMMY_RWDS_SDR 0x0DJDUMMY_RWDS_DDR 0x2DKJMP_ON_CS 0x1FLSTOP 0NFLEXSPI_1PAD 0OFLEXSPI_2PAD 1PFLEXSPI_4PAD 2QFLEXSPI_8PAD 3SFLEXSPI_LUT_SEQ(cmd0,pad0,op0,cmd1,pad1,op1) (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset)) _FSL_COMMON_H_   "MAKE_STATUS(group,code) ((((group)*100) + (code)))%MAKE_VERSION(major,minor,bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))*FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)).DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U/DEBUG_CONSOLE_DEVICE_TYPE_UART 1U0DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U1DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U2DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U3DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U4DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U5DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U6DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U7DEBUG_CONSOLE_DEVICE_TYPE_SWO 9UFSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1MIN(a,b) (((a) < (b)) ? (a) : (b))MAX(a,b) (((a) > (b)) ? (a) : (b))ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))USEC_TO_COUNT(us,clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)COUNT_TO_USEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)MSEC_TO_COUNT(ms,clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)COUNT_TO_MSEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)SDK_ALIGN(var,alignbytes) __attribute__((aligned(alignbytes))) varSDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) varSDK_SIZEALIGN(var,alignbytes) ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) varAT_NONCACHEABLE_SECTION_ALIGN(var,alignbytes) __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) varAT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) varAT_NONCACHEABLE_SECTION_ALIGN_INIT(var,alignbytes) __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) varAT_QUICKACCESS_SECTION_CODE(func) funcAT_QUICKACCESS_SECTION_DATA(func) funcRAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) funcSUPPRESS_FALL_THROUGH_WARNING() 3_MIMXRT1015_H_ 7MCU_MEM_MAP_VERSION 0x0100U9MCU_MEM_MAP_VERSION_MINOR 0x0002UFNUMBER_OF_INT_VECTORS 150__MPU_PRESENT 1__ICACHE_PRESENT 1__DCACHE_PRESENT 1__DTCM_PRESENT 1__NVIC_PRIO_BITS 4__Vendor_SysTickConfig 0__FPU_PRESENT 1ADC_HC_ADCH_MASK (0x1FU)ADC_HC_ADCH_SHIFT (0U)ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)ADC_HC_AIEN_MASK (0x80U)ADC_HC_AIEN_SHIFT (7U)ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)ADC_HC_COUNT (8U)ADC_HS_COCO0_MASK (0x1U)ADC_HS_COCO0_SHIFT (0U)ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)ADC_R_CDATA_MASK (0xFFFU)ADC_R_CDATA_SHIFT (0U)ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)ADC_R_COUNT (8U)ADC_CFG_ADICLK_MASK (0x3U)ADC_CFG_ADICLK_SHIFT (0U)ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)ADC_CFG_MODE_MASK (0xCU)ADC_CFG_MODE_SHIFT (2U)ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)ADC_CFG_ADLSMP_MASK (0x10U)ADC_CFG_ADLSMP_SHIFT (4U)ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)ADC_CFG_ADIV_MASK (0x60U)ADC_CFG_ADIV_SHIFT (5U)ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)ADC_CFG_ADLPC_MASK (0x80U)ADC_CFG_ADLPC_SHIFT (7U)ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)ADC_CFG_ADSTS_MASK (0x300U)ADC_CFG_ADSTS_SHIFT (8U)ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)ADC_CFG_ADHSC_MASK (0x400U)ADC_CFG_ADHSC_SHIFT (10U)ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)ADC_CFG_REFSEL_MASK (0x1800U)ADC_CFG_REFSEL_SHIFT (11U)ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)ADC_CFG_ADTRG_MASK (0x2000U)ADC_CFG_ADTRG_SHIFT (13U)ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)ADC_CFG_AVGS_MASK (0xC000U)ADC_CFG_AVGS_SHIFT (14U)ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)ADC_CFG_OVWREN_MASK (0x10000U)ADC_CFG_OVWREN_SHIFT (16U)ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)ADC_GC_ADACKEN_MASK (0x1U)ADC_GC_ADACKEN_SHIFT (0U)ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)ADC_GC_DMAEN_MASK (0x2U)ADC_GC_DMAEN_SHIFT (1U)ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)ADC_GC_ACREN_MASK (0x4U)ADC_GC_ACREN_SHIFT (2U)ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)ADC_GC_ACFGT_MASK (0x8U)ADC_GC_ACFGT_SHIFT (3U)ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)ADC_GC_ACFE_MASK (0x10U)ADC_GC_ACFE_SHIFT (4U)ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)ADC_GC_AVGE_MASK (0x20U)ADC_GC_AVGE_SHIFT (5U)ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)ADC_GC_ADCO_MASK (0x40U)ADC_GC_ADCO_SHIFT (6U)ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)ADC_GC_CAL_MASK (0x80U)ADC_GC_CAL_SHIFT (7U)ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)ADC_GS_ADACT_MASK (0x1U)ADC_GS_ADACT_SHIFT (0U)ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)ADC_GS_CALF_MASK (0x2U)ADC_GS_CALF_SHIFT (1U)ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)ADC_GS_AWKST_MASK (0x4U)ADC_GS_AWKST_SHIFT (2U) ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) ADC_CV_CV1_MASK (0xFFFU) ADC_CV_CV1_SHIFT (0U) ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) ADC_CV_CV2_MASK (0xFFF0000U) ADC_CV_CV2_SHIFT (16U) ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) ADC_OFS_OFS_MASK (0xFFFU) ADC_OFS_OFS_SHIFT (0U) ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) ADC_OFS_SIGN_MASK (0x1000U) ADC_OFS_SIGN_SHIFT (12U) ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) ADC_CAL_CAL_CODE_MASK (0xFU) ADC_CAL_CAL_CODE_SHIFT (0U) ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) ADC1_BASE (0x400C4000u) ADC1 ((ADC_Type *)ADC1_BASE) ADC_BASE_ADDRS { 0u, ADC1_BASE } ADC_BASE_PTRS { (ADC_Type *)0u, ADC1 } ADC_IRQS { NotAvail_IRQn, ADC1_IRQn } ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) ADC_ETC_CTRL_SOFTRST_SHIFT (31U) ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) ADC_ETC_TRIGn_CTRL_COUNT (4U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) ADC_ETC_TRIGn_COUNTER_COUNT (4U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_COUNT (4U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_COUNT (4U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_COUNT (4U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_COUNT (4U) ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) ADC_ETC_TRIGn_RESULT_1_0_COUNT (4U) ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) ADC_ETC_TRIGn_RESULT_3_2_COUNT (4U) ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) ADC_ETC_TRIGn_RESULT_5_4_COUNT (4U) ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) ADC_ETC_TRIGn_RESULT_7_6_COUNT (4U) ADC_ETC_BASE (0x403B0000u) ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } ADC_ETC_BASE_PTRS { ADC_ETC } ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } AIPSTZ_MPR_MPROT5_MASK (0xF00U) AIPSTZ_MPR_MPROT5_SHIFT (8U) AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) AIPSTZ_MPR_MPROT3_MASK (0xF0000U) AIPSTZ_MPR_MPROT3_SHIFT (16U) AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) AIPSTZ_MPR_MPROT2_MASK (0xF00000U) AIPSTZ_MPR_MPROT2_SHIFT (20U) AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) AIPSTZ_MPR_MPROT1_MASK (0xF000000U) AIPSTZ_MPR_MPROT1_SHIFT (24U) AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) AIPSTZ_MPR_MPROT0_SHIFT (28U) AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) AIPSTZ_OPACR_OPAC7_MASK (0xFU) AIPSTZ_OPACR_OPAC7_SHIFT (0U) AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) AIPSTZ_OPACR_OPAC6_MASK (0xF0U) AIPSTZ_OPACR_OPAC6_SHIFT (4U)AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)AIPSTZ_OPACR_OPAC5_MASK (0xF00U)AIPSTZ_OPACR_OPAC5_SHIFT (8U)AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)AIPSTZ_OPACR_OPAC4_MASK (0xF000U)AIPSTZ_OPACR_OPAC4_SHIFT (12U)AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)AIPSTZ_OPACR_OPAC3_SHIFT (16U)AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)AIPSTZ_OPACR_OPAC2_SHIFT (20U)AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)AIPSTZ_OPACR_OPAC1_SHIFT (24U)AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)AIPSTZ_OPACR_OPAC0_SHIFT (28U)AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)AIPSTZ_OPACR1_OPAC15_MASK (0xFU)AIPSTZ_OPACR1_OPAC15_SHIFT (0U)AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)AIPSTZ_OPACR1_OPAC14_SHIFT (4U)AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)AIPSTZ_OPACR1_OPAC13_SHIFT (8U)AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)AIPSTZ_OPACR1_OPAC12_SHIFT (12U)AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)AIPSTZ_OPACR1_OPAC11_SHIFT (16U)AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)AIPSTZ_OPACR1_OPAC10_SHIFT (20U)AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)AIPSTZ_OPACR1_OPAC9_SHIFT (24U)AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)AIPSTZ_OPACR1_OPAC8_SHIFT (28U)AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)AIPSTZ_OPACR2_OPAC23_MASK (0xFU)AIPSTZ_OPACR2_OPAC23_SHIFT (0U)AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)AIPSTZ_OPACR2_OPAC22_SHIFT (4U)AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)AIPSTZ_OPACR2_OPAC21_SHIFT (8U)AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)AIPSTZ_OPACR2_OPAC20_SHIFT (12U)AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)AIPSTZ_OPACR2_OPAC19_SHIFT (16U)AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)AIPSTZ_OPACR2_OPAC18_SHIFT (20U)AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)AIPSTZ_OPACR2_OPAC17_SHIFT (24U)AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)AIPSTZ_OPACR2_OPAC16_SHIFT (28U)AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)AIPSTZ_OPACR3_OPAC31_MASK (0xFU)AIPSTZ_OPACR3_OPAC31_SHIFT (0U)AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)AIPSTZ_OPACR3_OPAC30_SHIFT (4U)AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)AIPSTZ_OPACR3_OPAC29_SHIFT (8U)AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)AIPSTZ_OPACR3_OPAC28_SHIFT (12U)AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)AIPSTZ_OPACR3_OPAC27_SHIFT (16U)AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)AIPSTZ_OPACR3_OPAC26_SHIFT (20U)AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)AIPSTZ_OPACR3_OPAC25_SHIFT (24U)AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)AIPSTZ_OPACR3_OPAC24_SHIFT (28U)AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)AIPSTZ_OPACR4_OPAC33_SHIFT (24U)AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)AIPSTZ_OPACR4_OPAC32_SHIFT (28U)AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)AIPSTZ1_BASE (0x4007C000u)AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)AIPSTZ2_BASE (0x4017C000u)AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)AIPSTZ3_BASE (0x4027C000u)AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)AIPSTZ4_BASE (0x4037C000u)AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }AOI_BFCRT01_PT1_DC_MASK (0x3U)AOI_BFCRT01_PT1_DC_SHIFT (0U)AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)AOI_BFCRT01_PT1_CC_MASK (0xCU)AOI_BFCRT01_PT1_CC_SHIFT (2U)AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)AOI_BFCRT01_PT1_BC_MASK (0x30U)AOI_BFCRT01_PT1_BC_SHIFT (4U)AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)AOI_BFCRT01_PT1_AC_MASK (0xC0U)AOI_BFCRT01_PT1_AC_SHIFT (6U)AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)AOI_BFCRT01_PT0_DC_MASK (0x300U)AOI_BFCRT01_PT0_DC_SHIFT (8U)AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)AOI_BFCRT01_PT0_CC_MASK (0xC00U)AOI_BFCRT01_PT0_CC_SHIFT (10U)AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)AOI_BFCRT01_PT0_BC_MASK (0x3000U)AOI_BFCRT01_PT0_BC_SHIFT (12U)AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)AOI_BFCRT01_PT0_AC_MASK (0xC000U)AOI_BFCRT01_PT0_AC_SHIFT (14U)AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)AOI_BFCRT01_COUNT (4U)AOI_BFCRT23_PT3_DC_MASK (0x3U)AOI_BFCRT23_PT3_DC_SHIFT (0U)AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)AOI_BFCRT23_PT3_CC_MASK (0xCU)AOI_BFCRT23_PT3_CC_SHIFT (2U)AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)AOI_BFCRT23_PT3_BC_MASK (0x30U)AOI_BFCRT23_PT3_BC_SHIFT (4U)AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)AOI_BFCRT23_PT3_AC_MASK (0xC0U)AOI_BFCRT23_PT3_AC_SHIFT (6U)AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)AOI_BFCRT23_PT2_DC_MASK (0x300U)AOI_BFCRT23_PT2_DC_SHIFT (8U)AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)AOI_BFCRT23_PT2_CC_MASK (0xC00U)AOI_BFCRT23_PT2_CC_SHIFT (10U)AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)AOI_BFCRT23_PT2_BC_MASK (0x3000U)AOI_BFCRT23_PT2_BC_SHIFT (12U)AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)AOI_BFCRT23_PT2_AC_MASK (0xC000U)AOI_BFCRT23_PT2_AC_SHIFT (14U)AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)AOI_BFCRT23_COUNT (4U)AOI_BASE (0x403B4000u)AOI ((AOI_Type *)AOI_BASE)AOI_BASE_ADDRS { AOI_BASE }AOI_BASE_PTRS { AOI }BEE_CTRL_BEE_ENABLE_MASK (0x1U)BEE_CTRL_BEE_ENABLE_SHIFT (0U)BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)BEE_CTRL_KEY_VALID_MASK (0x10U)BEE_CTRL_KEY_VALID_SHIFT (4U)BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)BEE_CTRL_AC_PROT_EN_MASK (0x40U)BEE_CTRL_AC_PROT_EN_SHIFT (6U)BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W0_KEY0_SHIFT (0U)BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W1_KEY1_SHIFT (0U)BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W2_KEY2_SHIFT (0U)BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W3_KEY3_SHIFT (0U)BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)BEE_STATUS_IRQ_VEC_MASK (0xFFU)BEE_STATUS_IRQ_VEC_SHIFT (0U)BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)BEE_STATUS_BEE_IDLE_MASK (0x100U)BEE_STATUS_BEE_IDLE_SHIFT (8U)BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)BEE_BASE (0x403EC000u)BEE ((BEE_Type *)BEE_BASE)BEE_BASE_ADDRS { BEE_BASE }BEE_BASE_PTRS { BEE }CCM_CCR_OSCNT_MASK (0xFFU)CCM_CCR_OSCNT_SHIFT (0U)CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)CCM_CCR_COSC_EN_MASK (0x1000U)CCM_CCR_COSC_EN_SHIFT (12U)CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)CCM_CCR_RBC_EN_MASK (0x8000000U)CCM_CCR_RBC_EN_SHIFT (27U)CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)CCM_CSR_REF_EN_B_MASK (0x1U)CCM_CSR_REF_EN_B_SHIFT (0U)CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)CCM_CSR_CAMP2_READY_MASK (0x8U)CCM_CSR_CAMP2_READY_SHIFT (3U)CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)CCM_CSR_COSC_READY_MASK (0x20U)CCM_CSR_COSC_READY_SHIFT (5U)CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)CCM_CACRR_ARM_PODF_MASK (0x7U)CCM_CACRR_ARM_PODF_SHIFT (0U)CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)CCM_CBCDR_IPG_PODF_MASK (0x300U)CCM_CBCDR_IPG_PODF_SHIFT (8U)CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)CCM_CBCDR_AHB_PODF_MASK (0x1C00U)CCM_CBCDR_AHB_PODF_SHIFT (10U)CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)CCM_CBCDR_SEMC_PODF_MASK (0x70000U)CCM_CBCDR_SEMC_PODF_SHIFT (16U)CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)CCM_CBCMR_LPSPI_PODF_SHIFT (26U)CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U)CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U)CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK)CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)CCM_CSCDR1_TRACE_PODF_SHIFT (25U)CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U)CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U)CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK)CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0xE000000U)CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U)CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)CCM_CLPCR_LPM_MASK (0x3U)CCM_CLPCR_LPM_SHIFT (0U)CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)CCM_CLPCR_SBYOS_MASK (0x40U)CCM_CLPCR_SBYOS_SHIFT (6U)CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)CCM_CLPCR_VSTBY_MASK (0x100U)CCM_CLPCR_VSTBY_SHIFT (8U)CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)CCM_CLPCR_STBY_COUNT_MASK (0x600U)CCM_CLPCR_STBY_COUNT_SHIFT (9U)CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)CCM_CISR_LRF_PLL_MASK (0x1U)CCM_CISR_LRF_PLL_SHIFT (0U)CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)CCM_CISR_COSC_READY_MASK (0x40U)CCM_CISR_COSC_READY_SHIFT (6U)CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)CCM_CIMR_MASK_COSC_READY_MASK (0x40U)CCM_CIMR_MASK_COSC_READY_SHIFT (6U)CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)CCM_CCOSR_CLKO1_SEL_MASK (0xFU)CCM_CCOSR_CLKO1_SEL_SHIFT (0U)CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)CCM_CCOSR_CLKO1_DIV_MASK (0x70U)CCM_CCOSR_CLKO1_DIV_SHIFT (4U)CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)CCM_CCOSR_CLKO1_EN_MASK (0x80U)CCM_CCOSR_CLKO1_EN_SHIFT (7U)CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)CCM_CCOSR_CLKO2_SEL_SHIFT (16U)CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)CCM_CCOSR_CLKO2_DIV_SHIFT (21U) CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) CCM_CCOSR_CLKO2_EN_SHIFT (24U) CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) CCM_CGPR_FPL_MASK (0x10000U) CCM_CGPR_FPL_SHIFT (16U) CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) CCM_CCGR0_CG0_MASK (0x3U) CCM_CCGR0_CG0_SHIFT (0U) CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) CCM_CCGR0_CG1_MASK (0xCU) CCM_CCGR0_CG1_SHIFT (2U) CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) CCM_CCGR0_CG2_MASK (0x30U) CCM_CCGR0_CG2_SHIFT (4U) CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) CCM_CCGR0_CG3_MASK (0xC0U) CCM_CCGR0_CG3_SHIFT (6U) CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) CCM_CCGR0_CG4_MASK (0x300U) CCM_CCGR0_CG4_SHIFT (8U) CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) CCM_CCGR0_CG5_MASK (0xC00U) CCM_CCGR0_CG5_SHIFT (10U) CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) CCM_CCGR0_CG6_MASK (0x3000U) CCM_CCGR0_CG6_SHIFT (12U) CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) CCM_CCGR0_CG7_MASK (0xC000U) CCM_CCGR0_CG7_SHIFT (14U) CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) CCM_CCGR0_CG8_MASK (0x30000U) CCM_CCGR0_CG8_SHIFT (16U) CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) CCM_CCGR0_CG9_MASK (0xC0000U) CCM_CCGR0_CG9_SHIFT (18U) CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) CCM_CCGR0_CG10_MASK (0x300000U) CCM_CCGR0_CG10_SHIFT (20U) CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) CCM_CCGR0_CG11_MASK (0xC00000U) CCM_CCGR0_CG11_SHIFT (22U) CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) CCM_CCGR0_CG12_MASK (0x3000000U) CCM_CCGR0_CG12_SHIFT (24U) CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) CCM_CCGR0_CG13_MASK (0xC000000U) CCM_CCGR0_CG13_SHIFT (26U) CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) CCM_CCGR0_CG14_MASK (0x30000000U) CCM_CCGR0_CG14_SHIFT (28U) CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) CCM_CCGR0_CG15_MASK (0xC0000000U) CCM_CCGR0_CG15_SHIFT (30U) CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) CCM_CCGR1_CG0_MASK (0x3U) CCM_CCGR1_CG0_SHIFT (0U) CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) CCM_CCGR1_CG1_MASK (0xCU) CCM_CCGR1_CG1_SHIFT (2U) CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) CCM_CCGR1_CG2_MASK (0x30U) CCM_CCGR1_CG2_SHIFT (4U) CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) CCM_CCGR1_CG3_MASK (0xC0U) CCM_CCGR1_CG3_SHIFT (6U) CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) CCM_CCGR1_CG4_MASK (0x300U) CCM_CCGR1_CG4_SHIFT (8U) CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) CCM_CCGR1_CG5_MASK (0xC00U) CCM_CCGR1_CG5_SHIFT (10U) CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) CCM_CCGR1_CG6_MASK (0x3000U)!CCM_CCGR1_CG6_SHIFT (12U)!CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)!CCM_CCGR1_CG7_MASK (0xC000U)!CCM_CCGR1_CG7_SHIFT (14U)!CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)!CCM_CCGR1_CG8_MASK (0x30000U)!CCM_CCGR1_CG8_SHIFT (16U)!CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)!CCM_CCGR1_CG9_MASK (0xC0000U)!CCM_CCGR1_CG9_SHIFT (18U)!CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)!CCM_CCGR1_CG10_MASK (0x300000U)!CCM_CCGR1_CG10_SHIFT (20U)!CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)!CCM_CCGR1_CG11_MASK (0xC00000U)!CCM_CCGR1_CG11_SHIFT (22U)!CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)!CCM_CCGR1_CG12_MASK (0x3000000U)!CCM_CCGR1_CG12_SHIFT (24U)!CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)!CCM_CCGR1_CG13_MASK (0xC000000U)!CCM_CCGR1_CG13_SHIFT (26U)!CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)!CCM_CCGR1_CG14_MASK (0x30000000U)!CCM_CCGR1_CG14_SHIFT (28U)!CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)!CCM_CCGR1_CG15_MASK (0xC0000000U)!CCM_CCGR1_CG15_SHIFT (30U)!CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)!CCM_CCGR2_CG0_MASK (0x3U)!CCM_CCGR2_CG0_SHIFT (0U)!CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)!CCM_CCGR2_CG1_MASK (0xCU)!CCM_CCGR2_CG1_SHIFT (2U)!CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)!CCM_CCGR2_CG2_MASK (0x30U)!CCM_CCGR2_CG2_SHIFT (4U)!CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)!CCM_CCGR2_CG3_MASK (0xC0U)!CCM_CCGR2_CG3_SHIFT (6U)!CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)!CCM_CCGR2_CG4_MASK (0x300U)!CCM_CCGR2_CG4_SHIFT (8U)!CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)!CCM_CCGR2_CG5_MASK (0xC00U)!CCM_CCGR2_CG5_SHIFT (10U)!CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)!CCM_CCGR2_CG6_MASK (0x3000U)!CCM_CCGR2_CG6_SHIFT (12U)!CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)!CCM_CCGR2_CG7_MASK (0xC000U)!CCM_CCGR2_CG7_SHIFT (14U)!CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)!CCM_CCGR2_CG8_MASK (0x30000U)!CCM_CCGR2_CG8_SHIFT (16U)!CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)!CCM_CCGR2_CG9_MASK (0xC0000U)!CCM_CCGR2_CG9_SHIFT (18U)!CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)!CCM_CCGR2_CG10_MASK (0x300000U)!CCM_CCGR2_CG10_SHIFT (20U)!CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)!CCM_CCGR2_CG11_MASK (0xC00000U)!CCM_CCGR2_CG11_SHIFT (22U)!CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)!CCM_CCGR2_CG12_MASK (0x3000000U)!CCM_CCGR2_CG12_SHIFT (24U)!CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)!CCM_CCGR2_CG13_MASK (0xC000000U)!CCM_CCGR2_CG13_SHIFT (26U)!CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)!CCM_CCGR2_CG14_MASK (0x30000000U)!CCM_CCGR2_CG14_SHIFT (28U)!CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)!CCM_CCGR2_CG15_MASK (0xC0000000U)!CCM_CCGR2_CG15_SHIFT (30U)!CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)!CCM_CCGR3_CG0_MASK (0x3U)!CCM_CCGR3_CG0_SHIFT (0U)!CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)!CCM_CCGR3_CG1_MASK (0xCU)!CCM_CCGR3_CG1_SHIFT (2U)!CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)!CCM_CCGR3_CG2_MASK (0x30U)!CCM_CCGR3_CG2_SHIFT (4U)!CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)!CCM_CCGR3_CG3_MASK (0xC0U)!CCM_CCGR3_CG3_SHIFT (6U)!CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)!CCM_CCGR3_CG4_MASK (0x300U)!CCM_CCGR3_CG4_SHIFT (8U)!CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)!CCM_CCGR3_CG5_MASK (0xC00U)!CCM_CCGR3_CG5_SHIFT (10U)!CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)!CCM_CCGR3_CG6_MASK (0x3000U)!CCM_CCGR3_CG6_SHIFT (12U)!CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)!CCM_CCGR3_CG7_MASK (0xC000U)!CCM_CCGR3_CG7_SHIFT (14U)!CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)!CCM_CCGR3_CG8_MASK (0x30000U)!CCM_CCGR3_CG8_SHIFT (16U)!CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)!CCM_CCGR3_CG9_MASK (0xC0000U)!CCM_CCGR3_CG9_SHIFT (18U)!CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)!CCM_CCGR3_CG10_MASK (0x300000U)!CCM_CCGR3_CG10_SHIFT (20U)!CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)!CCM_CCGR3_CG11_MASK (0xC00000U)!CCM_CCGR3_CG11_SHIFT (22U)!CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)!CCM_CCGR3_CG12_MASK (0x3000000U)!CCM_CCGR3_CG12_SHIFT (24U)!CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)!CCM_CCGR3_CG13_MASK (0xC000000U)!CCM_CCGR3_CG13_SHIFT (26U)!CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)!CCM_CCGR3_CG14_MASK (0x30000000U)"CCM_CCGR3_CG14_SHIFT (28U)"CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)"CCM_CCGR3_CG15_MASK (0xC0000000U)"CCM_CCGR3_CG15_SHIFT (30U)"CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)"CCM_CCGR4_CG0_MASK (0x3U)"CCM_CCGR4_CG0_SHIFT (0U)"CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)"CCM_CCGR4_CG1_MASK (0xCU)"CCM_CCGR4_CG1_SHIFT (2U)"CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)"CCM_CCGR4_CG2_MASK (0x30U)"CCM_CCGR4_CG2_SHIFT (4U)"CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)"CCM_CCGR4_CG3_MASK (0xC0U)"CCM_CCGR4_CG3_SHIFT (6U)"CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)"CCM_CCGR4_CG4_MASK (0x300U)"CCM_CCGR4_CG4_SHIFT (8U)"CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)"CCM_CCGR4_CG5_MASK (0xC00U)"CCM_CCGR4_CG5_SHIFT (10U)"CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)"CCM_CCGR4_CG6_MASK (0x3000U)"CCM_CCGR4_CG6_SHIFT (12U)"CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)"CCM_CCGR4_CG7_MASK (0xC000U)"CCM_CCGR4_CG7_SHIFT (14U)"CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)"CCM_CCGR4_CG8_MASK (0x30000U)"CCM_CCGR4_CG8_SHIFT (16U)"CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)"CCM_CCGR4_CG9_MASK (0xC0000U)"CCM_CCGR4_CG9_SHIFT (18U)"CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)"CCM_CCGR4_CG10_MASK (0x300000U)"CCM_CCGR4_CG10_SHIFT (20U)"CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)"CCM_CCGR4_CG11_MASK (0xC00000U)"CCM_CCGR4_CG11_SHIFT (22U)"CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)"CCM_CCGR4_CG12_MASK (0x3000000U)"CCM_CCGR4_CG12_SHIFT (24U)"CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)"CCM_CCGR4_CG13_MASK (0xC000000U)"CCM_CCGR4_CG13_SHIFT (26U)"CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)"CCM_CCGR4_CG14_MASK (0x30000000U)"CCM_CCGR4_CG14_SHIFT (28U)"CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)"CCM_CCGR4_CG15_MASK (0xC0000000U)"CCM_CCGR4_CG15_SHIFT (30U)"CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)"CCM_CCGR5_CG0_MASK (0x3U)"CCM_CCGR5_CG0_SHIFT (0U)"CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)"CCM_CCGR5_CG1_MASK (0xCU)"CCM_CCGR5_CG1_SHIFT (2U)"CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)"CCM_CCGR5_CG2_MASK (0x30U)"CCM_CCGR5_CG2_SHIFT (4U)"CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)"CCM_CCGR5_CG3_MASK (0xC0U)"CCM_CCGR5_CG3_SHIFT (6U)"CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)"CCM_CCGR5_CG4_MASK (0x300U)"CCM_CCGR5_CG4_SHIFT (8U)"CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)"CCM_CCGR5_CG5_MASK (0xC00U)"CCM_CCGR5_CG5_SHIFT (10U)"CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)"CCM_CCGR5_CG6_MASK (0x3000U)"CCM_CCGR5_CG6_SHIFT (12U)"CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)"CCM_CCGR5_CG7_MASK (0xC000U)"CCM_CCGR5_CG7_SHIFT (14U)"CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)"CCM_CCGR5_CG8_MASK (0x30000U)"CCM_CCGR5_CG8_SHIFT (16U)"CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)"CCM_CCGR5_CG9_MASK (0xC0000U)"CCM_CCGR5_CG9_SHIFT (18U)"CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)"CCM_CCGR5_CG10_MASK (0x300000U)"CCM_CCGR5_CG10_SHIFT (20U)"CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)"CCM_CCGR5_CG11_MASK (0xC00000U)"CCM_CCGR5_CG11_SHIFT (22U)"CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)"CCM_CCGR5_CG12_MASK (0x3000000U)"CCM_CCGR5_CG12_SHIFT (24U)"CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)"CCM_CCGR5_CG13_MASK (0xC000000U)"CCM_CCGR5_CG13_SHIFT (26U)"CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)"CCM_CCGR5_CG14_MASK (0x30000000U)"CCM_CCGR5_CG14_SHIFT (28U)"CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)"CCM_CCGR5_CG15_MASK (0xC0000000U)"CCM_CCGR5_CG15_SHIFT (30U)"CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)"CCM_CCGR6_CG0_MASK (0x3U)"CCM_CCGR6_CG0_SHIFT (0U)"CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)"CCM_CCGR6_CG1_MASK (0xCU)"CCM_CCGR6_CG1_SHIFT (2U)"CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)"CCM_CCGR6_CG2_MASK (0x30U)"CCM_CCGR6_CG2_SHIFT (4U)"CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)"CCM_CCGR6_CG3_MASK (0xC0U)"CCM_CCGR6_CG3_SHIFT (6U)"CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)"CCM_CCGR6_CG4_MASK (0x300U)"CCM_CCGR6_CG4_SHIFT (8U)"CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)#CCM_CCGR6_CG5_MASK (0xC00U)#CCM_CCGR6_CG5_SHIFT (10U)#CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)#CCM_CCGR6_CG6_MASK (0x3000U)#CCM_CCGR6_CG6_SHIFT (12U)#CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)#CCM_CCGR6_CG7_MASK (0xC000U)#CCM_CCGR6_CG7_SHIFT (14U)#CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)#CCM_CCGR6_CG8_MASK (0x30000U)#CCM_CCGR6_CG8_SHIFT (16U)#CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)#CCM_CCGR6_CG9_MASK (0xC0000U)#CCM_CCGR6_CG9_SHIFT (18U)#CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)#CCM_CCGR6_CG10_MASK (0x300000U)#CCM_CCGR6_CG10_SHIFT (20U)#CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)#CCM_CCGR6_CG11_MASK (0xC00000U)#CCM_CCGR6_CG11_SHIFT (22U)#CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)#CCM_CCGR6_CG12_MASK (0x3000000U)#CCM_CCGR6_CG12_SHIFT (24U)#CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)#CCM_CCGR6_CG13_MASK (0xC000000U)#CCM_CCGR6_CG13_SHIFT (26U)#CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)#CCM_CCGR6_CG14_MASK (0x30000000U)#CCM_CCGR6_CG14_SHIFT (28U)#CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)#CCM_CCGR6_CG15_MASK (0xC0000000U)#CCM_CCGR6_CG15_SHIFT (30U)#CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)#CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)#CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)#CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)#CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)#CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)#CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)#CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)#CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)#CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)#CCM_BASE (0x400FC000u)#CCM ((CCM_Type *)CCM_BASE)#CCM_BASE_ADDRS { CCM_BASE }#CCM_BASE_PTRS { CCM }#CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }$CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)$CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)$CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)$CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)$CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)$CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)$CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)$CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)$CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)$CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)$CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)$CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)$CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)$CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)$CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)$CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)$CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)$CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)$CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)$CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)$CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)$CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)$CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)$CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)$CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)$CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)$CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)$CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)$CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)$CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)$CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)$CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)$CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)$CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)$CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)$CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)$CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)$CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)$CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)$CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)$CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)$CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)$CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)$CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)$CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)$CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)$CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)$CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)$CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)$CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)$CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)$CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)$CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)$CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)$CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)$CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)$CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)$CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)$CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)$CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)$CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)$CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)$CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)$CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)$CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)$CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)$CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)%CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)%CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)%CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)%CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)%CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)%CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)%CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)%CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)%CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)%CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)%CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)%CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)%CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)%CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)%CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)%CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)%CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)%CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)%CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)%CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)%CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)%CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)%CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)%CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)%CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)%CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)%CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)%CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)%CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)%CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)%CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)%CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)%CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)%CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)%CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)%CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)%CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)%CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)%CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)%CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)%CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)%CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)%CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)%CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)%CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)%CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)%CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)%CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)%CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)%CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)%CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)%CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)%CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)%CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)%CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)%CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)%CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)%CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)%CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)%CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)%CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)%CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)%CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)%CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)%CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)%CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)%CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)%CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)%CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)%CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)%CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)%CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)%CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)%CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)%CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)%CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)%CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)%CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)%CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)%CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)%CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)%CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)%CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)%CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)%CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)%CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)%CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)%CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)%CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)&CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)&CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)&CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)&CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)&CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)&CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)&CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)&CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)&CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)&CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)&CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)&CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)&CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)&CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)&CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)&CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)&CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)&CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)&CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)&CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)&CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)&CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)&CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)&CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)&CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)&CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)&CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)&CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)&CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)&CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)&CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)&CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)&CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)&CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)&CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)&CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)&CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)&CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)&CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)&CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)&CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)&CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)&CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)&CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)&CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)&CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)&CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)'CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)'CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)'CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)'CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)'CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)'CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)'CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)'CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)'CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)'CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)'CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)'CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)'CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)'CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)'CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)'CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)'CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)'CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)'CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)'CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)'CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)'CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)'CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)'CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)'CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)'CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)'CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)'CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)'CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)'CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)'CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)'CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)'CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)'CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)'CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)'CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)'CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)'CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)'CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)'CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)'CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK (0x400000U)'CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT (22U)'CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK)'CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)'CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)'CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)'CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)'CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)'CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)'CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)'CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)'CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)'CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)'CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)'CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)'CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK (0x400000U)'CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT (22U)'CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK)'CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)'CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)'CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)'CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)'CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)'CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)'CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)'CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)'CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)'CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)'CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)'CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)'CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK (0x400000U)'CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT (22U)'CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK)'CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)'CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)(CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)(CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)(CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)(CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)(CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)(CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)(CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)(CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)(CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)(CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)(CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK (0x400000U)(CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT (22U)(CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK)(CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)(CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)(CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)(CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)(CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)(CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)(CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)(CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)(CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)(CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)(CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)(CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)(CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)(CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)(CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)(CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)(CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)(CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)(CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)(CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)(CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)(CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)(CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)(CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)(CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)(CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)(CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)(CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)(CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)(CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)(CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)(CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)(CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)(CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)(CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)(CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)(CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)(CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)(CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)(CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)(CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)(CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)(CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)(CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)(CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)(CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)(CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)(CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)(CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)(CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)(CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)(CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)(CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)(CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)(CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)(CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)(CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)(CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)(CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)(CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)(CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)(CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)(CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)(CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)(CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)(CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)(CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)(CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)(CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)(CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)(CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)(CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)(CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)(CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)(CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)(CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)(CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)(CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)(CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)(CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)(CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)(CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)(CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)(CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)(CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)(CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)(CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)(CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)(CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)(CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)(CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)(CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)(CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)(CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U))CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U))CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK))CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U))CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U))CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK))CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U))CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U))CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK))CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U))CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U))CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK))CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U))CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U))CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK))CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U))CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U))CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK))CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU))CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U))CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK))CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U))CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U))CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK))CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U))CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U))CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK))CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U))CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U))CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK))CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U))CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U))CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK))CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U))CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U))CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK))CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U))CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U))CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK))CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U))CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U))CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK))CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U))CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U))CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK))CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U))CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U))CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK))CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U))CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U))CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK))CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U))CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U))CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK))CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU))CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U))CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK))CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U))CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U))CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK))CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U))CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U))CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK))CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U))CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U))CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK))CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U))CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U))CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK))CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U))CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U))CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK))CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U))CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U))CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK))CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U))CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U))CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK))CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U))CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U))CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK))CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U))CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U))CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK))CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U))CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U))CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK))CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U))CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U))CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK))CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU))CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U))CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK))CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U))CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U))CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK))CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U))CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U))CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK))CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U))CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U))CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK))CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U))CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U))CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK))CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U))CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U))CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK))CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U))CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U))CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK))CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U))CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U))CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK))CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U))CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U))CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)*CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)*CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)*CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)*CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)*CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)*CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)*CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)*CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)*CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)*CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)*CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)*CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)*CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)*CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)*CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)*CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)*CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)*CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)*CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)*CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)*CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)*CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)*CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)*CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)*CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)*CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)*CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)*CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)*CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)*CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)*CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)*CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)*CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)*CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)*CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)*CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)*CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)*CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)*CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)*CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)*CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)*CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)*CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)*CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)*CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)*CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)*CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)*CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)*CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)*CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)*CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)*CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)*CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)*CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)*CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)*CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)*CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)*CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)*CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)*CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)*CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)*CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)*CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)*CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)*CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)*CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)*CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)*CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)*CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)*CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)*CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)*CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)*CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)*CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)*CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)*CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)*CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)*CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)*CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)*CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)*CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)*CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)*CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)*CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)*CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)*CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)*CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)*CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)*CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)*CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)*CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)*CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)*CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)*CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)*CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)+CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)+CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)+CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)+CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)+CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)+CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)+CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)+CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)+CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)+CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)+CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)+CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)+CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)+CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)+CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)+CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)+CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)+CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)+CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)+CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)+CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)+CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)+CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)+CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)+CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)+CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)+CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)+CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)+CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)+CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)+CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)+CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)+CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)+CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)+CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)+CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)+CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)+CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)+CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)+CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)+CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)+CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)+CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)+CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)+CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)+CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)+CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)+CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)+CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)+CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)+CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)+CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)+CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)+CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)+CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)+CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)+CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U),CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK),CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U),CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U),CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK),CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U),CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U),CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK),CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U),CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U),CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK),CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U),CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U),CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK),CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U),CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U),CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK),CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U),CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U),CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK),CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U),CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U),CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK),CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U),CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U),CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK),CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U),CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U),CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK),CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U),CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U),CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK),CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U),CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U),CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK),CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U),CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U),CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK),CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U),CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U),CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK),CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U),CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U),CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK),CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U),CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U),CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK),CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U),CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U),CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK),CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U),CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U),CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK),CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U),CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)-CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)-CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)-CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)-CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)-CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)-CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)-CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)-CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)-CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)-CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)-CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)-CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)-CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)-CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)-CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)-CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)-CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)-CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)-CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)-CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)-CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)-CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)-CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)-CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)-CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)-CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)-CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)-CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)-CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)-CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)-CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)-CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)-CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)-CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)-CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)-CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)-CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)-CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)-CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)-CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)-CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)-CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)-CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)-CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)-CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)-CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)-CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)-CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)-CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)-CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)-CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)-CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)-CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)-CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)-CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)-CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)-CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)-CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)-CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)-CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)-CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)-CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)-CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)-CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)-CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)-CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)-CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)-CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)-CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)-CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)-CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)-CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)-CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)-CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U).CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U).CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK).CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U).CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U).CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK).CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U).CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U).CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK).CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U).CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U).CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK).CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U).CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U).CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK).CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U).CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U).CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK).CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U).CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U).CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK).CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U).CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U).CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK).CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U).CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U).CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK).CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U).CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U).CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK).CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U).CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U).CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK).CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U).CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U).CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK).CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U).CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U).CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK).CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U).CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U).CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK).CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U).CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U).CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK).CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U).CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U).CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK).CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U).CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U).CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK).CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U).CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U).CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK).CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U).CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U).CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK).CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U).CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U).CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK).CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U).CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U).CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK).CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U).CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U).CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK).CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U).CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U).CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK).CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U).CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U).CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK).CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U).CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U).CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK).CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U).CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U).CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK).CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U).CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U).CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK).CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U).CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U).CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK).CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U).CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U).CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK).CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U).CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)/CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)/CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)/CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)/CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)/CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)/CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)/CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)/CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)/CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)/CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)/CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)/CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)/CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)/CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)/CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)/CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)/CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)/CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)/CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)/CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)/CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)/CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)/CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)/CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)/CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)/CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)/CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)/CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)/CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)/CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)/CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)/CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)/CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)/CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)/CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)/CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)/CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)/CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)/CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)/CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)/CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)/CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)/CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)/CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)/CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)/CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)/CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)/CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)/CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)/CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)/CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)/CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)/CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)/CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)/CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)/CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)/CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)/CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)/CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)/CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)0CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)0CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)0CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)0CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)0CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)0CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)0CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)0CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)0CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)0CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)0CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)0CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)0CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)0CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)0CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)0CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)0CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)0CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)0CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)0CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)0CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)0CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)0CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)0CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)0CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)0CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)0CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)0CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)0CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)0CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)0CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)0CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)0CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)0CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)0CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)0CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)0CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)0CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)0CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)0CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)0CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)0CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)0CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)0CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)0CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)0CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)0CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)0CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)0CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)0CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)0CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)0CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)0CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)0CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)0CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)0CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)0CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)0CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)0CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)0CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)0CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)0CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)0CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)0CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)0CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)1CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)1CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)1CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)1CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)1CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)1CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)1CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)1CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)1CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)1CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)1CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)1CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)1CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)1CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)1CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)1CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)1CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)1CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)1CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)1CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)1CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)1CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)1CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)1CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)1CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)1CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)1CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)1CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)1CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)1CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)1CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)1CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)1CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)1CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)1CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)1CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)1CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)1CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)1CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)1CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)1CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)1CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)1CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)1CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)1CCM_ANALOG_BASE (0x400D8000u)1CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)1CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }1CCM_ANALOG_BASE_PTRS { CCM_ANALOG }2CSU_CSL_SUR_S2_MASK (0x1U)2CSU_CSL_SUR_S2_SHIFT (0U)2CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)2CSU_CSL_SSR_S2_MASK (0x2U)2CSU_CSL_SSR_S2_SHIFT (1U)2CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)2CSU_CSL_NUR_S2_MASK (0x4U)2CSU_CSL_NUR_S2_SHIFT (2U)2CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)2CSU_CSL_NSR_S2_MASK (0x8U)2CSU_CSL_NSR_S2_SHIFT (3U)2CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)2CSU_CSL_SUW_S2_MASK (0x10U)2CSU_CSL_SUW_S2_SHIFT (4U)2CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)2CSU_CSL_SSW_S2_MASK (0x20U)2CSU_CSL_SSW_S2_SHIFT (5U)2CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)2CSU_CSL_NUW_S2_MASK (0x40U)2CSU_CSL_NUW_S2_SHIFT (6U)2CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)2CSU_CSL_NSW_S2_MASK (0x80U)2CSU_CSL_NSW_S2_SHIFT (7U)2CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)2CSU_CSL_LOCK_S2_MASK (0x100U)2CSU_CSL_LOCK_S2_SHIFT (8U)2CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)2CSU_CSL_SUR_S1_MASK (0x10000U)2CSU_CSL_SUR_S1_SHIFT (16U)2CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)2CSU_CSL_SSR_S1_MASK (0x20000U)2CSU_CSL_SSR_S1_SHIFT (17U)2CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)2CSU_CSL_NUR_S1_MASK (0x40000U)2CSU_CSL_NUR_S1_SHIFT (18U)2CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)2CSU_CSL_NSR_S1_MASK (0x80000U)2CSU_CSL_NSR_S1_SHIFT (19U)2CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)2CSU_CSL_SUW_S1_MASK (0x100000U)2CSU_CSL_SUW_S1_SHIFT (20U)2CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)2CSU_CSL_SSW_S1_MASK (0x200000U)2CSU_CSL_SSW_S1_SHIFT (21U)2CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)2CSU_CSL_NUW_S1_MASK (0x400000U)2CSU_CSL_NUW_S1_SHIFT (22U)2CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)2CSU_CSL_NSW_S1_MASK (0x800000U)2CSU_CSL_NSW_S1_SHIFT (23U)3CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)3CSU_CSL_LOCK_S1_MASK (0x1000000U)3CSU_CSL_LOCK_S1_SHIFT (24U)3CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)3CSU_CSL_COUNT (32U)3CSU_HP0_HP_DMA_MASK (0x4U)3CSU_HP0_HP_DMA_SHIFT (2U)3CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)3CSU_HP0_L_DMA_MASK (0x8U)3CSU_HP0_L_DMA_SHIFT (3U)3CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)3CSU_HP0_HP_LCDIF_MASK (0x10U)3CSU_HP0_HP_LCDIF_SHIFT (4U)3CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)3CSU_HP0_L_LCDIF_MASK (0x20U)3CSU_HP0_L_LCDIF_SHIFT (5U)3CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)3CSU_HP0_HP_CSI_MASK (0x40U)3CSU_HP0_HP_CSI_SHIFT (6U)3CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)3CSU_HP0_L_CSI_MASK (0x80U)3CSU_HP0_L_CSI_SHIFT (7U)3CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)3CSU_HP0_HP_PXP_MASK (0x100U)3CSU_HP0_HP_PXP_SHIFT (8U)3CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)3CSU_HP0_L_PXP_MASK (0x200U)3CSU_HP0_L_PXP_SHIFT (9U)3CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)3CSU_HP0_HP_DCP_MASK (0x400U)3CSU_HP0_HP_DCP_SHIFT (10U)3CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)3CSU_HP0_L_DCP_MASK (0x800U)3CSU_HP0_L_DCP_SHIFT (11U)3CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)3CSU_HP0_HP_ENET_MASK (0x4000U)3CSU_HP0_HP_ENET_SHIFT (14U)3CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)3CSU_HP0_L_ENET_MASK (0x8000U)3CSU_HP0_L_ENET_SHIFT (15U)3CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)3CSU_HP0_HP_USDHC1_MASK (0x10000U)3CSU_HP0_HP_USDHC1_SHIFT (16U)3CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)3CSU_HP0_L_USDHC1_MASK (0x20000U)3CSU_HP0_L_USDHC1_SHIFT (17U)3CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)3CSU_HP0_HP_USDHC2_MASK (0x40000U)3CSU_HP0_HP_USDHC2_SHIFT (18U)3CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)3CSU_HP0_L_USDHC2_MASK (0x80000U)3CSU_HP0_L_USDHC2_SHIFT (19U)3CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)4CSU_HP0_HP_TPSMP_MASK (0x100000U)4CSU_HP0_HP_TPSMP_SHIFT (20U)4CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)4CSU_HP0_L_TPSMP_MASK (0x200000U)4CSU_HP0_L_TPSMP_SHIFT (21U)4CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)4CSU_HP0_HP_USB_MASK (0x400000U)4CSU_HP0_HP_USB_SHIFT (22U)4CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)4CSU_HP0_L_USB_MASK (0x800000U)4CSU_HP0_L_USB_SHIFT (23U)4CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)4CSU_SA_NSA_DMA_MASK (0x4U)4CSU_SA_NSA_DMA_SHIFT (2U)4CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)4CSU_SA_L_DMA_MASK (0x8U)4CSU_SA_L_DMA_SHIFT (3U)4CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)4CSU_SA_NSA_LCDIF_MASK (0x10U)4CSU_SA_NSA_LCDIF_SHIFT (4U)4CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)4CSU_SA_L_LCDIF_MASK (0x20U)4CSU_SA_L_LCDIF_SHIFT (5U)4CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)4CSU_SA_NSA_CSI_MASK (0x40U)4CSU_SA_NSA_CSI_SHIFT (6U)4CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)4CSU_SA_L_CSI_MASK (0x80U)4CSU_SA_L_CSI_SHIFT (7U)4CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)4CSU_SA_NSA_PXP_MASK (0x100U)4CSU_SA_NSA_PXP_SHIFT (8U)4CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)4CSU_SA_L_PXP_MASK (0x200U)4CSU_SA_L_PXP_SHIFT (9U)4CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)4CSU_SA_NSA_DCP_MASK (0x400U)4CSU_SA_NSA_DCP_SHIFT (10U)4CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)4CSU_SA_L_DCP_MASK (0x800U)4CSU_SA_L_DCP_SHIFT (11U)4CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)4CSU_SA_NSA_ENET_MASK (0x4000U)4CSU_SA_NSA_ENET_SHIFT (14U)4CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)4CSU_SA_L_ENET_MASK (0x8000U)4CSU_SA_L_ENET_SHIFT (15U)4CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)4CSU_SA_NSA_USDHC1_MASK (0x10000U)4CSU_SA_NSA_USDHC1_SHIFT (16U)4CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)4CSU_SA_L_USDHC1_MASK (0x20000U)4CSU_SA_L_USDHC1_SHIFT (17U)5CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)5CSU_SA_NSA_USDHC2_MASK (0x40000U)5CSU_SA_NSA_USDHC2_SHIFT (18U)5CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)5CSU_SA_L_USDHC2_MASK (0x80000U)5CSU_SA_L_USDHC2_SHIFT (19U)5CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)5CSU_SA_NSA_TPSMP_MASK (0x100000U)5CSU_SA_NSA_TPSMP_SHIFT (20U)5CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)5CSU_SA_L_TPSMP_MASK (0x200000U)5CSU_SA_L_TPSMP_SHIFT (21U)5CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)5CSU_SA_NSA_USB_MASK (0x400000U)5CSU_SA_NSA_USB_SHIFT (22U)5CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)5CSU_SA_L_USB_MASK (0x800000U)5CSU_SA_L_USB_SHIFT (23U)5CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)5CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)5CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)5CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)5CSU_HPCONTROL0_L_DMA_MASK (0x8U)5CSU_HPCONTROL0_L_DMA_SHIFT (3U)5CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)5CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)5CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)5CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)5CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)5CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)5CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)5CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)5CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)5CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)5CSU_HPCONTROL0_L_CSI_MASK (0x80U)5CSU_HPCONTROL0_L_CSI_SHIFT (7U)5CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)5CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)5CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)5CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)5CSU_HPCONTROL0_L_PXP_MASK (0x200U)5CSU_HPCONTROL0_L_PXP_SHIFT (9U)5CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)5CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)5CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)5CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)5CSU_HPCONTROL0_L_DCP_MASK (0x800U)5CSU_HPCONTROL0_L_DCP_SHIFT (11U)5CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)5CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)5CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)5CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)5CSU_HPCONTROL0_L_ENET_MASK (0x8000U)5CSU_HPCONTROL0_L_ENET_SHIFT (15U)6CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)6CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)6CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)6CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)6CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)6CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)6CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)6CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)6CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)6CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)6CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)6CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)6CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)6CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)6CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)6CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)6CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)6CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)6CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)6CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)6CSU_HPCONTROL0_HPC_USB_SHIFT (22U)6CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)6CSU_HPCONTROL0_L_USB_MASK (0x800000U)6CSU_HPCONTROL0_L_USB_SHIFT (23U)6CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)6CSU_BASE (0x400DC000u)6CSU ((CSU_Type *)CSU_BASE)6CSU_BASE_ADDRS { CSU_BASE }6CSU_BASE_PTRS { CSU }6DCDC_REG0_PWD_ZCD_MASK (0x1U)6DCDC_REG0_PWD_ZCD_SHIFT (0U)6DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)6DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)6DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)6DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)6DCDC_REG0_SEL_CLK_MASK (0x4U)6DCDC_REG0_SEL_CLK_SHIFT (2U)6DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)6DCDC_REG0_PWD_OSC_INT_MASK (0x8U)6DCDC_REG0_PWD_OSC_INT_SHIFT (3U)6DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)6DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)6DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)6DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)6DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)6DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)7DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)7DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)7DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)7DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)7DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)7DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)7DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)7DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)7DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)7DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)7DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)7DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)7DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)7DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)7DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)7DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)7DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)7DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)7DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)7DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)7DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)7DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)7DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)7DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)7DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)7DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)7DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)7DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)7DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)7DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)7DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)7DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)7DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)7DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)7DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)7DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)7DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)7DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)7DCDC_REG0_XTAL_24M_OK_SHIFT (29U)7DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)7DCDC_REG0_STS_DC_OK_MASK (0x80000000U)7DCDC_REG0_STS_DC_OK_SHIFT (31U)7DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)7DCDC_REG1_REG_FBK_SEL_MASK (0x180U)7DCDC_REG1_REG_FBK_SEL_SHIFT (7U)7DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)7DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)7DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)7DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)7DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)7DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)7DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)7DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)7DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)7DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)7DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)7DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)7DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)7DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)7DCDC_REG1_VBG_TRIM_SHIFT (24U)7DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)7DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)7DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)7DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)7DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)7DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)7DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)7DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)7DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)7DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)7DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)7DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)7DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)7DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)7DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)7DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)7DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)7DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)7DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)7DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U)7DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U)7DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)7DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)7DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)7DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)7DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)7DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)7DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)7DCDC_REG3_TRG_MASK (0x1FU)7DCDC_REG3_TRG_SHIFT (0U)7DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)7DCDC_REG3_TARGET_LP_MASK (0x700U)7DCDC_REG3_TARGET_LP_SHIFT (8U)7DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)7DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)7DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)7DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)7DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)7DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)7DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)7DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)7DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)7DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)7DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)7DCDC_REG3_DISABLE_STEP_SHIFT (30U)7DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)8DCDC_BASE (0x40080000u)8DCDC ((DCDC_Type *)DCDC_BASE)8DCDC_BASE_ADDRS { DCDC_BASE }8DCDC_BASE_PTRS { DCDC }8DCDC_IRQS { DCDC_IRQn }9DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)9DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)9DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)9DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)9DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)9DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)9DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)9DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)9DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)9DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)9DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)9DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)9DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)9DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)9DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)9DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)9DCP_CTRL_PRESENT_SHA_SHIFT (28U)9DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)9DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)9DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)9DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)9DCP_CTRL_CLKGATE_MASK (0x40000000U)9DCP_CTRL_CLKGATE_SHIFT (30U)9DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)9DCP_CTRL_SFTRST_MASK (0x80000000U)9DCP_CTRL_SFTRST_SHIFT (31U)9DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)9DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)9DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)9DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)9DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)9DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)9DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)9DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)9DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)9DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)9DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)9DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)9DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)9DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)9DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)9DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)9DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U)9DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U)9DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)9DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U)9DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U)9DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)9DCP_CTRL_SET_CLKGATE_MASK (0x40000000U)9DCP_CTRL_SET_CLKGATE_SHIFT (30U)9DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)9DCP_CTRL_SET_SFTRST_MASK (0x80000000U)9DCP_CTRL_SET_SFTRST_SHIFT (31U)9DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)9DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)9DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)9DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)9DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)9DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)9DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)9DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)9DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)9DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)9DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)9DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)9DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)9DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)9DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)9DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)9DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U)9DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U)9DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)9DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U)9DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U)9DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK):DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U):DCP_CTRL_CLR_CLKGATE_SHIFT (30U):DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK):DCP_CTRL_CLR_SFTRST_MASK (0x80000000U):DCP_CTRL_CLR_SFTRST_SHIFT (31U):DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK):DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU):DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U):DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK):DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U):DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U):DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK):DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U):DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U):DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK):DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U):DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U):DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK):DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U):DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U):DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK):DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U):DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U):DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK):DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U):DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U):DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK):DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U):DCP_CTRL_TOG_CLKGATE_SHIFT (30U):DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK):DCP_CTRL_TOG_SFTRST_MASK (0x80000000U):DCP_CTRL_TOG_SFTRST_SHIFT (31U):DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK):DCP_STAT_IRQ_MASK (0xFU):DCP_STAT_IRQ_SHIFT (0U):DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK):DCP_STAT_RSVD_IRQ_MASK (0x100U):DCP_STAT_RSVD_IRQ_SHIFT (8U):DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK):DCP_STAT_READY_CHANNELS_MASK (0xFF0000U):DCP_STAT_READY_CHANNELS_SHIFT (16U):DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK):DCP_STAT_CUR_CHANNEL_MASK (0xF000000U):DCP_STAT_CUR_CHANNEL_SHIFT (24U):DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK):DCP_STAT_OTP_KEY_READY_MASK (0x10000000U):DCP_STAT_OTP_KEY_READY_SHIFT (28U):DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK):DCP_STAT_SET_IRQ_MASK (0xFU):DCP_STAT_SET_IRQ_SHIFT (0U):DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK):DCP_STAT_SET_RSVD_IRQ_MASK (0x100U):DCP_STAT_SET_RSVD_IRQ_SHIFT (8U):DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK):DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U):DCP_STAT_SET_READY_CHANNELS_SHIFT (16U):DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK):DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U):DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U):DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK):DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U):DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U):DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK):DCP_STAT_CLR_IRQ_MASK (0xFU):DCP_STAT_CLR_IRQ_SHIFT (0U):DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK):DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U):DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U):DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK):DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U):DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U);DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK);DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U);DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U);DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK);DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U);DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U);DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK);DCP_STAT_TOG_IRQ_MASK (0xFU);DCP_STAT_TOG_IRQ_SHIFT (0U);DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK);DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U);DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U);DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK);DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U);DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U);DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK);DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U);DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U);DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK);DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U);DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U);DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK);DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU);DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U);DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK);DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U);DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U);DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK);DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U);DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U);DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK);DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U);DCP_CHANNELCTRL_RSVD_SHIFT (17U);DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK);DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU);DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U);DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK);DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U);DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U);DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK);DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U);DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U);DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK);DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U);DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U);DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK);DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU);DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U);DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK);DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U);DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)>DCP_PACKET5_COUNT_SHIFT (0U)>DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)>DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)>DCP_PACKET6_ADDR_SHIFT (0U)>DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)>DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)>DCP_CH0CMDPTR_ADDR_SHIFT (0U)>DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)>DCP_CH0SEMA_INCREMENT_MASK (0xFFU)>DCP_CH0SEMA_INCREMENT_SHIFT (0U)>DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)>DCP_CH0SEMA_VALUE_MASK (0xFF0000U)>DCP_CH0SEMA_VALUE_SHIFT (16U)>DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)>DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)>DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)>DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)>DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)>DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)>DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)>DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)>DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)>DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)>DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)>DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)>DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)>DCP_CH0STAT_ERROR_SRC_MASK (0x10U)>DCP_CH0STAT_ERROR_SRC_SHIFT (4U)>DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)>DCP_CH0STAT_ERROR_DST_MASK (0x20U)>DCP_CH0STAT_ERROR_DST_SHIFT (5U)>DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)>DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)>DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)>DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)>DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)>DCP_CH0STAT_ERROR_CODE_SHIFT (16U)>DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)>DCP_CH0STAT_TAG_MASK (0xFF000000U)>DCP_CH0STAT_TAG_SHIFT (24U)>DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)>DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U)>DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U)>DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)>DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U)>DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U)>DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)>DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U)>DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U)>DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)>DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U)>DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U)>DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)>DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U)>DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U)>DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)>DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U)>DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U)>DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)>DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)>DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)>DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)>DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U)>DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U)>DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)>DCP_CH0STAT_SET_TAG_MASK (0xFF000000U)>DCP_CH0STAT_SET_TAG_SHIFT (24U)>DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)>DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U)>DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U)>DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)>DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U)>DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U)>DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)>DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U)>DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U)>DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)>DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U)>DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U)>DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)>DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U)>DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U)>DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)>DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U)>DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U)>DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)?DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)?DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)?DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)?DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U)?DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U)?DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)?DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U)?DCP_CH0STAT_CLR_TAG_SHIFT (24U)?DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)?DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U)?DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U)?DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)?DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U)?DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U)?DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)?DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U)?DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U)?DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)?DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U)?DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U)?DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)?DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U)?DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U)?DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)?DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U)?DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U)?DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)?DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)?DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)?DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)?DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U)?DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U)?DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)?DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U)?DCP_CH0STAT_TOG_TAG_SHIFT (24U)?DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)?DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)?DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)?DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)?DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)?DCP_CH0OPTS_RSVD_SHIFT (16U)?DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)?DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)?DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U)?DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)?DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U)?DCP_CH0OPTS_SET_RSVD_SHIFT (16U)?DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)?DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)?DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)?DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)?DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U)?DCP_CH0OPTS_CLR_RSVD_SHIFT (16U)?DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)?DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)?DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)?DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)?DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U)?DCP_CH0OPTS_TOG_RSVD_SHIFT (16U)?DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)?DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)?DCP_CH1CMDPTR_ADDR_SHIFT (0U)?DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)?DCP_CH1SEMA_INCREMENT_MASK (0xFFU)?DCP_CH1SEMA_INCREMENT_SHIFT (0U)?DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)?DCP_CH1SEMA_VALUE_MASK (0xFF0000U)?DCP_CH1SEMA_VALUE_SHIFT (16U)?DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)?DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)?DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)?DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)?DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)?DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)?DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)?DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)?DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)?DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)?DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)?DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)?DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)?DCP_CH1STAT_ERROR_SRC_MASK (0x10U)@DCP_CH1STAT_ERROR_SRC_SHIFT (4U)@DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)@DCP_CH1STAT_ERROR_DST_MASK (0x20U)@DCP_CH1STAT_ERROR_DST_SHIFT (5U)@DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)@DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)@DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)@DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)@DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)@DCP_CH1STAT_ERROR_CODE_SHIFT (16U)@DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)@DCP_CH1STAT_TAG_MASK (0xFF000000U)@DCP_CH1STAT_TAG_SHIFT (24U)@DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)@DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U)@DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U)@DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)@DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U)@DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U)@DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)@DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U)@DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U)@DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)@DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U)@DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U)@DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)@DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U)@DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U)@DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)@DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U)@DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U)@DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)@DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)@DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)@DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)@DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U)@DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U)@DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)@DCP_CH1STAT_SET_TAG_MASK (0xFF000000U)@DCP_CH1STAT_SET_TAG_SHIFT (24U)@DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)@DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U)@DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U)@DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)@DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U)@DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U)@DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)@DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U)@DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U)@DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)@DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U)@DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U)@DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)@DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U)@DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U)@DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)@DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U)@DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U)@DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)@DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)@DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)@DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)@DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U)@DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U)@DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)@DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U)@DCP_CH1STAT_CLR_TAG_SHIFT (24U)@DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)@DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U)@DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U)@DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)@DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U)@DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U)@DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)@DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U)@DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U)@DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)@DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U)@DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U)@DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)@DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U)@DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U)@DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)@DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U)@DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U)@DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)@DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)@DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)@DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)@DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U)@DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U)ADCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)ADCP_CH1STAT_TOG_TAG_MASK (0xFF000000U)ADCP_CH1STAT_TOG_TAG_SHIFT (24U)ADCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)ADCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)ADCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)ADCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)ADCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)ADCP_CH1OPTS_RSVD_SHIFT (16U)ADCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)ADCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)ADCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U)ADCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)ADCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U)ADCP_CH1OPTS_SET_RSVD_SHIFT (16U)ADCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)ADCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)ADCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)ADCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)ADCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U)ADCP_CH1OPTS_CLR_RSVD_SHIFT (16U)ADCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)ADCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)ADCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)ADCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)ADCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U)ADCP_CH1OPTS_TOG_RSVD_SHIFT (16U)ADCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)ADCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)ADCP_CH2CMDPTR_ADDR_SHIFT (0U)ADCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)ADCP_CH2SEMA_INCREMENT_MASK (0xFFU)ADCP_CH2SEMA_INCREMENT_SHIFT (0U)ADCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)ADCP_CH2SEMA_VALUE_MASK (0xFF0000U)ADCP_CH2SEMA_VALUE_SHIFT (16U)ADCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)ADCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)ADCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)ADCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)ADCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)ADCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)ADCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)ADCP_CH2STAT_ERROR_SETUP_MASK (0x4U)ADCP_CH2STAT_ERROR_SETUP_SHIFT (2U)ADCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)ADCP_CH2STAT_ERROR_PACKET_MASK (0x8U)ADCP_CH2STAT_ERROR_PACKET_SHIFT (3U)ADCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)ADCP_CH2STAT_ERROR_SRC_MASK (0x10U)ADCP_CH2STAT_ERROR_SRC_SHIFT (4U)ADCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)ADCP_CH2STAT_ERROR_DST_MASK (0x20U)ADCP_CH2STAT_ERROR_DST_SHIFT (5U)ADCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)ADCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)ADCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)ADCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)ADCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)ADCP_CH2STAT_ERROR_CODE_SHIFT (16U)ADCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)ADCP_CH2STAT_TAG_MASK (0xFF000000U)ADCP_CH2STAT_TAG_SHIFT (24U)ADCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)ADCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U)ADCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U)ADCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)ADCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U)ADCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U)ADCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)ADCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U)ADCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U)ADCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)ADCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U)ADCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U)ADCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)ADCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U)ADCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U)ADCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)ADCP_CH2STAT_SET_ERROR_DST_MASK (0x20U)ADCP_CH2STAT_SET_ERROR_DST_SHIFT (5U)ADCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)ADCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)ADCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)ADCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)ADCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U)BDCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U)BDCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)BDCP_CH2STAT_SET_TAG_MASK (0xFF000000U)BDCP_CH2STAT_SET_TAG_SHIFT (24U)BDCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)BDCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U)BDCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U)BDCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)BDCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U)BDCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U)BDCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)BDCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U)BDCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U)BDCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)BDCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U)BDCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U)BDCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)BDCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U)BDCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U)BDCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)BDCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U)BDCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U)BDCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)BDCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)BDCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)BDCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)BDCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U)BDCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U)BDCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)BDCP_CH2STAT_CLR_TAG_MASK (0xFF000000U)BDCP_CH2STAT_CLR_TAG_SHIFT (24U)BDCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)BDCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U)BDCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U)BDCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)BDCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U)BDCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U)BDCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)BDCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U)BDCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U)BDCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)BDCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U)BDCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U)BDCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)BDCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U)BDCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U)BDCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)BDCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U)BDCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U)BDCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)BDCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)BDCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)BDCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)BDCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U)BDCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U)BDCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)BDCP_CH2STAT_TOG_TAG_MASK (0xFF000000U)BDCP_CH2STAT_TOG_TAG_SHIFT (24U)BDCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)BDCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)BDCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)BDCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)BDCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)BDCP_CH2OPTS_RSVD_SHIFT (16U)BDCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)BDCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)BDCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U)BDCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)BDCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U)BDCP_CH2OPTS_SET_RSVD_SHIFT (16U)BDCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)BDCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)BDCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)BDCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)BDCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U)BDCP_CH2OPTS_CLR_RSVD_SHIFT (16U)BDCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)BDCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)BDCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)BDCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)BDCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U)BDCP_CH2OPTS_TOG_RSVD_SHIFT (16U)BDCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)CDCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)CDCP_CH3CMDPTR_ADDR_SHIFT (0U)CDCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)CDCP_CH3SEMA_INCREMENT_MASK (0xFFU)CDCP_CH3SEMA_INCREMENT_SHIFT (0U)CDCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)CDCP_CH3SEMA_VALUE_MASK (0xFF0000U)CDCP_CH3SEMA_VALUE_SHIFT (16U)CDCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)CDCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)CDCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)CDCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)CDCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)CDCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)CDCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)CDCP_CH3STAT_ERROR_SETUP_MASK (0x4U)CDCP_CH3STAT_ERROR_SETUP_SHIFT (2U)CDCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)CDCP_CH3STAT_ERROR_PACKET_MASK (0x8U)CDCP_CH3STAT_ERROR_PACKET_SHIFT (3U)CDCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)CDCP_CH3STAT_ERROR_SRC_MASK (0x10U)CDCP_CH3STAT_ERROR_SRC_SHIFT (4U)CDCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)CDCP_CH3STAT_ERROR_DST_MASK (0x20U)CDCP_CH3STAT_ERROR_DST_SHIFT (5U)CDCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)CDCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)CDCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)CDCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)CDCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)CDCP_CH3STAT_ERROR_CODE_SHIFT (16U)CDCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)CDCP_CH3STAT_TAG_MASK (0xFF000000U)CDCP_CH3STAT_TAG_SHIFT (24U)CDCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)CDCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U)CDCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U)CDCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)CDCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U)CDCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U)CDCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)CDCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U)CDCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U)CDCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)CDCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U)CDCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U)CDCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)CDCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U)CDCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U)CDCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)CDCP_CH3STAT_SET_ERROR_DST_MASK (0x20U)CDCP_CH3STAT_SET_ERROR_DST_SHIFT (5U)CDCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)CDCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)CDCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)CDCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)CDCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U)CDCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U)CDCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)CDCP_CH3STAT_SET_TAG_MASK (0xFF000000U)CDCP_CH3STAT_SET_TAG_SHIFT (24U)CDCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)CDCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U)CDCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U)CDCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)CDCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U)CDCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U)CDCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)CDCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U)CDCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U)CDCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)CDCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U)CDCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U)CDCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)CDCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U)CDCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U)CDCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)CDCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U)CDCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U)CDCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)CDCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)CDCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)CDCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)CDCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U)CDCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U)CDCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)DDCP_CH3STAT_CLR_TAG_MASK (0xFF000000U)DDCP_CH3STAT_CLR_TAG_SHIFT (24U)DDCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)DDCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U)DDCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U)DDCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)DDCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U)DDCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U)DDCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)DDCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U)DDCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U)DDCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)DDCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U)DDCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U)DDCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)DDCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U)DDCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U)DDCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)DDCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U)DDCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U)DDCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)DDCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)DDCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)DDCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)DDCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U)DDCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U)DDCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)DDCP_CH3STAT_TOG_TAG_MASK (0xFF000000U)DDCP_CH3STAT_TOG_TAG_SHIFT (24U)DDCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)DDCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)DDCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)DDCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)DDCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)DDCP_CH3OPTS_RSVD_SHIFT (16U)DDCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)DDCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)DDCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U)DDCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)DDCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U)DDCP_CH3OPTS_SET_RSVD_SHIFT (16U)DDCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)DDCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)DDCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)DDCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)DDCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U)DDCP_CH3OPTS_CLR_RSVD_SHIFT (16U)DDCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)DDCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)DDCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)DDCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)DDCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U)DDCP_CH3OPTS_TOG_RSVD_SHIFT (16U)DDCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)DDCP_DBGSELECT_INDEX_MASK (0xFFU)DDCP_DBGSELECT_INDEX_SHIFT (0U)DDCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)DDCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)DDCP_DBGSELECT_RSVD_SHIFT (8U)DDCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)DDCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)DDCP_DBGDATA_DATA_SHIFT (0U)DDCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)DDCP_PAGETABLE_ENABLE_MASK (0x1U)DDCP_PAGETABLE_ENABLE_SHIFT (0U)DDCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)DDCP_PAGETABLE_FLUSH_MASK (0x2U)DDCP_PAGETABLE_FLUSH_SHIFT (1U)DDCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)DDCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)DDCP_PAGETABLE_BASE_SHIFT (2U)DDCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)DDCP_VERSION_STEP_MASK (0xFFFFU)DDCP_VERSION_STEP_SHIFT (0U)DDCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)DDCP_VERSION_MINOR_MASK (0xFF0000U)DDCP_VERSION_MINOR_SHIFT (16U)DDCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)EDCP_VERSION_MAJOR_MASK (0xFF000000U)EDCP_VERSION_MAJOR_SHIFT (24U)EDCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)EDCP_BASE (0x402FC000u)EDCP ((DCP_Type *)DCP_BASE)EDCP_BASE_ADDRS { DCP_BASE }EDCP_BASE_PTRS { DCP }EDCP_IRQS { DCP_IRQn }EDCP_VMI_IRQS { DCP_VMI_IRQn }FDMA_CR_EDBG_MASK (0x2U)FDMA_CR_EDBG_SHIFT (1U)FDMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)FDMA_CR_ERCA_MASK (0x4U)FDMA_CR_ERCA_SHIFT (2U)FDMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)FDMA_CR_ERGA_MASK (0x8U)FDMA_CR_ERGA_SHIFT (3U)FDMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)FDMA_CR_HOE_MASK (0x10U)FDMA_CR_HOE_SHIFT (4U)FDMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)FDMA_CR_HALT_MASK (0x20U)FDMA_CR_HALT_SHIFT (5U)FDMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)FDMA_CR_CLM_MASK (0x40U)FDMA_CR_CLM_SHIFT (6U)FDMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)FDMA_CR_EMLM_MASK (0x80U)FDMA_CR_EMLM_SHIFT (7U)FDMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)FDMA_CR_GRP0PRI_MASK (0x100U)FDMA_CR_GRP0PRI_SHIFT (8U)FDMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)FDMA_CR_GRP1PRI_MASK (0x400U)FDMA_CR_GRP1PRI_SHIFT (10U)FDMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)FDMA_CR_ECX_MASK (0x10000U)FDMA_CR_ECX_SHIFT (16U)FDMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)FDMA_CR_CX_MASK (0x20000U)FDMA_CR_CX_SHIFT (17U)FDMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)FDMA_CR_ACTIVE_MASK (0x80000000U)FDMA_CR_ACTIVE_SHIFT (31U)FDMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)FDMA_ES_DBE_MASK (0x1U)FDMA_ES_DBE_SHIFT (0U)FDMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)FDMA_ES_SBE_MASK (0x2U)FDMA_ES_SBE_SHIFT (1U)FDMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)FDMA_ES_SGE_MASK (0x4U)FDMA_ES_SGE_SHIFT (2U)FDMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)FDMA_ES_NCE_MASK (0x8U)FDMA_ES_NCE_SHIFT (3U)GDMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)GDMA_ES_DOE_MASK (0x10U)GDMA_ES_DOE_SHIFT (4U)GDMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)GDMA_ES_DAE_MASK (0x20U)GDMA_ES_DAE_SHIFT (5U)GDMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)GDMA_ES_SOE_MASK (0x40U)GDMA_ES_SOE_SHIFT (6U)GDMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)GDMA_ES_SAE_MASK (0x80U)GDMA_ES_SAE_SHIFT (7U)GDMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)GDMA_ES_ERRCHN_MASK (0x1F00U)GDMA_ES_ERRCHN_SHIFT (8U)GDMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)GDMA_ES_CPE_MASK (0x4000U)GDMA_ES_CPE_SHIFT (14U)GDMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)GDMA_ES_GPE_MASK (0x8000U)GDMA_ES_GPE_SHIFT (15U)GDMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)GDMA_ES_ECX_MASK (0x10000U)GDMA_ES_ECX_SHIFT (16U)GDMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)GDMA_ES_VLD_MASK (0x80000000U)GDMA_ES_VLD_SHIFT (31U)GDMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)GDMA_ERQ_ERQ0_MASK (0x1U)GDMA_ERQ_ERQ0_SHIFT (0U)GDMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)GDMA_ERQ_ERQ1_MASK (0x2U)GDMA_ERQ_ERQ1_SHIFT (1U)GDMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)GDMA_ERQ_ERQ2_MASK (0x4U)GDMA_ERQ_ERQ2_SHIFT (2U)GDMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)GDMA_ERQ_ERQ3_MASK (0x8U)GDMA_ERQ_ERQ3_SHIFT (3U)GDMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)GDMA_ERQ_ERQ4_MASK (0x10U)GDMA_ERQ_ERQ4_SHIFT (4U)GDMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)GDMA_ERQ_ERQ5_MASK (0x20U)GDMA_ERQ_ERQ5_SHIFT (5U)GDMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)GDMA_ERQ_ERQ6_MASK (0x40U)GDMA_ERQ_ERQ6_SHIFT (6U)GDMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)GDMA_ERQ_ERQ7_MASK (0x80U)GDMA_ERQ_ERQ7_SHIFT (7U)GDMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)GDMA_ERQ_ERQ8_MASK (0x100U)GDMA_ERQ_ERQ8_SHIFT (8U)HDMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)HDMA_ERQ_ERQ9_MASK (0x200U)HDMA_ERQ_ERQ9_SHIFT (9U)HDMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)HDMA_ERQ_ERQ10_MASK (0x400U)HDMA_ERQ_ERQ10_SHIFT (10U)HDMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)HDMA_ERQ_ERQ11_MASK (0x800U)HDMA_ERQ_ERQ11_SHIFT (11U)HDMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)HDMA_ERQ_ERQ12_MASK (0x1000U)HDMA_ERQ_ERQ12_SHIFT (12U)HDMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)HDMA_ERQ_ERQ13_MASK (0x2000U)HDMA_ERQ_ERQ13_SHIFT (13U)HDMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)HDMA_ERQ_ERQ14_MASK (0x4000U)HDMA_ERQ_ERQ14_SHIFT (14U)HDMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)HDMA_ERQ_ERQ15_MASK (0x8000U)HDMA_ERQ_ERQ15_SHIFT (15U)HDMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)HDMA_ERQ_ERQ16_MASK (0x10000U)HDMA_ERQ_ERQ16_SHIFT (16U)HDMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)HDMA_ERQ_ERQ17_MASK (0x20000U)HDMA_ERQ_ERQ17_SHIFT (17U)HDMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)HDMA_ERQ_ERQ18_MASK (0x40000U)HDMA_ERQ_ERQ18_SHIFT (18U)HDMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)HDMA_ERQ_ERQ19_MASK (0x80000U)HDMA_ERQ_ERQ19_SHIFT (19U)HDMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)HDMA_ERQ_ERQ20_MASK (0x100000U)HDMA_ERQ_ERQ20_SHIFT (20U)HDMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)HDMA_ERQ_ERQ21_MASK (0x200000U)HDMA_ERQ_ERQ21_SHIFT (21U)HDMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)HDMA_ERQ_ERQ22_MASK (0x400000U)HDMA_ERQ_ERQ22_SHIFT (22U)HDMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)HDMA_ERQ_ERQ23_MASK (0x800000U)HDMA_ERQ_ERQ23_SHIFT (23U)HDMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)HDMA_ERQ_ERQ24_MASK (0x1000000U)HDMA_ERQ_ERQ24_SHIFT (24U)HDMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)HDMA_ERQ_ERQ25_MASK (0x2000000U)HDMA_ERQ_ERQ25_SHIFT (25U)HDMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)HDMA_ERQ_ERQ26_MASK (0x4000000U)HDMA_ERQ_ERQ26_SHIFT (26U)HDMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)HDMA_ERQ_ERQ27_MASK (0x8000000U)IDMA_ERQ_ERQ27_SHIFT (27U)IDMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)IDMA_ERQ_ERQ28_MASK (0x10000000U)IDMA_ERQ_ERQ28_SHIFT (28U)IDMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)IDMA_ERQ_ERQ29_MASK (0x20000000U)IDMA_ERQ_ERQ29_SHIFT (29U)IDMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)IDMA_ERQ_ERQ30_MASK (0x40000000U)IDMA_ERQ_ERQ30_SHIFT (30U)IDMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)IDMA_ERQ_ERQ31_MASK (0x80000000U)IDMA_ERQ_ERQ31_SHIFT (31U)IDMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)IDMA_EEI_EEI0_MASK (0x1U)IDMA_EEI_EEI0_SHIFT (0U)IDMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)IDMA_EEI_EEI1_MASK (0x2U)IDMA_EEI_EEI1_SHIFT (1U)IDMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)IDMA_EEI_EEI2_MASK (0x4U)IDMA_EEI_EEI2_SHIFT (2U)IDMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)IDMA_EEI_EEI3_MASK (0x8U)IDMA_EEI_EEI3_SHIFT (3U)IDMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)IDMA_EEI_EEI4_MASK (0x10U)IDMA_EEI_EEI4_SHIFT (4U)IDMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)IDMA_EEI_EEI5_MASK (0x20U)IDMA_EEI_EEI5_SHIFT (5U)IDMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)IDMA_EEI_EEI6_MASK (0x40U)IDMA_EEI_EEI6_SHIFT (6U)IDMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)IDMA_EEI_EEI7_MASK (0x80U)IDMA_EEI_EEI7_SHIFT (7U)IDMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)IDMA_EEI_EEI8_MASK (0x100U)IDMA_EEI_EEI8_SHIFT (8U)IDMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)IDMA_EEI_EEI9_MASK (0x200U)IDMA_EEI_EEI9_SHIFT (9U)IDMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)IDMA_EEI_EEI10_MASK (0x400U)IDMA_EEI_EEI10_SHIFT (10U)IDMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)IDMA_EEI_EEI11_MASK (0x800U)IDMA_EEI_EEI11_SHIFT (11U)IDMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)IDMA_EEI_EEI12_MASK (0x1000U)IDMA_EEI_EEI12_SHIFT (12U)JDMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)JDMA_EEI_EEI13_MASK (0x2000U)JDMA_EEI_EEI13_SHIFT (13U)JDMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)JDMA_EEI_EEI14_MASK (0x4000U)JDMA_EEI_EEI14_SHIFT (14U)JDMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)JDMA_EEI_EEI15_MASK (0x8000U)JDMA_EEI_EEI15_SHIFT (15U)JDMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)JDMA_EEI_EEI16_MASK (0x10000U)JDMA_EEI_EEI16_SHIFT (16U)JDMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)JDMA_EEI_EEI17_MASK (0x20000U)JDMA_EEI_EEI17_SHIFT (17U)JDMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)JDMA_EEI_EEI18_MASK (0x40000U)JDMA_EEI_EEI18_SHIFT (18U)JDMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)JDMA_EEI_EEI19_MASK (0x80000U)JDMA_EEI_EEI19_SHIFT (19U)JDMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)JDMA_EEI_EEI20_MASK (0x100000U)JDMA_EEI_EEI20_SHIFT (20U)JDMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)JDMA_EEI_EEI21_MASK (0x200000U)JDMA_EEI_EEI21_SHIFT (21U)JDMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)JDMA_EEI_EEI22_MASK (0x400000U)JDMA_EEI_EEI22_SHIFT (22U)JDMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)JDMA_EEI_EEI23_MASK (0x800000U)JDMA_EEI_EEI23_SHIFT (23U)JDMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)JDMA_EEI_EEI24_MASK (0x1000000U)JDMA_EEI_EEI24_SHIFT (24U)JDMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)JDMA_EEI_EEI25_MASK (0x2000000U)JDMA_EEI_EEI25_SHIFT (25U)JDMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)JDMA_EEI_EEI26_MASK (0x4000000U)JDMA_EEI_EEI26_SHIFT (26U)JDMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)JDMA_EEI_EEI27_MASK (0x8000000U)JDMA_EEI_EEI27_SHIFT (27U)JDMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)JDMA_EEI_EEI28_MASK (0x10000000U)JDMA_EEI_EEI28_SHIFT (28U)JDMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)JDMA_EEI_EEI29_MASK (0x20000000U)JDMA_EEI_EEI29_SHIFT (29U)JDMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)JDMA_EEI_EEI30_MASK (0x40000000U)JDMA_EEI_EEI30_SHIFT (30U)JDMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)JDMA_EEI_EEI31_MASK (0x80000000U)KDMA_EEI_EEI31_SHIFT (31U)KDMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)KDMA_CEEI_CEEI_MASK (0x1FU)KDMA_CEEI_CEEI_SHIFT (0U)KDMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)KDMA_CEEI_CAEE_MASK (0x40U)KDMA_CEEI_CAEE_SHIFT (6U)KDMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)KDMA_CEEI_NOP_MASK (0x80U)KDMA_CEEI_NOP_SHIFT (7U)KDMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)KDMA_SEEI_SEEI_MASK (0x1FU)KDMA_SEEI_SEEI_SHIFT (0U)KDMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)KDMA_SEEI_SAEE_MASK (0x40U)KDMA_SEEI_SAEE_SHIFT (6U)KDMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)KDMA_SEEI_NOP_MASK (0x80U)KDMA_SEEI_NOP_SHIFT (7U)KDMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)KDMA_CERQ_CERQ_MASK (0x1FU)KDMA_CERQ_CERQ_SHIFT (0U)KDMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)KDMA_CERQ_CAER_MASK (0x40U)KDMA_CERQ_CAER_SHIFT (6U)KDMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)KDMA_CERQ_NOP_MASK (0x80U)KDMA_CERQ_NOP_SHIFT (7U)KDMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)KDMA_SERQ_SERQ_MASK (0x1FU)KDMA_SERQ_SERQ_SHIFT (0U)KDMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)KDMA_SERQ_SAER_MASK (0x40U)KDMA_SERQ_SAER_SHIFT (6U)KDMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)KDMA_SERQ_NOP_MASK (0x80U)KDMA_SERQ_NOP_SHIFT (7U)KDMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)KDMA_CDNE_CDNE_MASK (0x1FU)KDMA_CDNE_CDNE_SHIFT (0U)KDMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)KDMA_CDNE_CADN_MASK (0x40U)KDMA_CDNE_CADN_SHIFT (6U)KDMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)KDMA_CDNE_NOP_MASK (0x80U)KDMA_CDNE_NOP_SHIFT (7U)KDMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)KDMA_SSRT_SSRT_MASK (0x1FU)KDMA_SSRT_SSRT_SHIFT (0U)KDMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)KDMA_SSRT_SAST_MASK (0x40U)KDMA_SSRT_SAST_SHIFT (6U)KDMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)KDMA_SSRT_NOP_MASK (0x80U)KDMA_SSRT_NOP_SHIFT (7U)LDMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)LDMA_CERR_CERR_MASK (0x1FU)LDMA_CERR_CERR_SHIFT (0U)LDMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)LDMA_CERR_CAEI_MASK (0x40U)LDMA_CERR_CAEI_SHIFT (6U)LDMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)LDMA_CERR_NOP_MASK (0x80U)LDMA_CERR_NOP_SHIFT (7U)LDMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)LDMA_CINT_CINT_MASK (0x1FU)LDMA_CINT_CINT_SHIFT (0U)LDMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)LDMA_CINT_CAIR_MASK (0x40U)LDMA_CINT_CAIR_SHIFT (6U)LDMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)LDMA_CINT_NOP_MASK (0x80U)LDMA_CINT_NOP_SHIFT (7U)LDMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)LDMA_INT_INT0_MASK (0x1U)LDMA_INT_INT0_SHIFT (0U)LDMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)LDMA_INT_INT1_MASK (0x2U)LDMA_INT_INT1_SHIFT (1U)LDMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)LDMA_INT_INT2_MASK (0x4U)LDMA_INT_INT2_SHIFT (2U)LDMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)LDMA_INT_INT3_MASK (0x8U)LDMA_INT_INT3_SHIFT (3U)LDMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)LDMA_INT_INT4_MASK (0x10U)LDMA_INT_INT4_SHIFT (4U)LDMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)LDMA_INT_INT5_MASK (0x20U)LDMA_INT_INT5_SHIFT (5U)LDMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)LDMA_INT_INT6_MASK (0x40U)LDMA_INT_INT6_SHIFT (6U)LDMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)LDMA_INT_INT7_MASK (0x80U)LDMA_INT_INT7_SHIFT (7U)LDMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)LDMA_INT_INT8_MASK (0x100U)LDMA_INT_INT8_SHIFT (8U)LDMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)LDMA_INT_INT9_MASK (0x200U)LDMA_INT_INT9_SHIFT (9U)LDMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)LDMA_INT_INT10_MASK (0x400U)LDMA_INT_INT10_SHIFT (10U)LDMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)LDMA_INT_INT11_MASK (0x800U)MDMA_INT_INT11_SHIFT (11U)MDMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)MDMA_INT_INT12_MASK (0x1000U)MDMA_INT_INT12_SHIFT (12U)MDMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)MDMA_INT_INT13_MASK (0x2000U)MDMA_INT_INT13_SHIFT (13U)MDMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)MDMA_INT_INT14_MASK (0x4000U)MDMA_INT_INT14_SHIFT (14U)MDMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)MDMA_INT_INT15_MASK (0x8000U)MDMA_INT_INT15_SHIFT (15U)MDMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)MDMA_INT_INT16_MASK (0x10000U)MDMA_INT_INT16_SHIFT (16U)MDMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)MDMA_INT_INT17_MASK (0x20000U)MDMA_INT_INT17_SHIFT (17U)MDMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)MDMA_INT_INT18_MASK (0x40000U)MDMA_INT_INT18_SHIFT (18U)MDMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)MDMA_INT_INT19_MASK (0x80000U)MDMA_INT_INT19_SHIFT (19U)MDMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)MDMA_INT_INT20_MASK (0x100000U)MDMA_INT_INT20_SHIFT (20U)MDMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)MDMA_INT_INT21_MASK (0x200000U)MDMA_INT_INT21_SHIFT (21U)MDMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)MDMA_INT_INT22_MASK (0x400000U)MDMA_INT_INT22_SHIFT (22U)MDMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)MDMA_INT_INT23_MASK (0x800000U)MDMA_INT_INT23_SHIFT (23U)MDMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)MDMA_INT_INT24_MASK (0x1000000U)MDMA_INT_INT24_SHIFT (24U)MDMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)MDMA_INT_INT25_MASK (0x2000000U)MDMA_INT_INT25_SHIFT (25U)MDMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)MDMA_INT_INT26_MASK (0x4000000U)MDMA_INT_INT26_SHIFT (26U)MDMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)MDMA_INT_INT27_MASK (0x8000000U)MDMA_INT_INT27_SHIFT (27U)MDMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)MDMA_INT_INT28_MASK (0x10000000U)MDMA_INT_INT28_SHIFT (28U)MDMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)MDMA_INT_INT29_MASK (0x20000000U)MDMA_INT_INT29_SHIFT (29U)NDMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)NDMA_INT_INT30_MASK (0x40000000U)NDMA_INT_INT30_SHIFT (30U)NDMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)NDMA_INT_INT31_MASK (0x80000000U)NDMA_INT_INT31_SHIFT (31U)NDMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)NDMA_ERR_ERR0_MASK (0x1U)NDMA_ERR_ERR0_SHIFT (0U)NDMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)NDMA_ERR_ERR1_MASK (0x2U)NDMA_ERR_ERR1_SHIFT (1U)NDMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)NDMA_ERR_ERR2_MASK (0x4U)NDMA_ERR_ERR2_SHIFT (2U)NDMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)NDMA_ERR_ERR3_MASK (0x8U)NDMA_ERR_ERR3_SHIFT (3U)NDMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)NDMA_ERR_ERR4_MASK (0x10U)NDMA_ERR_ERR4_SHIFT (4U)NDMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)NDMA_ERR_ERR5_MASK (0x20U)NDMA_ERR_ERR5_SHIFT (5U)NDMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)NDMA_ERR_ERR6_MASK (0x40U)NDMA_ERR_ERR6_SHIFT (6U)NDMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)NDMA_ERR_ERR7_MASK (0x80U)NDMA_ERR_ERR7_SHIFT (7U)NDMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)NDMA_ERR_ERR8_MASK (0x100U)NDMA_ERR_ERR8_SHIFT (8U)NDMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)NDMA_ERR_ERR9_MASK (0x200U)NDMA_ERR_ERR9_SHIFT (9U)NDMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)NDMA_ERR_ERR10_MASK (0x400U)NDMA_ERR_ERR10_SHIFT (10U)NDMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)NDMA_ERR_ERR11_MASK (0x800U)NDMA_ERR_ERR11_SHIFT (11U)NDMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)NDMA_ERR_ERR12_MASK (0x1000U)NDMA_ERR_ERR12_SHIFT (12U)NDMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)NDMA_ERR_ERR13_MASK (0x2000U)NDMA_ERR_ERR13_SHIFT (13U)NDMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)NDMA_ERR_ERR14_MASK (0x4000U)NDMA_ERR_ERR14_SHIFT (14U)NDMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)NDMA_ERR_ERR15_MASK (0x8000U)ODMA_ERR_ERR15_SHIFT (15U)ODMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)ODMA_ERR_ERR16_MASK (0x10000U)ODMA_ERR_ERR16_SHIFT (16U)ODMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)ODMA_ERR_ERR17_MASK (0x20000U)ODMA_ERR_ERR17_SHIFT (17U)ODMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)ODMA_ERR_ERR18_MASK (0x40000U)ODMA_ERR_ERR18_SHIFT (18U)ODMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)ODMA_ERR_ERR19_MASK (0x80000U)ODMA_ERR_ERR19_SHIFT (19U)ODMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)ODMA_ERR_ERR20_MASK (0x100000U)ODMA_ERR_ERR20_SHIFT (20U)ODMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)ODMA_ERR_ERR21_MASK (0x200000U)ODMA_ERR_ERR21_SHIFT (21U)ODMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)ODMA_ERR_ERR22_MASK (0x400000U)ODMA_ERR_ERR22_SHIFT (22U)ODMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)ODMA_ERR_ERR23_MASK (0x800000U)ODMA_ERR_ERR23_SHIFT (23U)ODMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)ODMA_ERR_ERR24_MASK (0x1000000U)ODMA_ERR_ERR24_SHIFT (24U)ODMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)ODMA_ERR_ERR25_MASK (0x2000000U)ODMA_ERR_ERR25_SHIFT (25U)ODMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)ODMA_ERR_ERR26_MASK (0x4000000U)ODMA_ERR_ERR26_SHIFT (26U)ODMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)ODMA_ERR_ERR27_MASK (0x8000000U)ODMA_ERR_ERR27_SHIFT (27U)ODMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)ODMA_ERR_ERR28_MASK (0x10000000U)ODMA_ERR_ERR28_SHIFT (28U)ODMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)ODMA_ERR_ERR29_MASK (0x20000000U)ODMA_ERR_ERR29_SHIFT (29U)ODMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)ODMA_ERR_ERR30_MASK (0x40000000U)ODMA_ERR_ERR30_SHIFT (30U)ODMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)ODMA_ERR_ERR31_MASK (0x80000000U)ODMA_ERR_ERR31_SHIFT (31U)ODMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)ODMA_HRS_HRS0_MASK (0x1U)ODMA_HRS_HRS0_SHIFT (0U)PDMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)PDMA_HRS_HRS1_MASK (0x2U)PDMA_HRS_HRS1_SHIFT (1U)PDMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)PDMA_HRS_HRS2_MASK (0x4U)PDMA_HRS_HRS2_SHIFT (2U)PDMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)PDMA_HRS_HRS3_MASK (0x8U)PDMA_HRS_HRS3_SHIFT (3U)PDMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)PDMA_HRS_HRS4_MASK (0x10U)PDMA_HRS_HRS4_SHIFT (4U)PDMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)PDMA_HRS_HRS5_MASK (0x20U)PDMA_HRS_HRS5_SHIFT (5U)PDMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)PDMA_HRS_HRS6_MASK (0x40U)PDMA_HRS_HRS6_SHIFT (6U)PDMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)PDMA_HRS_HRS7_MASK (0x80U)PDMA_HRS_HRS7_SHIFT (7U)PDMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)PDMA_HRS_HRS8_MASK (0x100U)PDMA_HRS_HRS8_SHIFT (8U)PDMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)PDMA_HRS_HRS9_MASK (0x200U)PDMA_HRS_HRS9_SHIFT (9U)PDMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)PDMA_HRS_HRS10_MASK (0x400U)PDMA_HRS_HRS10_SHIFT (10U)PDMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)PDMA_HRS_HRS11_MASK (0x800U)PDMA_HRS_HRS11_SHIFT (11U)PDMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)PDMA_HRS_HRS12_MASK (0x1000U)PDMA_HRS_HRS12_SHIFT (12U)PDMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)PDMA_HRS_HRS13_MASK (0x2000U)PDMA_HRS_HRS13_SHIFT (13U)PDMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)PDMA_HRS_HRS14_MASK (0x4000U)PDMA_HRS_HRS14_SHIFT (14U)PDMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)PDMA_HRS_HRS15_MASK (0x8000U)PDMA_HRS_HRS15_SHIFT (15U)PDMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)PDMA_HRS_HRS16_MASK (0x10000U)PDMA_HRS_HRS16_SHIFT (16U)PDMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)PDMA_HRS_HRS17_MASK (0x20000U)PDMA_HRS_HRS17_SHIFT (17U)PDMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)PDMA_HRS_HRS18_MASK (0x40000U)PDMA_HRS_HRS18_SHIFT (18U)PDMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)PDMA_HRS_HRS19_MASK (0x80000U)QDMA_HRS_HRS19_SHIFT (19U)QDMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)QDMA_HRS_HRS20_MASK (0x100000U)QDMA_HRS_HRS20_SHIFT (20U)QDMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)QDMA_HRS_HRS21_MASK (0x200000U)QDMA_HRS_HRS21_SHIFT (21U)QDMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)QDMA_HRS_HRS22_MASK (0x400000U)QDMA_HRS_HRS22_SHIFT (22U)QDMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)QDMA_HRS_HRS23_MASK (0x800000U)QDMA_HRS_HRS23_SHIFT (23U)QDMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)QDMA_HRS_HRS24_MASK (0x1000000U)QDMA_HRS_HRS24_SHIFT (24U)QDMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)QDMA_HRS_HRS25_MASK (0x2000000U)QDMA_HRS_HRS25_SHIFT (25U)QDMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)QDMA_HRS_HRS26_MASK (0x4000000U)QDMA_HRS_HRS26_SHIFT (26U)QDMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)QDMA_HRS_HRS27_MASK (0x8000000U)QDMA_HRS_HRS27_SHIFT (27U)QDMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)QDMA_HRS_HRS28_MASK (0x10000000U)QDMA_HRS_HRS28_SHIFT (28U)QDMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)QDMA_HRS_HRS29_MASK (0x20000000U)QDMA_HRS_HRS29_SHIFT (29U)QDMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)QDMA_HRS_HRS30_MASK (0x40000000U)QDMA_HRS_HRS30_SHIFT (30U)QDMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)QDMA_HRS_HRS31_MASK (0x80000000U)QDMA_HRS_HRS31_SHIFT (31U)QDMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)QDMA_EARS_EDREQ_0_MASK (0x1U)QDMA_EARS_EDREQ_0_SHIFT (0U)QDMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)QDMA_EARS_EDREQ_1_MASK (0x2U)QDMA_EARS_EDREQ_1_SHIFT (1U)QDMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)QDMA_EARS_EDREQ_2_MASK (0x4U)QDMA_EARS_EDREQ_2_SHIFT (2U)QDMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)QDMA_EARS_EDREQ_3_MASK (0x8U)QDMA_EARS_EDREQ_3_SHIFT (3U)QDMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)QDMA_EARS_EDREQ_4_MASK (0x10U)QDMA_EARS_EDREQ_4_SHIFT (4U)RDMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)RDMA_EARS_EDREQ_5_MASK (0x20U)RDMA_EARS_EDREQ_5_SHIFT (5U)RDMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)RDMA_EARS_EDREQ_6_MASK (0x40U)RDMA_EARS_EDREQ_6_SHIFT (6U)RDMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)RDMA_EARS_EDREQ_7_MASK (0x80U)RDMA_EARS_EDREQ_7_SHIFT (7U)RDMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)RDMA_EARS_EDREQ_8_MASK (0x100U)RDMA_EARS_EDREQ_8_SHIFT (8U)RDMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)RDMA_EARS_EDREQ_9_MASK (0x200U)RDMA_EARS_EDREQ_9_SHIFT (9U)RDMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)RDMA_EARS_EDREQ_10_MASK (0x400U)RDMA_EARS_EDREQ_10_SHIFT (10U)RDMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)RDMA_EARS_EDREQ_11_MASK (0x800U)RDMA_EARS_EDREQ_11_SHIFT (11U)RDMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)RDMA_EARS_EDREQ_12_MASK (0x1000U)RDMA_EARS_EDREQ_12_SHIFT (12U)RDMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)RDMA_EARS_EDREQ_13_MASK (0x2000U)RDMA_EARS_EDREQ_13_SHIFT (13U)RDMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)RDMA_EARS_EDREQ_14_MASK (0x4000U)RDMA_EARS_EDREQ_14_SHIFT (14U)RDMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)RDMA_EARS_EDREQ_15_MASK (0x8000U)RDMA_EARS_EDREQ_15_SHIFT (15U)RDMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)RDMA_EARS_EDREQ_16_MASK (0x10000U)RDMA_EARS_EDREQ_16_SHIFT (16U)RDMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)RDMA_EARS_EDREQ_17_MASK (0x20000U)RDMA_EARS_EDREQ_17_SHIFT (17U)RDMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)RDMA_EARS_EDREQ_18_MASK (0x40000U)RDMA_EARS_EDREQ_18_SHIFT (18U)RDMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)RDMA_EARS_EDREQ_19_MASK (0x80000U)RDMA_EARS_EDREQ_19_SHIFT (19U)RDMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)RDMA_EARS_EDREQ_20_MASK (0x100000U)RDMA_EARS_EDREQ_20_SHIFT (20U)RDMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)RDMA_EARS_EDREQ_21_MASK (0x200000U)RDMA_EARS_EDREQ_21_SHIFT (21U)RDMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)RDMA_EARS_EDREQ_22_MASK (0x400000U)RDMA_EARS_EDREQ_22_SHIFT (22U)RDMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)RDMA_EARS_EDREQ_23_MASK (0x800000U)SDMA_EARS_EDREQ_23_SHIFT (23U)SDMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)SDMA_EARS_EDREQ_24_MASK (0x1000000U)SDMA_EARS_EDREQ_24_SHIFT (24U)SDMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)SDMA_EARS_EDREQ_25_MASK (0x2000000U)SDMA_EARS_EDREQ_25_SHIFT (25U)SDMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)SDMA_EARS_EDREQ_26_MASK (0x4000000U)SDMA_EARS_EDREQ_26_SHIFT (26U)SDMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)SDMA_EARS_EDREQ_27_MASK (0x8000000U)SDMA_EARS_EDREQ_27_SHIFT (27U)SDMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)SDMA_EARS_EDREQ_28_MASK (0x10000000U)SDMA_EARS_EDREQ_28_SHIFT (28U)SDMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)SDMA_EARS_EDREQ_29_MASK (0x20000000U)SDMA_EARS_EDREQ_29_SHIFT (29U)SDMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)SDMA_EARS_EDREQ_30_MASK (0x40000000U)SDMA_EARS_EDREQ_30_SHIFT (30U)SDMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)SDMA_EARS_EDREQ_31_MASK (0x80000000U)SDMA_EARS_EDREQ_31_SHIFT (31U)SDMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)SDMA_DCHPRI3_CHPRI_MASK (0xFU)SDMA_DCHPRI3_CHPRI_SHIFT (0U)SDMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)SDMA_DCHPRI3_GRPPRI_MASK (0x30U)SDMA_DCHPRI3_GRPPRI_SHIFT (4U)SDMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)SDMA_DCHPRI3_DPA_MASK (0x40U)SDMA_DCHPRI3_DPA_SHIFT (6U)SDMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)SDMA_DCHPRI3_ECP_MASK (0x80U)SDMA_DCHPRI3_ECP_SHIFT (7U)SDMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)SDMA_DCHPRI2_CHPRI_MASK (0xFU)SDMA_DCHPRI2_CHPRI_SHIFT (0U)SDMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)SDMA_DCHPRI2_GRPPRI_MASK (0x30U)SDMA_DCHPRI2_GRPPRI_SHIFT (4U)SDMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)SDMA_DCHPRI2_DPA_MASK (0x40U)SDMA_DCHPRI2_DPA_SHIFT (6U)SDMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)SDMA_DCHPRI2_ECP_MASK (0x80U)SDMA_DCHPRI2_ECP_SHIFT (7U)SDMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)SDMA_DCHPRI1_CHPRI_MASK (0xFU)SDMA_DCHPRI1_CHPRI_SHIFT (0U)SDMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)SDMA_DCHPRI1_GRPPRI_MASK (0x30U)SDMA_DCHPRI1_GRPPRI_SHIFT (4U)SDMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)SDMA_DCHPRI1_DPA_MASK (0x40U)SDMA_DCHPRI1_DPA_SHIFT (6U)SDMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)SDMA_DCHPRI1_ECP_MASK (0x80U)TDMA_DCHPRI1_ECP_SHIFT (7U)TDMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)TDMA_DCHPRI0_CHPRI_MASK (0xFU)TDMA_DCHPRI0_CHPRI_SHIFT (0U)TDMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)TDMA_DCHPRI0_GRPPRI_MASK (0x30U)TDMA_DCHPRI0_GRPPRI_SHIFT (4U)TDMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)TDMA_DCHPRI0_DPA_MASK (0x40U)TDMA_DCHPRI0_DPA_SHIFT (6U)TDMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)TDMA_DCHPRI0_ECP_MASK (0x80U)TDMA_DCHPRI0_ECP_SHIFT (7U)TDMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)TDMA_DCHPRI7_CHPRI_MASK (0xFU)TDMA_DCHPRI7_CHPRI_SHIFT (0U)TDMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)TDMA_DCHPRI7_GRPPRI_MASK (0x30U)TDMA_DCHPRI7_GRPPRI_SHIFT (4U)TDMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)TDMA_DCHPRI7_DPA_MASK (0x40U)TDMA_DCHPRI7_DPA_SHIFT (6U)TDMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)TDMA_DCHPRI7_ECP_MASK (0x80U)TDMA_DCHPRI7_ECP_SHIFT (7U)TDMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)TDMA_DCHPRI6_CHPRI_MASK (0xFU)TDMA_DCHPRI6_CHPRI_SHIFT (0U)TDMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)TDMA_DCHPRI6_GRPPRI_MASK (0x30U)TDMA_DCHPRI6_GRPPRI_SHIFT (4U)TDMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)TDMA_DCHPRI6_DPA_MASK (0x40U)TDMA_DCHPRI6_DPA_SHIFT (6U)TDMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)TDMA_DCHPRI6_ECP_MASK (0x80U)TDMA_DCHPRI6_ECP_SHIFT (7U)TDMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)TDMA_DCHPRI5_CHPRI_MASK (0xFU)TDMA_DCHPRI5_CHPRI_SHIFT (0U)TDMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)TDMA_DCHPRI5_GRPPRI_MASK (0x30U)TDMA_DCHPRI5_GRPPRI_SHIFT (4U)TDMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)TDMA_DCHPRI5_DPA_MASK (0x40U)TDMA_DCHPRI5_DPA_SHIFT (6U)TDMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)TDMA_DCHPRI5_ECP_MASK (0x80U)TDMA_DCHPRI5_ECP_SHIFT (7U)TDMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)TDMA_DCHPRI4_CHPRI_MASK (0xFU)TDMA_DCHPRI4_CHPRI_SHIFT (0U)TDMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)TDMA_DCHPRI4_GRPPRI_MASK (0x30U)TDMA_DCHPRI4_GRPPRI_SHIFT (4U)TDMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)TDMA_DCHPRI4_DPA_MASK (0x40U)TDMA_DCHPRI4_DPA_SHIFT (6U)TDMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)TDMA_DCHPRI4_ECP_MASK (0x80U)TDMA_DCHPRI4_ECP_SHIFT (7U)TDMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)UDMA_DCHPRI11_CHPRI_MASK (0xFU)UDMA_DCHPRI11_CHPRI_SHIFT (0U)UDMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)UDMA_DCHPRI11_GRPPRI_MASK (0x30U)UDMA_DCHPRI11_GRPPRI_SHIFT (4U)UDMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)UDMA_DCHPRI11_DPA_MASK (0x40U)UDMA_DCHPRI11_DPA_SHIFT (6U)UDMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)UDMA_DCHPRI11_ECP_MASK (0x80U)UDMA_DCHPRI11_ECP_SHIFT (7U)UDMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)UDMA_DCHPRI10_CHPRI_MASK (0xFU)UDMA_DCHPRI10_CHPRI_SHIFT (0U)UDMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)UDMA_DCHPRI10_GRPPRI_MASK (0x30U)UDMA_DCHPRI10_GRPPRI_SHIFT (4U)UDMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)UDMA_DCHPRI10_DPA_MASK (0x40U)UDMA_DCHPRI10_DPA_SHIFT (6U)UDMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)UDMA_DCHPRI10_ECP_MASK (0x80U)UDMA_DCHPRI10_ECP_SHIFT (7U)UDMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)UDMA_DCHPRI9_CHPRI_MASK (0xFU)UDMA_DCHPRI9_CHPRI_SHIFT (0U)UDMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)UDMA_DCHPRI9_GRPPRI_MASK (0x30U)UDMA_DCHPRI9_GRPPRI_SHIFT (4U)UDMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)UDMA_DCHPRI9_DPA_MASK (0x40U)UDMA_DCHPRI9_DPA_SHIFT (6U)UDMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)UDMA_DCHPRI9_ECP_MASK (0x80U)UDMA_DCHPRI9_ECP_SHIFT (7U)UDMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)UDMA_DCHPRI8_CHPRI_MASK (0xFU)UDMA_DCHPRI8_CHPRI_SHIFT (0U)UDMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)UDMA_DCHPRI8_GRPPRI_MASK (0x30U)UDMA_DCHPRI8_GRPPRI_SHIFT (4U)UDMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)UDMA_DCHPRI8_DPA_MASK (0x40U)UDMA_DCHPRI8_DPA_SHIFT (6U)UDMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)UDMA_DCHPRI8_ECP_MASK (0x80U)UDMA_DCHPRI8_ECP_SHIFT (7U)UDMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)UDMA_DCHPRI15_CHPRI_MASK (0xFU)UDMA_DCHPRI15_CHPRI_SHIFT (0U)UDMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)UDMA_DCHPRI15_GRPPRI_MASK (0x30U)UDMA_DCHPRI15_GRPPRI_SHIFT (4U)UDMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)UDMA_DCHPRI15_DPA_MASK (0x40U)UDMA_DCHPRI15_DPA_SHIFT (6U)UDMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)UDMA_DCHPRI15_ECP_MASK (0x80U)UDMA_DCHPRI15_ECP_SHIFT (7U)UDMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)UDMA_DCHPRI14_CHPRI_MASK (0xFU)UDMA_DCHPRI14_CHPRI_SHIFT (0U)UDMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)UDMA_DCHPRI14_GRPPRI_MASK (0x30U)UDMA_DCHPRI14_GRPPRI_SHIFT (4U)UDMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)VDMA_DCHPRI14_DPA_MASK (0x40U)VDMA_DCHPRI14_DPA_SHIFT (6U)VDMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)VDMA_DCHPRI14_ECP_MASK (0x80U)VDMA_DCHPRI14_ECP_SHIFT (7U)VDMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)VDMA_DCHPRI13_CHPRI_MASK (0xFU)VDMA_DCHPRI13_CHPRI_SHIFT (0U)VDMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)VDMA_DCHPRI13_GRPPRI_MASK (0x30U)VDMA_DCHPRI13_GRPPRI_SHIFT (4U)VDMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)VDMA_DCHPRI13_DPA_MASK (0x40U)VDMA_DCHPRI13_DPA_SHIFT (6U)VDMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)VDMA_DCHPRI13_ECP_MASK (0x80U)VDMA_DCHPRI13_ECP_SHIFT (7U)VDMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)VDMA_DCHPRI12_CHPRI_MASK (0xFU)VDMA_DCHPRI12_CHPRI_SHIFT (0U)VDMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)VDMA_DCHPRI12_GRPPRI_MASK (0x30U)VDMA_DCHPRI12_GRPPRI_SHIFT (4U)VDMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)VDMA_DCHPRI12_DPA_MASK (0x40U)VDMA_DCHPRI12_DPA_SHIFT (6U)VDMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)VDMA_DCHPRI12_ECP_MASK (0x80U)VDMA_DCHPRI12_ECP_SHIFT (7U)VDMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)VDMA_DCHPRI19_CHPRI_MASK (0xFU)VDMA_DCHPRI19_CHPRI_SHIFT (0U)VDMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)VDMA_DCHPRI19_GRPPRI_MASK (0x30U)VDMA_DCHPRI19_GRPPRI_SHIFT (4U)VDMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)VDMA_DCHPRI19_DPA_MASK (0x40U)VDMA_DCHPRI19_DPA_SHIFT (6U)VDMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)VDMA_DCHPRI19_ECP_MASK (0x80U)VDMA_DCHPRI19_ECP_SHIFT (7U)VDMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)VDMA_DCHPRI18_CHPRI_MASK (0xFU)VDMA_DCHPRI18_CHPRI_SHIFT (0U)VDMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)VDMA_DCHPRI18_GRPPRI_MASK (0x30U)VDMA_DCHPRI18_GRPPRI_SHIFT (4U)VDMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)VDMA_DCHPRI18_DPA_MASK (0x40U)VDMA_DCHPRI18_DPA_SHIFT (6U)VDMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)VDMA_DCHPRI18_ECP_MASK (0x80U)VDMA_DCHPRI18_ECP_SHIFT (7U)VDMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)VDMA_DCHPRI17_CHPRI_MASK (0xFU)VDMA_DCHPRI17_CHPRI_SHIFT (0U)VDMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)VDMA_DCHPRI17_GRPPRI_MASK (0x30U)VDMA_DCHPRI17_GRPPRI_SHIFT (4U)VDMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)VDMA_DCHPRI17_DPA_MASK (0x40U)VDMA_DCHPRI17_DPA_SHIFT (6U)VDMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)VDMA_DCHPRI17_ECP_MASK (0x80U)WDMA_DCHPRI17_ECP_SHIFT (7U)WDMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)WDMA_DCHPRI16_CHPRI_MASK (0xFU)WDMA_DCHPRI16_CHPRI_SHIFT (0U)WDMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)WDMA_DCHPRI16_GRPPRI_MASK (0x30U)WDMA_DCHPRI16_GRPPRI_SHIFT (4U)WDMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)WDMA_DCHPRI16_DPA_MASK (0x40U)WDMA_DCHPRI16_DPA_SHIFT (6U)WDMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)WDMA_DCHPRI16_ECP_MASK (0x80U)WDMA_DCHPRI16_ECP_SHIFT (7U)WDMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)WDMA_DCHPRI23_CHPRI_MASK (0xFU)WDMA_DCHPRI23_CHPRI_SHIFT (0U)WDMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)WDMA_DCHPRI23_GRPPRI_MASK (0x30U)WDMA_DCHPRI23_GRPPRI_SHIFT (4U)WDMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)WDMA_DCHPRI23_DPA_MASK (0x40U)WDMA_DCHPRI23_DPA_SHIFT (6U)WDMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)WDMA_DCHPRI23_ECP_MASK (0x80U)WDMA_DCHPRI23_ECP_SHIFT (7U)WDMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)WDMA_DCHPRI22_CHPRI_MASK (0xFU)WDMA_DCHPRI22_CHPRI_SHIFT (0U)WDMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)WDMA_DCHPRI22_GRPPRI_MASK (0x30U)WDMA_DCHPRI22_GRPPRI_SHIFT (4U)WDMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)WDMA_DCHPRI22_DPA_MASK (0x40U)WDMA_DCHPRI22_DPA_SHIFT (6U)WDMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)WDMA_DCHPRI22_ECP_MASK (0x80U)WDMA_DCHPRI22_ECP_SHIFT (7U)WDMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)WDMA_DCHPRI21_CHPRI_MASK (0xFU)WDMA_DCHPRI21_CHPRI_SHIFT (0U)WDMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)WDMA_DCHPRI21_GRPPRI_MASK (0x30U)WDMA_DCHPRI21_GRPPRI_SHIFT (4U)WDMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)WDMA_DCHPRI21_DPA_MASK (0x40U)WDMA_DCHPRI21_DPA_SHIFT (6U)WDMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)WDMA_DCHPRI21_ECP_MASK (0x80U)WDMA_DCHPRI21_ECP_SHIFT (7U)WDMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)WDMA_DCHPRI20_CHPRI_MASK (0xFU)WDMA_DCHPRI20_CHPRI_SHIFT (0U)WDMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)WDMA_DCHPRI20_GRPPRI_MASK (0x30U)WDMA_DCHPRI20_GRPPRI_SHIFT (4U)WDMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)WDMA_DCHPRI20_DPA_MASK (0x40U)WDMA_DCHPRI20_DPA_SHIFT (6U)WDMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)WDMA_DCHPRI20_ECP_MASK (0x80U)WDMA_DCHPRI20_ECP_SHIFT (7U)WDMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)XDMA_DCHPRI27_CHPRI_MASK (0xFU)XDMA_DCHPRI27_CHPRI_SHIFT (0U)XDMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)XDMA_DCHPRI27_GRPPRI_MASK (0x30U)XDMA_DCHPRI27_GRPPRI_SHIFT (4U)XDMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)XDMA_DCHPRI27_DPA_MASK (0x40U)XDMA_DCHPRI27_DPA_SHIFT (6U)XDMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)XDMA_DCHPRI27_ECP_MASK (0x80U)XDMA_DCHPRI27_ECP_SHIFT (7U)XDMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)XDMA_DCHPRI26_CHPRI_MASK (0xFU)XDMA_DCHPRI26_CHPRI_SHIFT (0U)XDMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)XDMA_DCHPRI26_GRPPRI_MASK (0x30U)XDMA_DCHPRI26_GRPPRI_SHIFT (4U)XDMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)XDMA_DCHPRI26_DPA_MASK (0x40U)XDMA_DCHPRI26_DPA_SHIFT (6U)XDMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)XDMA_DCHPRI26_ECP_MASK (0x80U)XDMA_DCHPRI26_ECP_SHIFT (7U)XDMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)XDMA_DCHPRI25_CHPRI_MASK (0xFU)XDMA_DCHPRI25_CHPRI_SHIFT (0U)XDMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)XDMA_DCHPRI25_GRPPRI_MASK (0x30U)XDMA_DCHPRI25_GRPPRI_SHIFT (4U)XDMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)XDMA_DCHPRI25_DPA_MASK (0x40U)XDMA_DCHPRI25_DPA_SHIFT (6U)XDMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)XDMA_DCHPRI25_ECP_MASK (0x80U)XDMA_DCHPRI25_ECP_SHIFT (7U)XDMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)XDMA_DCHPRI24_CHPRI_MASK (0xFU)XDMA_DCHPRI24_CHPRI_SHIFT (0U)XDMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)XDMA_DCHPRI24_GRPPRI_MASK (0x30U)XDMA_DCHPRI24_GRPPRI_SHIFT (4U)XDMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)XDMA_DCHPRI24_DPA_MASK (0x40U)XDMA_DCHPRI24_DPA_SHIFT (6U)XDMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)XDMA_DCHPRI24_ECP_MASK (0x80U)XDMA_DCHPRI24_ECP_SHIFT (7U)XDMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)XDMA_DCHPRI31_CHPRI_MASK (0xFU)XDMA_DCHPRI31_CHPRI_SHIFT (0U)XDMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)XDMA_DCHPRI31_GRPPRI_MASK (0x30U)XDMA_DCHPRI31_GRPPRI_SHIFT (4U)XDMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)XDMA_DCHPRI31_DPA_MASK (0x40U)XDMA_DCHPRI31_DPA_SHIFT (6U)XDMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)XDMA_DCHPRI31_ECP_MASK (0x80U)XDMA_DCHPRI31_ECP_SHIFT (7U)XDMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)XDMA_DCHPRI30_CHPRI_MASK (0xFU)XDMA_DCHPRI30_CHPRI_SHIFT (0U)XDMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)XDMA_DCHPRI30_GRPPRI_MASK (0x30U)XDMA_DCHPRI30_GRPPRI_SHIFT (4U)XDMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)YDMA_DCHPRI30_DPA_MASK (0x40U)YDMA_DCHPRI30_DPA_SHIFT (6U)YDMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)YDMA_DCHPRI30_ECP_MASK (0x80U)YDMA_DCHPRI30_ECP_SHIFT (7U)YDMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)YDMA_DCHPRI29_CHPRI_MASK (0xFU)YDMA_DCHPRI29_CHPRI_SHIFT (0U)YDMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)YDMA_DCHPRI29_GRPPRI_MASK (0x30U)YDMA_DCHPRI29_GRPPRI_SHIFT (4U)YDMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)YDMA_DCHPRI29_DPA_MASK (0x40U)YDMA_DCHPRI29_DPA_SHIFT (6U)YDMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)YDMA_DCHPRI29_ECP_MASK (0x80U)YDMA_DCHPRI29_ECP_SHIFT (7U)YDMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)YDMA_DCHPRI28_CHPRI_MASK (0xFU)YDMA_DCHPRI28_CHPRI_SHIFT (0U)YDMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)YDMA_DCHPRI28_GRPPRI_MASK (0x30U)YDMA_DCHPRI28_GRPPRI_SHIFT (4U)YDMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)YDMA_DCHPRI28_DPA_MASK (0x40U)YDMA_DCHPRI28_DPA_SHIFT (6U)YDMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)YDMA_DCHPRI28_ECP_MASK (0x80U)YDMA_DCHPRI28_ECP_SHIFT (7U)YDMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)YDMA_DCHMID_MID_MASK (0xFU)YDMA_DCHMID_MID_SHIFT (0U)YDMA_DCHMID_MID(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_MID_SHIFT)) & DMA_DCHMID_MID_MASK)YDMA_DCHMID_PAL_MASK (0x40U)YDMA_DCHMID_PAL_SHIFT (6U)YDMA_DCHMID_PAL(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_PAL_SHIFT)) & DMA_DCHMID_PAL_MASK)YDMA_DCHMID_EMI_MASK (0x80U)YDMA_DCHMID_EMI_SHIFT (7U)YDMA_DCHMID_EMI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_EMI_SHIFT)) & DMA_DCHMID_EMI_MASK)YDMA_DCHMID_COUNT (32U)YDMA_SADDR_SADDR_MASK (0xFFFFFFFFU)YDMA_SADDR_SADDR_SHIFT (0U)YDMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)YDMA_SADDR_COUNT (32U)YDMA_SOFF_SOFF_MASK (0xFFFFU)YDMA_SOFF_SOFF_SHIFT (0U)YDMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)YDMA_SOFF_COUNT (32U)YDMA_ATTR_DSIZE_MASK (0x7U)YDMA_ATTR_DSIZE_SHIFT (0U)YDMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)YDMA_ATTR_DMOD_MASK (0xF8U)YDMA_ATTR_DMOD_SHIFT (3U)YDMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)YDMA_ATTR_SSIZE_MASK (0x700U)YDMA_ATTR_SSIZE_SHIFT (8U)ZDMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)ZDMA_ATTR_SMOD_MASK (0xF800U)ZDMA_ATTR_SMOD_SHIFT (11U)ZDMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)ZDMA_ATTR_COUNT (32U)ZDMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)ZDMA_NBYTES_MLNO_NBYTES_SHIFT (0U)ZDMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)ZDMA_NBYTES_MLNO_COUNT (32U)ZDMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)ZDMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)ZDMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)ZDMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)ZDMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)ZDMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)ZDMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)ZDMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)ZDMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)ZDMA_NBYTES_MLOFFNO_COUNT (32U)ZDMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)ZDMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)ZDMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)ZDMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)ZDMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)ZDMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)ZDMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)ZDMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)ZDMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)ZDMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)ZDMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)ZDMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)ZDMA_NBYTES_MLOFFYES_COUNT (32U)ZDMA_SLAST_SLAST_MASK (0xFFFFFFFFU)ZDMA_SLAST_SLAST_SHIFT (0U)ZDMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)ZDMA_SLAST_COUNT (32U)ZDMA_DADDR_DADDR_MASK (0xFFFFFFFFU)ZDMA_DADDR_DADDR_SHIFT (0U)ZDMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)ZDMA_DADDR_COUNT (32U)ZDMA_DOFF_DOFF_MASK (0xFFFFU)ZDMA_DOFF_DOFF_SHIFT (0U)ZDMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)ZDMA_DOFF_COUNT (32U)ZDMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)ZDMA_CITER_ELINKNO_CITER_SHIFT (0U)ZDMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)ZDMA_CITER_ELINKNO_ELINK_MASK (0x8000U)ZDMA_CITER_ELINKNO_ELINK_SHIFT (15U)ZDMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)ZDMA_CITER_ELINKNO_COUNT (32U)[DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)[DMA_CITER_ELINKYES_CITER_SHIFT (0U)[DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)[DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)[DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)[DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)[DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)[DMA_CITER_ELINKYES_ELINK_SHIFT (15U)[DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)[DMA_CITER_ELINKYES_COUNT (32U)[DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)[DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)[DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)[DMA_DLAST_SGA_COUNT (32U)[DMA_CSR_START_MASK (0x1U)[DMA_CSR_START_SHIFT (0U)[DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)[DMA_CSR_INTMAJOR_MASK (0x2U)[DMA_CSR_INTMAJOR_SHIFT (1U)[DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)[DMA_CSR_INTHALF_MASK (0x4U)[DMA_CSR_INTHALF_SHIFT (2U)[DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)[DMA_CSR_DREQ_MASK (0x8U)[DMA_CSR_DREQ_SHIFT (3U)[DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)[DMA_CSR_ESG_MASK (0x10U)[DMA_CSR_ESG_SHIFT (4U)[DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)[DMA_CSR_MAJORELINK_MASK (0x20U)[DMA_CSR_MAJORELINK_SHIFT (5U)[DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)[DMA_CSR_ACTIVE_MASK (0x40U)[DMA_CSR_ACTIVE_SHIFT (6U)[DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)[DMA_CSR_DONE_MASK (0x80U)[DMA_CSR_DONE_SHIFT (7U)[DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)[DMA_CSR_MAJORLINKCH_MASK (0x1F00U)[DMA_CSR_MAJORLINKCH_SHIFT (8U)[DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)[DMA_CSR_BWC_MASK (0xC000U)[DMA_CSR_BWC_SHIFT (14U)[DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)[DMA_CSR_COUNT (32U)[DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)[DMA_BITER_ELINKNO_BITER_SHIFT (0U)[DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)[DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)[DMA_BITER_ELINKNO_ELINK_SHIFT (15U)[DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)[DMA_BITER_ELINKNO_COUNT (32U)[DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)[DMA_BITER_ELINKYES_BITER_SHIFT (0U)[DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)[DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)[DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)[DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)[DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)[DMA_BITER_ELINKYES_ELINK_SHIFT (15U)\DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)\DMA_BITER_ELINKYES_COUNT (32U)\DMA0_BASE (0x400E8000u)\DMA0 ((DMA_Type *)DMA0_BASE)\DMA_BASE_ADDRS { DMA0_BASE }\DMA_BASE_PTRS { DMA0 }\DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }\DMA_ERROR_IRQS { DMA_ERROR_IRQn }\DMAMUX_CHCFG_SOURCE_MASK (0x7FU)\DMAMUX_CHCFG_SOURCE_SHIFT (0U)\DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)\DMAMUX_CHCFG_A_ON_MASK (0x20000000U)\DMAMUX_CHCFG_A_ON_SHIFT (29U)\DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)\DMAMUX_CHCFG_TRIG_MASK (0x40000000U)\DMAMUX_CHCFG_TRIG_SHIFT (30U)\DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)\DMAMUX_CHCFG_ENBL_MASK (0x80000000U)\DMAMUX_CHCFG_ENBL_SHIFT (31U)\DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)\DMAMUX_CHCFG_COUNT (32U)\DMAMUX_BASE (0x400EC000u)\DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)\DMAMUX_BASE_ADDRS { DMAMUX_BASE }\DMAMUX_BASE_PTRS { DMAMUX }]ENC_CTRL_CMPIE_MASK (0x1U)]ENC_CTRL_CMPIE_SHIFT (0U)]ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)]ENC_CTRL_CMPIRQ_MASK (0x2U)]ENC_CTRL_CMPIRQ_SHIFT (1U)]ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)]ENC_CTRL_WDE_MASK (0x4U)]ENC_CTRL_WDE_SHIFT (2U)]ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)]ENC_CTRL_DIE_MASK (0x8U)]ENC_CTRL_DIE_SHIFT (3U)]ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)]ENC_CTRL_DIRQ_MASK (0x10U)]ENC_CTRL_DIRQ_SHIFT (4U)]ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)]ENC_CTRL_XNE_MASK (0x20U)]ENC_CTRL_XNE_SHIFT (5U)]ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)]ENC_CTRL_XIP_MASK (0x40U)]ENC_CTRL_XIP_SHIFT (6U)]ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)]ENC_CTRL_XIE_MASK (0x80U)]ENC_CTRL_XIE_SHIFT (7U)]ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)]ENC_CTRL_XIRQ_MASK (0x100U)]ENC_CTRL_XIRQ_SHIFT (8U)]ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)]ENC_CTRL_PH1_MASK (0x200U)]ENC_CTRL_PH1_SHIFT (9U)]ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)]ENC_CTRL_REV_MASK (0x400U)]ENC_CTRL_REV_SHIFT (10U)]ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)]ENC_CTRL_SWIP_MASK (0x800U)]ENC_CTRL_SWIP_SHIFT (11U)]ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)]ENC_CTRL_HNE_MASK (0x1000U)]ENC_CTRL_HNE_SHIFT (12U)]ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)]ENC_CTRL_HIP_MASK (0x2000U)]ENC_CTRL_HIP_SHIFT (13U)]ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)]ENC_CTRL_HIE_MASK (0x4000U)]ENC_CTRL_HIE_SHIFT (14U)^ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)^ENC_CTRL_HIRQ_MASK (0x8000U)^ENC_CTRL_HIRQ_SHIFT (15U)^ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)^ENC_FILT_FILT_PER_MASK (0xFFU)^ENC_FILT_FILT_PER_SHIFT (0U)^ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)^ENC_FILT_FILT_CNT_MASK (0x700U)^ENC_FILT_FILT_CNT_SHIFT (8U)^ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)^ENC_WTR_WDOG_MASK (0xFFFFU)^ENC_WTR_WDOG_SHIFT (0U)^ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)^ENC_POSD_POSD_MASK (0xFFFFU)^ENC_POSD_POSD_SHIFT (0U)^ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)^ENC_POSDH_POSDH_MASK (0xFFFFU)^ENC_POSDH_POSDH_SHIFT (0U)^ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)^ENC_REV_REV_MASK (0xFFFFU)^ENC_REV_REV_SHIFT (0U)^ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)^ENC_REVH_REVH_MASK (0xFFFFU)^ENC_REVH_REVH_SHIFT (0U)^ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)^ENC_UPOS_POS_MASK (0xFFFFU)^ENC_UPOS_POS_SHIFT (0U)^ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)^ENC_LPOS_POS_MASK (0xFFFFU)^ENC_LPOS_POS_SHIFT (0U)^ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)^ENC_UPOSH_POSH_MASK (0xFFFFU)^ENC_UPOSH_POSH_SHIFT (0U)^ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)^ENC_LPOSH_POSH_MASK (0xFFFFU)^ENC_LPOSH_POSH_SHIFT (0U)^ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)^ENC_UINIT_INIT_MASK (0xFFFFU)^ENC_UINIT_INIT_SHIFT (0U)^ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)^ENC_LINIT_INIT_MASK (0xFFFFU)^ENC_LINIT_INIT_SHIFT (0U)^ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)^ENC_IMR_HOME_MASK (0x1U)^ENC_IMR_HOME_SHIFT (0U)^ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)^ENC_IMR_INDEX_MASK (0x2U)^ENC_IMR_INDEX_SHIFT (1U)^ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)^ENC_IMR_PHB_MASK (0x4U)^ENC_IMR_PHB_SHIFT (2U)^ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)^ENC_IMR_PHA_MASK (0x8U)^ENC_IMR_PHA_SHIFT (3U)^ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)^ENC_IMR_FHOM_MASK (0x10U)^ENC_IMR_FHOM_SHIFT (4U)^ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)^ENC_IMR_FIND_MASK (0x20U)^ENC_IMR_FIND_SHIFT (5U)^ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)^ENC_IMR_FPHB_MASK (0x40U)^ENC_IMR_FPHB_SHIFT (6U)^ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)^ENC_IMR_FPHA_MASK (0x80U)^ENC_IMR_FPHA_SHIFT (7U)^ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)_ENC_TST_TEST_COUNT_MASK (0xFFU)_ENC_TST_TEST_COUNT_SHIFT (0U)_ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)_ENC_TST_TEST_PERIOD_MASK (0x1F00U)_ENC_TST_TEST_PERIOD_SHIFT (8U)_ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)_ENC_TST_QDN_MASK (0x2000U)_ENC_TST_QDN_SHIFT (13U)_ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)_ENC_TST_TCE_MASK (0x4000U)_ENC_TST_TCE_SHIFT (14U)_ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)_ENC_TST_TEN_MASK (0x8000U)_ENC_TST_TEN_SHIFT (15U)_ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)_ENC_CTRL2_UPDHLD_MASK (0x1U)_ENC_CTRL2_UPDHLD_SHIFT (0U)_ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)_ENC_CTRL2_UPDPOS_MASK (0x2U)_ENC_CTRL2_UPDPOS_SHIFT (1U)_ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)_ENC_CTRL2_MOD_MASK (0x4U)_ENC_CTRL2_MOD_SHIFT (2U)_ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)_ENC_CTRL2_DIR_MASK (0x8U)_ENC_CTRL2_DIR_SHIFT (3U)_ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)_ENC_CTRL2_RUIE_MASK (0x10U)_ENC_CTRL2_RUIE_SHIFT (4U)_ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)_ENC_CTRL2_RUIRQ_MASK (0x20U)_ENC_CTRL2_RUIRQ_SHIFT (5U)_ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)_ENC_CTRL2_ROIE_MASK (0x40U)_ENC_CTRL2_ROIE_SHIFT (6U)_ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)_ENC_CTRL2_ROIRQ_MASK (0x80U)_ENC_CTRL2_ROIRQ_SHIFT (7U)_ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)_ENC_CTRL2_REVMOD_MASK (0x100U)_ENC_CTRL2_REVMOD_SHIFT (8U)_ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)_ENC_CTRL2_OUTCTL_MASK (0x200U)_ENC_CTRL2_OUTCTL_SHIFT (9U)_ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)_ENC_CTRL2_SABIE_MASK (0x400U)_ENC_CTRL2_SABIE_SHIFT (10U)_ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)_ENC_CTRL2_SABIRQ_MASK (0x800U)_ENC_CTRL2_SABIRQ_SHIFT (11U)_ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)_ENC_UMOD_MOD_MASK (0xFFFFU)_ENC_UMOD_MOD_SHIFT (0U)_ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)_ENC_LMOD_MOD_MASK (0xFFFFU)`ENC_LMOD_MOD_SHIFT (0U)`ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)`ENC_UCOMP_COMP_MASK (0xFFFFU)`ENC_UCOMP_COMP_SHIFT (0U)`ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)`ENC_LCOMP_COMP_MASK (0xFFFFU)`ENC_LCOMP_COMP_SHIFT (0U)`ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)`ENC1_BASE (0x403C8000u)`ENC1 ((ENC_Type *)ENC1_BASE)`ENC_BASE_ADDRS { 0u, ENC1_BASE }`ENC_BASE_PTRS { (ENC_Type *)0u, ENC1 }`ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn }`ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn }`ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn }`ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn }`ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn }`EWM_CTRL_EWMEN_MASK (0x1U)`EWM_CTRL_EWMEN_SHIFT (0U)`EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)`EWM_CTRL_ASSIN_MASK (0x2U)`EWM_CTRL_ASSIN_SHIFT (1U)`EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)`EWM_CTRL_INEN_MASK (0x4U)`EWM_CTRL_INEN_SHIFT (2U)`EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)`EWM_CTRL_INTEN_MASK (0x8U)`EWM_CTRL_INTEN_SHIFT (3U)`EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)`EWM_SERV_SERVICE_MASK (0xFFU)`EWM_SERV_SERVICE_SHIFT (0U)`EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)`EWM_CMPL_COMPAREL_MASK (0xFFU)`EWM_CMPL_COMPAREL_SHIFT (0U)`EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)`EWM_CMPH_COMPAREH_MASK (0xFFU)`EWM_CMPH_COMPAREH_SHIFT (0U)`EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)`EWM_CLKCTRL_CLKSEL_MASK (0x3U)`EWM_CLKCTRL_CLKSEL_SHIFT (0U)`EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)`EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)`EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)`EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)aEWM_BASE (0x400B4000u)aEWM ((EWM_Type *)EWM_BASE)aEWM_BASE_ADDRS { EWM_BASE }aEWM_BASE_PTRS { EWM }aEWM_IRQS { EWM_IRQn }aFLEXIO_VERID_FEATURE_MASK (0xFFFFU)aFLEXIO_VERID_FEATURE_SHIFT (0U)aFLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)aFLEXIO_VERID_MINOR_MASK (0xFF0000U)aFLEXIO_VERID_MINOR_SHIFT (16U)aFLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)aFLEXIO_VERID_MAJOR_MASK (0xFF000000U)aFLEXIO_VERID_MAJOR_SHIFT (24U)aFLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)aFLEXIO_PARAM_SHIFTER_MASK (0xFFU)aFLEXIO_PARAM_SHIFTER_SHIFT (0U)aFLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)aFLEXIO_PARAM_TIMER_MASK (0xFF00U)aFLEXIO_PARAM_TIMER_SHIFT (8U)aFLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)aFLEXIO_PARAM_PIN_MASK (0xFF0000U)aFLEXIO_PARAM_PIN_SHIFT (16U)aFLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)aFLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)aFLEXIO_PARAM_TRIGGER_SHIFT (24U)aFLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)aFLEXIO_CTRL_FLEXEN_MASK (0x1U)aFLEXIO_CTRL_FLEXEN_SHIFT (0U)aFLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)aFLEXIO_CTRL_SWRST_MASK (0x2U)aFLEXIO_CTRL_SWRST_SHIFT (1U)bFLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)bFLEXIO_CTRL_FASTACC_MASK (0x4U)bFLEXIO_CTRL_FASTACC_SHIFT (2U)bFLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)bFLEXIO_CTRL_DBGE_MASK (0x40000000U)bFLEXIO_CTRL_DBGE_SHIFT (30U)bFLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)bFLEXIO_CTRL_DOZEN_MASK (0x80000000U)bFLEXIO_CTRL_DOZEN_SHIFT (31U)bFLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)bFLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)bFLEXIO_PIN_PDI_SHIFT (0U)bFLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)bFLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)bFLEXIO_SHIFTSTAT_SSF_SHIFT (0U)bFLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)bFLEXIO_SHIFTERR_SEF_MASK (0xFFU)bFLEXIO_SHIFTERR_SEF_SHIFT (0U)bFLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)bFLEXIO_TIMSTAT_TSF_MASK (0xFFU)bFLEXIO_TIMSTAT_TSF_SHIFT (0U)bFLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)bFLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)bFLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)bFLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)bFLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)bFLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)bFLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)bFLEXIO_TIMIEN_TEIE_MASK (0xFFU)bFLEXIO_TIMIEN_TEIE_SHIFT (0U)bFLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)bFLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)bFLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)bFLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)bFLEXIO_SHIFTSTATE_STATE_MASK (0x7U)bFLEXIO_SHIFTSTATE_STATE_SHIFT (0U)bFLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)bFLEXIO_SHIFTCTL_SMOD_MASK (0x7U)bFLEXIO_SHIFTCTL_SMOD_SHIFT (0U)bFLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)bFLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)bFLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)bFLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)bFLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)bFLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)bFLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)bFLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)bFLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)bFLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)bFLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)bFLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)bFLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)cFLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)cFLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)cFLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)cFLEXIO_SHIFTCTL_COUNT (8U)cFLEXIO_SHIFTCFG_SSTART_MASK (0x3U)cFLEXIO_SHIFTCFG_SSTART_SHIFT (0U)cFLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)cFLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)cFLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)cFLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)cFLEXIO_SHIFTCFG_INSRC_MASK (0x100U)cFLEXIO_SHIFTCFG_INSRC_SHIFT (8U)cFLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)cFLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)cFLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)cFLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)cFLEXIO_SHIFTCFG_COUNT (8U)cFLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)cFLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)cFLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)cFLEXIO_SHIFTBUF_COUNT (8U)cFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)cFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)cFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)cFLEXIO_SHIFTBUFBIS_COUNT (8U)cFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)cFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)cFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)cFLEXIO_SHIFTBUFBYS_COUNT (8U)cFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)cFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)cFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)cFLEXIO_SHIFTBUFBBS_COUNT (8U)cFLEXIO_TIMCTL_TIMOD_MASK (0x3U)cFLEXIO_TIMCTL_TIMOD_SHIFT (0U)cFLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)cFLEXIO_TIMCTL_PINPOL_MASK (0x80U)cFLEXIO_TIMCTL_PINPOL_SHIFT (7U)cFLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)cFLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)cFLEXIO_TIMCTL_PINSEL_SHIFT (8U)cFLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)cFLEXIO_TIMCTL_PINCFG_MASK (0x30000U)cFLEXIO_TIMCTL_PINCFG_SHIFT (16U)cFLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)cFLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)cFLEXIO_TIMCTL_TRGSRC_SHIFT (22U)cFLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)cFLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)cFLEXIO_TIMCTL_TRGPOL_SHIFT (23U)cFLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)cFLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)dFLEXIO_TIMCTL_TRGSEL_SHIFT (24U)dFLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)dFLEXIO_TIMCTL_COUNT (8U)dFLEXIO_TIMCFG_TSTART_MASK (0x2U)dFLEXIO_TIMCFG_TSTART_SHIFT (1U)dFLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)dFLEXIO_TIMCFG_TSTOP_MASK (0x30U)dFLEXIO_TIMCFG_TSTOP_SHIFT (4U)dFLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)dFLEXIO_TIMCFG_TIMENA_MASK (0x700U)dFLEXIO_TIMCFG_TIMENA_SHIFT (8U)dFLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)dFLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)dFLEXIO_TIMCFG_TIMDIS_SHIFT (12U)dFLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)dFLEXIO_TIMCFG_TIMRST_MASK (0x70000U)dFLEXIO_TIMCFG_TIMRST_SHIFT (16U)dFLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)dFLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)dFLEXIO_TIMCFG_TIMDEC_SHIFT (20U)dFLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)dFLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)dFLEXIO_TIMCFG_TIMOUT_SHIFT (24U)dFLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)dFLEXIO_TIMCFG_COUNT (8U)dFLEXIO_TIMCMP_CMP_MASK (0xFFFFU)dFLEXIO_TIMCMP_CMP_SHIFT (0U)dFLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)dFLEXIO_TIMCMP_COUNT (8U)dFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)dFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)dFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)dFLEXIO_SHIFTBUFNBS_COUNT (8U)dFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)dFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)dFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)dFLEXIO_SHIFTBUFHWS_COUNT (8U)dFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)dFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)dFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)dFLEXIO_SHIFTBUFNIS_COUNT (8U)eFLEXIO1_BASE (0x401AC000u)eFLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)eFLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE }eFLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1 }eFLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn }eFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)eFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)eFLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)eFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)eFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)eFLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)eFLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)eFLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)eFLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)eFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)eFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)eFLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)eFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)eFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)eFLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)eFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)eFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)eFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)eFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)eFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)eFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)eFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)eFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)eFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)eFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)eFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)eFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)eFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)eFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)fFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)fFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)fFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)fFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)fFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)fFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)fFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)fFLEXRAM_BASE (0x400B0000u)fFLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)fFLEXRAM_BASE_ADDRS { FLEXRAM_BASE }fFLEXRAM_BASE_PTRS { FLEXRAM }fFLEXRAM_IRQS { FLEXRAM_IRQn }fFLEXSPI_MCR0_SWRESET_MASK (0x1U)fFLEXSPI_MCR0_SWRESET_SHIFT (0U)fFLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)fFLEXSPI_MCR0_MDIS_MASK (0x2U)fFLEXSPI_MCR0_MDIS_SHIFT (1U)fFLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)fFLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)fFLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)fFLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)fFLEXSPI_MCR0_ARDFEN_MASK (0x40U)fFLEXSPI_MCR0_ARDFEN_SHIFT (6U)fFLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)fFLEXSPI_MCR0_ATDFEN_MASK (0x80U)fFLEXSPI_MCR0_ATDFEN_SHIFT (7U)fFLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)gFLEXSPI_MCR0_HSEN_MASK (0x800U)gFLEXSPI_MCR0_HSEN_SHIFT (11U)gFLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)gFLEXSPI_MCR0_DOZEEN_MASK (0x1000U)gFLEXSPI_MCR0_DOZEEN_SHIFT (12U)gFLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)gFLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)gFLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)gFLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)gFLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)gFLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)gFLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)gFLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)gFLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)gFLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)gFLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)gFLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)gFLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)gFLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)gFLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)gFLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)gFLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)gFLEXSPI_MCR1_SEQWAIT_SHIFT (16U)gFLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)gFLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)gFLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)gFLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)gFLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)gFLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)gFLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)gFLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)gFLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)gFLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)gFLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)gFLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)gFLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)gFLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)gFLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)gFLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)gFLEXSPI_AHBCR_APAREN_MASK (0x1U)gFLEXSPI_AHBCR_APAREN_SHIFT (0U)gFLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)gFLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)gFLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)gFLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)gFLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)gFLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)gFLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)gFLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)gFLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)gFLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)gFLEXSPI_AHBCR_READADDROPT_MASK (0x40U)gFLEXSPI_AHBCR_READADDROPT_SHIFT (6U)gFLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)hFLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)hFLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)hFLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)hFLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)hFLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)hFLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)hFLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)hFLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)hFLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)hFLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)hFLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)hFLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)hFLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)hFLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)hFLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)hFLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)hFLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)hFLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)hFLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)hFLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)hFLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)hFLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)hFLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)hFLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)hFLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)hFLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)hFLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)hFLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)hFLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)hFLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)hFLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)hFLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)hFLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)hFLEXSPI_INTR_IPCMDDONE_MASK (0x1U)hFLEXSPI_INTR_IPCMDDONE_SHIFT (0U)hFLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)hFLEXSPI_INTR_IPCMDGE_MASK (0x2U)hFLEXSPI_INTR_IPCMDGE_SHIFT (1U)hFLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)hFLEXSPI_INTR_AHBCMDGE_MASK (0x4U)hFLEXSPI_INTR_AHBCMDGE_SHIFT (2U)hFLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)hFLEXSPI_INTR_IPCMDERR_MASK (0x8U)hFLEXSPI_INTR_IPCMDERR_SHIFT (3U)hFLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)hFLEXSPI_INTR_AHBCMDERR_MASK (0x10U)hFLEXSPI_INTR_AHBCMDERR_SHIFT (4U)hFLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)hFLEXSPI_INTR_IPRXWA_MASK (0x20U)hFLEXSPI_INTR_IPRXWA_SHIFT (5U)hFLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)hFLEXSPI_INTR_IPTXWE_MASK (0x40U)hFLEXSPI_INTR_IPTXWE_SHIFT (6U)hFLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)hFLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)hFLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)hFLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)hFLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)hFLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)hFLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)hFLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)hFLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)hFLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)hFLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)hFLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)hFLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)hFLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)hFLEXSPI_LUTKEY_KEY_SHIFT (0U)hFLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)hFLEXSPI_LUTCR_LOCK_MASK (0x1U)hFLEXSPI_LUTCR_LOCK_SHIFT (0U)hFLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)hFLEXSPI_LUTCR_UNLOCK_MASK (0x2U)hFLEXSPI_LUTCR_UNLOCK_SHIFT (1U)hFLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)hFLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)hFLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)hFLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)hFLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)hFLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)hFLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)hFLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)hFLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)hFLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)hFLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)hFLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)hFLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)hFLEXSPI_AHBRXBUFCR0_COUNT (4U)hFLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)hFLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)hFLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)hFLEXSPI_FLSHCR0_COUNT (4U)hFLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)hFLEXSPI_FLSHCR1_TCSS_SHIFT (0U)hFLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)hFLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)hFLEXSPI_FLSHCR1_TCSH_SHIFT (5U)hFLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)hFLEXSPI_FLSHCR1_WA_MASK (0x400U)hFLEXSPI_FLSHCR1_WA_SHIFT (10U)iFLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)iFLEXSPI_FLSHCR1_CAS_MASK (0x7800U)iFLEXSPI_FLSHCR1_CAS_SHIFT (11U)iFLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)iFLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)iFLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)iFLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)iFLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)iFLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)iFLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)iFLEXSPI_FLSHCR1_COUNT (4U)iFLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)iFLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)iFLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)iFLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)iFLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)iFLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)iFLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)iFLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)iFLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)iFLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)iFLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)iFLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)iFLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)iFLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)iFLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)iFLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)iFLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)iFLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)iFLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)iFLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)iFLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)iFLEXSPI_FLSHCR2_COUNT (4U)iFLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)iFLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)iFLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)iFLEXSPI_FLSHCR4_WMENA_MASK (0x4U)iFLEXSPI_FLSHCR4_WMENA_SHIFT (2U)iFLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)iFLEXSPI_FLSHCR4_WMENB_MASK (0x8U)iFLEXSPI_FLSHCR4_WMENB_SHIFT (3U)iFLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)iFLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)iFLEXSPI_IPCR0_SFAR_SHIFT (0U)iFLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)iFLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)iFLEXSPI_IPCR1_IDATSZ_SHIFT (0U)iFLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)iFLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)iFLEXSPI_IPCR1_ISEQID_SHIFT (16U)iFLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)iFLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)iFLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)iFLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)iFLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)iFLEXSPI_IPCR1_IPAREN_SHIFT (31U)iFLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)iFLEXSPI_IPCMD_TRG_MASK (0x1U)iFLEXSPI_IPCMD_TRG_SHIFT (0U)iFLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)iFLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)iFLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)iFLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)iFLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)iFLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)jFLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)jFLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)jFLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)jFLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)jFLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)jFLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)jFLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)jFLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)jFLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)jFLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)jFLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)jFLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)jFLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)jFLEXSPI_DLLCR_DLLEN_MASK (0x1U)jFLEXSPI_DLLCR_DLLEN_SHIFT (0U)jFLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)jFLEXSPI_DLLCR_DLLRESET_MASK (0x2U)jFLEXSPI_DLLCR_DLLRESET_SHIFT (1U)jFLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)jFLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)jFLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)jFLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)jFLEXSPI_DLLCR_OVRDEN_MASK (0x100U)jFLEXSPI_DLLCR_OVRDEN_SHIFT (8U)jFLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)jFLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)jFLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)jFLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)jFLEXSPI_DLLCR_COUNT (2U)jFLEXSPI_STS0_SEQIDLE_MASK (0x1U)jFLEXSPI_STS0_SEQIDLE_SHIFT (0U)jFLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)jFLEXSPI_STS0_ARBIDLE_MASK (0x2U)jFLEXSPI_STS0_ARBIDLE_SHIFT (1U)jFLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)jFLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)jFLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)jFLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)jFLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)jFLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)jFLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)jFLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)jFLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)jFLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)jFLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)jFLEXSPI_STS1_IPCMDERRID_SHIFT (16U)jFLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)jFLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)jFLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)jFLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)jFLEXSPI_STS2_ASLVLOCK_MASK (0x1U)jFLEXSPI_STS2_ASLVLOCK_SHIFT (0U)jFLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)jFLEXSPI_STS2_AREFLOCK_MASK (0x2U)jFLEXSPI_STS2_AREFLOCK_SHIFT (1U)jFLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)jFLEXSPI_STS2_ASLVSEL_MASK (0xFCU)jFLEXSPI_STS2_ASLVSEL_SHIFT (2U)jFLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)jFLEXSPI_STS2_AREFSEL_MASK (0x3F00U)jFLEXSPI_STS2_AREFSEL_SHIFT (8U)jFLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)jFLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)jFLEXSPI_STS2_BSLVLOCK_SHIFT (16U)jFLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)jFLEXSPI_STS2_BREFLOCK_MASK (0x20000U)jFLEXSPI_STS2_BREFLOCK_SHIFT (17U)jFLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)jFLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)jFLEXSPI_STS2_BSLVSEL_SHIFT (18U)jFLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)jFLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)kFLEXSPI_STS2_BREFSEL_SHIFT (24U)kFLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)kFLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)kFLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)kFLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)kFLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)kFLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)kFLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)kFLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)kFLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)kFLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)kFLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)kFLEXSPI_IPRXFSTS_FILL_SHIFT (0U)kFLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)kFLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)kFLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)kFLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)kFLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)kFLEXSPI_IPTXFSTS_FILL_SHIFT (0U)kFLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)kFLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)kFLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)kFLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)kFLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)kFLEXSPI_RFDR_RXDATA_SHIFT (0U)kFLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)kFLEXSPI_RFDR_COUNT (32U)kFLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)kFLEXSPI_TFDR_TXDATA_SHIFT (0U)kFLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)kFLEXSPI_TFDR_COUNT (32U)kFLEXSPI_LUT_OPERAND0_MASK (0xFFU)kFLEXSPI_LUT_OPERAND0_SHIFT (0U)kFLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)kFLEXSPI_LUT_NUM_PADS0_MASK (0x300U)kFLEXSPI_LUT_NUM_PADS0_SHIFT (8U)kFLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)kFLEXSPI_LUT_OPCODE0_MASK (0xFC00U)kFLEXSPI_LUT_OPCODE0_SHIFT (10U)kFLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)kFLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)kFLEXSPI_LUT_OPERAND1_SHIFT (16U)kFLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)kFLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)kFLEXSPI_LUT_NUM_PADS1_SHIFT (24U)kFLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)kFLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)kFLEXSPI_LUT_OPCODE1_SHIFT (26U)kFLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)kFLEXSPI_LUT_COUNT (64U)kFLEXSPI_BASE (0x402A8000u)kFLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)kFLEXSPI_BASE_ADDRS { FLEXSPI_BASE }kFLEXSPI_BASE_PTRS { FLEXSPI }kFLEXSPI_IRQS { FLEXSPI_IRQn }kFlexSPI_AMBA_BASE (0x60000000U)kFlexSPI_ASFM_BASE (0x60000000U)kFlexSPI_ARDF_BASE (0x7FC00000U)kFlexSPI_ATDF_BASE (0x7F800000U)lGPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)lGPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)lGPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)lGPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)lGPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)lGPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)lGPC_CNTR_PDRAM0_PGE_MASK (0x400000U)lGPC_CNTR_PDRAM0_PGE_SHIFT (22U)lGPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)lGPC_IMR_IMR1_MASK (0xFFFFFFFFU)lGPC_IMR_IMR1_SHIFT (0U)lGPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)lGPC_IMR_IMR2_MASK (0xFFFFFFFFU)lGPC_IMR_IMR2_SHIFT (0U)lGPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)lGPC_IMR_IMR3_MASK (0xFFFFFFFFU)lGPC_IMR_IMR3_SHIFT (0U)lGPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)lGPC_IMR_IMR4_MASK (0xFFFFFFFFU)lGPC_IMR_IMR4_SHIFT (0U)lGPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)lGPC_IMR_COUNT (4U)lGPC_ISR_ISR1_MASK (0xFFFFFFFFU)lGPC_ISR_ISR1_SHIFT (0U)lGPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)lGPC_ISR_ISR2_MASK (0xFFFFFFFFU)lGPC_ISR_ISR2_SHIFT (0U)lGPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)lGPC_ISR_ISR3_MASK (0xFFFFFFFFU)lGPC_ISR_ISR3_SHIFT (0U)lGPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)lGPC_ISR_ISR4_MASK (0xFFFFFFFFU)lGPC_ISR_ISR4_SHIFT (0U)lGPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)lGPC_ISR_COUNT (4U)lGPC_IMR5_IMR5_MASK (0xFFFFFFFFU)lGPC_IMR5_IMR5_SHIFT (0U)lGPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)lGPC_ISR5_ISR4_MASK (0xFFFFFFFFU)lGPC_ISR5_ISR4_SHIFT (0U)lGPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)lGPC_BASE (0x400F4000u)lGPC ((GPC_Type *)GPC_BASE)lGPC_BASE_ADDRS { GPC_BASE }lGPC_BASE_PTRS { GPC }lGPC_IRQS { GPC_IRQn }mGPIO_DR_DR_MASK (0xFFFFFFFFU)mGPIO_DR_DR_SHIFT (0U)mGPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)mGPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)mGPIO_GDIR_GDIR_SHIFT (0U)mGPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)mGPIO_PSR_PSR_MASK (0xFFFFFFFFU)mGPIO_PSR_PSR_SHIFT (0U)mGPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)mGPIO_ICR1_ICR0_MASK (0x3U)mGPIO_ICR1_ICR0_SHIFT (0U)mGPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)mGPIO_ICR1_ICR1_MASK (0xCU)mGPIO_ICR1_ICR1_SHIFT (2U)mGPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)mGPIO_ICR1_ICR2_MASK (0x30U)mGPIO_ICR1_ICR2_SHIFT (4U)mGPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)mGPIO_ICR1_ICR3_MASK (0xC0U)mGPIO_ICR1_ICR3_SHIFT (6U)mGPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)mGPIO_ICR1_ICR4_MASK (0x300U)mGPIO_ICR1_ICR4_SHIFT (8U)mGPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)mGPIO_ICR1_ICR5_MASK (0xC00U)mGPIO_ICR1_ICR5_SHIFT (10U)mGPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)mGPIO_ICR1_ICR6_MASK (0x3000U)mGPIO_ICR1_ICR6_SHIFT (12U)mGPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)mGPIO_ICR1_ICR7_MASK (0xC000U)mGPIO_ICR1_ICR7_SHIFT (14U)mGPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)mGPIO_ICR1_ICR8_MASK (0x30000U)mGPIO_ICR1_ICR8_SHIFT (16U)mGPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)mGPIO_ICR1_ICR9_MASK (0xC0000U)mGPIO_ICR1_ICR9_SHIFT (18U)nGPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)nGPIO_ICR1_ICR10_MASK (0x300000U)nGPIO_ICR1_ICR10_SHIFT (20U)nGPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)nGPIO_ICR1_ICR11_MASK (0xC00000U)nGPIO_ICR1_ICR11_SHIFT (22U)nGPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)nGPIO_ICR1_ICR12_MASK (0x3000000U)nGPIO_ICR1_ICR12_SHIFT (24U)nGPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)nGPIO_ICR1_ICR13_MASK (0xC000000U)nGPIO_ICR1_ICR13_SHIFT (26U)nGPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)nGPIO_ICR1_ICR14_MASK (0x30000000U)nGPIO_ICR1_ICR14_SHIFT (28U)nGPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)nGPIO_ICR1_ICR15_MASK (0xC0000000U)nGPIO_ICR1_ICR15_SHIFT (30U)nGPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)nGPIO_ICR2_ICR16_MASK (0x3U)nGPIO_ICR2_ICR16_SHIFT (0U)nGPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)nGPIO_ICR2_ICR17_MASK (0xCU)nGPIO_ICR2_ICR17_SHIFT (2U)nGPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)nGPIO_ICR2_ICR18_MASK (0x30U)nGPIO_ICR2_ICR18_SHIFT (4U)nGPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)nGPIO_ICR2_ICR19_MASK (0xC0U)nGPIO_ICR2_ICR19_SHIFT (6U)nGPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)nGPIO_ICR2_ICR20_MASK (0x300U)nGPIO_ICR2_ICR20_SHIFT (8U)nGPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)nGPIO_ICR2_ICR21_MASK (0xC00U)nGPIO_ICR2_ICR21_SHIFT (10U)nGPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)nGPIO_ICR2_ICR22_MASK (0x3000U)nGPIO_ICR2_ICR22_SHIFT (12U)nGPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)nGPIO_ICR2_ICR23_MASK (0xC000U)oGPIO_ICR2_ICR23_SHIFT (14U)oGPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)oGPIO_ICR2_ICR24_MASK (0x30000U)oGPIO_ICR2_ICR24_SHIFT (16U)oGPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)oGPIO_ICR2_ICR25_MASK (0xC0000U)oGPIO_ICR2_ICR25_SHIFT (18U)oGPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)oGPIO_ICR2_ICR26_MASK (0x300000U)oGPIO_ICR2_ICR26_SHIFT (20U)oGPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)oGPIO_ICR2_ICR27_MASK (0xC00000U)oGPIO_ICR2_ICR27_SHIFT (22U)oGPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)oGPIO_ICR2_ICR28_MASK (0x3000000U)oGPIO_ICR2_ICR28_SHIFT (24U)oGPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)oGPIO_ICR2_ICR29_MASK (0xC000000U)oGPIO_ICR2_ICR29_SHIFT (26U)oGPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)oGPIO_ICR2_ICR30_MASK (0x30000000U)oGPIO_ICR2_ICR30_SHIFT (28U)oGPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)oGPIO_ICR2_ICR31_MASK (0xC0000000U)oGPIO_ICR2_ICR31_SHIFT (30U)oGPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)oGPIO_IMR_IMR_MASK (0xFFFFFFFFU)oGPIO_IMR_IMR_SHIFT (0U)oGPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)oGPIO_ISR_ISR_MASK (0xFFFFFFFFU)oGPIO_ISR_ISR_SHIFT (0U)oGPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)oGPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)oGPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)oGPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)oGPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)oGPIO_DR_SET_DR_SET_SHIFT (0U)oGPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)oGPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)oGPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)oGPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)oGPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)oGPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)oGPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)pGPIO1_BASE (0x401B8000u)pGPIO1 ((GPIO_Type *)GPIO1_BASE)pGPIO2_BASE (0x401BC000u)pGPIO2 ((GPIO_Type *)GPIO2_BASE)pGPIO3_BASE (0x401C0000u)pGPIO3 ((GPIO_Type *)GPIO3_BASE)pGPIO5_BASE (0x400C0000u)pGPIO5 ((GPIO_Type *)GPIO5_BASE)pGPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, 0u, GPIO5_BASE }pGPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, (GPIO_Type *)0u, GPIO5 }pGPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }pGPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, NotAvail_IRQn, GPIO5_Combined_0_15_IRQn }pGPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, NotAvail_IRQn, GPIO5_Combined_16_31_IRQn }pGPT_CR_EN_MASK (0x1U)pGPT_CR_EN_SHIFT (0U)pGPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)pGPT_CR_ENMOD_MASK (0x2U)pGPT_CR_ENMOD_SHIFT (1U)pGPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)pGPT_CR_DBGEN_MASK (0x4U)pGPT_CR_DBGEN_SHIFT (2U)pGPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)pGPT_CR_WAITEN_MASK (0x8U)pGPT_CR_WAITEN_SHIFT (3U)pGPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)pGPT_CR_DOZEEN_MASK (0x10U)pGPT_CR_DOZEEN_SHIFT (4U)pGPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)pGPT_CR_STOPEN_MASK (0x20U)pGPT_CR_STOPEN_SHIFT (5U)pGPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)pGPT_CR_CLKSRC_MASK (0x1C0U)pGPT_CR_CLKSRC_SHIFT (6U)pGPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)pGPT_CR_FRR_MASK (0x200U)pGPT_CR_FRR_SHIFT (9U)pGPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)pGPT_CR_EN_24M_MASK (0x400U)pGPT_CR_EN_24M_SHIFT (10U)qGPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)qGPT_CR_SWR_MASK (0x8000U)qGPT_CR_SWR_SHIFT (15U)qGPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)qGPT_CR_IM1_MASK (0x30000U)qGPT_CR_IM1_SHIFT (16U)qGPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)qGPT_CR_IM2_MASK (0xC0000U)qGPT_CR_IM2_SHIFT (18U)qGPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)qGPT_CR_OM1_MASK (0x700000U)qGPT_CR_OM1_SHIFT (20U)qGPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)qGPT_CR_OM2_MASK (0x3800000U)qGPT_CR_OM2_SHIFT (23U)qGPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)qGPT_CR_OM3_MASK (0x1C000000U)qGPT_CR_OM3_SHIFT (26U)qGPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)qGPT_CR_FO1_MASK (0x20000000U)qGPT_CR_FO1_SHIFT (29U)qGPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)qGPT_CR_FO2_MASK (0x40000000U)qGPT_CR_FO2_SHIFT (30U)qGPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)qGPT_CR_FO3_MASK (0x80000000U)qGPT_CR_FO3_SHIFT (31U)qGPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)qGPT_PR_PRESCALER_MASK (0xFFFU)qGPT_PR_PRESCALER_SHIFT (0U)qGPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)qGPT_PR_PRESCALER24M_MASK (0xF000U)qGPT_PR_PRESCALER24M_SHIFT (12U)qGPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)qGPT_SR_OF1_MASK (0x1U)qGPT_SR_OF1_SHIFT (0U)qGPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)qGPT_SR_OF2_MASK (0x2U)qGPT_SR_OF2_SHIFT (1U)qGPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)qGPT_SR_OF3_MASK (0x4U)qGPT_SR_OF3_SHIFT (2U)qGPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)qGPT_SR_IF1_MASK (0x8U)qGPT_SR_IF1_SHIFT (3U)qGPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)qGPT_SR_IF2_MASK (0x10U)qGPT_SR_IF2_SHIFT (4U)qGPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)qGPT_SR_ROV_MASK (0x20U)qGPT_SR_ROV_SHIFT (5U)qGPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)qGPT_IR_OF1IE_MASK (0x1U)qGPT_IR_OF1IE_SHIFT (0U)qGPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)qGPT_IR_OF2IE_MASK (0x2U)qGPT_IR_OF2IE_SHIFT (1U)qGPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)qGPT_IR_OF3IE_MASK (0x4U)qGPT_IR_OF3IE_SHIFT (2U)qGPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)qGPT_IR_IF1IE_MASK (0x8U)qGPT_IR_IF1IE_SHIFT (3U)qGPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)qGPT_IR_IF2IE_MASK (0x10U)qGPT_IR_IF2IE_SHIFT (4U)rGPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)rGPT_IR_ROVIE_MASK (0x20U)rGPT_IR_ROVIE_SHIFT (5U)rGPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)rGPT_OCR_COMP_MASK (0xFFFFFFFFU)rGPT_OCR_COMP_SHIFT (0U)rGPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)rGPT_OCR_COUNT (3U)rGPT_ICR_CAPT_MASK (0xFFFFFFFFU)rGPT_ICR_CAPT_SHIFT (0U)rGPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)rGPT_ICR_COUNT (2U)rGPT_CNT_COUNT_MASK (0xFFFFFFFFU)rGPT_CNT_COUNT_SHIFT (0U)rGPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)rGPT1_BASE (0x401EC000u)rGPT1 ((GPT_Type *)GPT1_BASE)rGPT2_BASE (0x401F0000u)rGPT2 ((GPT_Type *)GPT2_BASE)rGPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }rGPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }rGPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }rI2S_VERID_FEATURE_MASK (0xFFFFU)rI2S_VERID_FEATURE_SHIFT (0U)rI2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)rI2S_VERID_MINOR_MASK (0xFF0000U)rI2S_VERID_MINOR_SHIFT (16U)rI2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)rI2S_VERID_MAJOR_MASK (0xFF000000U)rI2S_VERID_MAJOR_SHIFT (24U)rI2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)sI2S_PARAM_DATALINE_MASK (0xFU)sI2S_PARAM_DATALINE_SHIFT (0U)sI2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)sI2S_PARAM_FIFO_MASK (0xF00U)sI2S_PARAM_FIFO_SHIFT (8U)sI2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)sI2S_PARAM_FRAME_MASK (0xF0000U)sI2S_PARAM_FRAME_SHIFT (16U)sI2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)sI2S_TCSR_FRDE_MASK (0x1U)sI2S_TCSR_FRDE_SHIFT (0U)sI2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)sI2S_TCSR_FWDE_MASK (0x2U)sI2S_TCSR_FWDE_SHIFT (1U)sI2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)sI2S_TCSR_FRIE_MASK (0x100U)sI2S_TCSR_FRIE_SHIFT (8U)sI2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)sI2S_TCSR_FWIE_MASK (0x200U)sI2S_TCSR_FWIE_SHIFT (9U)sI2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)sI2S_TCSR_FEIE_MASK (0x400U)sI2S_TCSR_FEIE_SHIFT (10U)sI2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)sI2S_TCSR_SEIE_MASK (0x800U)sI2S_TCSR_SEIE_SHIFT (11U)sI2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)sI2S_TCSR_WSIE_MASK (0x1000U)sI2S_TCSR_WSIE_SHIFT (12U)sI2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)sI2S_TCSR_FRF_MASK (0x10000U)sI2S_TCSR_FRF_SHIFT (16U)sI2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)sI2S_TCSR_FWF_MASK (0x20000U)sI2S_TCSR_FWF_SHIFT (17U)sI2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)sI2S_TCSR_FEF_MASK (0x40000U)sI2S_TCSR_FEF_SHIFT (18U)sI2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)sI2S_TCSR_SEF_MASK (0x80000U)sI2S_TCSR_SEF_SHIFT (19U)sI2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)sI2S_TCSR_WSF_MASK (0x100000U)sI2S_TCSR_WSF_SHIFT (20U)sI2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)sI2S_TCSR_SR_MASK (0x1000000U)sI2S_TCSR_SR_SHIFT (24U)sI2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)sI2S_TCSR_FR_MASK (0x2000000U)sI2S_TCSR_FR_SHIFT (25U)sI2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)sI2S_TCSR_BCE_MASK (0x10000000U)sI2S_TCSR_BCE_SHIFT (28U)sI2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)sI2S_TCSR_DBGE_MASK (0x20000000U)sI2S_TCSR_DBGE_SHIFT (29U)tI2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)tI2S_TCSR_STOPE_MASK (0x40000000U)tI2S_TCSR_STOPE_SHIFT (30U)tI2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)tI2S_TCSR_TE_MASK (0x80000000U)tI2S_TCSR_TE_SHIFT (31U)tI2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)tI2S_TCR1_TFW_MASK (0x1FU)tI2S_TCR1_TFW_SHIFT (0U)tI2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)tI2S_TCR2_DIV_MASK (0xFFU)tI2S_TCR2_DIV_SHIFT (0U)tI2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)tI2S_TCR2_BCD_MASK (0x1000000U)tI2S_TCR2_BCD_SHIFT (24U)tI2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)tI2S_TCR2_BCP_MASK (0x2000000U)tI2S_TCR2_BCP_SHIFT (25U)tI2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)tI2S_TCR2_MSEL_MASK (0xC000000U)tI2S_TCR2_MSEL_SHIFT (26U)tI2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)tI2S_TCR2_BCI_MASK (0x10000000U)tI2S_TCR2_BCI_SHIFT (28U)tI2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)tI2S_TCR2_BCS_MASK (0x20000000U)tI2S_TCR2_BCS_SHIFT (29U)tI2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)tI2S_TCR2_SYNC_MASK (0xC0000000U)tI2S_TCR2_SYNC_SHIFT (30U)tI2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)tI2S_TCR3_WDFL_MASK (0x1FU)tI2S_TCR3_WDFL_SHIFT (0U)tI2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)tI2S_TCR3_TCE_MASK (0xF0000U)tI2S_TCR3_TCE_SHIFT (16U)tI2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)tI2S_TCR3_CFR_MASK (0xF000000U)tI2S_TCR3_CFR_SHIFT (24U)tI2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)tI2S_TCR4_FSD_MASK (0x1U)tI2S_TCR4_FSD_SHIFT (0U)tI2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)tI2S_TCR4_FSP_MASK (0x2U)tI2S_TCR4_FSP_SHIFT (1U)tI2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)tI2S_TCR4_ONDEM_MASK (0x4U)tI2S_TCR4_ONDEM_SHIFT (2U)tI2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)tI2S_TCR4_FSE_MASK (0x8U)tI2S_TCR4_FSE_SHIFT (3U)tI2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)tI2S_TCR4_MF_MASK (0x10U)tI2S_TCR4_MF_SHIFT (4U)tI2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)tI2S_TCR4_CHMOD_MASK (0x20U)uI2S_TCR4_CHMOD_SHIFT (5U)uI2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)uI2S_TCR4_SYWD_MASK (0x1F00U)uI2S_TCR4_SYWD_SHIFT (8U)uI2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)uI2S_TCR4_FRSZ_MASK (0x1F0000U)uI2S_TCR4_FRSZ_SHIFT (16U)uI2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)uI2S_TCR4_FPACK_MASK (0x3000000U)uI2S_TCR4_FPACK_SHIFT (24U)uI2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)uI2S_TCR4_FCOMB_MASK (0xC000000U)uI2S_TCR4_FCOMB_SHIFT (26U)uI2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)uI2S_TCR4_FCONT_MASK (0x10000000U)uI2S_TCR4_FCONT_SHIFT (28U)uI2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)uI2S_TCR5_FBT_MASK (0x1F00U)uI2S_TCR5_FBT_SHIFT (8U)uI2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)uI2S_TCR5_W0W_MASK (0x1F0000U)uI2S_TCR5_W0W_SHIFT (16U)uI2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)uI2S_TCR5_WNW_MASK (0x1F000000U)uI2S_TCR5_WNW_SHIFT (24U)uI2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)uI2S_TDR_TDR_MASK (0xFFFFFFFFU)uI2S_TDR_TDR_SHIFT (0U)uI2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)uI2S_TDR_COUNT (4U)uI2S_TFR_RFP_MASK (0x3FU)uI2S_TFR_RFP_SHIFT (0U)uI2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)uI2S_TFR_WFP_MASK (0x3F0000U)uI2S_TFR_WFP_SHIFT (16U)uI2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)uI2S_TFR_WCP_MASK (0x80000000U)uI2S_TFR_WCP_SHIFT (31U)uI2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)uI2S_TFR_COUNT (4U)uI2S_TMR_TWM_MASK (0xFFFFFFFFU)uI2S_TMR_TWM_SHIFT (0U)uI2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)uI2S_RCSR_FRDE_MASK (0x1U)uI2S_RCSR_FRDE_SHIFT (0U)uI2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)uI2S_RCSR_FWDE_MASK (0x2U)uI2S_RCSR_FWDE_SHIFT (1U)uI2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)uI2S_RCSR_FRIE_MASK (0x100U)uI2S_RCSR_FRIE_SHIFT (8U)uI2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)uI2S_RCSR_FWIE_MASK (0x200U)uI2S_RCSR_FWIE_SHIFT (9U)uI2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)uI2S_RCSR_FEIE_MASK (0x400U)uI2S_RCSR_FEIE_SHIFT (10U)vI2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)vI2S_RCSR_SEIE_MASK (0x800U)vI2S_RCSR_SEIE_SHIFT (11U)vI2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)vI2S_RCSR_WSIE_MASK (0x1000U)vI2S_RCSR_WSIE_SHIFT (12U)vI2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)vI2S_RCSR_FRF_MASK (0x10000U)vI2S_RCSR_FRF_SHIFT (16U)vI2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)vI2S_RCSR_FWF_MASK (0x20000U)vI2S_RCSR_FWF_SHIFT (17U)vI2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)vI2S_RCSR_FEF_MASK (0x40000U)vI2S_RCSR_FEF_SHIFT (18U)vI2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)vI2S_RCSR_SEF_MASK (0x80000U)vI2S_RCSR_SEF_SHIFT (19U)vI2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)vI2S_RCSR_WSF_MASK (0x100000U)vI2S_RCSR_WSF_SHIFT (20U)vI2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)vI2S_RCSR_SR_MASK (0x1000000U)vI2S_RCSR_SR_SHIFT (24U)vI2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)vI2S_RCSR_FR_MASK (0x2000000U)vI2S_RCSR_FR_SHIFT (25U)vI2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)vI2S_RCSR_BCE_MASK (0x10000000U)vI2S_RCSR_BCE_SHIFT (28U)vI2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)vI2S_RCSR_DBGE_MASK (0x20000000U)vI2S_RCSR_DBGE_SHIFT (29U)vI2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)vI2S_RCSR_STOPE_MASK (0x40000000U)vI2S_RCSR_STOPE_SHIFT (30U)vI2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)vI2S_RCSR_RE_MASK (0x80000000U)vI2S_RCSR_RE_SHIFT (31U)vI2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)vI2S_RCR1_RFW_MASK (0x1FU)vI2S_RCR1_RFW_SHIFT (0U)vI2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)vI2S_RCR2_DIV_MASK (0xFFU)vI2S_RCR2_DIV_SHIFT (0U)vI2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)vI2S_RCR2_BCD_MASK (0x1000000U)vI2S_RCR2_BCD_SHIFT (24U)vI2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)vI2S_RCR2_BCP_MASK (0x2000000U)vI2S_RCR2_BCP_SHIFT (25U)vI2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)vI2S_RCR2_MSEL_MASK (0xC000000U)vI2S_RCR2_MSEL_SHIFT (26U)wI2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)wI2S_RCR2_BCI_MASK (0x10000000U)wI2S_RCR2_BCI_SHIFT (28U)wI2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)wI2S_RCR2_BCS_MASK (0x20000000U)wI2S_RCR2_BCS_SHIFT (29U)wI2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)wI2S_RCR2_SYNC_MASK (0xC0000000U)wI2S_RCR2_SYNC_SHIFT (30U)wI2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)wI2S_RCR3_WDFL_MASK (0x1FU)wI2S_RCR3_WDFL_SHIFT (0U)wI2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)wI2S_RCR3_RCE_MASK (0xF0000U)wI2S_RCR3_RCE_SHIFT (16U)wI2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)wI2S_RCR3_CFR_MASK (0xF000000U)wI2S_RCR3_CFR_SHIFT (24U)wI2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)wI2S_RCR4_FSD_MASK (0x1U)wI2S_RCR4_FSD_SHIFT (0U)wI2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)wI2S_RCR4_FSP_MASK (0x2U)wI2S_RCR4_FSP_SHIFT (1U)wI2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)wI2S_RCR4_ONDEM_MASK (0x4U)wI2S_RCR4_ONDEM_SHIFT (2U)wI2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)wI2S_RCR4_FSE_MASK (0x8U)wI2S_RCR4_FSE_SHIFT (3U)wI2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)wI2S_RCR4_MF_MASK (0x10U)wI2S_RCR4_MF_SHIFT (4U)wI2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)wI2S_RCR4_SYWD_MASK (0x1F00U)wI2S_RCR4_SYWD_SHIFT (8U)wI2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)wI2S_RCR4_FRSZ_MASK (0x1F0000U)wI2S_RCR4_FRSZ_SHIFT (16U)wI2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)wI2S_RCR4_FPACK_MASK (0x3000000U)wI2S_RCR4_FPACK_SHIFT (24U)wI2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)wI2S_RCR4_FCOMB_MASK (0xC000000U)wI2S_RCR4_FCOMB_SHIFT (26U)wI2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)wI2S_RCR4_FCONT_MASK (0x10000000U)wI2S_RCR4_FCONT_SHIFT (28U)wI2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)wI2S_RCR5_FBT_MASK (0x1F00U)wI2S_RCR5_FBT_SHIFT (8U)wI2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)wI2S_RCR5_W0W_MASK (0x1F0000U)wI2S_RCR5_W0W_SHIFT (16U)wI2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)wI2S_RCR5_WNW_MASK (0x1F000000U)wI2S_RCR5_WNW_SHIFT (24U)wI2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)wI2S_RDR_RDR_MASK (0xFFFFFFFFU)wI2S_RDR_RDR_SHIFT (0U)wI2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)xI2S_RDR_COUNT (4U)xI2S_RFR_RFP_MASK (0x3FU)xI2S_RFR_RFP_SHIFT (0U)xI2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)xI2S_RFR_RCP_MASK (0x8000U)xI2S_RFR_RCP_SHIFT (15U)xI2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)xI2S_RFR_WFP_MASK (0x3F0000U)xI2S_RFR_WFP_SHIFT (16U)xI2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)xI2S_RFR_COUNT (4U)xI2S_RMR_RWM_MASK (0xFFFFFFFFU)xI2S_RMR_RWM_SHIFT (0U)xI2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)xSAI1_BASE (0x40384000u)xSAI1 ((I2S_Type *)SAI1_BASE)xSAI2_BASE (0x40388000u)xSAI2 ((I2S_Type *)SAI2_BASE)xSAI3_BASE (0x4038C000u)xSAI3 ((I2S_Type *)SAI3_BASE)xI2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }xI2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }xI2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }xI2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }xIOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)xIOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)xIOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)xIOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)xIOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)xIOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)xIOMUXC_SW_MUX_CTL_PAD_COUNT (89U)xIOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)xIOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)yIOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)yIOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)yIOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)yIOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)yIOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)yIOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)yIOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)yIOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)yIOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)yIOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)yIOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)yIOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)yIOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)yIOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)yIOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)yIOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)yIOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)yIOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)yIOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)yIOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)yIOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)yIOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)yIOMUXC_SW_PAD_CTL_PAD_COUNT (89U)yIOMUXC_SELECT_INPUT_DAISY_MASK (0x3U)yIOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)yIOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)yIOMUXC_SELECT_INPUT_COUNT (114U)yIOMUXC_BASE (0x401F8000u)yIOMUXC ((IOMUXC_Type *)IOMUXC_BASE)yIOMUXC_BASE_ADDRS { IOMUXC_BASE }yIOMUXC_BASE_PTRS { IOMUXC }zIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)zIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)zIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)zIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)zIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)zIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)zIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)zIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)zIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)zIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)zIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)zIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)zIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)zIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)zIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)zIOMUXC_GPR_GPR1_GINT_MASK (0x1000U)zIOMUXC_GPR_GPR1_GINT_SHIFT (12U)zIOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)zIOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)zIOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)zIOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)zIOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)zIOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)zIOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)zIOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)zIOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)zIOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)zIOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)zIOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)zIOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)zIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)zIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)zIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)zIOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)zIOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U){IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK){IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U){IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U){IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK){IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U){IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U){IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK){IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U){IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)}IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)}IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)}IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)}IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)}IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)}IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)}IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)}IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)}IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)}IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)}IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)}IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)}IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)}IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)}IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)}IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)}IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)}IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)}IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)}IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)}IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)}IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)}IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)}IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)}IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)}IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)}IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)}IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)}IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)}IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)}IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)}IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)}IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)}IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)}IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)}IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)}IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)}IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)}IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)}IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)}IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)}IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)}IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)}IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)}IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)~IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)~IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)~IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)~IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)~IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)~IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)~IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)~IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)~IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)~IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)~IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)~IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)~IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)~IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)~IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)~IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)~IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)~IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)~IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)~IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)~IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)~IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)~IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)~IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)~IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)~IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)~IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)~IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)~IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)~IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)~IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)~IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)~IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)~IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)~IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)~IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)~IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)~IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)~IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)~IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)~IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)~IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)~IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)~IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)~IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)ĀIOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)ŀIOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)ƀIOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)ˀIOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)̀IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)̀IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)ҀIOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)ӀIOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)ԀIOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)ـIOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)ހIOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)߀IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)ƁIOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)ǁIOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)ȁIOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)́IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)ҁIOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)ӁIOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)؁IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)فIOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)ځIOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)߁IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x7E00U)IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)‚IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)ÂIOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)ʂIOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)˂IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)̂IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)͂IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)΂IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)ςIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)ЂIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)тIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)҂IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)ӂIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)ԂIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)ՂIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)ւIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)ׂIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)؂IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)قIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)ڂIOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)ۂIOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)܂IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)ÃIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFU)ăIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)ŃIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)ʃIOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)˃IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)ЃIOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)уIOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)҃IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)ӃIOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)؃IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)كIOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)ރIOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)߃IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)IOMUXC_GPR_BASE (0x400AC000u)„IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)ĄIOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }ƄIOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)…IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)ÅIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)ȅIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)ɅIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)ʅIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)ՅIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)օIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)ׅIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)ۅIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)܅IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)݅IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)ÆIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)ȆIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)ɆIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)ΆIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)φIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)ІIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)ۆIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)܆IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)݆IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)IOMUXC_SNVS_BASE (0x400A8000u)IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)‡IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)ÇIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)ćIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)ŇIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)ƇIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)LJIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)ȇIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)ɇIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)ʇIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)ˇIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)̇IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)͇IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)·IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)هIOMUXC_SNVS_GPR_BASE (0x400A4000u)ۇIOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)݇IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }߇IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }KPP_KPCR_KRE_MASK (0xFFU)KPP_KPCR_KRE_SHIFT (0U)KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)KPP_KPCR_KCO_MASK (0xFF00U)KPP_KPCR_KCO_SHIFT (8U)KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)KPP_KPSR_KPKD_MASK (0x1U)KPP_KPSR_KPKD_SHIFT (0U)KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)KPP_KPSR_KPKR_MASK (0x2U)KPP_KPSR_KPKR_SHIFT (1U)KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)KPP_KPSR_KDSC_MASK (0x4U)KPP_KPSR_KDSC_SHIFT (2U)KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)KPP_KPSR_KRSS_MASK (0x8U)KPP_KPSR_KRSS_SHIFT (3U)KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)KPP_KPSR_KDIE_MASK (0x100U)KPP_KPSR_KDIE_SHIFT (8U)KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)KPP_KPSR_KRIE_MASK (0x200U)KPP_KPSR_KRIE_SHIFT (9U)KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)ˆKPP_KDDR_KRDD_MASK (0xFFU)ÈKPP_KDDR_KRDD_SHIFT (0U)ȈKPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)ɈKPP_KDDR_KCDD_MASK (0xFF00U)ʈKPP_KDDR_KCDD_SHIFT (8U)ψKPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)ԈKPP_KPDR_KRD_MASK (0xFFU)ՈKPP_KPDR_KRD_SHIFT (0U)ֈKPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)׈KPP_KPDR_KCD_MASK (0xFF00U)؈KPP_KPDR_KCD_SHIFT (8U)وKPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)KPP_BASE (0x401FC000u)KPP ((KPP_Type *)KPP_BASE)KPP_BASE_ADDRS { KPP_BASE }KPP_BASE_PTRS { KPP }KPP_IRQS { KPP_IRQn }LPI2C_VERID_FEATURE_MASK (0xFFFFU)LPI2C_VERID_FEATURE_SHIFT (0U)LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)LPI2C_VERID_MINOR_MASK (0xFF0000U)LPI2C_VERID_MINOR_SHIFT (16U)LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)LPI2C_VERID_MAJOR_MASK (0xFF000000U)LPI2C_VERID_MAJOR_SHIFT (24U)LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)ĉLPI2C_PARAM_MTXFIFO_MASK (0xFU)ʼnLPI2C_PARAM_MTXFIFO_SHIFT (0U)ƉLPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)ljLPI2C_PARAM_MRXFIFO_MASK (0xF00U)ȉLPI2C_PARAM_MRXFIFO_SHIFT (8U)ɉLPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)ΉLPI2C_MCR_MEN_MASK (0x1U)ωLPI2C_MCR_MEN_SHIFT (0U)ԉLPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)ՉLPI2C_MCR_RST_MASK (0x2U)։LPI2C_MCR_RST_SHIFT (1U)ۉLPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)܉LPI2C_MCR_DOZEN_MASK (0x4U)݉LPI2C_MCR_DOZEN_SHIFT (2U)LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)LPI2C_MCR_DBGEN_MASK (0x8U)LPI2C_MCR_DBGEN_SHIFT (3U)LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)LPI2C_MCR_RTF_MASK (0x100U)LPI2C_MCR_RTF_SHIFT (8U)LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)LPI2C_MCR_RRF_MASK (0x200U)LPI2C_MCR_RRF_SHIFT (9U)LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)LPI2C_MSR_TDF_MASK (0x1U)LPI2C_MSR_TDF_SHIFT (0U)LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)LPI2C_MSR_RDF_MASK (0x2U)LPI2C_MSR_RDF_SHIFT (1U)LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)LPI2C_MSR_EPF_MASK (0x100U)LPI2C_MSR_EPF_SHIFT (8U)LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)LPI2C_MSR_SDF_MASK (0x200U)LPI2C_MSR_SDF_SHIFT (9U)LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)LPI2C_MSR_NDF_MASK (0x400U)LPI2C_MSR_NDF_SHIFT (10U)LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)LPI2C_MSR_ALF_MASK (0x800U)LPI2C_MSR_ALF_SHIFT (11U)LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)LPI2C_MSR_FEF_MASK (0x1000U)LPI2C_MSR_FEF_SHIFT (12U)LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)LPI2C_MSR_PLTF_MASK (0x2000U)LPI2C_MSR_PLTF_SHIFT (13U)LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)LPI2C_MSR_DMF_MASK (0x4000U)LPI2C_MSR_DMF_SHIFT (14U)LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)LPI2C_MSR_MBF_MASK (0x1000000U)LPI2C_MSR_MBF_SHIFT (24U)LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)ŠLPI2C_MSR_BBF_MASK (0x2000000U)ÊLPI2C_MSR_BBF_SHIFT (25U)ȊLPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)͊LPI2C_MIER_TDIE_MASK (0x1U)ΊLPI2C_MIER_TDIE_SHIFT (0U)ӊLPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)ԊLPI2C_MIER_RDIE_MASK (0x2U)ՊLPI2C_MIER_RDIE_SHIFT (1U)ڊLPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)ۊLPI2C_MIER_EPIE_MASK (0x100U)܊LPI2C_MIER_EPIE_SHIFT (8U)LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)LPI2C_MIER_SDIE_MASK (0x200U)LPI2C_MIER_SDIE_SHIFT (9U)LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)LPI2C_MIER_NDIE_MASK (0x400U)LPI2C_MIER_NDIE_SHIFT (10U)LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)LPI2C_MIER_ALIE_MASK (0x800U)LPI2C_MIER_ALIE_SHIFT (11U)LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)LPI2C_MIER_FEIE_MASK (0x1000U)LPI2C_MIER_FEIE_SHIFT (12U)LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)LPI2C_MIER_PLTIE_MASK (0x2000U)LPI2C_MIER_PLTIE_SHIFT (13U)LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)LPI2C_MIER_DMIE_MASK (0x4000U)LPI2C_MIER_DMIE_SHIFT (14U)LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)LPI2C_MDER_TDDE_MASK (0x1U)LPI2C_MDER_TDDE_SHIFT (0U)LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)LPI2C_MDER_RDDE_MASK (0x2U)LPI2C_MDER_RDDE_SHIFT (1U)LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)LPI2C_MCFGR0_HREN_MASK (0x1U)LPI2C_MCFGR0_HREN_SHIFT (0U)LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)LPI2C_MCFGR0_HRPOL_MASK (0x2U)LPI2C_MCFGR0_HRPOL_SHIFT (1U)LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)LPI2C_MCFGR0_HRSEL_MASK (0x4U)LPI2C_MCFGR0_HRSEL_SHIFT (2U)LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)LPI2C_MCFGR0_RDMO_MASK (0x200U)LPI2C_MCFGR0_RDMO_SHIFT (9U)ċLPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)ɋLPI2C_MCFGR1_PRESCALE_MASK (0x7U)ʋLPI2C_MCFGR1_PRESCALE_SHIFT (0U)ՋLPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)֋LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)׋LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)܋LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)݋LPI2C_MCFGR1_IGNACK_MASK (0x200U)ދLPI2C_MCFGR1_IGNACK_SHIFT (9U)LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)LPI2C_MCFGR1_TIMECFG_MASK (0x400U)LPI2C_MCFGR1_TIMECFG_SHIFT (10U)LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)LPI2C_MCFGR1_MATCFG_MASK (0x70000U)LPI2C_MCFGR1_MATCFG_SHIFT (16U)LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)LPI2C_MCFGR1_PINCFG_SHIFT (24U)LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)LPI2C_MCFGR2_FILTSCL_SHIFT (16U)LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)LPI2C_MCFGR2_FILTSDA_SHIFT (24U)LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)LPI2C_MCFGR3_PINLOW_SHIFT (8U)LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)LPI2C_MDMR_MATCH0_MASK (0xFFU)LPI2C_MDMR_MATCH0_SHIFT (0U)LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)LPI2C_MDMR_MATCH1_MASK (0xFF0000U)LPI2C_MDMR_MATCH1_SHIFT (16U)LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)LPI2C_MCCR0_CLKLO_MASK (0x3FU)LPI2C_MCCR0_CLKLO_SHIFT (0U)LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)LPI2C_MCCR0_CLKHI_MASK (0x3F00U)LPI2C_MCCR0_CLKHI_SHIFT (8U)LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)LPI2C_MCCR0_SETHOLD_SHIFT (16U)LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)LPI2C_MCCR0_DATAVD_SHIFT (24U)LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)LPI2C_MCCR1_CLKLO_MASK (0x3FU)LPI2C_MCCR1_CLKLO_SHIFT (0U)LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)LPI2C_MCCR1_CLKHI_MASK (0x3F00U)LPI2C_MCCR1_CLKHI_SHIFT (8U)LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)LPI2C_MCCR1_SETHOLD_SHIFT (16U)LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)LPI2C_MCCR1_DATAVD_SHIFT (24U)ŒLPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)njLPI2C_MFCR_TXWATER_MASK (0x3U)ȌLPI2C_MFCR_TXWATER_SHIFT (0U)ɌLPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)ʌLPI2C_MFCR_RXWATER_MASK (0x30000U)ˌLPI2C_MFCR_RXWATER_SHIFT (16U)̌LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)ьLPI2C_MFSR_TXCOUNT_MASK (0x7U)ҌLPI2C_MFSR_TXCOUNT_SHIFT (0U)ӌLPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)ԌLPI2C_MFSR_RXCOUNT_MASK (0x70000U)ՌLPI2C_MFSR_RXCOUNT_SHIFT (16U)֌LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)یLPI2C_MTDR_DATA_MASK (0xFFU)܌LPI2C_MTDR_DATA_SHIFT (0U)݌LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)ތLPI2C_MTDR_CMD_MASK (0x700U)ߌLPI2C_MTDR_CMD_SHIFT (8U)LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)LPI2C_MRDR_DATA_MASK (0xFFU)LPI2C_MRDR_DATA_SHIFT (0U)LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)LPI2C_MRDR_RXEMPTY_MASK (0x4000U)LPI2C_MRDR_RXEMPTY_SHIFT (14U)LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)LPI2C_SCR_SEN_MASK (0x1U)LPI2C_SCR_SEN_SHIFT (0U)LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)LPI2C_SCR_RST_MASK (0x2U)LPI2C_SCR_RST_SHIFT (1U)LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)LPI2C_SCR_FILTEN_MASK (0x10U)LPI2C_SCR_FILTEN_SHIFT (4U)LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)LPI2C_SCR_FILTDZ_MASK (0x20U)LPI2C_SCR_FILTDZ_SHIFT (5U)LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)LPI2C_SCR_RTF_MASK (0x100U)LPI2C_SCR_RTF_SHIFT (8U)LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)LPI2C_SCR_RRF_MASK (0x200U)LPI2C_SCR_RRF_SHIFT (9U)LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)LPI2C_SSR_TDF_MASK (0x1U)LPI2C_SSR_TDF_SHIFT (0U)LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)LPI2C_SSR_RDF_MASK (0x2U)LPI2C_SSR_RDF_SHIFT (1U)LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)LPI2C_SSR_AVF_MASK (0x4U)LPI2C_SSR_AVF_SHIFT (2U)LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)LPI2C_SSR_TAF_MASK (0x8U)LPI2C_SSR_TAF_SHIFT (3U)ƍLPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)ǍLPI2C_SSR_RSF_MASK (0x100U)ȍLPI2C_SSR_RSF_SHIFT (8U)͍LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)΍LPI2C_SSR_SDF_MASK (0x200U)ύLPI2C_SSR_SDF_SHIFT (9U)ԍLPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)ՍLPI2C_SSR_BEF_MASK (0x400U)֍LPI2C_SSR_BEF_SHIFT (10U)ۍLPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)܍LPI2C_SSR_FEF_MASK (0x800U)ݍLPI2C_SSR_FEF_SHIFT (11U)LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)LPI2C_SSR_AM0F_MASK (0x1000U)LPI2C_SSR_AM0F_SHIFT (12U)LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)LPI2C_SSR_AM1F_MASK (0x2000U)LPI2C_SSR_AM1F_SHIFT (13U)LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)LPI2C_SSR_GCF_MASK (0x4000U)LPI2C_SSR_GCF_SHIFT (14U)LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)LPI2C_SSR_SARF_MASK (0x8000U)LPI2C_SSR_SARF_SHIFT (15U)LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)LPI2C_SSR_SBF_MASK (0x1000000U)LPI2C_SSR_SBF_SHIFT (24U)LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)LPI2C_SSR_BBF_MASK (0x2000000U)LPI2C_SSR_BBF_SHIFT (25U)LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)LPI2C_SIER_TDIE_MASK (0x1U)LPI2C_SIER_TDIE_SHIFT (0U)LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)LPI2C_SIER_RDIE_MASK (0x2U)LPI2C_SIER_RDIE_SHIFT (1U)LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)LPI2C_SIER_AVIE_MASK (0x4U)LPI2C_SIER_AVIE_SHIFT (2U)LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)LPI2C_SIER_TAIE_MASK (0x8U)LPI2C_SIER_TAIE_SHIFT (3U)LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)LPI2C_SIER_RSIE_MASK (0x100U)LPI2C_SIER_RSIE_SHIFT (8U)LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)LPI2C_SIER_SDIE_MASK (0x200U)LPI2C_SIER_SDIE_SHIFT (9U)LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)LPI2C_SIER_BEIE_MASK (0x400U)LPI2C_SIER_BEIE_SHIFT (10U)LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)ŽLPI2C_SIER_FEIE_MASK (0x800U)ÎLPI2C_SIER_FEIE_SHIFT (11U)ȎLPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)ɎLPI2C_SIER_AM0IE_MASK (0x1000U)ʎLPI2C_SIER_AM0IE_SHIFT (12U)ώLPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)ЎLPI2C_SIER_AM1F_MASK (0x2000U)юLPI2C_SIER_AM1F_SHIFT (13U)֎LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)׎LPI2C_SIER_GCIE_MASK (0x4000U)؎LPI2C_SIER_GCIE_SHIFT (14U)ݎLPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)ގLPI2C_SIER_SARIE_MASK (0x8000U)ߎLPI2C_SIER_SARIE_SHIFT (15U)LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)LPI2C_SDER_TDDE_MASK (0x1U)LPI2C_SDER_TDDE_SHIFT (0U)LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)LPI2C_SDER_RDDE_MASK (0x2U)LPI2C_SDER_RDDE_SHIFT (1U)LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)LPI2C_SDER_AVDE_MASK (0x4U)LPI2C_SDER_AVDE_SHIFT (2U)LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)LPI2C_SCFGR1_RXSTALL_MASK (0x2U)LPI2C_SCFGR1_RXSTALL_SHIFT (1U)LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)LPI2C_SCFGR1_GCEN_MASK (0x100U)LPI2C_SCFGR1_GCEN_SHIFT (8U)LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)LPI2C_SCFGR1_SAEN_MASK (0x200U)LPI2C_SCFGR1_SAEN_SHIFT (9U)LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)LPI2C_SCFGR1_TXCFG_MASK (0x400U)LPI2C_SCFGR1_TXCFG_SHIFT (10U)LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)LPI2C_SCFGR1_RXCFG_MASK (0x800U)LPI2C_SCFGR1_RXCFG_SHIFT (11U)LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)LPI2C_SCFGR1_IGNACK_MASK (0x1000U)LPI2C_SCFGR1_IGNACK_SHIFT (12U)LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)ÏLPI2C_SCFGR1_HSMEN_MASK (0x2000U)ďLPI2C_SCFGR1_HSMEN_SHIFT (13U)ɏLPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)ʏLPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)ˏLPI2C_SCFGR1_ADDRCFG_SHIFT (16U)֏LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)ۏLPI2C_SCFGR2_CLKHOLD_MASK (0xFU)܏LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)ݏLPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)ޏLPI2C_SCFGR2_DATAVD_MASK (0x3F00U)ߏLPI2C_SCFGR2_DATAVD_SHIFT (8U)LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)LPI2C_SCFGR2_FILTSCL_SHIFT (16U)LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)LPI2C_SCFGR2_FILTSDA_SHIFT (24U)LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)LPI2C_SAMR_ADDR0_MASK (0x7FEU)LPI2C_SAMR_ADDR0_SHIFT (1U)LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)LPI2C_SAMR_ADDR1_SHIFT (17U)LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)LPI2C_SASR_RADDR_MASK (0x7FFU)LPI2C_SASR_RADDR_SHIFT (0U)LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)LPI2C_SASR_ANV_MASK (0x4000U)LPI2C_SASR_ANV_SHIFT (14U)LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)LPI2C_STAR_TXNACK_MASK (0x1U)LPI2C_STAR_TXNACK_SHIFT (0U)LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)LPI2C_STDR_DATA_MASK (0xFFU)LPI2C_STDR_DATA_SHIFT (0U)LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)LPI2C_SRDR_DATA_MASK (0xFFU)LPI2C_SRDR_DATA_SHIFT (0U)LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)LPI2C_SRDR_RXEMPTY_MASK (0x4000U)LPI2C_SRDR_RXEMPTY_SHIFT (14U)LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)LPI2C_SRDR_SOF_MASK (0x8000U)LPI2C_SRDR_SOF_SHIFT (15U)LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)LPI2C1_BASE (0x403F0000u)LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)LPI2C2_BASE (0x403F4000u)LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE }LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2 }LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn }LPSPI_VERID_FEATURE_MASK (0xFFFFU)LPSPI_VERID_FEATURE_SHIFT (0U)LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)LPSPI_VERID_MINOR_MASK (0xFF0000U)LPSPI_VERID_MINOR_SHIFT (16U)LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)LPSPI_VERID_MAJOR_MASK (0xFF000000U)LPSPI_VERID_MAJOR_SHIFT (24U)LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)LPSPI_PARAM_TXFIFO_MASK (0xFFU)LPSPI_PARAM_TXFIFO_SHIFT (0U)LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)LPSPI_PARAM_RXFIFO_MASK (0xFF00U)LPSPI_PARAM_RXFIFO_SHIFT (8U)LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)LPSPI_PARAM_PCSNUM_SHIFT (16U)LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)LPSPI_CR_MEN_MASK (0x1U)LPSPI_CR_MEN_SHIFT (0U)LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)LPSPI_CR_RST_MASK (0x2U)LPSPI_CR_RST_SHIFT (1U)LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)LPSPI_CR_DOZEN_MASK (0x4U)LPSPI_CR_DOZEN_SHIFT (2U)LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)LPSPI_CR_DBGEN_MASK (0x8U)LPSPI_CR_DBGEN_SHIFT (3U)LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)LPSPI_CR_RTF_MASK (0x100U)LPSPI_CR_RTF_SHIFT (8U)LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)LPSPI_CR_RRF_MASK (0x200U)LPSPI_CR_RRF_SHIFT (9U)LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)LPSPI_SR_TDF_MASK (0x1U)LPSPI_SR_TDF_SHIFT (0U)‘LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)ÑLPSPI_SR_RDF_MASK (0x2U)đLPSPI_SR_RDF_SHIFT (1U)ɑLPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)ʑLPSPI_SR_WCF_MASK (0x100U)ˑLPSPI_SR_WCF_SHIFT (8U)БLPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)ёLPSPI_SR_FCF_MASK (0x200U)ґLPSPI_SR_FCF_SHIFT (9U)בLPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)ؑLPSPI_SR_TCF_MASK (0x400U)ّLPSPI_SR_TCF_SHIFT (10U)ޑLPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)ߑLPSPI_SR_TEF_MASK (0x800U)LPSPI_SR_TEF_SHIFT (11U)LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)LPSPI_SR_REF_MASK (0x1000U)LPSPI_SR_REF_SHIFT (12U)LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)LPSPI_SR_DMF_MASK (0x2000U)LPSPI_SR_DMF_SHIFT (13U)LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)LPSPI_SR_MBF_MASK (0x1000000U)LPSPI_SR_MBF_SHIFT (24U)LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)LPSPI_IER_TDIE_MASK (0x1U)LPSPI_IER_TDIE_SHIFT (0U)LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)LPSPI_IER_RDIE_MASK (0x2U)LPSPI_IER_RDIE_SHIFT (1U)LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)LPSPI_IER_WCIE_MASK (0x100U)LPSPI_IER_WCIE_SHIFT (8U)LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)LPSPI_IER_FCIE_MASK (0x200U)LPSPI_IER_FCIE_SHIFT (9U)LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)LPSPI_IER_TCIE_MASK (0x400U)LPSPI_IER_TCIE_SHIFT (10U)LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)LPSPI_IER_TEIE_MASK (0x800U)LPSPI_IER_TEIE_SHIFT (11U)LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)LPSPI_IER_REIE_MASK (0x1000U)LPSPI_IER_REIE_SHIFT (12U)LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)LPSPI_IER_DMIE_MASK (0x2000U)LPSPI_IER_DMIE_SHIFT (13U)LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)LPSPI_DER_TDDE_MASK (0x1U)LPSPI_DER_TDDE_SHIFT (0U)LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)’LPSPI_DER_RDDE_MASK (0x2U)ÒLPSPI_DER_RDDE_SHIFT (1U)ȒLPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)͒LPSPI_CFGR0_HREN_MASK (0x1U)ΒLPSPI_CFGR0_HREN_SHIFT (0U)ӒLPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)ԒLPSPI_CFGR0_HRPOL_MASK (0x2U)ՒLPSPI_CFGR0_HRPOL_SHIFT (1U)ڒLPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)ےLPSPI_CFGR0_HRSEL_MASK (0x4U)ܒLPSPI_CFGR0_HRSEL_SHIFT (2U)LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)LPSPI_CFGR0_CIRFIFO_MASK (0x100U)LPSPI_CFGR0_CIRFIFO_SHIFT (8U)LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)LPSPI_CFGR0_RDMO_MASK (0x200U)LPSPI_CFGR0_RDMO_SHIFT (9U)LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)LPSPI_CFGR1_MASTER_MASK (0x1U)LPSPI_CFGR1_MASTER_SHIFT (0U)LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)LPSPI_CFGR1_SAMPLE_MASK (0x2U)LPSPI_CFGR1_SAMPLE_SHIFT (1U)LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)LPSPI_CFGR1_AUTOPCS_MASK (0x4U)LPSPI_CFGR1_AUTOPCS_SHIFT (2U)LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)LPSPI_CFGR1_NOSTALL_MASK (0x8U)LPSPI_CFGR1_NOSTALL_SHIFT (3U)LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)LPSPI_CFGR1_PCSPOL_MASK (0xF00U)LPSPI_CFGR1_PCSPOL_SHIFT (8U)LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)LPSPI_CFGR1_MATCFG_MASK (0x70000U)LPSPI_CFGR1_MATCFG_SHIFT (16U)LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)LPSPI_CFGR1_PINCFG_MASK (0x3000000U)LPSPI_CFGR1_PINCFG_SHIFT (24U)LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)LPSPI_CFGR1_OUTCFG_SHIFT (26U)LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)LPSPI_CFGR1_PCSCFG_SHIFT (27U)LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)“LPSPI_DMR0_MATCH0_SHIFT (0U)ÓLPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)ȓLPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)ɓLPSPI_DMR1_MATCH1_SHIFT (0U)ʓLPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)ϓLPSPI_CCR_SCKDIV_MASK (0xFFU)ГLPSPI_CCR_SCKDIV_SHIFT (0U)ѓLPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)ғLPSPI_CCR_DBT_MASK (0xFF00U)ӓLPSPI_CCR_DBT_SHIFT (8U)ԓLPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)ՓLPSPI_CCR_PCSSCK_MASK (0xFF0000U)֓LPSPI_CCR_PCSSCK_SHIFT (16U)דLPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)ؓLPSPI_CCR_SCKPCS_MASK (0xFF000000U)ٓLPSPI_CCR_SCKPCS_SHIFT (24U)ړLPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)ߓLPSPI_FCR_TXWATER_MASK (0xFU)LPSPI_FCR_TXWATER_SHIFT (0U)LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)LPSPI_FCR_RXWATER_MASK (0xF0000U)LPSPI_FCR_RXWATER_SHIFT (16U)LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)LPSPI_FSR_TXCOUNT_MASK (0x1FU)LPSPI_FSR_TXCOUNT_SHIFT (0U)LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)LPSPI_FSR_RXCOUNT_SHIFT (16U)LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)LPSPI_TCR_FRAMESZ_MASK (0xFFFU)LPSPI_TCR_FRAMESZ_SHIFT (0U)LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)LPSPI_TCR_WIDTH_MASK (0x30000U)LPSPI_TCR_WIDTH_SHIFT (16U)LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)LPSPI_TCR_TXMSK_MASK (0x40000U)LPSPI_TCR_TXMSK_SHIFT (18U)LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)LPSPI_TCR_RXMSK_MASK (0x80000U)LPSPI_TCR_RXMSK_SHIFT (19U)LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)LPSPI_TCR_CONTC_MASK (0x100000U)LPSPI_TCR_CONTC_SHIFT (20U)LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)LPSPI_TCR_CONT_MASK (0x200000U)LPSPI_TCR_CONT_SHIFT (21U)LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)LPSPI_TCR_BYSW_MASK (0x400000U)LPSPI_TCR_BYSW_SHIFT (22U)LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)LPSPI_TCR_LSBF_MASK (0x800000U)LPSPI_TCR_LSBF_SHIFT (23U)LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)LPSPI_TCR_PCS_MASK (0x3000000U)LPSPI_TCR_PCS_SHIFT (24U)LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)LPSPI_TCR_PRESCALE_MASK (0x38000000U)LPSPI_TCR_PRESCALE_SHIFT (27U)LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)LPSPI_TCR_CPHA_MASK (0x40000000U)LPSPI_TCR_CPHA_SHIFT (30U)ŔLPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)ƔLPSPI_TCR_CPOL_MASK (0x80000000U)ǔLPSPI_TCR_CPOL_SHIFT (31U)̔LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)єLPSPI_TDR_DATA_MASK (0xFFFFFFFFU)ҔLPSPI_TDR_DATA_SHIFT (0U)ӔLPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)ؔLPSPI_RSR_SOF_MASK (0x1U)ٔLPSPI_RSR_SOF_SHIFT (0U)ޔLPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)ߔLPSPI_RSR_RXEMPTY_MASK (0x2U)LPSPI_RSR_RXEMPTY_SHIFT (1U)LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)LPSPI_RDR_DATA_SHIFT (0U)LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)LPSPI1_BASE (0x40394000u)LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)LPSPI2_BASE (0x40398000u)LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE }LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2 }LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn }LPUART_VERID_FEATURE_MASK (0xFFFFU)LPUART_VERID_FEATURE_SHIFT (0U)LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)LPUART_VERID_MINOR_MASK (0xFF0000U)LPUART_VERID_MINOR_SHIFT (16U)LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)LPUART_VERID_MAJOR_MASK (0xFF000000U)LPUART_VERID_MAJOR_SHIFT (24U)LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)LPUART_PARAM_TXFIFO_MASK (0xFFU)LPUART_PARAM_TXFIFO_SHIFT (0U)LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)•LPUART_PARAM_RXFIFO_MASK (0xFF00U)ÕLPUART_PARAM_RXFIFO_SHIFT (8U)ĕLPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)ɕLPUART_GLOBAL_RST_MASK (0x2U)ʕLPUART_GLOBAL_RST_SHIFT (1U)ϕLPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)ԕLPUART_PINCFG_TRGSEL_MASK (0x3U)ՕLPUART_PINCFG_TRGSEL_SHIFT (0U)ܕLPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)LPUART_BAUD_SBR_MASK (0x1FFFU)LPUART_BAUD_SBR_SHIFT (0U)LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)LPUART_BAUD_SBNS_MASK (0x2000U)LPUART_BAUD_SBNS_SHIFT (13U)LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)LPUART_BAUD_RXEDGIE_MASK (0x4000U)LPUART_BAUD_RXEDGIE_SHIFT (14U)LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)LPUART_BAUD_LBKDIE_MASK (0x8000U)LPUART_BAUD_LBKDIE_SHIFT (15U)LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)LPUART_BAUD_RESYNCDIS_MASK (0x10000U)LPUART_BAUD_RESYNCDIS_SHIFT (16U)LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)LPUART_BAUD_BOTHEDGE_MASK (0x20000U)LPUART_BAUD_BOTHEDGE_SHIFT (17U)LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)LPUART_BAUD_MATCFG_MASK (0xC0000U)LPUART_BAUD_MATCFG_SHIFT (18U)LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)LPUART_BAUD_RDMAE_MASK (0x200000U)LPUART_BAUD_RDMAE_SHIFT (21U)LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)LPUART_BAUD_TDMAE_MASK (0x800000U)LPUART_BAUD_TDMAE_SHIFT (23U)LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)LPUART_BAUD_OSR_MASK (0x1F000000U)LPUART_BAUD_OSR_SHIFT (24U)–LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)ÖLPUART_BAUD_M10_MASK (0x20000000U)ĖLPUART_BAUD_M10_SHIFT (29U)ɖLPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)ʖLPUART_BAUD_MAEN2_MASK (0x40000000U)˖LPUART_BAUD_MAEN2_SHIFT (30U)ЖLPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)іLPUART_BAUD_MAEN1_MASK (0x80000000U)ҖLPUART_BAUD_MAEN1_SHIFT (31U)זLPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)ܖLPUART_STAT_MA2F_MASK (0x4000U)ݖLPUART_STAT_MA2F_SHIFT (14U)LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)LPUART_STAT_MA1F_MASK (0x8000U)LPUART_STAT_MA1F_SHIFT (15U)LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)LPUART_STAT_PF_MASK (0x10000U)LPUART_STAT_PF_SHIFT (16U)LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)LPUART_STAT_FE_MASK (0x20000U)LPUART_STAT_FE_SHIFT (17U)LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)LPUART_STAT_NF_MASK (0x40000U)LPUART_STAT_NF_SHIFT (18U)LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)LPUART_STAT_OR_MASK (0x80000U)LPUART_STAT_OR_SHIFT (19U)LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)LPUART_STAT_IDLE_MASK (0x100000U)LPUART_STAT_IDLE_SHIFT (20U)LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)LPUART_STAT_RDRF_MASK (0x200000U)LPUART_STAT_RDRF_SHIFT (21U)LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)LPUART_STAT_TC_MASK (0x400000U)LPUART_STAT_TC_SHIFT (22U)LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)LPUART_STAT_TDRE_MASK (0x800000U)LPUART_STAT_TDRE_SHIFT (23U)LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)LPUART_STAT_RAF_MASK (0x1000000U)LPUART_STAT_RAF_SHIFT (24U)LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)LPUART_STAT_LBKDE_MASK (0x2000000U)LPUART_STAT_LBKDE_SHIFT (25U)LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)LPUART_STAT_BRK13_MASK (0x4000000U)LPUART_STAT_BRK13_SHIFT (26U)LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)LPUART_STAT_RWUID_MASK (0x8000000U)LPUART_STAT_RWUID_SHIFT (27U)LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)LPUART_STAT_RXINV_MASK (0x10000000U)LPUART_STAT_RXINV_SHIFT (28U)ƗLPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)ǗLPUART_STAT_MSBF_MASK (0x20000000U)ȗLPUART_STAT_MSBF_SHIFT (29U)ЗLPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)їLPUART_STAT_RXEDGIF_MASK (0x40000000U)җLPUART_STAT_RXEDGIF_SHIFT (30U)חLPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)ؗLPUART_STAT_LBKDIF_MASK (0x80000000U)ٗLPUART_STAT_LBKDIF_SHIFT (31U)ޗLPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)LPUART_CTRL_PT_MASK (0x1U)LPUART_CTRL_PT_SHIFT (0U)LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)LPUART_CTRL_PE_MASK (0x2U)LPUART_CTRL_PE_SHIFT (1U)LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)LPUART_CTRL_ILT_MASK (0x4U)LPUART_CTRL_ILT_SHIFT (2U)LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)LPUART_CTRL_WAKE_MASK (0x8U)LPUART_CTRL_WAKE_SHIFT (3U)LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)LPUART_CTRL_M_MASK (0x10U)LPUART_CTRL_M_SHIFT (4U)LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)LPUART_CTRL_RSRC_MASK (0x20U)LPUART_CTRL_RSRC_SHIFT (5U)LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)LPUART_CTRL_DOZEEN_MASK (0x40U)LPUART_CTRL_DOZEEN_SHIFT (6U)LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)LPUART_CTRL_LOOPS_MASK (0x80U)LPUART_CTRL_LOOPS_SHIFT (7U)LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)LPUART_CTRL_IDLECFG_MASK (0x700U)LPUART_CTRL_IDLECFG_SHIFT (8U)LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)LPUART_CTRL_M7_MASK (0x800U)LPUART_CTRL_M7_SHIFT (11U)LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)LPUART_CTRL_MA2IE_MASK (0x4000U)LPUART_CTRL_MA2IE_SHIFT (14U)LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)LPUART_CTRL_MA1IE_MASK (0x8000U)LPUART_CTRL_MA1IE_SHIFT (15U)LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)LPUART_CTRL_SBK_MASK (0x10000U)LPUART_CTRL_SBK_SHIFT (16U)ØLPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)ĘLPUART_CTRL_RWU_MASK (0x20000U)ŘLPUART_CTRL_RWU_SHIFT (17U)ʘLPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)˘LPUART_CTRL_RE_MASK (0x40000U)̘LPUART_CTRL_RE_SHIFT (18U)јLPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)ҘLPUART_CTRL_TE_MASK (0x80000U)ӘLPUART_CTRL_TE_SHIFT (19U)ؘLPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)٘LPUART_CTRL_ILIE_MASK (0x100000U)ژLPUART_CTRL_ILIE_SHIFT (20U)ߘLPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)LPUART_CTRL_RIE_MASK (0x200000U)LPUART_CTRL_RIE_SHIFT (21U)LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)LPUART_CTRL_TCIE_MASK (0x400000U)LPUART_CTRL_TCIE_SHIFT (22U)LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)LPUART_CTRL_TIE_MASK (0x800000U)LPUART_CTRL_TIE_SHIFT (23U)LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)LPUART_CTRL_PEIE_MASK (0x1000000U)LPUART_CTRL_PEIE_SHIFT (24U)LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)LPUART_CTRL_FEIE_MASK (0x2000000U)LPUART_CTRL_FEIE_SHIFT (25U)LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)LPUART_CTRL_NEIE_MASK (0x4000000U)LPUART_CTRL_NEIE_SHIFT (26U)LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)LPUART_CTRL_ORIE_MASK (0x8000000U)LPUART_CTRL_ORIE_SHIFT (27U)LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)LPUART_CTRL_TXINV_MASK (0x10000000U)LPUART_CTRL_TXINV_SHIFT (28U)LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)LPUART_CTRL_TXDIR_MASK (0x20000000U)LPUART_CTRL_TXDIR_SHIFT (29U)LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)LPUART_CTRL_R9T8_MASK (0x40000000U)LPUART_CTRL_R9T8_SHIFT (30U)LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)LPUART_CTRL_R8T9_MASK (0x80000000U)LPUART_CTRL_R8T9_SHIFT (31U)LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)LPUART_DATA_R0T0_MASK (0x1U)LPUART_DATA_R0T0_SHIFT (0U)LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)LPUART_DATA_R1T1_MASK (0x2U)LPUART_DATA_R1T1_SHIFT (1U)LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)LPUART_DATA_R2T2_MASK (0x4U)LPUART_DATA_R2T2_SHIFT (2U)LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)LPUART_DATA_R3T3_MASK (0x8U)LPUART_DATA_R3T3_SHIFT (3U)LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)LPUART_DATA_R4T4_MASK (0x10U)LPUART_DATA_R4T4_SHIFT (4U)LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)LPUART_DATA_R5T5_MASK (0x20U)LPUART_DATA_R5T5_SHIFT (5U)LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)LPUART_DATA_R6T6_MASK (0x40U)LPUART_DATA_R6T6_SHIFT (6U)LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)LPUART_DATA_R7T7_MASK (0x80U)LPUART_DATA_R7T7_SHIFT (7U)LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)LPUART_DATA_R8T8_MASK (0x100U)™LPUART_DATA_R8T8_SHIFT (8U)ÙLPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)ęLPUART_DATA_R9T9_MASK (0x200U)řLPUART_DATA_R9T9_SHIFT (9U)ƙLPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)ǙLPUART_DATA_IDLINE_MASK (0x800U)șLPUART_DATA_IDLINE_SHIFT (11U)͙LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)ΙLPUART_DATA_RXEMPT_MASK (0x1000U)ϙLPUART_DATA_RXEMPT_SHIFT (12U)ԙLPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)ՙLPUART_DATA_FRETSC_MASK (0x2000U)֙LPUART_DATA_FRETSC_SHIFT (13U)ۙLPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)ܙLPUART_DATA_PARITYE_MASK (0x4000U)ݙLPUART_DATA_PARITYE_SHIFT (14U)LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)LPUART_DATA_NOISY_MASK (0x8000U)LPUART_DATA_NOISY_SHIFT (15U)LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)LPUART_MATCH_MA1_MASK (0x3FFU)LPUART_MATCH_MA1_SHIFT (0U)LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)LPUART_MATCH_MA2_MASK (0x3FF0000U)LPUART_MATCH_MA2_SHIFT (16U)LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)LPUART_MODIR_TXCTSE_MASK (0x1U)LPUART_MODIR_TXCTSE_SHIFT (0U)LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)LPUART_MODIR_TXRTSE_MASK (0x2U)LPUART_MODIR_TXRTSE_SHIFT (1U)LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)LPUART_MODIR_TXRTSPOL_MASK (0x4U)LPUART_MODIR_TXRTSPOL_SHIFT (2U)LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)LPUART_MODIR_RXRTSE_MASK (0x8U)LPUART_MODIR_RXRTSE_SHIFT (3U)LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)LPUART_MODIR_TXCTSC_MASK (0x10U)LPUART_MODIR_TXCTSC_SHIFT (4U)LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)LPUART_MODIR_TXCTSSRC_MASK (0x20U)LPUART_MODIR_TXCTSSRC_SHIFT (5U)LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)LPUART_MODIR_RTSWATER_MASK (0x300U)LPUART_MODIR_RTSWATER_SHIFT (8U)LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)LPUART_MODIR_TNP_MASK (0x30000U)LPUART_MODIR_TNP_SHIFT (16U)LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)LPUART_MODIR_IREN_MASK (0x40000U)LPUART_MODIR_IREN_SHIFT (18U)LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)̚LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)͚LPUART_FIFO_RXFE_MASK (0x8U)ΚLPUART_FIFO_RXFE_SHIFT (3U)ӚLPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)ԚLPUART_FIFO_TXFIFOSIZE_MASK (0x70U)՚LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)LPUART_FIFO_TXFE_MASK (0x80U)LPUART_FIFO_TXFE_SHIFT (7U)LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)LPUART_FIFO_RXUFE_MASK (0x100U)LPUART_FIFO_RXUFE_SHIFT (8U)LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)LPUART_FIFO_TXOFE_MASK (0x200U)LPUART_FIFO_TXOFE_SHIFT (9U)LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)LPUART_FIFO_RXIDEN_MASK (0x1C00U)LPUART_FIFO_RXIDEN_SHIFT (10U)LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)LPUART_FIFO_RXFLUSH_MASK (0x4000U)LPUART_FIFO_RXFLUSH_SHIFT (14U)LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)LPUART_FIFO_TXFLUSH_MASK (0x8000U)LPUART_FIFO_TXFLUSH_SHIFT (15U)LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)LPUART_FIFO_RXUF_MASK (0x10000U)LPUART_FIFO_RXUF_SHIFT (16U)LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)LPUART_FIFO_TXOF_MASK (0x20000U)LPUART_FIFO_TXOF_SHIFT (17U)LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)LPUART_FIFO_RXEMPT_MASK (0x400000U)LPUART_FIFO_RXEMPT_SHIFT (22U)LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)LPUART_FIFO_TXEMPT_MASK (0x800000U)LPUART_FIFO_TXEMPT_SHIFT (23U)LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)LPUART_WATER_TXWATER_MASK (0x3U)LPUART_WATER_TXWATER_SHIFT (0U)LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)LPUART_WATER_TXCOUNT_MASK (0x700U)LPUART_WATER_TXCOUNT_SHIFT (8U)LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)LPUART_WATER_RXWATER_MASK (0x30000U)LPUART_WATER_RXWATER_SHIFT (16U)LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)LPUART_WATER_RXCOUNT_MASK (0x7000000U)LPUART_WATER_RXCOUNT_SHIFT (24U)LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)ǛLPUART1_BASE (0x40184000u)ɛLPUART1 ((LPUART_Type *)LPUART1_BASE)˛LPUART2_BASE (0x40188000u)͛LPUART2 ((LPUART_Type *)LPUART2_BASE)ϛLPUART3_BASE (0x4018C000u)ћLPUART3 ((LPUART_Type *)LPUART3_BASE)ӛLPUART4_BASE (0x40190000u)՛LPUART4 ((LPUART_Type *)LPUART4_BASE)כLPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE }ٛLPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4 }ۛLPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn }ޜOCOTP_CTRL_ADDR_MASK (0x3FU)ߜOCOTP_CTRL_ADDR_SHIFT (0U)OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)OCOTP_CTRL_BUSY_MASK (0x100U)OCOTP_CTRL_BUSY_SHIFT (8U)OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)OCOTP_CTRL_ERROR_MASK (0x200U)OCOTP_CTRL_ERROR_SHIFT (9U)OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)OCOTP_CTRL_SET_ADDR_MASK (0x3FU)OCOTP_CTRL_SET_ADDR_SHIFT (0U)OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)OCOTP_CTRL_SET_BUSY_MASK (0x100U)OCOTP_CTRL_SET_BUSY_SHIFT (8U)OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)OCOTP_CTRL_SET_ERROR_MASK (0x200U)OCOTP_CTRL_SET_ERROR_SHIFT (9U)OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)OCOTP_CTRL_CLR_ADDR_SHIFT (0U)OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)OCOTP_CTRL_CLR_BUSY_MASK (0x100U)OCOTP_CTRL_CLR_BUSY_SHIFT (8U)OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)OCOTP_CTRL_CLR_ERROR_MASK (0x200U)OCOTP_CTRL_CLR_ERROR_SHIFT (9U)OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)OCOTP_CTRL_TOG_ADDR_SHIFT (0U)OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)OCOTP_CTRL_TOG_BUSY_MASK (0x100U)OCOTP_CTRL_TOG_BUSY_SHIFT (8U)OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)OCOTP_CTRL_TOG_ERROR_MASK (0x200U)OCOTP_CTRL_TOG_ERROR_SHIFT (9U)OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)OCOTP_TIMING_STROBE_PROG_SHIFT (0U)OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)OCOTP_TIMING_RELAX_MASK (0xF000U)OCOTP_TIMING_RELAX_SHIFT (12U)OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)OCOTP_TIMING_STROBE_READ_SHIFT (16U)OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)OCOTP_TIMING_WAIT_MASK (0xFC00000U)OCOTP_TIMING_WAIT_SHIFT (22U)OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)OCOTP_DATA_DATA_SHIFT (0U)OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)ÝOCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)ȝOCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)ɝOCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)ʝOCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)ϝOCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)НOCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)ѝOCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)ҝOCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)ӝOCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)ԝOCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)ٝOCOTP_SCS_HAB_JDE_MASK (0x1U)ڝOCOTP_SCS_HAB_JDE_SHIFT (0U)۝OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)ܝOCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)ݝOCOTP_SCS_SPARE_SHIFT (1U)ޝOCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)ߝOCOTP_SCS_LOCK_MASK (0x80000000U)OCOTP_SCS_LOCK_SHIFT (31U)OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)OCOTP_SCS_SET_SPARE_SHIFT (1U)OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)OCOTP_SCS_SET_LOCK_MASK (0x80000000U)OCOTP_SCS_SET_LOCK_SHIFT (31U)OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)OCOTP_SCS_CLR_SPARE_SHIFT (1U)OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)OCOTP_SCS_CLR_LOCK_SHIFT (31U)OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)OCOTP_SCS_TOG_SPARE_SHIFT (1U)OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)OCOTP_SCS_TOG_LOCK_SHIFT (31U)OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)OCOTP_VERSION_STEP_MASK (0xFFFFU)OCOTP_VERSION_STEP_SHIFT (0U)OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)OCOTP_VERSION_MINOR_MASK (0xFF0000U)OCOTP_VERSION_MINOR_SHIFT (16U)OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)OCOTP_VERSION_MAJOR_MASK (0xFF000000U)OCOTP_VERSION_MAJOR_SHIFT (24U)OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)OCOTP_TIMING2_RELAX_READ_SHIFT (16U)OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U)OCOTP_TIMING2_RELAX1_SHIFT (22U)OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK)OCOTP_LOCK_TESTER_MASK (0x3U)OCOTP_LOCK_TESTER_SHIFT (0U)OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)OCOTP_LOCK_BOOT_CFG_MASK (0xCU)OCOTP_LOCK_BOOT_CFG_SHIFT (2U)OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)OCOTP_LOCK_MEM_TRIM_MASK (0x30U)OCOTP_LOCK_MEM_TRIM_SHIFT (4U)OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)OCOTP_LOCK_SJC_RESP_MASK (0x40U)OCOTP_LOCK_SJC_RESP_SHIFT (6U)OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)OCOTP_LOCK_MAC_ADDR_MASK (0x300U)OCOTP_LOCK_MAC_ADDR_SHIFT (8U)OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)OCOTP_LOCK_GP1_MASK (0xC00U)OCOTP_LOCK_GP1_SHIFT (10U)OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)OCOTP_LOCK_GP2_MASK (0x3000U)OCOTP_LOCK_GP2_SHIFT (12U)OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U)OCOTP_LOCK_OTPMK_MSB_SHIFT (15U)OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK)OCOTP_LOCK_SW_GP1_MASK (0x10000U)OCOTP_LOCK_SW_GP1_SHIFT (16U)OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)žOCOTP_LOCK_OTPMK_LSB_MASK (0x20000U)ÞOCOTP_LOCK_OTPMK_LSB_SHIFT (17U)ĞOCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK)ŞOCOTP_LOCK_ANALOG_MASK (0xC0000U)ƞOCOTP_LOCK_ANALOG_SHIFT (18U)ǞOCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)ȞOCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)ɞOCOTP_LOCK_OTPMK_CRC_SHIFT (20U)ʞOCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)˞OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)̞OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)͞OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)ΞOCOTP_LOCK_MISC_CONF_MASK (0x400000U)ϞOCOTP_LOCK_MISC_CONF_SHIFT (22U)ОOCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)ўOCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)ҞOCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)ӞOCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)ԞOCOTP_LOCK_GP3_MASK (0xC000000U)՞OCOTP_LOCK_GP3_SHIFT (26U)֞OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)מOCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)؞OCOTP_LOCK_FIELD_RETURN_SHIFT (28U)ٞOCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)ޞOCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)ߞOCOTP_CFG0_BITS_SHIFT (0U)OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)OCOTP_CFG1_BITS_SHIFT (0U)OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)OCOTP_CFG2_BITS_SHIFT (0U)OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)OCOTP_CFG3_BITS_SHIFT (0U)OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)OCOTP_CFG4_BITS_SHIFT (0U)OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)OCOTP_CFG5_BITS_SHIFT (0U)OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)OCOTP_CFG6_BITS_SHIFT (0U)OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)OCOTP_MEM0_BITS_SHIFT (0U)OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)OCOTP_MEM1_BITS_SHIFT (0U)OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)OCOTP_MEM2_BITS_SHIFT (0U)OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)OCOTP_MEM3_BITS_SHIFT (0U)OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)OCOTP_MEM4_BITS_SHIFT (0U)OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)OCOTP_ANA0_BITS_SHIFT (0U)OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)OCOTP_ANA1_BITS_SHIFT (0U)OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)OCOTP_ANA2_BITS_SHIFT (0U)ŸOCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)ǟOCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)ȟOCOTP_SRK0_BITS_SHIFT (0U)ɟOCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)ΟOCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)ϟOCOTP_SRK1_BITS_SHIFT (0U)ПOCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)՟OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)֟OCOTP_SRK2_BITS_SHIFT (0U)ןOCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)ܟOCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)ݟOCOTP_SRK3_BITS_SHIFT (0U)ޟOCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)OCOTP_SRK4_BITS_SHIFT (0U)OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)OCOTP_SRK5_BITS_SHIFT (0U)OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)OCOTP_SRK6_BITS_SHIFT (0U)OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)OCOTP_SRK7_BITS_SHIFT (0U)OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)OCOTP_SJC_RESP0_BITS_SHIFT (0U)OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)OCOTP_SJC_RESP1_BITS_SHIFT (0U)OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)OCOTP_MAC0_BITS_SHIFT (0U)OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)OCOTP_MAC1_BITS_SHIFT (0U)OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)OCOTP_GP3_BITS_MASK (0xFFFFFFFFU)OCOTP_GP3_BITS_SHIFT (0U)OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)OCOTP_GP1_BITS_SHIFT (0U)OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)OCOTP_GP2_BITS_SHIFT (0U)OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)OCOTP_SW_GP1_BITS_SHIFT (0U)OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)OCOTP_SW_GP20_BITS_SHIFT (0U)OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)OCOTP_SW_GP21_BITS_SHIFT (0U)OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)ŠOCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)ƠOCOTP_SW_GP22_BITS_SHIFT (0U)ǠOCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)̠OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)͠OCOTP_SW_GP23_BITS_SHIFT (0U)ΠOCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)ӠOCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)ԠOCOTP_MISC_CONF0_BITS_SHIFT (0U)ՠOCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)ڠOCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)۠OCOTP_MISC_CONF1_BITS_SHIFT (0U)ܠOCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)OCOTP_SRK_REVOKE_BITS_SHIFT (0U)OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)OCOTP_BASE (0x401F4000u)OCOTP ((OCOTP_Type *)OCOTP_BASE)OCOTP_BASE_ADDRS { OCOTP_BASE }OCOTP_BASE_PTRS { OCOTP }PGC_MEGA_CTRL_PCR_MASK (0x1U)PGC_MEGA_CTRL_PCR_SHIFT (0U)PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)PGC_MEGA_PUPSCR_SW_MASK (0x3FU)PGC_MEGA_PUPSCR_SW_SHIFT (0U)PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)PGC_MEGA_PDNSCR_ISO_SHIFT (0U)PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)PGC_MEGA_SR_PSR_MASK (0x1U)PGC_MEGA_SR_PSR_SHIFT (0U)¡PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)ǡPGC_CPU_CTRL_PCR_MASK (0x1U)ȡPGC_CPU_CTRL_PCR_SHIFT (0U)͡PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)ҡPGC_CPU_PUPSCR_SW_MASK (0x3FU)ӡPGC_CPU_PUPSCR_SW_SHIFT (0U)ԡPGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)աPGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)֡PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)סPGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)ܡPGC_CPU_PDNSCR_ISO_MASK (0x3FU)ݡPGC_CPU_PDNSCR_ISO_SHIFT (0U)ޡPGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)ߡPGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)PGC_CPU_SR_PSR_MASK (0x1U)PGC_CPU_SR_PSR_SHIFT (0U)PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)PGC_BASE (0x400F4000u)PGC ((PGC_Type *)PGC_BASE)PGC_BASE_ADDRS { PGC_BASE }PGC_BASE_PTRS { PGC }PIT_MCR_FRZ_MASK (0x1U)PIT_MCR_FRZ_SHIFT (0U)PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)PIT_MCR_MDIS_MASK (0x2U)PIT_MCR_MDIS_SHIFT (1U)PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)PIT_LTMR64H_LTH_SHIFT (0U)PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)PIT_LTMR64L_LTL_SHIFT (0U)¢PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)ǢPIT_LDVAL_TSV_MASK (0xFFFFFFU)ȢPIT_LDVAL_TSV_SHIFT (0U)ɢPIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)͢PIT_LDVAL_COUNT (4U)ѢPIT_CVAL_TVL_MASK (0xFFFFFFFFU)ҢPIT_CVAL_TVL_SHIFT (0U)ӢPIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)עPIT_CVAL_COUNT (4U)ۢPIT_TCTRL_TEN_MASK (0x1U)ܢPIT_TCTRL_TEN_SHIFT (0U)PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)PIT_TCTRL_TIE_MASK (0x2U)PIT_TCTRL_TIE_SHIFT (1U)PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)PIT_TCTRL_CHN_MASK (0x4U)PIT_TCTRL_CHN_SHIFT (2U)PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)PIT_TCTRL_COUNT (4U)PIT_TFLG_TIF_MASK (0x1U)PIT_TFLG_TIF_SHIFT (0U)PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)PIT_TFLG_COUNT (4U)PIT_BASE (0x40084000u)PIT ((PIT_Type *)PIT_BASE)PIT_BASE_ADDRS { PIT_BASE }PIT_BASE_PTRS { PIT }PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }ϣPMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)УPMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)ѣPMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)ңPMU_REG_1P1_ENABLE_BO_MASK (0x2U)ӣPMU_REG_1P1_ENABLE_BO_SHIFT (1U)ԣPMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)գPMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)֣PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)ףPMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)أPMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)٣PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)ڣPMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)ۣPMU_REG_1P1_BO_OFFSET_MASK (0x70U)ܣPMU_REG_1P1_BO_OFFSET_SHIFT (4U)ݣPMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)ޣPMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)ߣPMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)¤PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)äPMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)ĤPMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)ŤPMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)ƤPMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)ˤPMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)ФPMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)ѤPMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)ҤPMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)ӤPMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)ԤPMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)դPMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)֤PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)פPMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)ؤPMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)٤PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)ڤPMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)ۤPMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)ܤPMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)ݤPMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)ޤPMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)ߤPMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)PMU_REG_3P0_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)PMU_REG_3P0_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)PMU_REG_3P0_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)ťPMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)ƥPMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)ǥPMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)ȥPMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)ɥPMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)ʥPMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)˥PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)̥PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)ͥPMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)ΥPMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)ϥPMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)ХPMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)ѥPMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)ҥPMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)ץPMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)إPMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)٥PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)ߥPMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)PMU_REG_2P5_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)¦PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)æPMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)ɦPMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)ʦPMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)˦PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)̦PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)ͦPMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)ΦPMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)ϦPMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)ЦPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)ѦPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)ҦPMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)צPMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)ئPMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)٦PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)ڦPMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)ۦPMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)ܦPMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)ݦPMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)ަPMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)ߦPMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)PMU_REG_CORE_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_REG0_TARG_SHIFT (0U)PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)PMU_REG_CORE_REG0_ADJ_SHIFT (5U)PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)§PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)çPMU_REG_CORE_REG1_TARG_SHIFT (9U)ϧPMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)ЧPMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)ѧPMU_REG_CORE_REG1_ADJ_SHIFT (14U)PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_REG2_TARG_SHIFT (18U)PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)PMU_REG_CORE_REG2_ADJ_SHIFT (23U)PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)ʨPMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)˨PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)̨PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)ũPMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)ƩPMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)ǩPMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)ܩPMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)ݩPMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)ީPMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)ªPMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)תPMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)تPMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)٪PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)PMU_MISC0_REFTOP_PWD_MASK (0x1U)PMU_MISC0_REFTOP_PWD_SHIFT (0U)PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)PMU_MISC0_OSC_I_MASK (0x6000U)PMU_MISC0_OSC_I_SHIFT (13U)PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)PMU_MISC0_OSC_XTALOK_MASK (0x8000U)PMU_MISC0_OSC_XTALOK_SHIFT (15U)PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)«PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)ëPMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)īPMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)ūPMU_MISC0_CLKGATE_CTRL_SHIFT (25U)ʫPMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)˫PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)̫PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)׫PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)ثPMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)٫PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)ޫPMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)߫PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)PMU_MISC0_SET_OSC_I_MASK (0x6000U)PMU_MISC0_SET_OSC_I_SHIFT (13U)PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)¬PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)ìPMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)ĬPMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)ŬPMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)ʬPMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)ˬPMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)̬PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)׬PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)جPMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)٬PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)ڬPMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)۬PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)ܬPMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)PMU_MISC0_CLR_OSC_I_MASK (0x6000U)PMU_MISC0_CLR_OSC_I_SHIFT (13U)PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)ŭPMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)ƭPMU_MISC0_TOG_OSC_I_MASK (0x6000U)ǭPMU_MISC0_TOG_OSC_I_SHIFT (13U)έPMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)ϭPMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)ЭPMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)ѭPMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)ҭPMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)ӭPMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)ԭPMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)խPMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)֭PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)ۭPMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)ܭPMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)ݭPMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)®PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)îPMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)ĮPMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)ŮPMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)ƮPMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)ǮPMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)ȮPMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)ɮPMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)ʮPMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)ˮPMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)̮PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)ͮPMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)ήPMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)ϮPMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)ЮPMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)ѮPMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)ҮPMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)ӮPMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)ԮPMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)ծPMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)֮PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)ۮPMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)ܮPMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)PMU_MISC2_PLL3_disable_MASK (0x80U)PMU_MISC2_PLL3_disable_SHIFT (7U)PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)PMU_MISC2_REG2_OK_MASK (0x400000U)PMU_MISC2_REG2_OK_SHIFT (22U)PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)¯PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)ïPMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)ǯPMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)ȯPMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)ɯPMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)ʯPMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)˯PMU_MISC2_SET_PLL3_disable_MASK (0x80U)̯PMU_MISC2_SET_PLL3_disable_SHIFT (7U)ͯPMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)ίPMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)ϯPMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)ԯPMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)կPMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)֯PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)گPMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)ۯPMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)ܯPMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)ݯPMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)ޯPMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)߯PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)PMU_MISC2_SET_REG2_OK_MASK (0x400000U)PMU_MISC2_SET_REG2_OK_SHIFT (22U)PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)İPMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)ŰPMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)ưPMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)˰PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)̰PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)ͰPMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)ΰPMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)ϰPMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)аPMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)ѰPMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)ҰPMU_MISC2_CLR_REG2_OK_MASK (0x400000U)ӰPMU_MISC2_CLR_REG2_OK_SHIFT (22U)԰PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)հPMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)ְPMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)۰PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)ܰPMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)ݰPMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)PMU_MISC2_TOG_REG2_OK_SHIFT (22U)PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)ıPMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)űPMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)ƱPMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)ͱPMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)αPMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)ϱPMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)ֱPMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)PMU_BASE (0x400D8000u)PMU ((PMU_Type *)PMU_BASE)PMU_BASE_ADDRS { PMU_BASE }PMU_BASE_PTRS { PMU }PWM_CNT_CNT_MASK (0xFFFFU)PWM_CNT_CNT_SHIFT (0U)PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)ŲPWM_CNT_COUNT (4U)ɲPWM_INIT_INIT_MASK (0xFFFFU)ʲPWM_INIT_INIT_SHIFT (0U)˲PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)ϲPWM_INIT_COUNT (4U)ӲPWM_CTRL2_CLK_SEL_MASK (0x3U)ԲPWM_CTRL2_CLK_SEL_SHIFT (0U)ܲPWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)ݲPWM_CTRL2_RELOAD_SEL_MASK (0x4U)޲PWM_CTRL2_RELOAD_SEL_SHIFT (2U)PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)PWM_CTRL2_FORCE_SEL_MASK (0x38U)PWM_CTRL2_FORCE_SEL_SHIFT (3U)PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)PWM_CTRL2_FORCE_MASK (0x40U)PWM_CTRL2_FORCE_SHIFT (6U)PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)PWM_CTRL2_FRCEN_MASK (0x80U)PWM_CTRL2_FRCEN_SHIFT (7U)PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)PWM_CTRL2_INIT_SEL_MASK (0x300U)PWM_CTRL2_INIT_SEL_SHIFT (8U)PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)PWM_CTRL2_PWMX_INIT_MASK (0x400U)PWM_CTRL2_PWMX_INIT_SHIFT (10U)PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)PWM_CTRL2_PWM45_INIT_MASK (0x800U)PWM_CTRL2_PWM45_INIT_SHIFT (11U)PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)PWM_CTRL2_PWM23_INIT_MASK (0x1000U)PWM_CTRL2_PWM23_INIT_SHIFT (12U)PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)PWM_CTRL2_INDEP_MASK (0x2000U)PWM_CTRL2_INDEP_SHIFT (13U)PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)PWM_CTRL2_WAITEN_MASK (0x4000U)PWM_CTRL2_WAITEN_SHIFT (14U)PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)PWM_CTRL2_DBGEN_MASK (0x8000U)PWM_CTRL2_DBGEN_SHIFT (15U)PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)PWM_CTRL2_COUNT (4U)PWM_CTRL_DBLEN_MASK (0x1U)PWM_CTRL_DBLEN_SHIFT (0U)PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)PWM_CTRL_DBLX_MASK (0x2U)PWM_CTRL_DBLX_SHIFT (1U)PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)PWM_CTRL_LDMOD_MASK (0x4U)PWM_CTRL_LDMOD_SHIFT (2U)PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)PWM_CTRL_SPLIT_MASK (0x8U)PWM_CTRL_SPLIT_SHIFT (3U)ijPWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)ųPWM_CTRL_PRSC_MASK (0x70U)ƳPWM_CTRL_PRSC_SHIFT (4U)ѳPWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)ҳPWM_CTRL_COMPMODE_MASK (0x80U)ӳPWM_CTRL_COMPMODE_SHIFT (7U)޳PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)߳PWM_CTRL_DT_MASK (0x300U)PWM_CTRL_DT_SHIFT (8U)PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)PWM_CTRL_FULL_MASK (0x400U)PWM_CTRL_FULL_SHIFT (10U)PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)PWM_CTRL_HALF_MASK (0x800U)PWM_CTRL_HALF_SHIFT (11U)PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)PWM_CTRL_LDFQ_MASK (0xF000U)PWM_CTRL_LDFQ_SHIFT (12U)PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)PWM_CTRL_COUNT (4U)PWM_VAL0_VAL0_MASK (0xFFFFU)PWM_VAL0_VAL0_SHIFT (0U)PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)PWM_VAL0_COUNT (4U)PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)PWM_FRACVAL1_FRACVAL1_SHIFT (11U)PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)PWM_FRACVAL1_COUNT (4U)PWM_VAL1_VAL1_MASK (0xFFFFU)PWM_VAL1_VAL1_SHIFT (0U)PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)PWM_VAL1_COUNT (4U)PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)PWM_FRACVAL2_FRACVAL2_SHIFT (11U)PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)PWM_FRACVAL2_COUNT (4U)PWM_VAL2_VAL2_MASK (0xFFFFU)PWM_VAL2_VAL2_SHIFT (0U)PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)PWM_VAL2_COUNT (4U)PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)PWM_FRACVAL3_FRACVAL3_SHIFT (11U)PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)ĴPWM_FRACVAL3_COUNT (4U)ȴPWM_VAL3_VAL3_MASK (0xFFFFU)ɴPWM_VAL3_VAL3_SHIFT (0U)ʴPWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)δPWM_VAL3_COUNT (4U)ҴPWM_FRACVAL4_FRACVAL4_MASK (0xF800U)ӴPWM_FRACVAL4_FRACVAL4_SHIFT (11U)ԴPWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)شPWM_FRACVAL4_COUNT (4U)ܴPWM_VAL4_VAL4_MASK (0xFFFFU)ݴPWM_VAL4_VAL4_SHIFT (0U)޴PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)PWM_VAL4_COUNT (4U)PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)PWM_FRACVAL5_FRACVAL5_SHIFT (11U)PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)PWM_FRACVAL5_COUNT (4U)PWM_VAL5_VAL5_MASK (0xFFFFU)PWM_VAL5_VAL5_SHIFT (0U)PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)PWM_VAL5_COUNT (4U)PWM_FRCTRL_FRAC1_EN_MASK (0x2U)PWM_FRCTRL_FRAC1_EN_SHIFT (1U)PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)PWM_FRCTRL_FRAC23_EN_MASK (0x4U)PWM_FRCTRL_FRAC23_EN_SHIFT (2U)PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)PWM_FRCTRL_FRAC45_EN_MASK (0x10U)PWM_FRCTRL_FRAC45_EN_SHIFT (4U)PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)PWM_FRCTRL_FRAC_PU_MASK (0x100U)PWM_FRCTRL_FRAC_PU_SHIFT (8U)PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)PWM_FRCTRL_TEST_MASK (0x8000U)PWM_FRCTRL_TEST_SHIFT (15U)PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)PWM_FRCTRL_COUNT (4U)PWM_OCTRL_PWMXFS_MASK (0x3U)PWM_OCTRL_PWMXFS_SHIFT (0U)PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)PWM_OCTRL_PWMBFS_MASK (0xCU)PWM_OCTRL_PWMBFS_SHIFT (2U)PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)PWM_OCTRL_PWMAFS_MASK (0x30U)PWM_OCTRL_PWMAFS_SHIFT (4U)PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)PWM_OCTRL_POLX_MASK (0x100U)PWM_OCTRL_POLX_SHIFT (8U)PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)µPWM_OCTRL_POLB_MASK (0x200U)õPWM_OCTRL_POLB_SHIFT (9U)ȵPWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)ɵPWM_OCTRL_POLA_MASK (0x400U)ʵPWM_OCTRL_POLA_SHIFT (10U)ϵPWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)еPWM_OCTRL_PWMX_IN_MASK (0x2000U)ѵPWM_OCTRL_PWMX_IN_SHIFT (13U)ҵPWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)ӵPWM_OCTRL_PWMB_IN_MASK (0x4000U)ԵPWM_OCTRL_PWMB_IN_SHIFT (14U)յPWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)ֵPWM_OCTRL_PWMA_IN_MASK (0x8000U)׵PWM_OCTRL_PWMA_IN_SHIFT (15U)صPWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)ܵPWM_OCTRL_COUNT (4U)PWM_STS_CMPF_MASK (0x3FU)PWM_STS_CMPF_SHIFT (0U)PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)PWM_STS_CFX0_MASK (0x40U)PWM_STS_CFX0_SHIFT (6U)PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)PWM_STS_CFX1_MASK (0x80U)PWM_STS_CFX1_SHIFT (7U)PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)PWM_STS_CFB0_MASK (0x100U)PWM_STS_CFB0_SHIFT (8U)PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)PWM_STS_CFB1_MASK (0x200U)PWM_STS_CFB1_SHIFT (9U)PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)PWM_STS_CFA0_MASK (0x400U)PWM_STS_CFA0_SHIFT (10U)PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)PWM_STS_CFA1_MASK (0x800U)PWM_STS_CFA1_SHIFT (11U)PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)PWM_STS_RF_MASK (0x1000U)PWM_STS_RF_SHIFT (12U)PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)PWM_STS_REF_MASK (0x2000U)PWM_STS_REF_SHIFT (13U)PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)PWM_STS_RUF_MASK (0x4000U)PWM_STS_RUF_SHIFT (14U)PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)PWM_STS_COUNT (4U)PWM_INTEN_CMPIE_MASK (0x3FU)PWM_INTEN_CMPIE_SHIFT (0U)PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)PWM_INTEN_CX0IE_MASK (0x40U)PWM_INTEN_CX0IE_SHIFT (6U)PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)PWM_INTEN_CX1IE_MASK (0x80U)PWM_INTEN_CX1IE_SHIFT (7U)PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)PWM_INTEN_CB0IE_MASK (0x100U)PWM_INTEN_CB0IE_SHIFT (8U)PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)PWM_INTEN_CB1IE_MASK (0x200U)PWM_INTEN_CB1IE_SHIFT (9U)PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)PWM_INTEN_CA0IE_MASK (0x400U)PWM_INTEN_CA0IE_SHIFT (10U)PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)PWM_INTEN_CA1IE_MASK (0x800U)PWM_INTEN_CA1IE_SHIFT (11U)ŶPWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)ƶPWM_INTEN_RIE_MASK (0x1000U)ǶPWM_INTEN_RIE_SHIFT (12U)̶PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)ͶPWM_INTEN_REIE_MASK (0x2000U)ζPWM_INTEN_REIE_SHIFT (13U)ӶPWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)׶PWM_INTEN_COUNT (4U)۶PWM_DMAEN_CX0DE_MASK (0x1U)ܶPWM_DMAEN_CX0DE_SHIFT (0U)ݶPWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)޶PWM_DMAEN_CX1DE_MASK (0x2U)߶PWM_DMAEN_CX1DE_SHIFT (1U)PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)PWM_DMAEN_CB0DE_MASK (0x4U)PWM_DMAEN_CB0DE_SHIFT (2U)PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)PWM_DMAEN_CB1DE_MASK (0x8U)PWM_DMAEN_CB1DE_SHIFT (3U)PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)PWM_DMAEN_CA0DE_MASK (0x10U)PWM_DMAEN_CA0DE_SHIFT (4U)PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)PWM_DMAEN_CA1DE_MASK (0x20U)PWM_DMAEN_CA1DE_SHIFT (5U)PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)PWM_DMAEN_CAPTDE_MASK (0xC0U)PWM_DMAEN_CAPTDE_SHIFT (6U)PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)PWM_DMAEN_FAND_MASK (0x100U)PWM_DMAEN_FAND_SHIFT (8U)PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)PWM_DMAEN_VALDE_MASK (0x200U)PWM_DMAEN_VALDE_SHIFT (9U)PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)PWM_DMAEN_COUNT (4U)PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)PWM_TCTRL_TRGFRQ_MASK (0x1000U)PWM_TCTRL_TRGFRQ_SHIFT (12U)PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)PWM_TCTRL_PWBOT1_MASK (0x4000U)PWM_TCTRL_PWBOT1_SHIFT (14U)PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)PWM_TCTRL_PWAOT0_MASK (0x8000U)PWM_TCTRL_PWAOT0_SHIFT (15U)PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)PWM_TCTRL_COUNT (4U)PWM_DISMAP_DIS0A_MASK (0xFU)PWM_DISMAP_DIS0A_SHIFT (0U)PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)PWM_DISMAP_DIS1A_MASK (0xFU)PWM_DISMAP_DIS1A_SHIFT (0U)PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)PWM_DISMAP_DIS0B_MASK (0xF0U)PWM_DISMAP_DIS0B_SHIFT (4U)PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)PWM_DISMAP_DIS1B_MASK (0xF0U)PWM_DISMAP_DIS1B_SHIFT (4U)PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)PWM_DISMAP_DIS0X_MASK (0xF00U)PWM_DISMAP_DIS0X_SHIFT (8U)PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)PWM_DISMAP_DIS1X_MASK (0xF00U)PWM_DISMAP_DIS1X_SHIFT (8U)·PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)ƷPWM_DISMAP_COUNT (4U)ɷPWM_DISMAP_COUNT2 (2U)ͷPWM_DTCNT0_DTCNT0_MASK (0xFFFFU)ηPWM_DTCNT0_DTCNT0_SHIFT (0U)ϷPWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)ӷPWM_DTCNT0_COUNT (4U)׷PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)طPWM_DTCNT1_DTCNT1_SHIFT (0U)ٷPWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)ݷPWM_DTCNT1_COUNT (4U)PWM_CAPTCTRLA_ARMA_MASK (0x1U)PWM_CAPTCTRLA_ARMA_SHIFT (0U)PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)PWM_CAPTCTRLA_EDGA0_MASK (0xCU)PWM_CAPTCTRLA_EDGA0_SHIFT (2U)PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)PWM_CAPTCTRLA_EDGA1_MASK (0x30U)PWM_CAPTCTRLA_EDGA1_SHIFT (4U)PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)PWM_CAPTCTRLA_CFAWM_MASK (0x300U)PWM_CAPTCTRLA_CFAWM_SHIFT (8U)PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)PWM_CAPTCTRLA_COUNT (4U)PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)PWM_CAPTCOMPA_COUNT (4U)PWM_CAPTCTRLB_ARMB_MASK (0x1U)PWM_CAPTCTRLB_ARMB_SHIFT (0U)PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)̸PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)͸PWM_CAPTCTRLB_EDGB0_MASK (0xCU)θPWM_CAPTCTRLB_EDGB0_SHIFT (2U)ոPWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)ָPWM_CAPTCTRLB_EDGB1_MASK (0x30U)׸PWM_CAPTCTRLB_EDGB1_SHIFT (4U)޸PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)߸PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)PWM_CAPTCTRLB_CFBWM_MASK (0x300U)PWM_CAPTCTRLB_CFBWM_SHIFT (8U)PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)PWM_CAPTCTRLB_COUNT (4U)PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)PWM_CAPTCOMPB_COUNT (4U)PWM_CAPTCTRLX_ARMX_MASK (0x1U)PWM_CAPTCTRLX_ARMX_SHIFT (0U)PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)PWM_CAPTCTRLX_EDGX0_MASK (0xCU)PWM_CAPTCTRLX_EDGX0_SHIFT (2U)PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)PWM_CAPTCTRLX_EDGX1_MASK (0x30U)PWM_CAPTCTRLX_EDGX1_SHIFT (4U)PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)ŹPWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)ƹPWM_CAPTCTRLX_CFXWM_MASK (0x300U)ǹPWM_CAPTCTRLX_CFXWM_SHIFT (8U)ȹPWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)ɹPWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)ʹPWM_CAPTCTRLX_CX0CNT_SHIFT (10U)˹PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)̹PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)͹PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)ιPWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)ҹPWM_CAPTCTRLX_COUNT (4U)ֹPWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)׹PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)عPWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)ٹPWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)ڹPWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)۹PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)߹PWM_CAPTCOMPX_COUNT (4U)PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)PWM_CVAL0_CAPTVAL0_SHIFT (0U)PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)PWM_CVAL0_COUNT (4U)PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)PWM_CVAL0CYC_COUNT (4U)PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)PWM_CVAL1_CAPTVAL1_SHIFT (0U)PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)PWM_CVAL1_COUNT (4U)PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)PWM_CVAL1CYC_COUNT (4U)PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)PWM_CVAL2_CAPTVAL2_SHIFT (0U)PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)PWM_CVAL2_COUNT (4U)PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)PWM_CVAL2CYC_COUNT (4U)PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)PWM_CVAL3_CAPTVAL3_SHIFT (0U)PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)PWM_CVAL3_COUNT (4U)PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)PWM_CVAL3CYC_COUNT (4U)PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)PWM_CVAL4_CAPTVAL4_SHIFT (0U)PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)PWM_CVAL4_COUNT (4U)PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)úPWM_CVAL4CYC_COUNT (4U)ǺPWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)ȺPWM_CVAL5_CAPTVAL5_SHIFT (0U)ɺPWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)ͺPWM_CVAL5_COUNT (4U)ѺPWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)ҺPWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)ӺPWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)׺PWM_CVAL5CYC_COUNT (4U)ۺPWM_OUTEN_PWMX_EN_MASK (0xFU)ܺPWM_OUTEN_PWMX_EN_SHIFT (0U)PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)PWM_OUTEN_PWMB_EN_MASK (0xF0U)PWM_OUTEN_PWMB_EN_SHIFT (4U)PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)PWM_OUTEN_PWMA_EN_MASK (0xF00U)PWM_OUTEN_PWMA_EN_SHIFT (8U)PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)PWM_MASK_MASKX_MASK (0xFU)PWM_MASK_MASKX_SHIFT (0U)PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)PWM_MASK_MASKB_MASK (0xF0U)PWM_MASK_MASKB_SHIFT (4U)PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)PWM_MASK_MASKA_MASK (0xF00U)PWM_MASK_MASKA_SHIFT (8U)PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)PWM_MASK_UPDATE_MASK_MASK (0xF000U)PWM_MASK_UPDATE_MASK_SHIFT (12U)PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)PWM_SWCOUT_SM0OUT45_MASK (0x1U)PWM_SWCOUT_SM0OUT45_SHIFT (0U)PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)PWM_SWCOUT_SM0OUT23_MASK (0x2U)PWM_SWCOUT_SM0OUT23_SHIFT (1U)PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)PWM_SWCOUT_SM1OUT45_MASK (0x4U)PWM_SWCOUT_SM1OUT45_SHIFT (2U)PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)PWM_SWCOUT_SM1OUT23_MASK (0x8U)PWM_SWCOUT_SM1OUT23_SHIFT (3U)PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)PWM_SWCOUT_SM2OUT45_MASK (0x10U)PWM_SWCOUT_SM2OUT45_SHIFT (4U)PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)PWM_SWCOUT_SM2OUT23_MASK (0x20U)PWM_SWCOUT_SM2OUT23_SHIFT (5U)PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)PWM_SWCOUT_SM3OUT45_MASK (0x40U)PWM_SWCOUT_SM3OUT45_SHIFT (6U)ĻPWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)ŻPWM_SWCOUT_SM3OUT23_MASK (0x80U)ƻPWM_SWCOUT_SM3OUT23_SHIFT (7U)˻PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)лPWM_DTSRCSEL_SM0SEL45_MASK (0x3U)ѻPWM_DTSRCSEL_SM0SEL45_SHIFT (0U)ػPWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)ٻPWM_DTSRCSEL_SM0SEL23_MASK (0xCU)ڻPWM_DTSRCSEL_SM0SEL23_SHIFT (2U)PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)PWM_MCTRL_LDOK_MASK (0xFU)PWM_MCTRL_LDOK_SHIFT (0U)PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)PWM_MCTRL_CLDOK_MASK (0xF0U)PWM_MCTRL_CLDOK_SHIFT (4U)PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)PWM_MCTRL_RUN_MASK (0xF00U)PWM_MCTRL_RUN_SHIFT (8U)PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)PWM_MCTRL_IPOL_MASK (0xF000U)PWM_MCTRL_IPOL_SHIFT (12U)PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)PWM_MCTRL2_MONPLL_MASK (0x3U)PWM_MCTRL2_MONPLL_SHIFT (0U)¼PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)ǼPWM_FCTRL_FIE_MASK (0xFU)ȼPWM_FCTRL_FIE_SHIFT (0U)ͼPWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)μPWM_FCTRL_FSAFE_MASK (0xF0U)ϼPWM_FCTRL_FSAFE_SHIFT (4U)ټPWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)ڼPWM_FCTRL_FAUTO_MASK (0xF00U)ۼPWM_FCTRL_FAUTO_SHIFT (8U)PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)PWM_FCTRL_FLVL_MASK (0xF000U)PWM_FCTRL_FLVL_SHIFT (12U)PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)PWM_FSTS_FFLAG_MASK (0xFU)PWM_FSTS_FFLAG_SHIFT (0U)PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)PWM_FSTS_FFULL_MASK (0xF0U)PWM_FSTS_FFULL_SHIFT (4U)PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)PWM_FSTS_FFPIN_MASK (0xF00U)PWM_FSTS_FFPIN_SHIFT (8U)PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)PWM_FSTS_FHALF_MASK (0xF000U)PWM_FSTS_FHALF_SHIFT (12U)PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)PWM_FFILT_FILT_PER_MASK (0xFFU)PWM_FFILT_FILT_PER_SHIFT (0U)PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)PWM_FFILT_FILT_CNT_MASK (0x700U)PWM_FFILT_FILT_CNT_SHIFT (8U)PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)PWM_FFILT_GSTR_MASK (0x8000U)PWM_FFILT_GSTR_SHIFT (15U)PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)PWM_FTST_FTEST_MASK (0x1U)PWM_FTST_FTEST_SHIFT (0U)PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)PWM_FCTRL2_NOCOMB_MASK (0xFU)PWM_FCTRL2_NOCOMB_SHIFT (0U)PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)PWM1_BASE (0x403DC000u)PWM1 ((PWM_Type *)PWM1_BASE)PWM_BASE_ADDRS { 0u, PWM1_BASE }PWM_BASE_PTRS { (PWM_Type *)0u, PWM1 }ýPWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn } }ĽPWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn } }ŽPWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn } }ƽPWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn }ǽPWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn }ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)ROMC_ROMPATCHD_DATAX_SHIFT (0U)ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)ROMC_ROMPATCHD_COUNT (8U)ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)ROMC_ROMPATCHA_THUMBX_MASK (0x1U)ROMC_ROMPATCHA_THUMBX_SHIFT (0U)ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)ROMC_ROMPATCHA_ADDRX_SHIFT (1U)ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)ROMC_ROMPATCHA_COUNT (16U)ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)ROMC_ROMPATCHSR_SW_MASK (0x20000U)ROMC_ROMPATCHSR_SW_SHIFT (17U)ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)ROMC_BASE (0x40180000u)ROMC ((ROMC_Type *)ROMC_BASE)þROMC_BASE_ADDRS { ROMC_BASE }žROMC_BASE_PTRS { ROMC }RTWDOG_CS_STOP_MASK (0x1U)RTWDOG_CS_STOP_SHIFT (0U)RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)RTWDOG_CS_WAIT_MASK (0x2U)RTWDOG_CS_WAIT_SHIFT (1U)RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)RTWDOG_CS_DBG_MASK (0x4U)RTWDOG_CS_DBG_SHIFT (2U)RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)RTWDOG_CS_TST_MASK (0x18U)RTWDOG_CS_TST_SHIFT (3U)RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)RTWDOG_CS_UPDATE_MASK (0x20U)RTWDOG_CS_UPDATE_SHIFT (5U)RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)RTWDOG_CS_INT_MASK (0x40U)RTWDOG_CS_INT_SHIFT (6U)RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)RTWDOG_CS_EN_MASK (0x80U)RTWDOG_CS_EN_SHIFT (7U)RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)RTWDOG_CS_CLK_MASK (0x300U)RTWDOG_CS_CLK_SHIFT (8U)RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)RTWDOG_CS_RCS_MASK (0x400U)RTWDOG_CS_RCS_SHIFT (10U)RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)RTWDOG_CS_ULK_MASK (0x800U)RTWDOG_CS_ULK_SHIFT (11U)RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)RTWDOG_CS_PRES_MASK (0x1000U)RTWDOG_CS_PRES_SHIFT (12U)RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)RTWDOG_CS_CMD32EN_MASK (0x2000U)RTWDOG_CS_CMD32EN_SHIFT (13U)RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)RTWDOG_CS_FLG_MASK (0x4000U)¿RTWDOG_CS_FLG_SHIFT (14U)ǿRTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)ȿRTWDOG_CS_WIN_MASK (0x8000U)ɿRTWDOG_CS_WIN_SHIFT (15U)οRTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)ӿRTWDOG_CNT_CNTLOW_MASK (0xFFU)ԿRTWDOG_CNT_CNTLOW_SHIFT (0U)տRTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)ֿRTWDOG_CNT_CNTHIGH_MASK (0xFF00U)׿RTWDOG_CNT_CNTHIGH_SHIFT (8U)ؿRTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)ݿRTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)޿RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)߿RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)RTWDOG_WIN_WINLOW_MASK (0xFFU)RTWDOG_WIN_WINLOW_SHIFT (0U)RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)RTWDOG_WIN_WINHIGH_MASK (0xFF00U)RTWDOG_WIN_WINHIGH_SHIFT (8U)RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)RTWDOG_BASE (0x400BC000u)RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)RTWDOG_BASE_ADDRS { RTWDOG_BASE }RTWDOG_BASE_PTRS { RTWDOG }RTWDOG_IRQS { RTWDOG_IRQn }RTWDOG_UPDATE_KEY (0xD928C520U)RTWDOG_REFRESH_KEY (0xB480A602U)SNVS_HPLR_ZMK_WSL_MASK (0x1U)SNVS_HPLR_ZMK_WSL_SHIFT (0U)SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)SNVS_HPLR_ZMK_RSL_MASK (0x2U)SNVS_HPLR_ZMK_RSL_SHIFT (1U)SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)SNVS_HPLR_SRTC_SL_MASK (0x4U)SNVS_HPLR_SRTC_SL_SHIFT (2U)SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)SNVS_HPLR_LPCALB_SL_MASK (0x8U)SNVS_HPLR_LPCALB_SL_SHIFT (3U)SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)SNVS_HPLR_MC_SL_MASK (0x10U)SNVS_HPLR_MC_SL_SHIFT (4U)SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)SNVS_HPLR_GPR_SL_MASK (0x20U)SNVS_HPLR_GPR_SL_SHIFT (5U)SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)SNVS_HPLR_LPSVCR_SL_MASK (0x40U)SNVS_HPLR_LPSVCR_SL_SHIFT (6U)SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)SNVS_HPLR_LPTDCR_SL_MASK (0x100U)SNVS_HPLR_LPTDCR_SL_SHIFT (8U)SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)SNVS_HPLR_MKS_SL_MASK (0x200U)SNVS_HPLR_MKS_SL_SHIFT (9U)SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)SNVS_HPLR_HPSVCR_L_MASK (0x10000U)SNVS_HPLR_HPSVCR_L_SHIFT (16U)SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)SNVS_HPLR_HPSICR_L_MASK (0x20000U)SNVS_HPLR_HPSICR_L_SHIFT (17U)SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)SNVS_HPLR_HAC_L_MASK (0x40000U)SNVS_HPLR_HAC_L_SHIFT (18U)SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)SNVS_HPCOMR_SSM_ST_MASK (0x1U)SNVS_HPCOMR_SSM_ST_SHIFT (0U)SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)SNVS_HPCOMR_LP_SWR_MASK (0x10U)SNVS_HPCOMR_LP_SWR_SHIFT (4U)SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)SNVS_HPCOMR_SW_SV_MASK (0x100U)SNVS_HPCOMR_SW_SV_SHIFT (8U)SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)SNVS_HPCOMR_SW_FSV_MASK (0x200U)SNVS_HPCOMR_SW_FSV_SHIFT (9U)SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)SNVS_HPCOMR_SW_LPSV_MASK (0x400U)SNVS_HPCOMR_SW_LPSV_SHIFT (10U)SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)SNVS_HPCOMR_MKS_EN_MASK (0x2000U)SNVS_HPCOMR_MKS_EN_SHIFT (13U)SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)SNVS_HPCOMR_HAC_EN_MASK (0x10000U)SNVS_HPCOMR_HAC_EN_SHIFT (16U)SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)SNVS_HPCOMR_HAC_STOP_SHIFT (19U)SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)SNVS_HPCR_RTC_EN_MASK (0x1U)SNVS_HPCR_RTC_EN_SHIFT (0U)SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)SNVS_HPCR_HPTA_EN_MASK (0x2U)SNVS_HPCR_HPTA_EN_SHIFT (1U)SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)SNVS_HPCR_DIS_PI_MASK (0x4U)SNVS_HPCR_DIS_PI_SHIFT (2U)SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)SNVS_HPCR_PI_EN_MASK (0x8U)SNVS_HPCR_PI_EN_SHIFT (3U)SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)SNVS_HPCR_PI_FREQ_MASK (0xF0U)SNVS_HPCR_PI_FREQ_SHIFT (4U)SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)SNVS_HPCR_HPCALB_EN_MASK (0x100U)SNVS_HPCR_HPCALB_EN_SHIFT (8U)SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)SNVS_HPCR_HPCALB_VAL_SHIFT (10U)SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)SNVS_HPCR_HP_TS_MASK (0x10000U)SNVS_HPCR_HP_TS_SHIFT (16U)SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)SNVS_HPCR_BTN_CONFIG_SHIFT (24U)SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)SNVS_HPCR_BTN_MASK_MASK (0x8000000U)SNVS_HPCR_BTN_MASK_SHIFT (27U)SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)SNVS_HPSICR_SV0_EN_MASK (0x1U)SNVS_HPSICR_SV0_EN_SHIFT (0U)SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)SNVS_HPSICR_SV1_EN_MASK (0x2U)SNVS_HPSICR_SV1_EN_SHIFT (1U)SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)SNVS_HPSICR_SV2_EN_MASK (0x4U)SNVS_HPSICR_SV2_EN_SHIFT (2U)SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)SNVS_HPSICR_SV3_EN_MASK (0x8U)SNVS_HPSICR_SV3_EN_SHIFT (3U)SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)SNVS_HPSICR_SV4_EN_MASK (0x10U)SNVS_HPSICR_SV4_EN_SHIFT (4U)SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)SNVS_HPSICR_SV5_EN_MASK (0x20U)SNVS_HPSICR_SV5_EN_SHIFT (5U)SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)SNVS_HPSICR_LPSVI_EN_SHIFT (31U)SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)SNVS_HPSVCR_SV0_CFG_MASK (0x1U)SNVS_HPSVCR_SV0_CFG_SHIFT (0U)SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)SNVS_HPSVCR_SV1_CFG_MASK (0x2U)SNVS_HPSVCR_SV1_CFG_SHIFT (1U)SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)SNVS_HPSVCR_SV2_CFG_MASK (0x4U)SNVS_HPSVCR_SV2_CFG_SHIFT (2U)SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)SNVS_HPSVCR_SV3_CFG_MASK (0x8U)SNVS_HPSVCR_SV3_CFG_SHIFT (3U)SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)SNVS_HPSVCR_SV4_CFG_MASK (0x10U)SNVS_HPSVCR_SV4_CFG_SHIFT (4U)SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)SNVS_HPSVCR_SV5_CFG_MASK (0x60U)SNVS_HPSVCR_SV5_CFG_SHIFT (5U)SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)SNVS_HPSR_HPTA_MASK (0x1U)SNVS_HPSR_HPTA_SHIFT (0U)SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)SNVS_HPSR_PI_MASK (0x2U)SNVS_HPSR_PI_SHIFT (1U)SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)SNVS_HPSR_LPDIS_MASK (0x10U)SNVS_HPSR_LPDIS_SHIFT (4U)SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)SNVS_HPSR_BTN_MASK (0x40U)SNVS_HPSR_BTN_SHIFT (6U)SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)SNVS_HPSR_BI_MASK (0x80U)SNVS_HPSR_BI_SHIFT (7U)SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)SNVS_HPSR_SSM_STATE_MASK (0xF00U)SNVS_HPSR_SSM_STATE_SHIFT (8U)SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)SNVS_HPSR_ZMK_ZERO_SHIFT (31U)SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)SNVS_HPSVSR_SV0_MASK (0x1U)SNVS_HPSVSR_SV0_SHIFT (0U)SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)SNVS_HPSVSR_SV1_MASK (0x2U)SNVS_HPSVSR_SV1_SHIFT (1U)SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)SNVS_HPSVSR_SV2_MASK (0x4U)SNVS_HPSVSR_SV2_SHIFT (2U)SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)SNVS_HPSVSR_SV3_MASK (0x8U)SNVS_HPSVSR_SV3_SHIFT (3U)SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)SNVS_HPSVSR_SV4_MASK (0x10U)SNVS_HPSVSR_SV4_SHIFT (4U)SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)SNVS_HPSVSR_SV5_MASK (0x20U)SNVS_HPSVSR_SV5_SHIFT (5U)SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)SNVS_HPSVSR_SW_SV_MASK (0x2000U)SNVS_HPSVSR_SW_SV_SHIFT (13U)SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)SNVS_HPSVSR_SW_FSV_MASK (0x4000U)SNVS_HPSVSR_SW_FSV_SHIFT (14U)SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)SNVS_HPSVSR_SW_LPSV_SHIFT (15U)SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)SNVS_HPRTCMR_RTC_MASK (0x7FFFU)SNVS_HPRTCMR_RTC_SHIFT (0U)SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)SNVS_HPRTCLR_RTC_SHIFT (0U)SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)SNVS_HPTAMR_HPTA_MS_SHIFT (0U)SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)SNVS_HPTALR_HPTA_LS_SHIFT (0U)SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)SNVS_LPLR_ZMK_WHL_MASK (0x1U)SNVS_LPLR_ZMK_WHL_SHIFT (0U)SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)SNVS_LPLR_ZMK_RHL_MASK (0x2U)SNVS_LPLR_ZMK_RHL_SHIFT (1U)SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)SNVS_LPLR_SRTC_HL_MASK (0x4U)SNVS_LPLR_SRTC_HL_SHIFT (2U)SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)SNVS_LPLR_LPCALB_HL_MASK (0x8U)SNVS_LPLR_LPCALB_HL_SHIFT (3U)SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)SNVS_LPLR_MC_HL_MASK (0x10U)SNVS_LPLR_MC_HL_SHIFT (4U)SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)SNVS_LPLR_GPR_HL_MASK (0x20U)SNVS_LPLR_GPR_HL_SHIFT (5U)SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)SNVS_LPLR_LPSVCR_HL_MASK (0x40U)SNVS_LPLR_LPSVCR_HL_SHIFT (6U)SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)SNVS_LPLR_LPTDCR_HL_MASK (0x100U)SNVS_LPLR_LPTDCR_HL_SHIFT (8U)SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)SNVS_LPLR_MKS_HL_MASK (0x200U)SNVS_LPLR_MKS_HL_SHIFT (9U)SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)SNVS_LPCR_SRTC_ENV_MASK (0x1U)SNVS_LPCR_SRTC_ENV_SHIFT (0U)SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)SNVS_LPCR_LPTA_EN_MASK (0x2U)SNVS_LPCR_LPTA_EN_SHIFT (1U)SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)SNVS_LPCR_MC_ENV_MASK (0x4U)SNVS_LPCR_MC_ENV_SHIFT (2U)SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)SNVS_LPCR_LPWUI_EN_MASK (0x8U)SNVS_LPCR_LPWUI_EN_SHIFT (3U)SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)SNVS_LPCR_DP_EN_MASK (0x20U)SNVS_LPCR_DP_EN_SHIFT (5U)SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)SNVS_LPCR_TOP_MASK (0x40U)SNVS_LPCR_TOP_SHIFT (6U)SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)SNVS_LPCR_LPCALB_EN_MASK (0x100U)SNVS_LPCR_LPCALB_EN_SHIFT (8U)SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)SNVS_LPCR_LPCALB_VAL_SHIFT (10U)SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)SNVS_LPCR_DEBOUNCE_SHIFT (18U)SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)SNVS_LPCR_ON_TIME_MASK (0x300000U)SNVS_LPCR_ON_TIME_SHIFT (20U)SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)SNVS_LPCR_PK_EN_MASK (0x400000U)SNVS_LPCR_PK_EN_SHIFT (22U)SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)SNVS_LPSVCR_SV0_EN_MASK (0x1U)SNVS_LPSVCR_SV0_EN_SHIFT (0U)SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)SNVS_LPSVCR_SV1_EN_MASK (0x2U)SNVS_LPSVCR_SV1_EN_SHIFT (1U)SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)SNVS_LPSVCR_SV2_EN_MASK (0x4U)SNVS_LPSVCR_SV2_EN_SHIFT (2U)SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)SNVS_LPSVCR_SV3_EN_MASK (0x8U)SNVS_LPSVCR_SV3_EN_SHIFT (3U)SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)SNVS_LPSVCR_SV4_EN_MASK (0x10U)SNVS_LPSVCR_SV4_EN_SHIFT (4U)SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)SNVS_LPSVCR_SV5_EN_MASK (0x20U)SNVS_LPSVCR_SV5_EN_SHIFT (5U)SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)SNVS_LPTDCR_MCR_EN_MASK (0x4U)SNVS_LPTDCR_MCR_EN_SHIFT (2U)SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)SNVS_LPTDCR_ET1_EN_MASK (0x200U)SNVS_LPTDCR_ET1_EN_SHIFT (9U)SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)SNVS_LPTDCR_ET1P_MASK (0x800U)SNVS_LPTDCR_ET1P_SHIFT (11U)SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)SNVS_LPTDCR_OSCB_MASK (0x10000000U)SNVS_LPTDCR_OSCB_SHIFT (28U)SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)SNVS_LPSR_LPTA_MASK (0x1U)SNVS_LPSR_LPTA_SHIFT (0U)SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)SNVS_LPSR_SRTCR_MASK (0x2U)SNVS_LPSR_SRTCR_SHIFT (1U)SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)SNVS_LPSR_MCR_MASK (0x4U)SNVS_LPSR_MCR_SHIFT (2U)SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)SNVS_LPSR_PGD_MASK (0x8U)SNVS_LPSR_PGD_SHIFT (3U)SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)SNVS_LPSR_ET1D_MASK (0x200U)SNVS_LPSR_ET1D_SHIFT (9U)SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)SNVS_LPSR_ESVD_MASK (0x10000U)SNVS_LPSR_ESVD_SHIFT (16U)SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)SNVS_LPSR_EO_MASK (0x20000U)SNVS_LPSR_EO_SHIFT (17U)SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)SNVS_LPSR_SPO_MASK (0x40000U)SNVS_LPSR_SPO_SHIFT (18U)SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)SNVS_LPSR_SED_MASK (0x100000U)SNVS_LPSR_SED_SHIFT (20U)SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)SNVS_LPSR_LPNS_MASK (0x40000000U)SNVS_LPSR_LPNS_SHIFT (30U)SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)SNVS_LPSR_LPS_MASK (0x80000000U)SNVS_LPSR_LPS_SHIFT (31U)SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)SNVS_LPSRTCMR_SRTC_SHIFT (0U)SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)SNVS_LPSRTCLR_SRTC_SHIFT (0U)SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)SNVS_LPTAR_LPTA_SHIFT (0U)SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)SNVS_LPPGDR_PGD_SHIFT (0U)SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)SNVS_LPZMKR_ZMK_SHIFT (0U)SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)SNVS_LPZMKR_COUNT (8U)SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)SNVS_LPGPR_ALIAS_COUNT (4U)SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR_GPR_SHIFT (0U)SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)SNVS_LPGPR_COUNT (4U)SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)SNVS_HPVIDR1_IP_ID_SHIFT (16U)SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)SNVS_HPVIDR2_ECO_REV_SHIFT (8U)SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)SNVS_HPVIDR2_IP_ERA_SHIFT (24U)SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)SNVS_BASE (0x400D4000u)SNVS ((SNVS_Type *)SNVS_BASE)SNVS_BASE_ADDRS { SNVS_BASE }SNVS_BASE_PTRS { SNVS }SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }SPDIF_SCR_USRC_SEL_MASK (0x3U)SPDIF_SCR_USRC_SEL_SHIFT (0U)SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)SPDIF_SCR_TXSEL_MASK (0x1CU)SPDIF_SCR_TXSEL_SHIFT (2U)SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)SPDIF_SCR_VALCTRL_MASK (0x20U)SPDIF_SCR_VALCTRL_SHIFT (5U)SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)SPDIF_SCR_DMA_TX_EN_MASK (0x100U)SPDIF_SCR_DMA_TX_EN_SHIFT (8U)SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)SPDIF_SCR_DMA_RX_EN_MASK (0x200U)SPDIF_SCR_DMA_RX_EN_SHIFT (9U)SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)SPDIF_SCR_SOFT_RESET_MASK (0x1000U)SPDIF_SCR_SOFT_RESET_SHIFT (12U)SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)SPDIF_SCR_LOW_POWER_MASK (0x2000U)SPDIF_SCR_LOW_POWER_SHIFT (13U)SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)SPDIF_SCR_RXFIFO_RST_SHIFT (21U)SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)SPDIF_SRCD_USYNCMODE_MASK (0x2U)SPDIF_SRCD_USYNCMODE_SHIFT (1U)SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)SPDIF_SRPC_GAINSEL_MASK (0x38U)SPDIF_SRPC_GAINSEL_SHIFT (3U)SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)SPDIF_SRPC_LOCK_MASK (0x40U)SPDIF_SRPC_LOCK_SHIFT (6U)SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)SPDIF_SIE_RXFIFOFUL_MASK (0x1U)SPDIF_SIE_RXFIFOFUL_SHIFT (0U)SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)SPDIF_SIE_TXEM_MASK (0x2U)SPDIF_SIE_TXEM_SHIFT (1U)SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)SPDIF_SIE_LOCKLOSS_MASK (0x4U)SPDIF_SIE_LOCKLOSS_SHIFT (2U)SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)SPDIF_SIE_RXFIFORESYN_MASK (0x8U)SPDIF_SIE_RXFIFORESYN_SHIFT (3U)SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)SPDIF_SIE_UQERR_MASK (0x20U)SPDIF_SIE_UQERR_SHIFT (5U)SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)SPDIF_SIE_UQSYNC_MASK (0x40U)SPDIF_SIE_UQSYNC_SHIFT (6U)SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)SPDIF_SIE_QRXOV_MASK (0x80U)SPDIF_SIE_QRXOV_SHIFT (7U)SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)SPDIF_SIE_QRXFUL_MASK (0x100U)SPDIF_SIE_QRXFUL_SHIFT (8U)SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)SPDIF_SIE_URXOV_MASK (0x200U)SPDIF_SIE_URXOV_SHIFT (9U)SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)SPDIF_SIE_URXFUL_MASK (0x400U)SPDIF_SIE_URXFUL_SHIFT (10U)SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)SPDIF_SIE_BITERR_MASK (0x4000U)SPDIF_SIE_BITERR_SHIFT (14U)SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)SPDIF_SIE_SYMERR_MASK (0x8000U)SPDIF_SIE_SYMERR_SHIFT (15U)SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)SPDIF_SIE_VALNOGOOD_MASK (0x10000U)SPDIF_SIE_VALNOGOOD_SHIFT (16U)SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)SPDIF_SIE_CNEW_MASK (0x20000U)SPDIF_SIE_CNEW_SHIFT (17U)SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)SPDIF_SIE_TXRESYN_MASK (0x40000U)SPDIF_SIE_TXRESYN_SHIFT (18U)SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)SPDIF_SIE_TXUNOV_MASK (0x80000U)SPDIF_SIE_TXUNOV_SHIFT (19U)SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)SPDIF_SIE_LOCK_MASK (0x100000U)SPDIF_SIE_LOCK_SHIFT (20U)SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)SPDIF_SIC_LOCKLOSS_MASK (0x4U)SPDIF_SIC_LOCKLOSS_SHIFT (2U)SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)SPDIF_SIC_RXFIFORESYN_MASK (0x8U)SPDIF_SIC_RXFIFORESYN_SHIFT (3U)SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)SPDIF_SIC_UQERR_MASK (0x20U)SPDIF_SIC_UQERR_SHIFT (5U)SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)SPDIF_SIC_UQSYNC_MASK (0x40U)SPDIF_SIC_UQSYNC_SHIFT (6U)SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)SPDIF_SIC_QRXOV_MASK (0x80U)SPDIF_SIC_QRXOV_SHIFT (7U)SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)SPDIF_SIC_URXOV_MASK (0x200U)SPDIF_SIC_URXOV_SHIFT (9U)SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)SPDIF_SIC_BITERR_MASK (0x4000U)SPDIF_SIC_BITERR_SHIFT (14U)SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)SPDIF_SIC_SYMERR_MASK (0x8000U)SPDIF_SIC_SYMERR_SHIFT (15U)SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)SPDIF_SIC_VALNOGOOD_MASK (0x10000U)SPDIF_SIC_VALNOGOOD_SHIFT (16U)SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)SPDIF_SIC_CNEW_MASK (0x20000U)SPDIF_SIC_CNEW_SHIFT (17U)SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)SPDIF_SIC_TXRESYN_MASK (0x40000U)SPDIF_SIC_TXRESYN_SHIFT (18U)SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)SPDIF_SIC_TXUNOV_MASK (0x80000U)SPDIF_SIC_TXUNOV_SHIFT (19U)SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)SPDIF_SIC_LOCK_MASK (0x100000U)SPDIF_SIC_LOCK_SHIFT (20U)SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)SPDIF_SIS_RXFIFOFUL_MASK (0x1U)SPDIF_SIS_RXFIFOFUL_SHIFT (0U)SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)SPDIF_SIS_TXEM_MASK (0x2U)SPDIF_SIS_TXEM_SHIFT (1U)SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)SPDIF_SIS_LOCKLOSS_MASK (0x4U)SPDIF_SIS_LOCKLOSS_SHIFT (2U)SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)SPDIF_SIS_RXFIFORESYN_MASK (0x8U)SPDIF_SIS_RXFIFORESYN_SHIFT (3U)SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)SPDIF_SIS_UQERR_MASK (0x20U)SPDIF_SIS_UQERR_SHIFT (5U)SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)SPDIF_SIS_UQSYNC_MASK (0x40U)SPDIF_SIS_UQSYNC_SHIFT (6U)SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)SPDIF_SIS_QRXOV_MASK (0x80U)SPDIF_SIS_QRXOV_SHIFT (7U)SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)SPDIF_SIS_QRXFUL_MASK (0x100U)SPDIF_SIS_QRXFUL_SHIFT (8U)SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)SPDIF_SIS_URXOV_MASK (0x200U)SPDIF_SIS_URXOV_SHIFT (9U)SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)SPDIF_SIS_URXFUL_MASK (0x400U)SPDIF_SIS_URXFUL_SHIFT (10U)SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)SPDIF_SIS_BITERR_MASK (0x4000U)SPDIF_SIS_BITERR_SHIFT (14U)SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)SPDIF_SIS_SYMERR_MASK (0x8000U)SPDIF_SIS_SYMERR_SHIFT (15U)SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)SPDIF_SIS_VALNOGOOD_MASK (0x10000U)SPDIF_SIS_VALNOGOOD_SHIFT (16U)SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)SPDIF_SIS_CNEW_MASK (0x20000U)SPDIF_SIS_CNEW_SHIFT (17U)SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)SPDIF_SIS_TXRESYN_MASK (0x40000U)SPDIF_SIS_TXRESYN_SHIFT (18U)SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)SPDIF_SIS_TXUNOV_MASK (0x80000U)SPDIF_SIS_TXUNOV_SHIFT (19U)SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)SPDIF_SIS_LOCK_MASK (0x100000U)SPDIF_SIS_LOCK_SHIFT (20U)SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)SPDIF_SRL_RXDATALEFT_SHIFT (0U)SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)SPDIF_SRR_RXDATARIGHT_SHIFT (0U)SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)SPDIF_SRU_RXUCHANNEL_SHIFT (0U)SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)SPDIF_STL_TXDATALEFT_SHIFT (0U)SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)SPDIF_STR_TXDATARIGHT_SHIFT (0U)SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)SPDIF_SRFM_FREQMEAS_SHIFT (0U)SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)SPDIF_STC_TXCLK_DF_MASK (0x7FU)SPDIF_STC_TXCLK_DF_SHIFT (0U)SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)SPDIF_STC_SYSCLK_DF_SHIFT (11U)SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)SPDIF_BASE (0x40380000u)SPDIF ((SPDIF_Type *)SPDIF_BASE)SPDIF_BASE_ADDRS { SPDIF_BASE }SPDIF_BASE_PTRS { SPDIF }SPDIF_IRQS { SPDIF_IRQn }SRC_SCR_LOCKUP_RST_MASK (0x10U)SRC_SCR_LOCKUP_RST_SHIFT (4U)SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK)SRC_SCR_MASK_WDOG_RST_MASK (0x780U)SRC_SCR_MASK_WDOG_RST_SHIFT (7U)SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)SRC_SCR_CORE0_RST_MASK (0x2000U)SRC_SCR_CORE0_RST_SHIFT (13U)SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)SRC_SCR_CORE0_DBG_RST_SHIFT (17U)SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)SRC_SBMR1_BOOT_CFG1_SHIFT (0U)SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)SRC_SBMR1_BOOT_CFG2_SHIFT (8U)SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)SRC_SBMR1_BOOT_CFG3_SHIFT (16U)SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)SRC_SBMR1_BOOT_CFG4_SHIFT (24U)SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)SRC_SRSR_IPP_RESET_B_MASK (0x1U)SRC_SRSR_IPP_RESET_B_SHIFT (0U)SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)SRC_SRSR_LOCKUP_MASK (0x2U)SRC_SRSR_LOCKUP_SHIFT (1U)SRC_SRSR_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SHIFT)) & SRC_SRSR_LOCKUP_MASK)SRC_SRSR_CSU_RESET_B_MASK (0x4U)SRC_SRSR_CSU_RESET_B_SHIFT (2U)SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)SRC_SRSR_WDOG_RST_B_MASK (0x10U)SRC_SRSR_WDOG_RST_B_SHIFT (4U)SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)SRC_SRSR_JTAG_RST_B_MASK (0x20U)SRC_SRSR_JTAG_RST_B_SHIFT (5U)SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)SRC_SRSR_JTAG_SW_RST_MASK (0x40U)SRC_SRSR_JTAG_SW_RST_SHIFT (6U)SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)SRC_SRSR_WDOG3_RST_B_MASK (0x80U)SRC_SRSR_WDOG3_RST_B_SHIFT (7U)SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)SRC_SBMR2_SEC_CONFIG_MASK (0x3U)SRC_SBMR2_SEC_CONFIG_SHIFT (0U)SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)SRC_SBMR2_BMOD_MASK (0x3000000U)SRC_SBMR2_BMOD_SHIFT (24U)SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)SRC_GPR_COUNT (10U)SRC_BASE (0x400F8000u)SRC ((SRC_Type *)SRC_BASE)SRC_BASE_ADDRS { SRC_BASE }SRC_BASE_PTRS { SRC }SRC_IRQS { SRC_IRQn }SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASKSRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFTSRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASKSRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFTSRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASKSRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFTSRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASKSRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFTSRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASKSRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFTSRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK | SRC_SRSR_JTAG_SW_RST_MASK | SRC_SRSR_JTAG_RST_B_MASK | SRC_SRSR_WDOG_RST_B_MASK | SRC_SRSR_IPP_USER_RESET_B_MASK | SRC_SRSR_CSU_RESET_B_MASK | SRC_SRSR_LOCKUP_MASK | SRC_SRSR_IPP_RESET_B_MASK)TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)TEMPMON_BASE (0x400D8000u)TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)TEMPMON_BASE_ADDRS { TEMPMON_BASE }TEMPMON_BASE_PTRS { TEMPMON }TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)TMR_COMP1_COMPARISON_1_SHIFT (0U)TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)TMR_COMP1_COUNT (4U)TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)TMR_COMP2_COMPARISON_2_SHIFT (0U)TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)TMR_COMP2_COUNT (4U)TMR_CAPT_CAPTURE_MASK (0xFFFFU)TMR_CAPT_CAPTURE_SHIFT (0U)TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)TMR_CAPT_COUNT (4U)TMR_LOAD_LOAD_MASK (0xFFFFU)TMR_LOAD_LOAD_SHIFT (0U)TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)TMR_LOAD_COUNT (4U)TMR_HOLD_HOLD_MASK (0xFFFFU)TMR_HOLD_HOLD_SHIFT (0U)TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)TMR_HOLD_COUNT (4U)TMR_CNTR_COUNTER_MASK (0xFFFFU)TMR_CNTR_COUNTER_SHIFT (0U)TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)TMR_CNTR_COUNT (4U)TMR_CTRL_OUTMODE_MASK (0x7U)TMR_CTRL_OUTMODE_SHIFT (0U)TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)TMR_CTRL_COINIT_MASK (0x8U)TMR_CTRL_COINIT_SHIFT (3U)TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)TMR_CTRL_DIR_MASK (0x10U)TMR_CTRL_DIR_SHIFT (4U)TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)TMR_CTRL_LENGTH_MASK (0x20U)TMR_CTRL_LENGTH_SHIFT (5U)TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)TMR_CTRL_ONCE_MASK (0x40U)TMR_CTRL_ONCE_SHIFT (6U)TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)TMR_CTRL_SCS_MASK (0x180U)TMR_CTRL_SCS_SHIFT (7U)TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)TMR_CTRL_PCS_MASK (0x1E00U)TMR_CTRL_PCS_SHIFT (9U)TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)TMR_CTRL_CM_MASK (0xE000U)TMR_CTRL_CM_SHIFT (13U)TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)TMR_CTRL_COUNT (4U)TMR_SCTRL_OEN_MASK (0x1U)TMR_SCTRL_OEN_SHIFT (0U)TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)TMR_SCTRL_OPS_MASK (0x2U)TMR_SCTRL_OPS_SHIFT (1U)TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)TMR_SCTRL_FORCE_MASK (0x4U)TMR_SCTRL_FORCE_SHIFT (2U)TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)TMR_SCTRL_VAL_MASK (0x8U)TMR_SCTRL_VAL_SHIFT (3U)TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)TMR_SCTRL_EEOF_MASK (0x10U)TMR_SCTRL_EEOF_SHIFT (4U)TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)TMR_SCTRL_MSTR_MASK (0x20U)TMR_SCTRL_MSTR_SHIFT (5U)TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)TMR_SCTRL_INPUT_MASK (0x100U)TMR_SCTRL_INPUT_SHIFT (8U)TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)TMR_SCTRL_IPS_MASK (0x200U)TMR_SCTRL_IPS_SHIFT (9U)TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)TMR_SCTRL_IEFIE_MASK (0x400U)TMR_SCTRL_IEFIE_SHIFT (10U)TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)TMR_SCTRL_IEF_MASK (0x800U)TMR_SCTRL_IEF_SHIFT (11U)TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)TMR_SCTRL_TOFIE_MASK (0x1000U)TMR_SCTRL_TOFIE_SHIFT (12U)TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)TMR_SCTRL_TOF_MASK (0x2000U)TMR_SCTRL_TOF_SHIFT (13U)TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)TMR_SCTRL_TCFIE_MASK (0x4000U)TMR_SCTRL_TCFIE_SHIFT (14U)TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)TMR_SCTRL_TCF_MASK (0x8000U)TMR_SCTRL_TCF_SHIFT (15U)TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)TMR_SCTRL_COUNT (4U)TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)TMR_CMPLD1_COUNT (4U)TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)TMR_CMPLD2_COUNT (4U)TMR_CSCTRL_CL1_MASK (0x3U)TMR_CSCTRL_CL1_SHIFT (0U)TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)TMR_CSCTRL_CL2_MASK (0xCU)TMR_CSCTRL_CL2_SHIFT (2U)TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)TMR_CSCTRL_TCF1_MASK (0x10U)TMR_CSCTRL_TCF1_SHIFT (4U)TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)TMR_CSCTRL_TCF2_MASK (0x20U)TMR_CSCTRL_TCF2_SHIFT (5U)TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)TMR_CSCTRL_TCF1EN_MASK (0x40U)TMR_CSCTRL_TCF1EN_SHIFT (6U)TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)TMR_CSCTRL_TCF2EN_MASK (0x80U)TMR_CSCTRL_TCF2EN_SHIFT (7U)TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)TMR_CSCTRL_UP_MASK (0x200U)TMR_CSCTRL_UP_SHIFT (9U)TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)TMR_CSCTRL_TCI_MASK (0x400U)TMR_CSCTRL_TCI_SHIFT (10U)TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)TMR_CSCTRL_ROC_MASK (0x800U)TMR_CSCTRL_ROC_SHIFT (11U)TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)TMR_CSCTRL_ALT_LOAD_SHIFT (12U)TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)TMR_CSCTRL_FAULT_MASK (0x2000U)TMR_CSCTRL_FAULT_SHIFT (13U)TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)TMR_CSCTRL_DBG_EN_MASK (0xC000U)TMR_CSCTRL_DBG_EN_SHIFT (14U)TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)TMR_CSCTRL_COUNT (4U)TMR_FILT_FILT_PER_MASK (0xFFU)TMR_FILT_FILT_PER_SHIFT (0U)TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)TMR_FILT_FILT_CNT_MASK (0x700U)TMR_FILT_FILT_CNT_SHIFT (8U)TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)TMR_FILT_COUNT (4U)TMR_DMA_IEFDE_MASK (0x1U)TMR_DMA_IEFDE_SHIFT (0U)TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)TMR_DMA_CMPLD1DE_MASK (0x2U)TMR_DMA_CMPLD1DE_SHIFT (1U)TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)TMR_DMA_CMPLD2DE_MASK (0x4U)TMR_DMA_CMPLD2DE_SHIFT (2U)TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)TMR_DMA_COUNT (4U)TMR_ENBL_ENBL_MASK (0xFU)TMR_ENBL_ENBL_SHIFT (0U)TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)TMR_ENBL_COUNT (4U)TMR1_BASE (0x401DC000u)TMR1 ((TMR_Type *)TMR1_BASE)TMR_BASE_ADDRS { 0u, TMR1_BASE }TMR_BASE_PTRS { (TMR_Type *)0u, TMR1 }TMR_IRQS { NotAvail_IRQn, TMR1_IRQn }TRNG_MCTL_SAMP_MODE_MASK (0x3U)TRNG_MCTL_SAMP_MODE_SHIFT (0U)TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)TRNG_MCTL_OSC_DIV_MASK (0xCU)TRNG_MCTL_OSC_DIV_SHIFT (2U)TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)TRNG_MCTL_UNUSED4_MASK (0x10U)TRNG_MCTL_UNUSED4_SHIFT (4U)TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)TRNG_MCTL_TRNG_ACC_MASK (0x20U)TRNG_MCTL_TRNG_ACC_SHIFT (5U)TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)TRNG_MCTL_RST_DEF_MASK (0x40U)TRNG_MCTL_RST_DEF_SHIFT (6U)TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)TRNG_MCTL_FOR_SCLK_MASK (0x80U)TRNG_MCTL_FOR_SCLK_SHIFT (7U)TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)TRNG_MCTL_FCT_FAIL_MASK (0x100U)TRNG_MCTL_FCT_FAIL_SHIFT (8U)TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)TRNG_MCTL_FCT_VAL_MASK (0x200U)TRNG_MCTL_FCT_VAL_SHIFT (9U)TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)TRNG_MCTL_ENT_VAL_MASK (0x400U)TRNG_MCTL_ENT_VAL_SHIFT (10U)TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)TRNG_MCTL_TST_OUT_MASK (0x800U)TRNG_MCTL_TST_OUT_SHIFT (11U)TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)TRNG_MCTL_ERR_MASK (0x1000U)TRNG_MCTL_ERR_SHIFT (12U)TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)TRNG_MCTL_TSTOP_OK_MASK (0x2000U)TRNG_MCTL_TSTOP_OK_SHIFT (13U)TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)TRNG_MCTL_LRUN_CONT_MASK (0x4000U)TRNG_MCTL_LRUN_CONT_SHIFT (14U)TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)TRNG_MCTL_PRGM_MASK (0x10000U)TRNG_MCTL_PRGM_SHIFT (16U)TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)TRNG_SCMISC_LRUN_MAX_SHIFT (0U)TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)TRNG_SCMISC_RTY_CT_MASK (0xF0000U)TRNG_SCMISC_RTY_CT_SHIFT (16U)TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)TRNG_PKRRNG_PKR_RNG_SHIFT (0U)TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)TRNG_PKRMAX_PKR_MAX_SHIFT (0U)TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)TRNG_PKRSQ_PKR_SQ_SHIFT (0U)TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)TRNG_SDCTL_ENT_DLY_SHIFT (16U)TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)TRNG_SBLIM_SB_LIM_MASK (0x3FFU)TRNG_SBLIM_SB_LIM_SHIFT (0U)TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)TRNG_TOTSAM_TOT_SAM_SHIFT (0U)TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)TRNG_FRQCNT_FRQ_CT_SHIFT (0U)TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)TRNG_SCMC_MONO_CT_MASK (0xFFFFU)TRNG_SCMC_MONO_CT_SHIFT (0U)TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)TRNG_SCML_MONO_MAX_MASK (0xFFFFU)TRNG_SCML_MONO_MAX_SHIFT (0U)TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)TRNG_SCML_MONO_RNG_SHIFT (16U)TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)TRNG_SCR1C_R1_0_CT_SHIFT (0U)TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)TRNG_SCR1C_R1_1_CT_SHIFT (16U)TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)TRNG_SCR1L_RUN1_MAX_SHIFT (0U)TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)TRNG_SCR1L_RUN1_RNG_SHIFT (16U)TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)TRNG_SCR2C_R2_0_CT_SHIFT (0U)TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)TRNG_SCR2C_R2_1_CT_SHIFT (16U)TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)TRNG_SCR2L_RUN2_MAX_SHIFT (0U)TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)TRNG_SCR2L_RUN2_RNG_SHIFT (16U)TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)TRNG_SCR3C_R3_0_CT_SHIFT (0U)TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)TRNG_SCR3C_R3_1_CT_SHIFT (16U)TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)TRNG_SCR3L_RUN3_MAX_SHIFT (0U)TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)TRNG_SCR3L_RUN3_RNG_SHIFT (16U)TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)TRNG_SCR4C_R4_0_CT_SHIFT (0U)TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)TRNG_SCR4C_R4_1_CT_SHIFT (16U)TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)TRNG_SCR4L_RUN4_MAX_SHIFT (0U)TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)TRNG_SCR4L_RUN4_RNG_SHIFT (16U)TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)TRNG_SCR5C_R5_0_CT_SHIFT (0U)TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)TRNG_SCR5C_R5_1_CT_SHIFT (16U)TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)TRNG_SCR5L_RUN5_MAX_SHIFT (0U)TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)TRNG_SCR5L_RUN5_RNG_SHIFT (16U)TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)TRNG_STATUS_TF1BR0_MASK (0x1U)TRNG_STATUS_TF1BR0_SHIFT (0U)TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)TRNG_STATUS_TF1BR1_MASK (0x2U)TRNG_STATUS_TF1BR1_SHIFT (1U)TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)TRNG_STATUS_TF2BR0_MASK (0x4U)TRNG_STATUS_TF2BR0_SHIFT (2U)TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)TRNG_STATUS_TF2BR1_MASK (0x8U)TRNG_STATUS_TF2BR1_SHIFT (3U)TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)TRNG_STATUS_TF3BR0_MASK (0x10U)TRNG_STATUS_TF3BR0_SHIFT (4U)TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)TRNG_STATUS_TF3BR1_MASK (0x20U)TRNG_STATUS_TF3BR1_SHIFT (5U)TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)TRNG_STATUS_TF4BR0_MASK (0x40U)TRNG_STATUS_TF4BR0_SHIFT (6U)TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)TRNG_STATUS_TF4BR1_MASK (0x80U)TRNG_STATUS_TF4BR1_SHIFT (7U)TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)TRNG_STATUS_TF5BR0_MASK (0x100U)TRNG_STATUS_TF5BR0_SHIFT (8U)TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)TRNG_STATUS_TF5BR1_MASK (0x200U)TRNG_STATUS_TF5BR1_SHIFT (9U)TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)TRNG_STATUS_TF6PBR0_MASK (0x400U)TRNG_STATUS_TF6PBR0_SHIFT (10U)TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)TRNG_STATUS_TF6PBR1_MASK (0x800U)TRNG_STATUS_TF6PBR1_SHIFT (11U)TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)TRNG_STATUS_TFSB_MASK (0x1000U)TRNG_STATUS_TFSB_SHIFT (12U)TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)TRNG_STATUS_TFLR_MASK (0x2000U)TRNG_STATUS_TFLR_SHIFT (13U)TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)TRNG_STATUS_TFP_MASK (0x4000U)TRNG_STATUS_TFP_SHIFT (14U)TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)TRNG_STATUS_TFMB_MASK (0x8000U)TRNG_STATUS_TFMB_SHIFT (15U)TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)TRNG_STATUS_RETRY_CT_MASK (0xF0000U)TRNG_STATUS_RETRY_CT_SHIFT (16U)TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)TRNG_ENT_ENT_MASK (0xFFFFFFFFU)TRNG_ENT_ENT_SHIFT (0U)TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)TRNG_ENT_COUNT (16U)TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)TRNG_SEC_CFG_UNUSED0_MASK (0x1U)TRNG_SEC_CFG_UNUSED0_SHIFT (0U)TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)TRNG_SEC_CFG_UNUSED2_MASK (0x4U)TRNG_SEC_CFG_UNUSED2_SHIFT (2U)TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)TRNG_INT_CTRL_HW_ERR_MASK (0x1U)TRNG_INT_CTRL_HW_ERR_SHIFT (0U)TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)TRNG_INT_CTRL_UNUSED_SHIFT (3U)TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)TRNG_INT_MASK_HW_ERR_MASK (0x1U)TRNG_INT_MASK_HW_ERR_SHIFT (0U)TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)TRNG_INT_MASK_ENT_VAL_MASK (0x2U)TRNG_INT_MASK_ENT_VAL_SHIFT (1U)TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)TRNG_INT_STATUS_HW_ERR_MASK (0x1U)TRNG_INT_STATUS_HW_ERR_SHIFT (0U)TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)TRNG_VID1_MIN_REV_MASK (0xFFU)TRNG_VID1_MIN_REV_SHIFT (0U)TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)TRNG_VID1_MAJ_REV_MASK (0xFF00U)TRNG_VID1_MAJ_REV_SHIFT (8U)TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)TRNG_VID1_IP_ID_MASK (0xFFFF0000U)TRNG_VID1_IP_ID_SHIFT (16U)TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)TRNG_VID2_CONFIG_OPT_MASK (0xFFU)TRNG_VID2_CONFIG_OPT_SHIFT (0U)TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)TRNG_VID2_ECO_REV_MASK (0xFF00U)TRNG_VID2_ECO_REV_SHIFT (8U)TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)TRNG_VID2_INTG_OPT_MASK (0xFF0000U)TRNG_VID2_INTG_OPT_SHIFT (16U)TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)TRNG_VID2_ERA_MASK (0xFF000000U)TRNG_VID2_ERA_SHIFT (24U)TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)TRNG_BASE (0x400CC000u)TRNG ((TRNG_Type *)TRNG_BASE)TRNG_BASE_ADDRS { TRNG_BASE }TRNG_BASE_PTRS { TRNG }TRNG_IRQS { TRNG_IRQn }USB_ID_ID_MASK (0x3FU)USB_ID_ID_SHIFT (0U)USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)USB_ID_NID_MASK (0x3F00U)USB_ID_NID_SHIFT (8U)USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)USB_ID_REVISION_MASK (0xFF0000U)USB_ID_REVISION_SHIFT (16U)USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)USB_HWGENERAL_PHYW_MASK (0x30U)USB_HWGENERAL_PHYW_SHIFT (4U)USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)USB_HWGENERAL_PHYM_MASK (0x1C0U)USB_HWGENERAL_PHYM_SHIFT (6U)USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)USB_HWGENERAL_SM_MASK (0x600U)USB_HWGENERAL_SM_SHIFT (9U)USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)USB_HWHOST_HC_MASK (0x1U)USB_HWHOST_HC_SHIFT (0U)USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)USB_HWHOST_NPORT_MASK (0xEU)USB_HWHOST_NPORT_SHIFT (1U)USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)USB_HWDEVICE_DC_MASK (0x1U)USB_HWDEVICE_DC_SHIFT (0U)USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)USB_HWDEVICE_DEVEP_MASK (0x3EU)USB_HWDEVICE_DEVEP_SHIFT (1U)USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)USB_HWTXBUF_TXBURST_MASK (0xFFU)USB_HWTXBUF_TXBURST_SHIFT (0U)USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)USB_HWTXBUF_TXCHANADD_SHIFT (16U)USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)USB_HWRXBUF_RXBURST_MASK (0xFFU)USB_HWRXBUF_RXBURST_SHIFT (0U)USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)USB_HWRXBUF_RXADD_MASK (0xFF00U)USB_HWRXBUF_RXADD_SHIFT (8U)USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER0LD_GPTLD_SHIFT (0U)USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER1LD_GPTLD_SHIFT (0U)USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)USB_SBUSCFG_AHBBRST_MASK (0x7U)USB_SBUSCFG_AHBBRST_SHIFT (0U)USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)USB_HCIVERSION_HCIVERSION_SHIFT (0U)USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)USB_HCSPARAMS_N_PORTS_MASK (0xFU)USB_HCSPARAMS_N_PORTS_SHIFT (0U)USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)USB_HCSPARAMS_PPC_MASK (0x10U)USB_HCSPARAMS_PPC_SHIFT (4U)USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)USB_HCSPARAMS_N_PCC_MASK (0xF00U)USB_HCSPARAMS_N_PCC_SHIFT (8U)USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)USB_HCSPARAMS_N_CC_MASK (0xF000U)USB_HCSPARAMS_N_CC_SHIFT (12U)USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)USB_HCSPARAMS_PI_MASK (0x10000U)USB_HCSPARAMS_PI_SHIFT (16U)USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)USB_HCSPARAMS_N_PTT_MASK (0xF00000U)USB_HCSPARAMS_N_PTT_SHIFT (20U)USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)USB_HCSPARAMS_N_TT_MASK (0xF000000U)USB_HCSPARAMS_N_TT_SHIFT (24U)USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)USB_HCCPARAMS_ADC_MASK (0x1U)USB_HCCPARAMS_ADC_SHIFT (0U)USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)USB_HCCPARAMS_PFL_MASK (0x2U)USB_HCCPARAMS_PFL_SHIFT (1U)USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)USB_HCCPARAMS_ASP_MASK (0x4U)USB_HCCPARAMS_ASP_SHIFT (2U)USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)USB_HCCPARAMS_IST_MASK (0xF0U)USB_HCCPARAMS_IST_SHIFT (4U)USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)USB_HCCPARAMS_EECP_MASK (0xFF00U)USB_HCCPARAMS_EECP_SHIFT (8U)USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)USB_DCIVERSION_DCIVERSION_SHIFT (0U)USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)USB_DCCPARAMS_DEN_MASK (0x1FU)USB_DCCPARAMS_DEN_SHIFT (0U)USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)USB_DCCPARAMS_DC_MASK (0x80U)USB_DCCPARAMS_DC_SHIFT (7U)USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)USB_DCCPARAMS_HC_MASK (0x100U)USB_DCCPARAMS_HC_SHIFT (8U)USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)USB_USBCMD_RS_MASK (0x1U)USB_USBCMD_RS_SHIFT (0U)USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)USB_USBCMD_RST_MASK (0x2U)USB_USBCMD_RST_SHIFT (1U)USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)USB_USBCMD_FS_1_MASK (0xCU)USB_USBCMD_FS_1_SHIFT (2U)USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)USB_USBCMD_PSE_MASK (0x10U)USB_USBCMD_PSE_SHIFT (4U)USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)USB_USBCMD_ASE_MASK (0x20U)USB_USBCMD_ASE_SHIFT (5U)USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)USB_USBCMD_IAA_MASK (0x40U)USB_USBCMD_IAA_SHIFT (6U)USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)USB_USBCMD_ASP_MASK (0x300U)USB_USBCMD_ASP_SHIFT (8U)USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)USB_USBCMD_ASPE_MASK (0x800U)USB_USBCMD_ASPE_SHIFT (11U)USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)USB_USBCMD_SUTW_MASK (0x2000U)USB_USBCMD_SUTW_SHIFT (13U)USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)USB_USBCMD_ATDTW_MASK (0x4000U)USB_USBCMD_ATDTW_SHIFT (14U)USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)USB_USBCMD_FS_2_MASK (0x8000U)USB_USBCMD_FS_2_SHIFT (15U)USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)USB_USBCMD_ITC_MASK (0xFF0000U)USB_USBCMD_ITC_SHIFT (16U)USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)USB_USBSTS_UI_MASK (0x1U)USB_USBSTS_UI_SHIFT (0U)USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)USB_USBSTS_UEI_MASK (0x2U)USB_USBSTS_UEI_SHIFT (1U)USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)USB_USBSTS_PCI_MASK (0x4U)USB_USBSTS_PCI_SHIFT (2U)USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)USB_USBSTS_FRI_MASK (0x8U)USB_USBSTS_FRI_SHIFT (3U)USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)USB_USBSTS_SEI_MASK (0x10U)USB_USBSTS_SEI_SHIFT (4U)USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)USB_USBSTS_AAI_MASK (0x20U)USB_USBSTS_AAI_SHIFT (5U)USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)USB_USBSTS_URI_MASK (0x40U)USB_USBSTS_URI_SHIFT (6U)USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)USB_USBSTS_SRI_MASK (0x80U)USB_USBSTS_SRI_SHIFT (7U)USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)USB_USBSTS_SLI_MASK (0x100U)USB_USBSTS_SLI_SHIFT (8U)USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)USB_USBSTS_ULPII_MASK (0x400U)USB_USBSTS_ULPII_SHIFT (10U)USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)USB_USBSTS_HCH_MASK (0x1000U)USB_USBSTS_HCH_SHIFT (12U)USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)USB_USBSTS_RCL_MASK (0x2000U)USB_USBSTS_RCL_SHIFT (13U)USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)USB_USBSTS_PS_MASK (0x4000U)USB_USBSTS_PS_SHIFT (14U)USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)USB_USBSTS_AS_MASK (0x8000U)USB_USBSTS_AS_SHIFT (15U)USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)USB_USBSTS_NAKI_MASK (0x10000U)USB_USBSTS_NAKI_SHIFT (16U)USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)USB_USBSTS_TI0_MASK (0x1000000U)USB_USBSTS_TI0_SHIFT (24U)USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)USB_USBSTS_TI1_MASK (0x2000000U)USB_USBSTS_TI1_SHIFT (25U)USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)USB_USBINTR_UE_MASK (0x1U)USB_USBINTR_UE_SHIFT (0U)USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)USB_USBINTR_UEE_MASK (0x2U)USB_USBINTR_UEE_SHIFT (1U)USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)USB_USBINTR_PCE_MASK (0x4U)USB_USBINTR_PCE_SHIFT (2U)USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)USB_USBINTR_FRE_MASK (0x8U)USB_USBINTR_FRE_SHIFT (3U)USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)USB_USBINTR_SEE_MASK (0x10U)USB_USBINTR_SEE_SHIFT (4U)USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)USB_USBINTR_AAE_MASK (0x20U)USB_USBINTR_AAE_SHIFT (5U)USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)USB_USBINTR_URE_MASK (0x40U)USB_USBINTR_URE_SHIFT (6U)USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)USB_USBINTR_SRE_MASK (0x80U)USB_USBINTR_SRE_SHIFT (7U)USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)USB_USBINTR_SLE_MASK (0x100U)USB_USBINTR_SLE_SHIFT (8U)USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)USB_USBINTR_ULPIE_MASK (0x400U)USB_USBINTR_ULPIE_SHIFT (10U)USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)USB_USBINTR_NAKE_MASK (0x10000U)USB_USBINTR_NAKE_SHIFT (16U)USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)USB_USBINTR_UAIE_MASK (0x40000U)USB_USBINTR_UAIE_SHIFT (18U)USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)USB_USBINTR_UPIE_MASK (0x80000U)USB_USBINTR_UPIE_SHIFT (19U)USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)USB_USBINTR_TIE0_MASK (0x1000000U)USB_USBINTR_TIE0_SHIFT (24U)USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)USB_USBINTR_TIE1_MASK (0x2000000U)USB_USBINTR_TIE1_SHIFT (25U)USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)USB_FRINDEX_FRINDEX_MASK (0x3FFFU)USB_FRINDEX_FRINDEX_SHIFT (0U)USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)USB_DEVICEADDR_USBADRA_MASK (0x1000000U)USB_DEVICEADDR_USBADRA_SHIFT (24U)USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)USB_DEVICEADDR_USBADR_MASK (0xFE000000U)USB_DEVICEADDR_USBADR_SHIFT (25U)USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)USB_BURSTSIZE_RXPBURST_MASK (0xFFU)USB_BURSTSIZE_RXPBURST_SHIFT (0U)USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)USB_BURSTSIZE_TXPBURST_SHIFT (8U)USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)USB_ENDPTNAK_EPRN_MASK (0xFFU)USB_ENDPTNAK_EPRN_SHIFT (0U)USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)USB_ENDPTNAK_EPTN_MASK (0xFF0000U)USB_ENDPTNAK_EPTN_SHIFT (16U)USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)USB_ENDPTNAKEN_EPRNE_SHIFT (0U)USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)USB_ENDPTNAKEN_EPTNE_SHIFT (16U)USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)USB_CONFIGFLAG_CF_MASK (0x1U)USB_CONFIGFLAG_CF_SHIFT (0U)USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)USB_PORTSC1_CCS_MASK (0x1U)USB_PORTSC1_CCS_SHIFT (0U)USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)USB_PORTSC1_CSC_MASK (0x2U)USB_PORTSC1_CSC_SHIFT (1U)USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)USB_PORTSC1_PE_MASK (0x4U)USB_PORTSC1_PE_SHIFT (2U)USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)USB_PORTSC1_PEC_MASK (0x8U)USB_PORTSC1_PEC_SHIFT (3U)USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)USB_PORTSC1_OCA_MASK (0x10U)USB_PORTSC1_OCA_SHIFT (4U)USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)USB_PORTSC1_OCC_MASK (0x20U)USB_PORTSC1_OCC_SHIFT (5U)USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)USB_PORTSC1_FPR_MASK (0x40U)USB_PORTSC1_FPR_SHIFT (6U)USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)USB_PORTSC1_SUSP_MASK (0x80U)USB_PORTSC1_SUSP_SHIFT (7U)USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)USB_PORTSC1_PR_MASK (0x100U)USB_PORTSC1_PR_SHIFT (8U)USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)USB_PORTSC1_HSP_MASK (0x200U)USB_PORTSC1_HSP_SHIFT (9U)USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)USB_PORTSC1_LS_MASK (0xC00U)USB_PORTSC1_LS_SHIFT (10U)USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)USB_PORTSC1_PP_MASK (0x1000U)USB_PORTSC1_PP_SHIFT (12U)USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)USB_PORTSC1_PO_MASK (0x2000U)USB_PORTSC1_PO_SHIFT (13U)USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)USB_PORTSC1_PIC_MASK (0xC000U)USB_PORTSC1_PIC_SHIFT (14U)USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)USB_PORTSC1_PTC_MASK (0xF0000U)USB_PORTSC1_PTC_SHIFT (16U)USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)USB_PORTSC1_WKCN_MASK (0x100000U)USB_PORTSC1_WKCN_SHIFT (20U)USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)USB_PORTSC1_WKDC_MASK (0x200000U)USB_PORTSC1_WKDC_SHIFT (21U)USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)USB_PORTSC1_WKOC_MASK (0x400000U)USB_PORTSC1_WKOC_SHIFT (22U)USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)USB_PORTSC1_PHCD_MASK (0x800000U)USB_PORTSC1_PHCD_SHIFT (23U)USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)USB_PORTSC1_PFSC_MASK (0x1000000U)USB_PORTSC1_PFSC_SHIFT (24U)USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)USB_PORTSC1_PTS_2_MASK (0x2000000U)USB_PORTSC1_PTS_2_SHIFT (25U)USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)USB_PORTSC1_PSPD_MASK (0xC000000U)USB_PORTSC1_PSPD_SHIFT (26U)USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)USB_PORTSC1_PTW_MASK (0x10000000U)USB_PORTSC1_PTW_SHIFT (28U)USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)USB_PORTSC1_STS_MASK (0x20000000U)USB_PORTSC1_STS_SHIFT (29U)USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)USB_PORTSC1_PTS_1_MASK (0xC0000000U)USB_PORTSC1_PTS_1_SHIFT (30U)USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)USB_OTGSC_VD_MASK (0x1U)USB_OTGSC_VD_SHIFT (0U)USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)USB_OTGSC_VC_MASK (0x2U)USB_OTGSC_VC_SHIFT (1U)USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)USB_OTGSC_OT_MASK (0x8U)USB_OTGSC_OT_SHIFT (3U)USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)USB_OTGSC_DP_MASK (0x10U)USB_OTGSC_DP_SHIFT (4U)USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)USB_OTGSC_IDPU_MASK (0x20U)USB_OTGSC_IDPU_SHIFT (5U)USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)USB_OTGSC_ID_MASK (0x100U)USB_OTGSC_ID_SHIFT (8U)USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)USB_OTGSC_AVV_MASK (0x200U)USB_OTGSC_AVV_SHIFT (9U)USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)USB_OTGSC_ASV_MASK (0x400U)USB_OTGSC_ASV_SHIFT (10U)USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)USB_OTGSC_BSV_MASK (0x800U)USB_OTGSC_BSV_SHIFT (11U)USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)USB_OTGSC_BSE_MASK (0x1000U)USB_OTGSC_BSE_SHIFT (12U)USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)USB_OTGSC_TOG_1MS_MASK (0x2000U)USB_OTGSC_TOG_1MS_SHIFT (13U)USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)USB_OTGSC_DPS_MASK (0x4000U)USB_OTGSC_DPS_SHIFT (14U)USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)USB_OTGSC_IDIS_MASK (0x10000U)USB_OTGSC_IDIS_SHIFT (16U)USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)USB_OTGSC_AVVIS_MASK (0x20000U)USB_OTGSC_AVVIS_SHIFT (17U)USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)USB_OTGSC_ASVIS_MASK (0x40000U)USB_OTGSC_ASVIS_SHIFT (18U)USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)USB_OTGSC_BSVIS_MASK (0x80000U)USB_OTGSC_BSVIS_SHIFT (19U)USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)USB_OTGSC_BSEIS_MASK (0x100000U)USB_OTGSC_BSEIS_SHIFT (20U)USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)USB_OTGSC_STATUS_1MS_MASK (0x200000U)USB_OTGSC_STATUS_1MS_SHIFT (21U)USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)USB_OTGSC_DPIS_MASK (0x400000U)USB_OTGSC_DPIS_SHIFT (22U)USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)USB_OTGSC_IDIE_MASK (0x1000000U)USB_OTGSC_IDIE_SHIFT (24U)USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)USB_OTGSC_AVVIE_MASK (0x2000000U)USB_OTGSC_AVVIE_SHIFT (25U)USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)USB_OTGSC_ASVIE_MASK (0x4000000U)USB_OTGSC_ASVIE_SHIFT (26U)USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)USB_OTGSC_BSVIE_MASK (0x8000000U)USB_OTGSC_BSVIE_SHIFT (27U)USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)USB_OTGSC_BSEIE_MASK (0x10000000U)USB_OTGSC_BSEIE_SHIFT (28U)USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)USB_OTGSC_EN_1MS_MASK (0x20000000U)USB_OTGSC_EN_1MS_SHIFT (29U)USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)USB_OTGSC_DPIE_MASK (0x40000000U)USB_OTGSC_DPIE_SHIFT (30U)USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)USB_USBMODE_CM_MASK (0x3U)USB_USBMODE_CM_SHIFT (0U)USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)USB_USBMODE_ES_MASK (0x4U)USB_USBMODE_ES_SHIFT (2U)USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)USB_USBMODE_SLOM_MASK (0x8U)USB_USBMODE_SLOM_SHIFT (3U)USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)USB_USBMODE_SDIS_MASK (0x10U)USB_USBMODE_SDIS_SHIFT (4U)USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)USB_ENDPTPRIME_PERB_MASK (0xFFU)USB_ENDPTPRIME_PERB_SHIFT (0U)USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)USB_ENDPTPRIME_PETB_MASK (0xFF0000U)USB_ENDPTPRIME_PETB_SHIFT (16U)USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)USB_ENDPTFLUSH_FERB_MASK (0xFFU)USB_ENDPTFLUSH_FERB_SHIFT (0U)USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)USB_ENDPTFLUSH_FETB_SHIFT (16U)USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)USB_ENDPTSTAT_ERBR_MASK (0xFFU)USB_ENDPTSTAT_ERBR_SHIFT (0U)USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)USB_ENDPTSTAT_ETBR_SHIFT (16U)USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)USB_ENDPTCTRL0_RXS_MASK (0x1U)USB_ENDPTCTRL0_RXS_SHIFT (0U)USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)USB_ENDPTCTRL0_RXT_MASK (0xCU)USB_ENDPTCTRL0_RXT_SHIFT (2U)USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)USB_ENDPTCTRL0_RXE_MASK (0x80U)USB_ENDPTCTRL0_RXE_SHIFT (7U)USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)USB_ENDPTCTRL0_TXS_MASK (0x10000U)USB_ENDPTCTRL0_TXS_SHIFT (16U)USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)USB_ENDPTCTRL0_TXT_MASK (0xC0000U)USB_ENDPTCTRL0_TXT_SHIFT (18U)USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)USB_ENDPTCTRL0_TXE_MASK (0x800000U)USB_ENDPTCTRL0_TXE_SHIFT (23U)USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)USB_ENDPTCTRL_RXS_MASK (0x1U)USB_ENDPTCTRL_RXS_SHIFT (0U)USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)USB_ENDPTCTRL_RXD_MASK (0x2U)USB_ENDPTCTRL_RXD_SHIFT (1U)USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)USB_ENDPTCTRL_RXT_MASK (0xCU)USB_ENDPTCTRL_RXT_SHIFT (2U)USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)USB_ENDPTCTRL_RXI_MASK (0x20U)USB_ENDPTCTRL_RXI_SHIFT (5U)USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)USB_ENDPTCTRL_RXR_MASK (0x40U)USB_ENDPTCTRL_RXR_SHIFT (6U)USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)USB_ENDPTCTRL_RXE_MASK (0x80U)USB_ENDPTCTRL_RXE_SHIFT (7U)USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)USB_ENDPTCTRL_TXS_MASK (0x10000U)USB_ENDPTCTRL_TXS_SHIFT (16U)USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)USB_ENDPTCTRL_TXD_MASK (0x20000U)USB_ENDPTCTRL_TXD_SHIFT (17U)USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)USB_ENDPTCTRL_TXT_MASK (0xC0000U)USB_ENDPTCTRL_TXT_SHIFT (18U)USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)USB_ENDPTCTRL_TXI_MASK (0x200000U)USB_ENDPTCTRL_TXI_SHIFT (21U)USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)USB_ENDPTCTRL_TXR_MASK (0x400000U)USB_ENDPTCTRL_TXR_SHIFT (22U)USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)USB_ENDPTCTRL_TXE_MASK (0x800000U)USB_ENDPTCTRL_TXE_SHIFT (23U)USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)USB_ENDPTCTRL_COUNT (7U)USB_BASE (0x402E0000u)USB ((USB_Type *)USB_BASE)USB_BASE_ADDRS { 0u, USB_BASE }USB_BASE_PTRS { (USB_Type *)0u, USB }USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn }GPTIMER0CTL GPTIMER0CTRLGPTIMER1CTL GPTIMER1CTRLUSB_SBUSCFG SBUSCFGEPLISTADDR ENDPTLISTADDREPSETUPSR ENDPTSETUPSTATEPPRIME ENDPTPRIMEEPFLUSH ENDPTFLUSHEPSR ENDPTSTATEPCOMPLETE ENDPTCOMPLETEEPCR ENDPTCTRLEPCR0 ENDPTCTRL0USBHS_ID_ID_MASK USB_ID_ID_MASKUSBHS_ID_ID_SHIFT USB_ID_ID_SHIFTUSBHS_ID_ID(x) USB_ID_ID(x)USBHS_ID_NID_MASK USB_ID_NID_MASKUSBHS_ID_NID_SHIFT USB_ID_NID_SHIFTUSBHS_ID_NID(x) USB_ID_NID(x)USBHS_ID_REVISION_MASK USB_ID_REVISION_MASKUSBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFTUSBHS_ID_REVISION(x) USB_ID_REVISION(x)USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASKUSBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFTUSBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASKUSBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFTUSBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASKUSBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFTUSBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASKUSBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFTUSBHS_HWHOST_HC(x) USB_HWHOST_HC(x)USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASKUSBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFTUSBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASKUSBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFTUSBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASKUSBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFTUSBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASKUSBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFTUSBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASKUSBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFTUSBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASKUSBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFTUSBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASKUSBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFTUSBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASKUSBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFTUSBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASKUSBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFTUSBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASKUSBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFTUSBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASKUSBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFTUSBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASKUSBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFTUSBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASKUSBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFTUSBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASKUSBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFTUSBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASKUSBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFTUSBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASKUSBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFTUSBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASKUSBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFTUSBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASKUSBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFTUSBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASKUSBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFTUSBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASKUSBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFTUSBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASKUSBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFTUSBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASKUSBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFTUSBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASKUSBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFTUSBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASKUSBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFTUSBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASKUSBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFTUSBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASKUSBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFTUSBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASKUSBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFTUSBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASKUSBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFTUSBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASKUSBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFTUSBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASKUSBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFTUSBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASKUSBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFTUSBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASKUSBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFTUSBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASKUSBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFTUSBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASKUSBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFTUSBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASKUSBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFTUSBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASKUSBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFTUSBHS_USBCMD_RS(x) USB_USBCMD_RS(x)USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASKUSBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFTUSBHS_USBCMD_RST(x) USB_USBCMD_RST(x)USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASKUSBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFTUSBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASKUSBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFTUSBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASKUSBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFTUSBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASKUSBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFTUSBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASKUSBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFTUSBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASKUSBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFTUSBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASKUSBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFTUSBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASKUSBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFTUSBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASKUSBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFTUSBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASKUSBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFTUSBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASKUSBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFTUSBHS_USBSTS_UI(x) USB_USBSTS_UI(x)USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASKUSBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFTUSBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASKUSBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFTUSBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASKUSBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFTUSBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASKUSBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFTUSBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASKUSBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFTUSBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASKUSBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFTUSBHS_USBSTS_URI(x) USB_USBSTS_URI(x)USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASKUSBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFTUSBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASKUSBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFTUSBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASKUSBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFTUSBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASKUSBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFTUSBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASKUSBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFTUSBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASKUSBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFTUSBHS_USBSTS_PS(x) USB_USBSTS_PS(x)USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASKUSBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFTUSBHS_USBSTS_AS(x) USB_USBSTS_AS(x)USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASKUSBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFTUSBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASKUSBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFTUSBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASKUSBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFTUSBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASKUSBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFTUSBHS_USBINTR_UE(x) USB_USBINTR_UE(x)USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASKUSBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFTUSBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASKUSBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFTUSBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASKUSBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFTUSBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASKUSBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFTUSBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASKUSBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFTUSBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASKUSBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFTUSBHS_USBINTR_URE(x) USB_USBINTR_URE(x)USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASKUSBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFTUSBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASKUSBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFTUSBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASKUSBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFTUSBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASKUSBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFTUSBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASKUSBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFTUSBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASKUSBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFTUSBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASKUSBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFTUSBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASKUSBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFTUSBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASKUSBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFTUSBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASKUSBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFTUSBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASKUSBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFTUSBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASKUSBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFTUSBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASKUSBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFTUSBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASKUSBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFTUSBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASKUSBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFTUSBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASKUSBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFTUSBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASKUSBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFTUSBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASKUSBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFTUSBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASKUSBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFTUSBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASKUSBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFTUSBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASKUSBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFTUSBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASKUSBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFTUSBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASKUSBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFTUSBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASKUSBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFTUSBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASKUSBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFTUSBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASKUSBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFTUSBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASKUSBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFTUSBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASKUSBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFTUSBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASKUSBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFTUSBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASKUSBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFTUSBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASKUSBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFTUSBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASKUSBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFTUSBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASKUSBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFTUSBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASKUSBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFTUSBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASKUSBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFTUSBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASKUSBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFTUSBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASKUSBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFTUSBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASKUSBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFTUSBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASKUSBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFTUSBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASKUSBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFTUSBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASKUSBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFTUSBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASKUSBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFTUSBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASKUSBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFTUSBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASKUSBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFTUSBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASKUSBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFTUSBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASKUSBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFTUSBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASKUSBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFTUSBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASKUSBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFTUSBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASKUSBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFTUSBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASKUSBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFTUSBHS_OTGSC_VD(x) USB_OTGSC_VD(x)USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASKUSBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFTUSBHS_OTGSC_VC(x) USB_OTGSC_VC(x)USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASKUSBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFTUSBHS_OTGSC_OT(x) USB_OTGSC_OT(x)USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASKUSBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFTUSBHS_OTGSC_DP(x) USB_OTGSC_DP(x)USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASKUSBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFTUSBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASKUSBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFTUSBHS_OTGSC_ID(x) USB_OTGSC_ID(x)USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASKUSBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFTUSBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASKUSBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFTUSBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASKUSBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFTUSBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASKUSBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFTUSBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASKUSBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFTUSBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASKUSBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFTUSBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASKUSBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFTUSBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASKUSBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFTUSBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASKUSBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFTUSBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASKUSBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFTUSBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASKUSBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFTUSBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASKUSBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFTUSBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASKUSBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFTUSBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASKUSBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFTUSBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASKUSBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFTUSBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASKUSBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFTUSBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASKUSBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFTUSBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASKUSBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFTUSBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASKUSBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFTUSBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASKUSBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFTUSBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASKUSBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFTUSBHS_USBMODE_CM(x) USB_USBMODE_CM(x)USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASKUSBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFTUSBHS_USBMODE_ES(x) USB_USBMODE_ES(x)USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASKUSBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFTUSBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASKUSBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFTUSBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASKUSBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFTUSBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASKUSBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFTUSBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASKUSBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFTUSBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASKUSBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFTUSBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASKUSBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFTUSBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASKUSBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFTUSBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASKUSBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFTUSBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASKUSBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFTUSBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASKUSBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFTUSBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASKUSBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFTUSBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASKUSBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFTUSBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASKUSBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFTUSBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASKUSBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFTUSBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASKUSBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFTUSBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASKUSBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFTUSBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASKUSBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFTUSBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASKUSBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFTUSBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASKUSBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFTUSBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASKUSBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFTUSBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASKUSBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFTUSBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASKUSBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFTUSBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASKUSBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFTUSBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASKUSBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFTUSBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASKUSBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFTUSBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASKUSBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFTUSBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASKUSBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFTUSBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASKUSBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFTUSBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNTUSBHS_Type USB_TypeUSBHS_BASE_ADDRS { USB_BASE }USBHS_IRQS { USB_OTG1_IRQn }USBHS_IRQHandler USB_OTG1_IRQHandlerUSBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)USBNC_BASE (0x402E0000u)USBNC ((USBNC_Type *)USBNC_BASE)USBNC_BASE_ADDRS { 0u, USBNC_BASE }USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC }USBPHY_PWD_RSVD0_MASK (0x3FFU)USBPHY_PWD_RSVD0_SHIFT (0U)USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)USBPHY_PWD_TXPWDFS_MASK (0x400U)USBPHY_PWD_TXPWDFS_SHIFT (10U)USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)USBPHY_PWD_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)USBPHY_PWD_RSVD1_MASK (0x1E000U)USBPHY_PWD_RSVD1_SHIFT (13U)USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)USBPHY_PWD_RXPWDENV_MASK (0x20000U)USBPHY_PWD_RXPWDENV_SHIFT (17U)USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)USBPHY_PWD_RXPWDRX_MASK (0x100000U)USBPHY_PWD_RXPWDRX_SHIFT (20U)USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)USBPHY_PWD_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_RSVD2_SHIFT (21U)USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)USBPHY_PWD_SET_RSVD0_SHIFT (0U)USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)USBPHY_PWD_SET_RSVD1_SHIFT (13U)USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_SET_RSVD2_SHIFT (21U)USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)USBPHY_PWD_CLR_RSVD0_SHIFT (0U)USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)USBPHY_PWD_CLR_RSVD1_SHIFT (13U)USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_CLR_RSVD2_SHIFT (21U)USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)USBPHY_PWD_TOG_RSVD0_SHIFT (0U)USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)USBPHY_PWD_TOG_RSVD1_SHIFT (13U)USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_TOG_RSVD2_SHIFT (21U)USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)USBPHY_TX_D_CAL_MASK (0xFU)USBPHY_TX_D_CAL_SHIFT (0U)USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)USBPHY_TX_RSVD0_MASK (0xF0U)USBPHY_TX_RSVD0_SHIFT (4U)USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)USBPHY_TX_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TXCAL45DN_SHIFT (8U)USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)USBPHY_TX_RSVD1_MASK (0xF000U)USBPHY_TX_RSVD1_SHIFT (12U)USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)USBPHY_TX_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TXCAL45DP_SHIFT (16U)USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)USBPHY_TX_RSVD2_MASK (0x3F00000U)USBPHY_TX_RSVD2_SHIFT (20U)USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_RSVD5_MASK (0xE0000000U)USBPHY_TX_RSVD5_SHIFT (29U)USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)USBPHY_TX_SET_D_CAL_MASK (0xFU)USBPHY_TX_SET_D_CAL_SHIFT (0U)USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)USBPHY_TX_SET_RSVD0_MASK (0xF0U)USBPHY_TX_SET_RSVD0_SHIFT (4U)USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)USBPHY_TX_SET_RSVD1_MASK (0xF000U)USBPHY_TX_SET_RSVD1_SHIFT (12U)USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)USBPHY_TX_SET_RSVD2_SHIFT (20U)USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)USBPHY_TX_SET_RSVD5_SHIFT (29U)USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)USBPHY_TX_CLR_D_CAL_MASK (0xFU)USBPHY_TX_CLR_D_CAL_SHIFT (0U)USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)USBPHY_TX_CLR_RSVD0_MASK (0xF0U)USBPHY_TX_CLR_RSVD0_SHIFT (4U)USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)USBPHY_TX_CLR_RSVD1_MASK (0xF000U)USBPHY_TX_CLR_RSVD1_SHIFT (12U)USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)USBPHY_TX_CLR_RSVD2_SHIFT (20U)USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)USBPHY_TX_CLR_RSVD5_SHIFT (29U)USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)USBPHY_TX_TOG_D_CAL_MASK (0xFU)USBPHY_TX_TOG_D_CAL_SHIFT (0U)USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)USBPHY_TX_TOG_RSVD0_MASK (0xF0U)USBPHY_TX_TOG_RSVD0_SHIFT (4U)USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)USBPHY_TX_TOG_RSVD1_MASK (0xF000U)USBPHY_TX_TOG_RSVD1_SHIFT (12U)USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)USBPHY_TX_TOG_RSVD2_SHIFT (20U)USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)USBPHY_TX_TOG_RSVD5_SHIFT (29U)USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)USBPHY_RX_ENVADJ_MASK (0x7U)USBPHY_RX_ENVADJ_SHIFT (0U)USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)USBPHY_RX_RSVD0_MASK (0x8U)USBPHY_RX_RSVD0_SHIFT (3U)USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)USBPHY_RX_DISCONADJ_MASK (0x70U)USBPHY_RX_DISCONADJ_SHIFT (4U)USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)USBPHY_RX_RSVD1_MASK (0x3FFF80U)USBPHY_RX_RSVD1_SHIFT (7U)USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)USBPHY_RX_RXDBYPASS_MASK (0x400000U)USBPHY_RX_RXDBYPASS_SHIFT (22U)USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)USBPHY_RX_RSVD2_MASK (0xFF800000U)USBPHY_RX_RSVD2_SHIFT (23U)USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)USBPHY_RX_SET_ENVADJ_MASK (0x7U)USBPHY_RX_SET_ENVADJ_SHIFT (0U)USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)USBPHY_RX_SET_RSVD0_MASK (0x8U)USBPHY_RX_SET_RSVD0_SHIFT (3U)USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)USBPHY_RX_SET_DISCONADJ_MASK (0x70U)USBPHY_RX_SET_DISCONADJ_SHIFT (4U)USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)USBPHY_RX_SET_RSVD1_SHIFT (7U)USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)USBPHY_RX_SET_RSVD2_SHIFT (23U)USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)USBPHY_RX_CLR_ENVADJ_MASK (0x7U)USBPHY_RX_CLR_ENVADJ_SHIFT (0U)USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)USBPHY_RX_CLR_RSVD0_MASK (0x8U)USBPHY_RX_CLR_RSVD0_SHIFT (3U)USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)USBPHY_RX_CLR_RSVD1_SHIFT (7U)USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)USBPHY_RX_CLR_RSVD2_SHIFT (23U)USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)USBPHY_RX_TOG_ENVADJ_MASK (0x7U)USBPHY_RX_TOG_ENVADJ_SHIFT (0U)USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)USBPHY_RX_TOG_RSVD0_MASK (0x8U)USBPHY_RX_TOG_RSVD0_SHIFT (3U)USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)USBPHY_RX_TOG_RSVD1_SHIFT (7U)USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)USBPHY_RX_TOG_RSVD2_SHIFT (23U)USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)USBPHY_CTRL_RSVD1_MASK (0x6000000U)USBPHY_CTRL_RSVD1_SHIFT (25U)USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)USBPHY_CTRL_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SFTRST_SHIFT (31U)USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)USBPHY_CTRL_SET_RSVD1_SHIFT (25U)USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SET_SFTRST_SHIFT (31U)USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)USBPHY_STATUS_RSVD0_MASK (0x7U)USBPHY_STATUS_RSVD0_SHIFT (0U)USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)USBPHY_STATUS_RSVD1_MASK (0x30U)USBPHY_STATUS_RSVD1_SHIFT (4U)USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)USBPHY_STATUS_RSVD2_MASK (0x80U)USBPHY_STATUS_RSVD2_SHIFT (7U)USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)USBPHY_STATUS_RSVD3_MASK (0x200U)USBPHY_STATUS_RSVD3_SHIFT (9U)USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)USBPHY_STATUS_RSVD4_SHIFT (11U)USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_RSVD0_SHIFT (6U)USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_RSVD1_SHIFT (13U)USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_RSVD2_SHIFT (21U)USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)USBPHY_DEBUG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_RSVD3_SHIFT (31U)USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_RSVD0_SHIFT (0U)USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_RSVD1_SHIFT (15U)USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)USBPHY_VERSION_STEP_MASK (0xFFFFU)USBPHY_VERSION_STEP_SHIFT (0U)USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)USBPHY_VERSION_MINOR_MASK (0xFF0000U)USBPHY_VERSION_MINOR_SHIFT (16U)USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)USBPHY_VERSION_MAJOR_MASK (0xFF000000U)USBPHY_VERSION_MAJOR_SHIFT (24U)USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)USBPHY_BASE (0x400D9000u)USBPHY ((USBPHY_Type *)USBPHY_BASE)USBPHY_BASE_ADDRS { 0u, USBPHY_BASE }USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY }USBPHY_IRQS { NotAvail_IRQn, USB_PHY_IRQn }USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASKUSBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFTUSBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASKUSBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFTUSBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_COUNT (1U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_COUNT (1U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_COUNT (1U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_COUNT (1U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)USB_ANALOG_CHRG_DETECT_COUNT (1U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)USB_ANALOG_CHRG_DETECT_SET_COUNT (1U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)USB_ANALOG_CHRG_DETECT_CLR_COUNT (1U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)USB_ANALOG_CHRG_DETECT_TOG_COUNT (1U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_COUNT (1U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_COUNT (1U)USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)USB_ANALOG_LOOPBACK_COUNT (1U)USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)USB_ANALOG_LOOPBACK_SET_COUNT (1U)USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)USB_ANALOG_LOOPBACK_CLR_COUNT (1U)USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)USB_ANALOG_LOOPBACK_TOG_COUNT (1U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_COUNT (1U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_SET_COUNT (1U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_CLR_COUNT (1U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_TOG_COUNT (1U)USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)USB_ANALOG_BASE (0x400D8000u)USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }USB_ANALOG_BASE_PTRS { USB_ANALOG }WDOG_WCR_WDZST_MASK (0x1U)WDOG_WCR_WDZST_SHIFT (0U)WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)WDOG_WCR_WDBG_MASK (0x2U)WDOG_WCR_WDBG_SHIFT (1U)WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)WDOG_WCR_WDE_MASK (0x4U)WDOG_WCR_WDE_SHIFT (2U)WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)WDOG_WCR_WDT_MASK (0x8U)WDOG_WCR_WDT_SHIFT (3U)WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)WDOG_WCR_SRS_MASK (0x10U)WDOG_WCR_SRS_SHIFT (4U)WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)WDOG_WCR_WDA_MASK (0x20U)WDOG_WCR_WDA_SHIFT (5U)WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)WDOG_WCR_SRE_MASK (0x40U)WDOG_WCR_SRE_SHIFT (6U)WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)WDOG_WCR_WDW_MASK (0x80U)WDOG_WCR_WDW_SHIFT (7U)WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)WDOG_WCR_WT_MASK (0xFF00U)WDOG_WCR_WT_SHIFT (8U)WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)WDOG_WSR_WSR_MASK (0xFFFFU)WDOG_WSR_WSR_SHIFT (0U)WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)WDOG_WRSR_SFTW_MASK (0x1U)WDOG_WRSR_SFTW_SHIFT (0U)WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)WDOG_WRSR_TOUT_MASK (0x2U)WDOG_WRSR_TOUT_SHIFT (1U)WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)WDOG_WRSR_POR_MASK (0x10U)WDOG_WRSR_POR_SHIFT (4U)WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)WDOG_WICR_WICT_MASK (0xFFU)WDOG_WICR_WICT_SHIFT (0U)WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)WDOG_WICR_WTIS_MASK (0x4000U)WDOG_WICR_WTIS_SHIFT (14U)WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)WDOG_WICR_WIE_MASK (0x8000U)WDOG_WICR_WIE_SHIFT (15U)WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)WDOG_WMCR_PDE_MASK (0x1U)WDOG_WMCR_PDE_SHIFT (0U)WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)WDOG1_BASE (0x400B8000u)WDOG1 ((WDOG_Type *)WDOG1_BASE)WDOG2_BASE (0x400D0000u)WDOG2 ((WDOG_Type *)WDOG2_BASE)WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }XBARA_SEL0_SEL0_MASK (0x7FU)XBARA_SEL0_SEL0_SHIFT (0U)XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)XBARA_SEL0_SEL1_MASK (0x7F00U)XBARA_SEL0_SEL1_SHIFT (8U)XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)XBARA_SEL1_SEL2_MASK (0x7FU)XBARA_SEL1_SEL2_SHIFT (0U)XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)XBARA_SEL1_SEL3_MASK (0x7F00U)XBARA_SEL1_SEL3_SHIFT (8U)XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)XBARA_SEL2_SEL4_MASK (0x7FU)XBARA_SEL2_SEL4_SHIFT (0U)XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)XBARA_SEL2_SEL5_MASK (0x7F00U)XBARA_SEL2_SEL5_SHIFT (8U)XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)XBARA_SEL3_SEL6_MASK (0x7FU)XBARA_SEL3_SEL6_SHIFT (0U)XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)XBARA_SEL3_SEL7_MASK (0x7F00U)XBARA_SEL3_SEL7_SHIFT (8U)XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)XBARA_SEL4_SEL8_MASK (0x7FU)XBARA_SEL4_SEL8_SHIFT (0U)XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)XBARA_SEL4_SEL9_MASK (0x7F00U)XBARA_SEL4_SEL9_SHIFT (8U)XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)XBARA_SEL5_SEL10_MASK (0x7FU)XBARA_SEL5_SEL10_SHIFT (0U)XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)XBARA_SEL5_SEL11_MASK (0x7F00U)XBARA_SEL5_SEL11_SHIFT (8U)XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)XBARA_SEL6_SEL12_MASK (0x7FU)XBARA_SEL6_SEL12_SHIFT (0U)XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)XBARA_SEL6_SEL13_MASK (0x7F00U)XBARA_SEL6_SEL13_SHIFT (8U)XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)XBARA_SEL7_SEL14_MASK (0x7FU)XBARA_SEL7_SEL14_SHIFT (0U)XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)XBARA_SEL7_SEL15_MASK (0x7F00U)XBARA_SEL7_SEL15_SHIFT (8U)XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)XBARA_SEL8_SEL16_MASK (0x7FU)XBARA_SEL8_SEL16_SHIFT (0U)XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)XBARA_SEL8_SEL17_MASK (0x7F00U)XBARA_SEL8_SEL17_SHIFT (8U)XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)XBARA_SEL9_SEL18_MASK (0x7FU)XBARA_SEL9_SEL18_SHIFT (0U)XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)XBARA_SEL9_SEL19_MASK (0x7F00U)XBARA_SEL9_SEL19_SHIFT (8U)XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)XBARA_SEL10_SEL20_MASK (0x7FU)XBARA_SEL10_SEL20_SHIFT (0U)XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)XBARA_SEL10_SEL21_MASK (0x7F00U)XBARA_SEL10_SEL21_SHIFT (8U)XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)XBARA_SEL11_SEL22_MASK (0x7FU)XBARA_SEL11_SEL22_SHIFT (0U)XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)XBARA_SEL11_SEL23_MASK (0x7F00U)XBARA_SEL11_SEL23_SHIFT (8U)XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)XBARA_SEL12_SEL24_MASK (0x7FU)XBARA_SEL12_SEL24_SHIFT (0U)XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)XBARA_SEL12_SEL25_MASK (0x7F00U)XBARA_SEL12_SEL25_SHIFT (8U)XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)XBARA_SEL13_SEL26_MASK (0x7FU)XBARA_SEL13_SEL26_SHIFT (0U)XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)XBARA_SEL13_SEL27_MASK (0x7F00U)XBARA_SEL13_SEL27_SHIFT (8U)XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)XBARA_SEL14_SEL28_MASK (0x7FU)XBARA_SEL14_SEL28_SHIFT (0U)XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)XBARA_SEL14_SEL29_MASK (0x7F00U)XBARA_SEL14_SEL29_SHIFT (8U)XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)XBARA_SEL15_SEL30_MASK (0x7FU)XBARA_SEL15_SEL30_SHIFT (0U)XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)XBARA_SEL15_SEL31_MASK (0x7F00U)XBARA_SEL15_SEL31_SHIFT (8U)XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)XBARA_SEL16_SEL32_MASK (0x7FU)XBARA_SEL16_SEL32_SHIFT (0U)XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)XBARA_SEL16_SEL33_MASK (0x7F00U)XBARA_SEL16_SEL33_SHIFT (8U)XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)XBARA_SEL17_SEL34_MASK (0x7FU)XBARA_SEL17_SEL34_SHIFT (0U)XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)XBARA_SEL17_SEL35_MASK (0x7F00U)XBARA_SEL17_SEL35_SHIFT (8U)XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)XBARA_SEL18_SEL36_MASK (0x7FU)XBARA_SEL18_SEL36_SHIFT (0U)XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)XBARA_SEL18_SEL37_MASK (0x7F00U)XBARA_SEL18_SEL37_SHIFT (8U)XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)XBARA_SEL19_SEL38_MASK (0x7FU)XBARA_SEL19_SEL38_SHIFT (0U)XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)XBARA_SEL19_SEL39_MASK (0x7F00U)XBARA_SEL19_SEL39_SHIFT (8U)XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)XBARA_SEL20_SEL40_MASK (0x7FU)XBARA_SEL20_SEL40_SHIFT (0U)XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)XBARA_SEL20_SEL41_MASK (0x7F00U)XBARA_SEL20_SEL41_SHIFT (8U)XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)XBARA_SEL21_SEL42_MASK (0x7FU)XBARA_SEL21_SEL42_SHIFT (0U)XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)XBARA_SEL21_SEL43_MASK (0x7F00U)XBARA_SEL21_SEL43_SHIFT (8U)XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)XBARA_SEL22_SEL44_MASK (0x7FU)XBARA_SEL22_SEL44_SHIFT (0U)XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)XBARA_SEL22_SEL45_MASK (0x7F00U)XBARA_SEL22_SEL45_SHIFT (8U)XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)XBARA_SEL23_SEL46_MASK (0x7FU)XBARA_SEL23_SEL46_SHIFT (0U)XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)XBARA_SEL23_SEL47_MASK (0x7F00U)XBARA_SEL23_SEL47_SHIFT (8U)XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)XBARA_SEL24_SEL48_MASK (0x7FU)XBARA_SEL24_SEL48_SHIFT (0U)XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)XBARA_SEL24_SEL49_MASK (0x7F00U)XBARA_SEL24_SEL49_SHIFT (8U)XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)XBARA_SEL25_SEL50_MASK (0x7FU)XBARA_SEL25_SEL50_SHIFT (0U)XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)XBARA_SEL25_SEL51_MASK (0x7F00U)XBARA_SEL25_SEL51_SHIFT (8U)XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)XBARA_SEL26_SEL52_MASK (0x7FU)XBARA_SEL26_SEL52_SHIFT (0U)XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)XBARA_SEL26_SEL53_MASK (0x7F00U)XBARA_SEL26_SEL53_SHIFT (8U)XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)XBARA_SEL27_SEL54_MASK (0x7FU)XBARA_SEL27_SEL54_SHIFT (0U)XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)XBARA_SEL27_SEL55_MASK (0x7F00U)XBARA_SEL27_SEL55_SHIFT (8U)XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)XBARA_SEL28_SEL56_MASK (0x7FU)XBARA_SEL28_SEL56_SHIFT (0U)XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)XBARA_SEL28_SEL57_MASK (0x7F00U)XBARA_SEL28_SEL57_SHIFT (8U)XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)XBARA_SEL29_SEL58_MASK (0x7FU)XBARA_SEL29_SEL58_SHIFT (0U)XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)XBARA_SEL29_SEL59_MASK (0x7F00U)XBARA_SEL29_SEL59_SHIFT (8U)XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)XBARA_SEL30_SEL60_MASK (0x7FU)XBARA_SEL30_SEL60_SHIFT (0U)XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)XBARA_SEL30_SEL61_MASK (0x7F00U)XBARA_SEL30_SEL61_SHIFT (8U)XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)XBARA_SEL31_SEL62_MASK (0x7FU)XBARA_SEL31_SEL62_SHIFT (0U)XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)XBARA_SEL31_SEL63_MASK (0x7F00U)XBARA_SEL31_SEL63_SHIFT (8U)XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)XBARA_SEL32_SEL64_MASK (0x7FU)XBARA_SEL32_SEL64_SHIFT (0U)XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)XBARA_SEL32_SEL65_MASK (0x7F00U)XBARA_SEL32_SEL65_SHIFT (8U)XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)XBARA_SEL33_SEL66_MASK (0x7FU)XBARA_SEL33_SEL66_SHIFT (0U)XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)XBARA_SEL33_SEL67_MASK (0x7F00U)XBARA_SEL33_SEL67_SHIFT (8U)XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)XBARA_SEL34_SEL68_MASK (0x7FU)XBARA_SEL34_SEL68_SHIFT (0U)XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)XBARA_SEL34_SEL69_MASK (0x7F00U)XBARA_SEL34_SEL69_SHIFT (8U)XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)XBARA_SEL35_SEL70_MASK (0x7FU)XBARA_SEL35_SEL70_SHIFT (0U)XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)XBARA_SEL35_SEL71_MASK (0x7F00U)XBARA_SEL35_SEL71_SHIFT (8U)XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)XBARA_SEL36_SEL72_MASK (0x7FU)XBARA_SEL36_SEL72_SHIFT (0U)XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)XBARA_SEL36_SEL73_MASK (0x7F00U)XBARA_SEL36_SEL73_SHIFT (8U)XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)XBARA_SEL37_SEL74_MASK (0x7FU)XBARA_SEL37_SEL74_SHIFT (0U)XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)XBARA_SEL37_SEL75_MASK (0x7F00U)XBARA_SEL37_SEL75_SHIFT (8U)XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)XBARA_SEL38_SEL76_MASK (0x7FU)XBARA_SEL38_SEL76_SHIFT (0U)XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)XBARA_SEL38_SEL77_MASK (0x7F00U)XBARA_SEL38_SEL77_SHIFT (8U)XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)XBARA_SEL39_SEL78_MASK (0x7FU)XBARA_SEL39_SEL78_SHIFT (0U)XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)XBARA_SEL39_SEL79_MASK (0x7F00U)XBARA_SEL39_SEL79_SHIFT (8U)XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)XBARA_SEL40_SEL80_MASK (0x7FU)XBARA_SEL40_SEL80_SHIFT (0U)XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)XBARA_SEL40_SEL81_MASK (0x7F00U)XBARA_SEL40_SEL81_SHIFT (8U)XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)XBARA_SEL41_SEL82_MASK (0x7FU)XBARA_SEL41_SEL82_SHIFT (0U)XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)XBARA_SEL41_SEL83_MASK (0x7F00U)XBARA_SEL41_SEL83_SHIFT (8U)XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)XBARA_SEL42_SEL84_MASK (0x7FU)XBARA_SEL42_SEL84_SHIFT (0U)XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)XBARA_SEL42_SEL85_MASK (0x7F00U)XBARA_SEL42_SEL85_SHIFT (8U)XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)XBARA_SEL43_SEL86_MASK (0x7FU)XBARA_SEL43_SEL86_SHIFT (0U)XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)XBARA_SEL43_SEL87_MASK (0x7F00U)XBARA_SEL43_SEL87_SHIFT (8U)XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)XBARA_SEL44_SEL88_MASK (0x7FU)XBARA_SEL44_SEL88_SHIFT (0U)XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)XBARA_SEL44_SEL89_MASK (0x7F00U)XBARA_SEL44_SEL89_SHIFT (8U)XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)XBARA_SEL45_SEL90_MASK (0x7FU)XBARA_SEL45_SEL90_SHIFT (0U)XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)XBARA_SEL45_SEL91_MASK (0x7F00U)XBARA_SEL45_SEL91_SHIFT (8U)XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)XBARA_SEL46_SEL92_MASK (0x7FU)XBARA_SEL46_SEL92_SHIFT (0U)XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)XBARA_SEL46_SEL93_MASK (0x7F00U)XBARA_SEL46_SEL93_SHIFT (8U)XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)XBARA_SEL47_SEL94_MASK (0x7FU)XBARA_SEL47_SEL94_SHIFT (0U)XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)XBARA_SEL47_SEL95_MASK (0x7F00U)XBARA_SEL47_SEL95_SHIFT (8U)XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)XBARA_SEL48_SEL96_MASK (0x7FU)XBARA_SEL48_SEL96_SHIFT (0U)XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)XBARA_SEL48_SEL97_MASK (0x7F00U)XBARA_SEL48_SEL97_SHIFT (8U)XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)XBARA_SEL49_SEL98_MASK (0x7FU)XBARA_SEL49_SEL98_SHIFT (0U)XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)XBARA_SEL49_SEL99_MASK (0x7F00U)XBARA_SEL49_SEL99_SHIFT (8U)XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)XBARA_SEL50_SEL100_MASK (0x7FU)XBARA_SEL50_SEL100_SHIFT (0U)XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)XBARA_SEL50_SEL101_MASK (0x7F00U)XBARA_SEL50_SEL101_SHIFT (8U)XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)XBARA_SEL51_SEL102_MASK (0x7FU)XBARA_SEL51_SEL102_SHIFT (0U)XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)XBARA_SEL51_SEL103_MASK (0x7F00U)XBARA_SEL51_SEL103_SHIFT (8U)XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)XBARA_SEL52_SEL104_MASK (0x7FU)XBARA_SEL52_SEL104_SHIFT (0U)XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)XBARA_SEL52_SEL105_MASK (0x7F00U)XBARA_SEL52_SEL105_SHIFT (8U)XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)XBARA_SEL53_SEL106_MASK (0x7FU)XBARA_SEL53_SEL106_SHIFT (0U)XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)XBARA_SEL53_SEL107_MASK (0x7F00U)XBARA_SEL53_SEL107_SHIFT (8U)XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)XBARA_SEL54_SEL108_MASK (0x7FU)XBARA_SEL54_SEL108_SHIFT (0U)XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)XBARA_SEL54_SEL109_MASK (0x7F00U)XBARA_SEL54_SEL109_SHIFT (8U)XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)XBARA_SEL55_SEL110_MASK (0x7FU)XBARA_SEL55_SEL110_SHIFT (0U)XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)XBARA_SEL55_SEL111_MASK (0x7F00U)XBARA_SEL55_SEL111_SHIFT (8U)XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)XBARA_SEL56_SEL112_MASK (0x7FU)XBARA_SEL56_SEL112_SHIFT (0U)XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)XBARA_SEL56_SEL113_MASK (0x7F00U)XBARA_SEL56_SEL113_SHIFT (8U)XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)XBARA_SEL57_SEL114_MASK (0x7FU)XBARA_SEL57_SEL114_SHIFT (0U)XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)XBARA_SEL57_SEL115_MASK (0x7F00U)XBARA_SEL57_SEL115_SHIFT (8U)XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)XBARA_SEL58_SEL116_MASK (0x7FU)XBARA_SEL58_SEL116_SHIFT (0U)XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)XBARA_SEL58_SEL117_MASK (0x7F00U)XBARA_SEL58_SEL117_SHIFT (8U)XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)XBARA_SEL59_SEL118_MASK (0x7FU)XBARA_SEL59_SEL118_SHIFT (0U)XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)XBARA_SEL59_SEL119_MASK (0x7F00U)XBARA_SEL59_SEL119_SHIFT (8U)XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)XBARA_SEL60_SEL120_MASK (0x7FU)XBARA_SEL60_SEL120_SHIFT (0U)XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)XBARA_SEL60_SEL121_MASK (0x7F00U)XBARA_SEL60_SEL121_SHIFT (8U)XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)XBARA_SEL61_SEL122_MASK (0x7FU)XBARA_SEL61_SEL122_SHIFT (0U)XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)XBARA_SEL61_SEL123_MASK (0x7F00U)XBARA_SEL61_SEL123_SHIFT (8U)XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)XBARA_SEL62_SEL124_MASK (0x7FU)XBARA_SEL62_SEL124_SHIFT (0U)XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)XBARA_SEL62_SEL125_MASK (0x7F00U)XBARA_SEL62_SEL125_SHIFT (8U)XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)XBARA_SEL63_SEL126_MASK (0x7FU)XBARA_SEL63_SEL126_SHIFT (0U)XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)XBARA_SEL63_SEL127_MASK (0x7F00U)XBARA_SEL63_SEL127_SHIFT (8U)XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)XBARA_SEL64_SEL128_MASK (0x7FU)XBARA_SEL64_SEL128_SHIFT (0U)XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)XBARA_SEL64_SEL129_MASK (0x7F00U)XBARA_SEL64_SEL129_SHIFT (8U)XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)XBARA_SEL65_SEL130_MASK (0x7FU)XBARA_SEL65_SEL130_SHIFT (0U)XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)XBARA_SEL65_SEL131_MASK (0x7F00U)XBARA_SEL65_SEL131_SHIFT (8U)XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)XBARA_CTRL0_DEN0_MASK (0x1U)XBARA_CTRL0_DEN0_SHIFT (0U)XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)XBARA_CTRL0_IEN0_MASK (0x2U)XBARA_CTRL0_IEN0_SHIFT (1U)XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)XBARA_CTRL0_EDGE0_MASK (0xCU)XBARA_CTRL0_EDGE0_SHIFT (2U)XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)XBARA_CTRL0_STS0_MASK (0x10U)XBARA_CTRL0_STS0_SHIFT (4U)XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)XBARA_CTRL0_DEN1_MASK (0x100U)XBARA_CTRL0_DEN1_SHIFT (8U)XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)XBARA_CTRL0_IEN1_MASK (0x200U)XBARA_CTRL0_IEN1_SHIFT (9U)XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)XBARA_CTRL0_EDGE1_MASK (0xC00U)XBARA_CTRL0_EDGE1_SHIFT (10U)XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)XBARA_CTRL0_STS1_MASK (0x1000U)XBARA_CTRL0_STS1_SHIFT (12U)XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)XBARA_CTRL1_DEN2_MASK (0x1U)XBARA_CTRL1_DEN2_SHIFT (0U)XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)XBARA_CTRL1_IEN2_MASK (0x2U)XBARA_CTRL1_IEN2_SHIFT (1U)XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)XBARA_CTRL1_EDGE2_MASK (0xCU)XBARA_CTRL1_EDGE2_SHIFT (2U)XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)XBARA_CTRL1_STS2_MASK (0x10U)XBARA_CTRL1_STS2_SHIFT (4U)XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)XBARA_CTRL1_DEN3_MASK (0x100U)XBARA_CTRL1_DEN3_SHIFT (8U)XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)XBARA_CTRL1_IEN3_MASK (0x200U)XBARA_CTRL1_IEN3_SHIFT (9U)XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)XBARA_CTRL1_EDGE3_MASK (0xC00U)XBARA_CTRL1_EDGE3_SHIFT (10U)XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)XBARA_CTRL1_STS3_MASK (0x1000U)XBARA_CTRL1_STS3_SHIFT (12U)XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)XBARA_BASE (0x403BC000u)XBARA ((XBARA_Type *)XBARA_BASE)XBARA_BASE_ADDRS { XBARA_BASE }XBARA_BASE_PTRS { XBARA }XBARB_SEL0_SEL0_MASK (0x3FU)XBARB_SEL0_SEL0_SHIFT (0U)XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)XBARB_SEL0_SEL1_MASK (0x3F00U)XBARB_SEL0_SEL1_SHIFT (8U)XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)XBARB_SEL1_SEL2_MASK (0x3FU)XBARB_SEL1_SEL2_SHIFT (0U)XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)XBARB_SEL1_SEL3_MASK (0x3F00U)XBARB_SEL1_SEL3_SHIFT (8U)XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)XBARB_SEL2_SEL4_MASK (0x3FU)XBARB_SEL2_SEL4_SHIFT (0U)XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)XBARB_SEL2_SEL5_MASK (0x3F00U)XBARB_SEL2_SEL5_SHIFT (8U)XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)XBARB_SEL3_SEL6_MASK (0x3FU)XBARB_SEL3_SEL6_SHIFT (0U)XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)XBARB_SEL3_SEL7_MASK (0x3F00U)XBARB_SEL3_SEL7_SHIFT (8U)XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)XBARB_SEL4_SEL8_MASK (0x3FU)XBARB_SEL4_SEL8_SHIFT (0U)XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)XBARB_SEL4_SEL9_MASK (0x3F00U)XBARB_SEL4_SEL9_SHIFT (8U)XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)XBARB_SEL5_SEL10_MASK (0x3FU)XBARB_SEL5_SEL10_SHIFT (0U)XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)XBARB_SEL5_SEL11_MASK (0x3F00U)XBARB_SEL5_SEL11_SHIFT (8U)XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)XBARB_SEL6_SEL12_MASK (0x3FU)XBARB_SEL6_SEL12_SHIFT (0U)XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)XBARB_SEL6_SEL13_MASK (0x3F00U)XBARB_SEL6_SEL13_SHIFT (8U)XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)XBARB_SEL7_SEL14_MASK (0x3FU)XBARB_SEL7_SEL14_SHIFT (0U)XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)XBARB_SEL7_SEL15_MASK (0x3F00U)XBARB_SEL7_SEL15_SHIFT (8U)XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)XBARB_BASE (0x403C0000u)XBARB ((XBARB_Type *)XBARB_BASE)XBARB_BASE_ADDRS { XBARB_BASE }XBARB_BASE_PTRS { XBARB }XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)€XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)ÀXTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)ĀXTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)ŀXTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)ƀXTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)ǀXTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)ȀXTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)ɀXTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)ʀXTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)ˀXTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)̀XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)̀XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)΀XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)πXTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)ЀXTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)рXTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)ҀXTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)ӀXTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)ԀXTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)ۀXTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)܀XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)݀XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)ÁXTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)āXTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)ŁXTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)ƁXTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)ǁXTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)ȁXTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)́XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)΁XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)ρXTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)ЁXTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)сXTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)ҁXTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)ӁXTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)ԁXTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)ՁXTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)ցXTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)ׁXTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)؁XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)فXTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)ځXTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)ہXTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)܁XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)݁XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)ށXTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)߁XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)‚XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)ÂXTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)ĂXTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)ɂXTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)ʂXTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)˂XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)̂XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)͂XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)΂XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)ςXTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)ЂXTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)тXTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)҂XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)ӂXTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)ԂXTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)قXTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)ڂXTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)ۂXTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)܂XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)݂XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)ނXTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)߂XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)XTALOSC24M_BASE (0x400D8000u)XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }XTALOSC24M_BASE_PTRS { XTALOSC24M }̃NXP_VAL2FLD(field,value) (((value) << (field ## _SHIFT)) & (field ## _MASK))ӃNXP_FLD2VAL(field,value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) __CORE_CM7_H_GENERIC "?B__CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)C__CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB)D__CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB )G__CORTEX_M (7U)U__FPU_USED 0U__CORE_CM7_H_DEPENDANT __I volatile const__O volatile__IO volatile__IM volatile const__OM volatile__IOM volatileAPSR_N_Pos 31UAPSR_N_Msk (1UL << APSR_N_Pos)APSR_Z_Pos 30UAPSR_Z_Msk (1UL << APSR_Z_Pos)APSR_C_Pos 29UAPSR_C_Msk (1UL << APSR_C_Pos)APSR_V_Pos 28UAPSR_V_Msk (1UL << APSR_V_Pos)APSR_Q_Pos 27UAPSR_Q_Msk (1UL << APSR_Q_Pos)APSR_GE_Pos 16UAPSR_GE_Msk (0xFUL << APSR_GE_Pos)IPSR_ISR_Pos 0UIPSR_ISR_Msk (0x1FFUL )xPSR_N_Pos 31UxPSR_N_Msk (1UL << xPSR_N_Pos)xPSR_Z_Pos 30UxPSR_Z_Msk (1UL << xPSR_Z_Pos)xPSR_C_Pos 29UxPSR_C_Msk (1UL << xPSR_C_Pos)xPSR_V_Pos 28UxPSR_V_Msk (1UL << xPSR_V_Pos)xPSR_Q_Pos 27UxPSR_Q_Msk (1UL << xPSR_Q_Pos)xPSR_ICI_IT_2_Pos 25UxPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)xPSR_T_Pos 24UxPSR_T_Msk (1UL << xPSR_T_Pos)xPSR_GE_Pos 16UxPSR_GE_Msk (0xFUL << xPSR_GE_Pos)xPSR_ICI_IT_1_Pos 10UxPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)xPSR_ISR_Pos 0UxPSR_ISR_Msk (0x1FFUL )CONTROL_FPCA_Pos 2UCONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)CONTROL_SPSEL_Pos 1UCONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)CONTROL_nPRIV_Pos 0UCONTROL_nPRIV_Msk (1UL )NVIC_STIR_INTID_Pos 0UNVIC_STIR_INTID_Msk (0x1FFUL )SCB_CPUID_IMPLEMENTER_Pos 24USCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)SCB_CPUID_VARIANT_Pos 20USCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)SCB_CPUID_ARCHITECTURE_Pos 16USCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)SCB_CPUID_PARTNO_Pos 4USCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)SCB_CPUID_REVISION_Pos 0USCB_CPUID_REVISION_Msk (0xFUL )SCB_ICSR_NMIPENDSET_Pos 31USCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)SCB_ICSR_PENDSVSET_Pos 28USCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)SCB_ICSR_PENDSVCLR_Pos 27USCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)SCB_ICSR_PENDSTSET_Pos 26USCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)SCB_ICSR_PENDSTCLR_Pos 25USCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)SCB_ICSR_ISRPREEMPT_Pos 23USCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)SCB_ICSR_ISRPENDING_Pos 22USCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)SCB_ICSR_VECTPENDING_Pos 12USCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)SCB_ICSR_RETTOBASE_Pos 11USCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)SCB_ICSR_VECTACTIVE_Pos 0USCB_ICSR_VECTACTIVE_Msk (0x1FFUL )SCB_VTOR_TBLOFF_Pos 7USCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)SCB_AIRCR_VECTKEY_Pos 16USCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)SCB_AIRCR_VECTKEYSTAT_Pos 16USCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)SCB_AIRCR_ENDIANESS_Pos 15USCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)SCB_AIRCR_PRIGROUP_Pos 8USCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)SCB_AIRCR_SYSRESETREQ_Pos 2USCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)SCB_AIRCR_VECTCLRACTIVE_Pos 1USCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)SCB_AIRCR_VECTRESET_Pos 0USCB_AIRCR_VECTRESET_Msk (1UL )SCB_SCR_SEVONPEND_Pos 4USCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)SCB_SCR_SLEEPDEEP_Pos 2USCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)SCB_SCR_SLEEPONEXIT_Pos 1USCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)SCB_CCR_BP_Pos 18USCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)SCB_CCR_IC_Pos 17USCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)SCB_CCR_DC_Pos 16USCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)SCB_CCR_STKALIGN_Pos 9USCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)SCB_CCR_BFHFNMIGN_Pos 8USCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)SCB_CCR_DIV_0_TRP_Pos 4USCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)SCB_CCR_UNALIGN_TRP_Pos 3USCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)SCB_CCR_USERSETMPEND_Pos 1USCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)SCB_CCR_NONBASETHRDENA_Pos 0USCB_CCR_NONBASETHRDENA_Msk (1UL )SCB_SHCSR_USGFAULTENA_Pos 18USCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)SCB_SHCSR_BUSFAULTENA_Pos 17USCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)SCB_SHCSR_MEMFAULTENA_Pos 16USCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)SCB_SHCSR_SVCALLPENDED_Pos 15USCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)SCB_SHCSR_BUSFAULTPENDED_Pos 14USCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)SCB_SHCSR_MEMFAULTPENDED_Pos 13USCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)SCB_SHCSR_USGFAULTPENDED_Pos 12USCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)SCB_SHCSR_SYSTICKACT_Pos 11USCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)SCB_SHCSR_PENDSVACT_Pos 10USCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)SCB_SHCSR_MONITORACT_Pos 8USCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)SCB_SHCSR_SVCALLACT_Pos 7USCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)SCB_SHCSR_USGFAULTACT_Pos 3USCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)SCB_SHCSR_BUSFAULTACT_Pos 1USCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)SCB_SHCSR_MEMFAULTACT_Pos 0USCB_SHCSR_MEMFAULTACT_Msk (1UL )SCB_CFSR_USGFAULTSR_Pos 16USCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)SCB_CFSR_BUSFAULTSR_Pos 8USCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)SCB_CFSR_MEMFAULTSR_Pos 0USCB_CFSR_MEMFAULTSR_Msk (0xFFUL )SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)SCB_CFSR_IACCVIOL_Msk (1UL )SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)SCB_HFSR_DEBUGEVT_Pos 31USCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)SCB_HFSR_FORCED_Pos 30USCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)SCB_HFSR_VECTTBL_Pos 1USCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)SCB_DFSR_EXTERNAL_Pos 4USCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)SCB_DFSR_VCATCH_Pos 3USCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)SCB_DFSR_DWTTRAP_Pos 2USCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)SCB_DFSR_BKPT_Pos 1USCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)SCB_DFSR_HALTED_Pos 0USCB_DFSR_HALTED_Msk (1UL )SCB_CLIDR_LOUU_Pos 27USCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)SCB_CLIDR_LOC_Pos 24USCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)SCB_CTR_FORMAT_Pos 29USCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)SCB_CTR_CWG_Pos 24USCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)SCB_CTR_ERG_Pos 20USCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)SCB_CTR_DMINLINE_Pos 16USCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)SCB_CTR_IMINLINE_Pos 0USCB_CTR_IMINLINE_Msk (0xFUL )SCB_CCSIDR_WT_Pos 31USCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)SCB_CCSIDR_WB_Pos 30USCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)SCB_CCSIDR_RA_Pos 29USCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)SCB_CCSIDR_WA_Pos 28USCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)SCB_CCSIDR_NUMSETS_Pos 13USCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)SCB_CCSIDR_ASSOCIATIVITY_Pos 3USCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)SCB_CCSIDR_LINESIZE_Pos 0USCB_CCSIDR_LINESIZE_Msk (7UL )SCB_CSSELR_LEVEL_Pos 1USCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)SCB_CSSELR_IND_Pos 0USCB_CSSELR_IND_Msk (1UL )SCB_STIR_INTID_Pos 0USCB_STIR_INTID_Msk (0x1FFUL )SCB_DCISW_WAY_Pos 30USCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)SCB_DCISW_SET_Pos 5USCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)SCB_DCCSW_WAY_Pos 30USCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)SCB_DCCSW_SET_Pos 5USCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)SCB_DCCISW_WAY_Pos 30USCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)SCB_DCCISW_SET_Pos 5USCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)SCB_ITCMCR_SZ_Pos 3USCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)SCB_ITCMCR_RETEN_Pos 2USCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)SCB_ITCMCR_RMW_Pos 1USCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)SCB_ITCMCR_EN_Pos 0USCB_ITCMCR_EN_Msk (1UL )SCB_DTCMCR_SZ_Pos 3USCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)SCB_DTCMCR_RETEN_Pos 2USCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)SCB_DTCMCR_RMW_Pos 1USCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)SCB_DTCMCR_EN_Pos 0USCB_DTCMCR_EN_Msk (1UL )SCB_AHBPCR_SZ_Pos 1USCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)SCB_AHBPCR_EN_Pos 0USCB_AHBPCR_EN_Msk (1UL )SCB_CACR_FORCEWT_Pos 2USCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)SCB_CACR_ECCEN_Pos 1USCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)SCB_CACR_SIWT_Pos 0USCB_CACR_SIWT_Msk (1UL )SCB_AHBSCR_INITCOUNT_Pos 11USCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)SCB_AHBSCR_TPRI_Pos 2USCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)SCB_AHBSCR_CTL_Pos 0USCB_AHBSCR_CTL_Msk (3UL )SCB_ABFSR_AXIMTYPE_Pos 8USCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)SCB_ABFSR_EPPB_Pos 4USCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)SCB_ABFSR_AXIM_Pos 3USCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)SCB_ABFSR_AHBP_Pos 2USCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)SCB_ABFSR_DTCM_Pos 1USCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)SCB_ABFSR_ITCM_Pos 0USCB_ABFSR_ITCM_Msk (1UL )SCnSCB_ICTR_INTLINESNUM_Pos 0USCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12USCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)SCnSCB_ACTLR_DISRAMODE_Pos 11USCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)SCnSCB_ACTLR_FPEXCODIS_Pos 10USCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)SCnSCB_ACTLR_DISFOLD_Pos 2USCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)SCnSCB_ACTLR_DISMCYCINT_Pos 0USCnSCB_ACTLR_DISMCYCINT_Msk (1UL )SysTick_CTRL_COUNTFLAG_Pos 16USysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)SysTick_CTRL_CLKSOURCE_Pos 2USysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)SysTick_CTRL_TICKINT_Pos 1USysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)SysTick_CTRL_ENABLE_Pos 0USysTick_CTRL_ENABLE_Msk (1UL )SysTick_LOAD_RELOAD_Pos 0USysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )SysTick_VAL_CURRENT_Pos 0USysTick_VAL_CURRENT_Msk (0xFFFFFFUL )SysTick_CALIB_NOREF_Pos 31USysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)SysTick_CALIB_SKEW_Pos 30USysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)SysTick_CALIB_TENMS_Pos 0USysTick_CALIB_TENMS_Msk (0xFFFFFFUL )ITM_TPR_PRIVMASK_Pos 0UITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL )ITM_TCR_BUSY_Pos 23UITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)ITM_TCR_TraceBusID_Pos 16UITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)ITM_TCR_GTSFREQ_Pos 10UITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)ITM_TCR_TSPrescale_Pos 8UITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)ITM_TCR_SWOENA_Pos 4UITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)ITM_TCR_DWTENA_Pos 3UITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)ITM_TCR_SYNCENA_Pos 2UITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)ITM_TCR_TSENA_Pos 1UITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)ITM_TCR_ITMENA_Pos 0UITM_TCR_ITMENA_Msk (1UL )ITM_IWR_ATVALIDM_Pos 0UITM_IWR_ATVALIDM_Msk (1UL )ITM_IRR_ATREADYM_Pos 0UITM_IRR_ATREADYM_Msk (1UL )ITM_IMCR_INTEGRATION_Pos 0UITM_IMCR_INTEGRATION_Msk (1UL )ITM_LSR_ByteAcc_Pos 2UITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)ITM_LSR_Access_Pos 1UITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)ITM_LSR_Present_Pos 0UITM_LSR_Present_Msk (1UL )DWT_CTRL_NUMCOMP_Pos 28UDWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)DWT_CTRL_NOTRCPKT_Pos 27UDWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) DWT_CTRL_NOEXTTRIG_Pos 26U DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) DWT_CTRL_NOCYCCNT_Pos 25U DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) DWT_CTRL_NOPRFCNT_Pos 24U DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) DWT_CTRL_CYCEVTENA_Pos 22U DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) DWT_CTRL_FOLDEVTENA_Pos 21U DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) DWT_CTRL_LSUEVTENA_Pos 20U DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) DWT_CTRL_SLEEPEVTENA_Pos 19U DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) DWT_CTRL_EXCEVTENA_Pos 18U DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) DWT_CTRL_CPIEVTENA_Pos 17U DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) DWT_CTRL_EXCTRCENA_Pos 16U DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) DWT_CTRL_PCSAMPLENA_Pos 12U DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) DWT_CTRL_SYNCTAP_Pos 10U DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) DWT_CTRL_CYCTAP_Pos 9U DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) DWT_CTRL_POSTINIT_Pos 5U DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) DWT_CTRL_POSTPRESET_Pos 1U DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) DWT_CTRL_CYCCNTENA_Pos 0U DWT_CTRL_CYCCNTENA_Msk (0x1UL ) DWT_CPICNT_CPICNT_Pos 0U DWT_CPICNT_CPICNT_Msk (0xFFUL ) DWT_EXCCNT_EXCCNT_Pos 0U DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) DWT_SLEEPCNT_SLEEPCNT_Pos 0U DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) DWT_LSUCNT_LSUCNT_Pos 0U DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) DWT_FOLDCNT_FOLDCNT_Pos 0U DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) DWT_MASK_MASK_Pos 0U DWT_MASK_MASK_Msk (0x1FUL ) DWT_FUNCTION_MATCHED_Pos 24U DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) DWT_FUNCTION_DATAVADDR1_Pos 16U DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) DWT_FUNCTION_DATAVADDR0_Pos 12U DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) DWT_FUNCTION_DATAVSIZE_Pos 10U DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) DWT_FUNCTION_LNK1ENA_Pos 9U DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) DWT_FUNCTION_DATAVMATCH_Pos 8U DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) DWT_FUNCTION_CYCMATCH_Pos 7U DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) DWT_FUNCTION_EMITRANGE_Pos 5U DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) DWT_FUNCTION_FUNCTION_Pos 0U DWT_FUNCTION_FUNCTION_Msk (0xFUL ) TPI_ACPR_PRESCALER_Pos 0U TPI_ACPR_PRESCALER_Msk (0x1FFFUL ) TPI_ACPR_SWOSCALER_Pos 0U TPI_ACPR_SWOSCALER_Msk (0xFFFFUL ) TPI_SPPR_TXMODE_Pos 0U TPI_SPPR_TXMODE_Msk (0x3UL ) TPI_FFSR_FtNonStop_Pos 3U TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) TPI_FFSR_TCPresent_Pos 2U TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) TPI_FFSR_FtStopped_Pos 1U TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) TPI_FFSR_FlInProg_Pos 0U TPI_FFSR_FlInProg_Msk (0x1UL ) TPI_FFCR_TrigIn_Pos 8U TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) TPI_FFCR_EnFCont_Pos 1U TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) TPI_TRIGGER_TRIGGER_Pos 0U TPI_TRIGGER_TRIGGER_Msk (0x1UL ) TPI_FIFO0_ITM_ATVALID_Pos 29U TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) TPI_FIFO0_ITM_bytecount_Pos 27U TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) TPI_FIFO0_ETM_ATVALID_Pos 26U TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) TPI_FIFO0_ETM_bytecount_Pos 24U TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) TPI_FIFO0_ETM2_Pos 16U TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) TPI_FIFO0_ETM1_Pos 8U TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) TPI_FIFO0_ETM0_Pos 0U TPI_FIFO0_ETM0_Msk (0xFFUL ) TPI_ITATBCTR2_ATREADY_Pos 0U TPI_ITATBCTR2_ATREADY_Msk (0x1UL ) TPI_FIFO1_ITM_ATVALID_Pos 29U TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) TPI_FIFO1_ITM_bytecount_Pos 27U TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) TPI_FIFO1_ETM_ATVALID_Pos 26U TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) TPI_FIFO1_ETM_bytecount_Pos 24U TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) TPI_FIFO1_ITM2_Pos 16U TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) TPI_FIFO1_ITM1_Pos 8U TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) TPI_FIFO1_ITM0_Pos 0U TPI_FIFO1_ITM0_Msk (0xFFUL ) TPI_ITATBCTR0_ATREADY_Pos 0U TPI_ITATBCTR0_ATREADY_Msk (0x1UL ) TPI_ITCTRL_Mode_Pos 0U TPI_ITCTRL_Mode_Msk (0x1UL ) TPI_DEVID_NRZVALID_Pos 11U TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) TPI_DEVID_MANCVALID_Pos 10U TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) TPI_DEVID_PTINVALID_Pos 9U TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) TPI_DEVID_MinBufSz_Pos 6U TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) TPI_DEVID_AsynClkIn_Pos 5U TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) TPI_DEVID_NrTraceInput_Pos 0U TPI_DEVID_NrTraceInput_Msk (0x1FUL ) TPI_DEVTYPE_MajorType_Pos 4U TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) TPI_DEVTYPE_SubType_Pos 0U TPI_DEVTYPE_SubType_Msk (0xFUL ) MPU_TYPE_RALIASES 4U MPU_TYPE_IREGION_Pos 16U MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) MPU_TYPE_DREGION_Pos 8U MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) MPU_TYPE_SEPARATE_Pos 0U MPU_TYPE_SEPARATE_Msk (1UL ) MPU_CTRL_PRIVDEFENA_Pos 2U MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) MPU_CTRL_HFNMIENA_Pos 1U MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) MPU_CTRL_ENABLE_Pos 0U MPU_CTRL_ENABLE_Msk (1UL ) MPU_RNR_REGION_Pos 0U MPU_RNR_REGION_Msk (0xFFUL ) MPU_RBAR_ADDR_Pos 5U MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) MPU_RBAR_VALID_Pos 4U MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) MPU_RBAR_REGION_Pos 0U MPU_RBAR_REGION_Msk (0xFUL ) MPU_RASR_ATTRS_Pos 16U MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) MPU_RASR_XN_Pos 28U MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) MPU_RASR_AP_Pos 24U MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) MPU_RASR_TEX_Pos 19U MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) MPU_RASR_S_Pos 18U MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) MPU_RASR_C_Pos 17U MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) MPU_RASR_B_Pos 16U MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) MPU_RASR_SRD_Pos 8U MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) MPU_RASR_SIZE_Pos 1U MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) MPU_RASR_ENABLE_Pos 0U MPU_RASR_ENABLE_Msk (1UL ) FPU_FPCCR_ASPEN_Pos 31U FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) FPU_FPCCR_LSPEN_Pos 30U FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) FPU_FPCCR_MONRDY_Pos 8U FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) FPU_FPCCR_BFRDY_Pos 6U FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) FPU_FPCCR_MMRDY_Pos 5U FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) FPU_FPCCR_HFRDY_Pos 4U FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) FPU_FPCCR_THREAD_Pos 3U FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) FPU_FPCCR_USER_Pos 1U FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) FPU_FPCCR_LSPACT_Pos 0U FPU_FPCCR_LSPACT_Msk (1UL ) FPU_FPCAR_ADDRESS_Pos 3U FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) FPU_FPDSCR_AHP_Pos 26U FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) FPU_FPDSCR_DN_Pos 25U FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) FPU_FPDSCR_FZ_Pos 24U FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) FPU_FPDSCR_RMode_Pos 22U FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) FPU_MVFR0_FP_rounding_modes_Pos 28U FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) FPU_MVFR0_Short_vectors_Pos 24U FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) FPU_MVFR0_Square_root_Pos 20U FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) FPU_MVFR0_Divide_Pos 16U FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) FPU_MVFR0_FP_excep_trapping_Pos 12U FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) FPU_MVFR0_Double_precision_Pos 8U FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) FPU_MVFR0_Single_precision_Pos 4U FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) FPU_MVFR0_A_SIMD_registers_Pos 0U FPU_MVFR0_A_SIMD_registers_Msk (0xFUL ) FPU_MVFR1_FP_fused_MAC_Pos 28U FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) FPU_MVFR1_FP_HPFP_Pos 24U FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) FPU_MVFR1_D_NaN_mode_Pos 4U FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) FPU_MVFR1_FtZ_mode_Pos 0U FPU_MVFR1_FtZ_mode_Msk (0xFUL ) CoreDebug_DHCSR_DBGKEY_Pos 16U CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) CoreDebug_DHCSR_S_RESET_ST_Pos 25U CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) CoreDebug_DHCSR_S_LOCKUP_Pos 19U CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) CoreDebug_DHCSR_S_SLEEP_Pos 18U CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) CoreDebug_DHCSR_S_HALT_Pos 17U CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) CoreDebug_DHCSR_S_REGRDY_Pos 16U CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) CoreDebug_DHCSR_C_MASKINTS_Pos 3U CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) CoreDebug_DHCSR_C_STEP_Pos 2U CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) CoreDebug_DHCSR_C_HALT_Pos 1U CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) CoreDebug_DHCSR_C_DEBUGEN_Pos 0U CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) CoreDebug_DCRSR_REGWnR_Pos 16U CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) CoreDebug_DCRSR_REGSEL_Pos 0U CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) CoreDebug_DEMCR_TRCENA_Pos 24U CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) CoreDebug_DEMCR_MON_REQ_Pos 19U CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) CoreDebug_DEMCR_MON_STEP_Pos 18U CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) CoreDebug_DEMCR_MON_PEND_Pos 17U CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) CoreDebug_DEMCR_MON_EN_Pos 16U CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) CoreDebug_DEMCR_VC_HARDERR_Pos 10U CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) CoreDebug_DEMCR_VC_INTERR_Pos 9U CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) CoreDebug_DEMCR_VC_BUSERR_Pos 8U CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) CoreDebug_DEMCR_VC_STATERR_Pos 7U CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) CoreDebug_DEMCR_VC_CHKERR_Pos 6U CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) CoreDebug_DEMCR_VC_NOCPERR_Pos 5U CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) CoreDebug_DEMCR_VC_MMERR_Pos 4U CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) CoreDebug_DEMCR_VC_CORERESET_Pos 0U CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) _VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) _FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) SCS_BASE (0xE000E000UL) ITM_BASE (0xE0000000UL) DWT_BASE (0xE0001000UL) TPI_BASE (0xE0040000UL) CoreDebug_BASE (0xE000EDF0UL) SysTick_BASE (SCS_BASE + 0x0010UL) NVIC_BASE (SCS_BASE + 0x0100UL) SCB_BASE (SCS_BASE + 0x0D00UL) SCnSCB ((SCnSCB_Type *) SCS_BASE ) SCB ((SCB_Type *) SCB_BASE ) SysTick ((SysTick_Type *) SysTick_BASE ) NVIC ((NVIC_Type *) NVIC_BASE ) ITM ((ITM_Type *) ITM_BASE ) DWT ((DWT_Type *) DWT_BASE ) TPI ((TPI_Type *) TPI_BASE ) CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) MPU_BASE (SCS_BASE + 0x0D90UL) MPU ((MPU_Type *) MPU_BASE ) FPU_BASE (SCS_BASE + 0x0F30UL) FPU ((FPU_Type *) FPU_BASE )NVIC_SetPriorityGrouping __NVIC_SetPriorityGroupingNVIC_GetPriorityGrouping __NVIC_GetPriorityGroupingNVIC_EnableIRQ __NVIC_EnableIRQNVIC_GetEnableIRQ __NVIC_GetEnableIRQNVIC_DisableIRQ __NVIC_DisableIRQNVIC_GetPendingIRQ __NVIC_GetPendingIRQNVIC_SetPendingIRQ __NVIC_SetPendingIRQNVIC_ClearPendingIRQ __NVIC_ClearPendingIRQNVIC_GetActive __NVIC_GetActiveNVIC_SetPriority __NVIC_SetPriorityNVIC_GetPriority __NVIC_GetPriorityNVIC_SystemReset __NVIC_SystemResetNVIC_SetVector __NVIC_SetVectorNVIC_GetVector __NVIC_GetVectorNVIC_USER_IRQ_OFFSET 16CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) __stdint_h  __ARMCLIB_VERSION 5060037__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS sINT8_MIN -128tINT16_MIN -32768uINT32_MIN (~0x7fffffff)vINT64_MIN __INT64_C(~0x7fffffffffffffff)yINT8_MAX 127zINT16_MAX 32767{INT32_MAX 2147483647|INT64_MAX __INT64_C(9223372036854775807)UINT8_MAX 255UINT16_MAX 65535UINT32_MAX 4294967295uUINT64_MAX __UINT64_C(18446744073709551615)INT_LEAST8_MIN -128INT_LEAST16_MIN -32768INT_LEAST32_MIN (~0x7fffffff)INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_LEAST8_MAX 127INT_LEAST16_MAX 32767INT_LEAST32_MAX 2147483647INT_LEAST64_MAX __INT64_C(9223372036854775807)UINT_LEAST8_MAX 255UINT_LEAST16_MAX 65535UINT_LEAST32_MAX 4294967295uUINT_LEAST64_MAX __UINT64_C(18446744073709551615)INT_FAST8_MIN (~0x7fffffff)INT_FAST16_MIN (~0x7fffffff)INT_FAST32_MIN (~0x7fffffff)INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_FAST8_MAX 2147483647INT_FAST16_MAX 2147483647INT_FAST32_MAX 2147483647INT_FAST64_MAX __INT64_C(9223372036854775807)UINT_FAST8_MAX 4294967295uUINT_FAST16_MAX 4294967295uUINT_FAST32_MAX 4294967295uUINT_FAST64_MAX __UINT64_C(18446744073709551615)INTPTR_MIN INT32_MININTPTR_MAX INT32_MAXUINTPTR_MAX UINT32_MAXINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)INTMAX_MAX __ESCAPE__(9223372036854775807ll)UINTMAX_MAX __ESCAPE__(18446744073709551615ull)PTRDIFF_MIN INT32_MINPTRDIFF_MAX INT32_MAXSIG_ATOMIC_MIN (~0x7fffffff)SIG_ATOMIC_MAX 2147483647SIZE_MAX UINT32_MAXWCHAR_MINWCHAR_MAXWCHAR_MIN 0WCHAR_MAX 65535WINT_MIN (~0x7fffffff)WINT_MAX 2147483647INT8_C(x) (x)INT16_C(x) (x)INT32_C(x) (x)INT64_C(x) __INT64_C(x)UINT8_C(x) (x ## u)UINT16_C(x) (x ## u)UINT32_C(x) (x ## u)UINT64_C(x) __UINT64_C(x)INTMAX_C(x) __ESCAPE__(x ## ll)UINTMAX_C(x) __ESCAPE__(x ## ull)__INT64__LONGLONG VERS 1 UNKNOWN 0ONCHIP 1EXT8BIT 2EXT16BIT 3EXT32BIT 4EXTSPI 5SECTOR_NUM 512PAGE_MAX 65536SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF0FLASH_DRV_VERS (0x0100 + VERS)ITM_RxBufferJHiSystemInitHookSystemInit"SystemCoreClockUpdate"kSystemCoreClockXLnsflexspi_is_parallel_modeflexspi_is_padsetting_override_enable&flexspi_is_differential_clock_enableflexspi_is_word_addressableflexspi_is_ck2_enabled.flexspi_is_ddr_mode_enableflexspi_configure_dllflexspi_get_ticks~flexspi_config_mcr1Nflexspi_config_flash_control_registersv flexspi_config_ahb_buffers flexspi_clear_sequence_pointer} flexspi_command_xfer4 flexspi_update_lut/flexspi_device_write_enableflexspi_device_wait_busyflexspi_initflexspi_wait_idleflexspi_clear_cacheIflexspi_half_clock_controlQflexspi_nor_flash_init0flexspi_nor_flash_page_program flexspi_nor_flash_erase_allflexspi_nor_flash_erase_sectorflexspi_nor_flash_erase_block get_page_sector_block_size_from_sfdpbflexspi_nor_restore_spi_protocol6flexspi_nor_get_configflexspi_nor_flash_eraseflexspi_nor_flash_read CLOCK_GetPllFreqCLOCK_GetSysPfdFreqICLOCK_GetUsb1PfdFreqCLOCK_InitExternalClk<CLOCK_DeinitExternalClkiCLOCK_SwitchOscCLOCK_InitRcOsc24MCLOCK_DeinitRcOsc24MCLOCK_GetAhbFreq,CLOCK_GetSemcFreqyCLOCK_GetIpgFreqCLOCK_GetFreq*CLOCK_GetPerClkFreqyCLOCK_EnableUsbhs0ClockCLOCK_InitUsb1Pll&CLOCK_EnableUsbhs0PhyPllClockCLOCK_DisableUsbhs0PhyPllClockCLOCK_InitSysPllCLOCK_DeinitSysPll8CLOCK_DeinitUsb1PllaCLOCK_InitAudioPllCLOCK_DeinitAudioPllCLOCK_InitEnetPll/CLOCK_DeinitEnetPllXCLOCK_InitSysPfdCLOCK_DeinitSysPfdCLOCK_InitUsb1Pfd_ CLOCK_DeinitUsb1Pfd SDK_DelayAtLeastUs/g_xtalFreqg_rtcXtalFreqXflexspi_iomux_configflexspi_set_failsafe_settingflexspi_nor_write_persistentEflexspi_nor_read_persistent/0 g_xtalFreq#g_rtcXtalFreq clock_initflexspi_clock_gate_enableaflexspi_clock_gate_disableflexspi_clock_configflexspi_get_clock9flexspi_get_max_supported_freqget_core_clockget_bus_clockWflexspi_sw_delay_us FlashDeviceEITM_RxBufferddisableWatchdogInit{UnInitEraseChipEraseSector*ProgramPageconfigF|rj  J b 4f""<'l'p++080v44|8899::>>CCI,IL MvNNPPP QQRT8*T6p<NRT_Tj<*X6|_Q(@*\6D*`26e |NTQTQH*d6D1Jbj |?FA R#$8> &k&8'fm'q,"1j336_QgL*h6::: : /;=>'>B=> ]}CT{9EFPQFgGP_RRP*lM6IKvELNT6 M6$N6N86N6:OZ    6P6P06P06P G6PGX6PX6P G6PG6PGGGG6 QGlGGGGGGG}89E=|AEI M9 Qj U Y ] a( eY i m q < E K c& ( }   3 H Z %(y M U sH  #: ]  g  t& : O Je  }   1  ?  M  N #  A   4 M L# Z5 ZS Mr i        l   6 6.B-"U:lmQ6c ]**38A 9Y:p::::;;"A;8=XJi=~^G>c?f?:@ruBCzChG)GI(;oI OI<jI"yIqJ^!M!M%NR%NNZNO3O3O7O7O 7O.;O<;OMOOZOOFjPpP~P PP PPPP P!Q4!UQ07QLRST^TlT|T$t$d$d.realdataFlashPrg.c.rev16_text.revsh_text.textSCB_DisableDCache.dataFlashDev.c.constdatabsp\\src\\clock_config_MIMXRT1015.cbsp\src\clock_config_MIMXRT1015.cbsp\\src\\hardware_init_MIMXRT1015.cbsp\src\hardware_init_MIMXRT1015.c..\\..\\..\\..\\devices\\MIMXRT1015\\drivers\\fsl_clock.c..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.cCLOCK_GetPeriphClkFreqCLOCK_GetOscFreqi.__ARM_common_switch8i.__ARM_common_ll_muluumiddleware\\flexspi_nor\\flexspi_nor_flash.cmiddleware\flexspi_nor\flexspi_nor_flash.cflexspi_nor_exit_no_cmd_modeflexspi_nor_write_enableflexspi_nor_restore_no_cmd_modeflexspi_nor_wait_busyflexspi_change_serial_clockflexspi_nor_read_sfdpprepare_quad_mode_enable_sequenceprepare_0_4_4_mode_enable_sequenceprobe_dtr_quad_read_dummy_cyclesparse_sfdpflexspi_nor_read_sfdp_infoflexspi_nor_generate_config_block_using_sfdpflexspi_nor_hyperbus_readflexspi_nor_hyperbus_writeflexspi_nor_generate_config_block_hyperflashflexspi_nor_generate_config_block_mxic_octalflashflexspi_nor_generate_config_block_micron_octalflashflexspi_nor_generate_config_block_adesto_octalflashmiddleware\\flexspi\\fsl_flexspi.cmiddleware\flexspi\fsl_flexspi.cflexspi_swresetflexspi_unlock_lutflexspi_lock_lutflexspi_get_module_baseflexspi_clear_ip_txfifoflexspi_clear_ip_rxfifoflexspi_wait_until_ip_idleflexspi_clear_error_statusflexspi_extract_parallel_dataflexspi_device_workmode_configflexspi_device_workmode_config_all_chipsflexspi_device_cmd_configflexspi_device_cmd_config_all_chipsg_flexSpiInstances..\\..\\..\\..\\devices\\MIMXRT1015\\system_MIMXRT1015.c..\..\..\..\devices\MIMXRT1015\system_MIMXRT1015.cSCB_EnableICacheSCB_EnableDCachedc.s../clib/division.c../clib/assert.c../clib/string.c../clib/memcpset.c.emb_text../clib/division.s../clib/angel/rt.s../clib/stdlib.c../clib/angel/sysapp.c../clib/signal.c../clib/angel/sys.s../clib/signal.sBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$RWPI$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2__aeabi_memcpy4__aeabi_memcpy8__asm___10_FlashPrg_c_config____REV16__asm___25_clock_config_MIMXRT1015_c_efd8dd31____REV16__asm___26_hardware_init_MIMXRT1015_c_753bbbb7____REV16__asm___11_fsl_clock_c_07a918fd____REV16__asm___19_flexspi_nor_flash_c_93f2e184____REV16__asm___13_fsl_flexspi_c_c729c902____REV16__asm___19_system_MIMXRT1015_c_5d646a67____REV16__asm___10_FlashPrg_c_config____REVSH__asm___25_clock_config_MIMXRT1015_c_efd8dd31____REVSH__asm___26_hardware_init_MIMXRT1015_c_753bbbb7____REVSH__asm___11_fsl_clock_c_07a918fd____REVSH__asm___19_flexspi_nor_flash_c_93f2e184____REVSH__asm___13_fsl_flexspi_c_c729c902____REVSH__asm___19_system_MIMXRT1015_c_5d646a67____REVSHdisableWatchdogInitUnInitEraseChipEraseSectorProgramPageclock_initflexspi_clock_gate_enableflexspi_clock_gate_disableflexspi_clock_configflexspi_get_clockflexspi_get_max_supported_freqget_core_clockget_bus_clockflexspi_sw_delay_usflexspi_iomux_configflexspi_set_failsafe_settingflexspi_nor_write_persistentflexspi_nor_read_persistentCLOCK_GetPllFreqCLOCK_GetSysPfdFreqCLOCK_GetUsb1PfdFreqCLOCK_InitExternalClkCLOCK_DeinitExternalClkCLOCK_SwitchOscCLOCK_InitRcOsc24MCLOCK_DeinitRcOsc24MCLOCK_GetAhbFreqCLOCK_GetSemcFreqCLOCK_GetIpgFreqCLOCK_GetFreqCLOCK_GetPerClkFreqCLOCK_EnableUsbhs0ClockCLOCK_InitUsb1PllCLOCK_EnableUsbhs0PhyPllClockCLOCK_DisableUsbhs0PhyPllClockCLOCK_InitSysPllCLOCK_DeinitSysPllCLOCK_DeinitUsb1PllCLOCK_InitAudioPllCLOCK_DeinitAudioPllCLOCK_InitEnetPllCLOCK_DeinitEnetPllCLOCK_InitSysPfdCLOCK_DeinitSysPfdCLOCK_InitUsb1PfdCLOCK_DeinitUsb1PfdSDK_DelayAtLeastUsflexspi_nor_flash_initflexspi_nor_flash_page_programflexspi_nor_flash_erase_allflexspi_nor_flash_erase_sectorflexspi_nor_flash_erase_blockget_page_sector_block_size_from_sfdpflexspi_nor_restore_spi_protocolflexspi_nor_get_configflexspi_nor_flash_eraseflexspi_nor_flash_readflexspi_is_parallel_modeflexspi_is_padsetting_override_enableflexspi_is_differential_clock_enableflexspi_is_word_addressableflexspi_is_ck2_enabledflexspi_is_ddr_mode_enableflexspi_configure_dllflexspi_get_ticksflexspi_config_mcr1flexspi_config_flash_control_registersflexspi_config_ahb_buffersflexspi_clear_sequence_pointerflexspi_command_xferflexspi_update_lutflexspi_device_write_enableflexspi_device_wait_busyflexspi_initflexspi_wait_idleflexspi_clear_cacheflexspi_half_clock_controlSystemInitHookSystemInitSystemCoreClockUpdate__aeabi_uldivmod_ll_udiv__aeabi_assert__assertmemcmp_memset_w_memset__aeabi_memclr__rt_memclr__aeabi_memclr4__aeabi_memclr8__rt_memclr_w__aeabi_uidiv__aeabi_uidivmod__aeabi_idiv__aeabi_idivmodabort__assert_puts_ttywrch_sys_exit__rt_SIGABRT__I$use$semihosting__use_no_semihosting_swi__semihosting_library_function__sig_exit__rt_SIGABRT_inner__default_signal_display__ARM_common_ll_muluu__ARM_common_switch8configg_xtalFreqg_rtcXtalFreqSystemCoreClockFlashDevice @ARMComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]ArmLink --strict --load_addr_map_info --map --symbols --diag_suppress=9931,L6305 --cpu=Cortex-M0 --list=.\MIMXRT1015_QSPI.map --output=.\Output\MIMXRT1015_QSPI.axf --scatter=.\Target.lin --info=summarysizes,sizes,totals,unused,veneers C:\Keil_v525\ARM\ARMCC\Bin\..\lib\armlib\c_pe.lC:\Keil_v525\ARM\ARMCC\Bin\..\lib\armlib\fz_ps.lC:\Keil_v525\ARM\ARMCC\Bin\..\lib\armlib\h_pe.lC:\Keil_v525\ARM\ARMCC\Bin\..\lib\armlib\m_ps.lC:\Keil_v525\ARM\ARMCC\Bin\..\lib\armlib\vfpsupport.lInput Comments:flashprg.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\flashprg.o --vfemode=force Input Comments:p32fc-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide flashprg.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flashprg.o --depend=.\output\flashprg.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi -O0 --diag_suppress=9931 -I.\middleware -I..\..\..\..\CMSIS\Include -I..\..\..\..\devices\MIMXRT1015 -I..\..\..\..\devices\MIMXRT1015\drivers -I..\..\..\..\platform\drivers\common -IC:\Keil_v525\ARM\RV31\INC -IC:\Keil_v525\ARM\CMSIS\Include -IC:\Keil_v525\ARM\INC\Philips -D__UVISION_VERSION=525 -DCPU_MIMXRT1015DAF5A --omf_browse=.\output\flashprg.crf FlashPrg.cflashdev.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flashdev.o --depend=.\output\flashdev.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi -O0 --diag_suppress=9931 -I.\middleware -I..\..\..\..\CMSIS\Include -I..\..\..\..\devices\MIMXRT1015 -I..\..\..\..\devices\MIMXRT1015\drivers -I..\..\..\..\platform\drivers\common -IC:\Keil_v525\ARM\RV31\INC -IC:\Keil_v525\ARM\CMSIS\Include -IC:\Keil_v525\ARM\INC\Philips -D__UVISION_VERSION=525 -DCPU_MIMXRT1015DAF5A --omf_browse=.\output\flashdev.crf FlashDev.cclock_config_mimxrt1015.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\clock_config_mimxrt1015.o --vfemode=force Input Comments:p4354-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide clock_config_mimxrt1015.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\clock_config_mimxrt1015.o --depend=.\output\clock_config_mimxrt1015.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi -O0 --diag_suppress=9931 -I.\middleware -I..\..\..\..\CMSIS\Include -I..\..\..\..\devices\MIMXRT1015 -I..\..\..\..\devices\MIMXRT1015\drivers -I..\..\..\..\platform\drivers\common -IC:\Keil_v525\ARM\RV31\INC -IC:\Keil_v525\ARM\CMSIS\Include -IC:\Keil_v525\ARM\INC\Philips -D__UVISION_VERSION=525 -DCPU_MIMXRT1015DAF5A --omf_browse=.\output\clock_config_mimxrt1015.crf bsp\src\clock_config_MIMXRT1015.chardware_init_mimxrt1015.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\hardware_init_mimxrt1015.o --vfemode=force Input Comments:p44fc-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide hardware_init_mimxrt1015.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\hardware_init_mimxrt1015.o --depend=.\output\hardware_init_mimxrt1015.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi -O0 --diag_suppress=9931 -I.\middleware -I..\..\..\..\CMSIS\Include -I..\..\..\..\devices\MIMXRT1015 -I..\..\..\..\devices\MIMXRT1015\drivers -I..\..\..\..\platform\drivers\common -IC:\Keil_v525\ARM\RV31\INC -IC:\Keil_v525\ARM\CMSIS\Include -IC:\Keil_v525\ARM\INC\Philips -D__UVISION_VERSION=525 -DCPU_MIMXRT1015DAF5A --omf_browse=.\output\hardware_init_mimxrt1015.crf bsp\src\hardware_init_MIMXRT1015.cfsl_clock.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\fsl_clock.o --vfemode=force Input Comments:pbd8-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide fsl_clock.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\fsl_clock.o --depend=.\output\fsl_clock.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi -O0 --diag_suppress=9931 -I.\middleware -I..\..\..\..\CMSIS\Include -I..\..\..\..\devices\MIMXRT1015 -I..\..\..\..\devices\MIMXRT1015\drivers -I..\..\..\..\platform\drivers\common -IC:\Keil_v525\ARM\RV31\INC -IC:\Keil_v525\ARM\CMSIS\Include -IC:\Keil_v525\ARM\INC\Philips -D__UVISION_VERSION=525 -DCPU_MIMXRT1015DAF5A --omf_browse=.\output\fsl_clock.crf ..\..\..\..\devices\MIMXRT1015\drivers\fsl_clock.cflexspi_nor_flash.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\flexspi_nor_flash.o --vfemode=force Input Comments:p3f8c-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide flexspi_nor_flash.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flexspi_nor_flash.o --depend=.\output\flexspi_nor_flash.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi -O0 --diag_suppress=9931 -I.\middleware -I..\..\..\..\CMSIS\Include -I..\..\..\..\devices\MIMXRT1015 -I..\..\..\..\devices\MIMXRT1015\drivers -I..\..\..\..\platform\drivers\common -IC:\Keil_v525\ARM\RV31\INC -IC:\Keil_v525\ARM\CMSIS\Include -IC:\Keil_v525\ARM\INC\Philips -D__UVISION_VERSION=525 -DCPU_MIMXRT1015DAF5A --omf_browse=.\output\flexspi_nor_flash.crf middleware\flexspi_nor\flexspi_nor_flash.cfsl_flexspi.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\fsl_flexspi.o --vfemode=force Input Comments:p412c-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide fsl_flexspi.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\fsl_flexspi.o --depend=.\output\fsl_flexspi.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi -O0 --diag_suppress=9931 -I.\middleware -I..\..\..\..\CMSIS\Include -I..\..\..\..\devices\MIMXRT1015 -I..\..\..\..\devices\MIMXRT1015\drivers -I..\..\..\..\platform\drivers\common -IC:\Keil_v525\ARM\RV31\INC -IC:\Keil_v525\ARM\CMSIS\Include -IC:\Keil_v525\ARM\INC\Philips -D__UVISION_VERSION=525 -DCPU_MIMXRT1015DAF5A --omf_browse=.\output\fsl_flexspi.crf middleware\flexspi\fsl_flexspi.csystem_mimxrt1015.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\system_mimxrt1015.o --vfemode=force Input Comments:pa4c-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide system_mimxrt1015.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\system_mimxrt1015.o --depend=.\output\system_mimxrt1015.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi -O0 --diag_suppress=9931 -I.\middleware -I..\..\..\..\CMSIS\Include -I..\..\..\..\devices\MIMXRT1015 -I..\..\..\..\devices\MIMXRT1015\drivers -I..\..\..\..\platform\drivers\common -IC:\Keil_v525\ARM\RV31\INC -IC:\Keil_v525\ARM\CMSIS\Include -IC:\Keil_v525\ARM\INC\Philips -D__UVISION_VERSION=525 -DCPU_MIMXRT1015DAF5A --omf_browse=.\output\system_mimxrt1015.crf ..\..\..\..\devices\MIMXRT1015\system_MIMXRT1015.cPrgCodePrgDataDevDscr.debug_abbrev.debug_frame.debug_info.debug_line.debug_loc.debug_macinfo.debug_pubnames.symtab.strtab.note.comment.shstrtab4TT0TTT 4R RRTTe'Tk4d{@E@GL,7WdfP v ~#X