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B F(FaiIi#@#ЙB iAHII aiII IID`H0kFI h!HC @ @ ( @@ @6n@e @FF FCsЮFF FAgfF'$=FAF:F!$eFvF/6 >C- A +C4eFvF/6 >C- A+C4eFvF/6 >C- A+C$eFvF>CAӕ+CeFvFv>CmAӒ[AdvFeFIAA `FAFF%@iAR*C[drFcF FFF*F#F FF F C* B!B  C*R x x@Ix x@IђF )ҋppG) p@I)Ӄ""" B, B#FNF C<"CB1 B BӔF? BRA BӋRAC BKRA B RABRABӋRACBKRAAFRAFpG]IB@BS@"F B- B" B ӉBӉBӉ:В BRA BӋRAC BKRA B RABRABӋRACBKRAAFcFRA[F@B+IBpGcF[@B FFI & pG(! SIGABRT: Abnormal terminationpF F m-(x(d , x( piFp  &F^C F7 XC6!yAFnC7 6yA&FnC0tFd%xdBFc][0G@x}@Ys"  !"3DUfwZ0$Z 1%Z 2&$` '` Z0$Z Z0$Z &Z 'ZZ *@@ܳMIMXRT1020 8mB QuadSPI NOR Flash`d!/!I$ > %%%% %C %C % % %%%C%C&I  ((      1 1 1 1 I8  I I8 4 ! I8 "I#7I$I%I&I 'I(I) * +,-./4  04 14 24 34 44 5.:;9? I6.:;9? 7.:;9G8.:;9? I 9.:;9? :.:;9G ;.:;9? I<.:;9? =.:;9G>.:;9? I@?.:;9? @@.:;9G@A.:;9? I@ B.:;9? @ C.:;9G@ D1E1F1XYWG1XYWH.1I.1@J.1@ K.1L.< 4 I? M.< 4 ? NIOPI:;9QI4 R S TUVW1X4I ,Y4I Z4I[4I,\4I]4I 4 ^4I ,4 _4I4 `4I,4 a4I4 b41 ,c41d41,e41f1g1hI iIjIkI 4 lI ,4 mI4 n1 o1p4I ? q4I? < r4I,s4It5Iu;v=w%x<%%.,armcc+|    (armcc+|  (armcc+|  (armcc+|  (armcc+|  (armcc+|   8 T0plA| \0B~0E~0F~ < X$0LA{CvZ {A 0`DA~0FA~0vA~0`*A~     0A~    A} p zL  $B~ $B~ ,>>A~|.A~  0 @ \0Az  $0AxCnI {A 0VA|   \ 0 A~08 @Az D `0 0Az * "  * H d0H *A| 0r 6A|ArX| 0 dAwBtn{ 0 BAwAn^{0N PAwBt 0 AxAvV{0P AwAn0AyAn0AxAn0AxAn 0b6A{CrV{$0.AwAhf {A $0AxC` {A $0RAwBu| {A $0hvAwAj {A 0AxB`$06AxBp {A 00AxBf{$0,AxA\{ 0AxCR{$0!4AxAD {A 0$Ax$0d%AwBvc {A 0%ZAwAnj{ 0N&pA|Anu|0&A{CR0'(A}AtQ}0'$A}At L h \' \' \( \( \ ( \.( 0<(&AyAt{0b)>Az$0)rA{Avt {A 0*AyAra{*PB~0*+$A~0N+Ax00-`Az 0-ZA|Crh|$0-AwBf {A 0.AxAn^{0/AyAr01A~01A~01$A| 01 01 0102A{Ar P l 0202A|0l3Az(04Axw {AA 05A~05ZB~ 8 05 06 0,6 006 46H6F>~ 0707 A~ 707 A~07A~074A|08 A~0X8A~K0(80AzC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] !x?signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_t8 Pint16_t9 Pint32_t: Pint64_t; Puint8_t> Puint16_t? Puint32_t@ Puint64_tA Pint_least8_tG Pint_least16_tH Pint_least32_tI Pint_least64_tJ Puint_least8_tM Puint_least16_tN Puint_least32_tO Puint_least64_tP Pint_fast8_tU Pint_fast16_tV Pint_fast32_tW Pint_fast64_tX Puint_fast8_t[ Puint_fast16_t\ Puint_fast32_t] Puint_fast64_t^ Pintptr_te Puintptr_tf Pintmax_tj!Puintmax_tk! .\devices\MIMXRT1021\MIMXRT1021.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashJ>IRQnNotAvail_IRQnNonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnDMA0_DMA16_IRQnDMA1_DMA17_IRQnDMA2_DMA18_IRQnDMA3_DMA19_IRQnDMA4_DMA20_IRQnDMA5_DMA21_IRQnDMA6_DMA22_IRQnDMA7_DMA23_IRQnDMA8_DMA24_IRQnDMA9_DMA25_IRQn DMA10_DMA26_IRQn DMA11_DMA27_IRQn DMA12_DMA28_IRQn DMA13_DMA29_IRQn DMA14_DMA30_IRQnDMA15_DMA31_IRQnDMA_ERROR_IRQnCTI0_ERROR_IRQnCTI1_ERROR_IRQnCORE_IRQnLPUART1_IRQnLPUART2_IRQnLPUART3_IRQnLPUART4_IRQnLPUART5_IRQnLPUART6_IRQnLPUART7_IRQnLPUART8_IRQnLPI2C1_IRQnLPI2C2_IRQnLPI2C3_IRQnLPI2C4_IRQnLPSPI1_IRQn LPSPI2_IRQn!LPSPI3_IRQn"LPSPI4_IRQn#CAN1_IRQn$CAN2_IRQn%FLEXRAM_IRQn&KPP_IRQn'Reserved56_IRQn(GPR_IRQ_IRQn)Reserved58_IRQn*Reserved59_IRQn+Reserved60_IRQn,WDOG2_IRQn-SNVS_HP_WRAPPER_IRQn.SNVS_HP_WRAPPER_TZ_IRQn/SNVS_LP_WRAPPER_IRQn0Reserved65_IRQn1DCP_IRQn2DCP_VMI_IRQn3Reserved68_IRQn4TRNG_IRQn5Reserved70_IRQn6Reserved71_IRQn7SAI1_IRQn8SAI2_IRQn9SAI3_RX_IRQn:SAI3_TX_IRQn;SPDIF_IRQn<PMU_IRQn=Reserved78_IRQn>TEMP_LOW_HIGH_IRQn?TEMP_PANIC_IRQnUSB_PHY1_IRQnReserved82_IRQnADC1_IRQnADC2_IRQnDCDC_IRQnReserved86_IRQnReserved87_IRQnGPIO1_INT0_IRQnGPIO1_INT1_IRQnGPIO1_INT2_IRQnGPIO1_INT3_IRQnGPIO1_INT4_IRQnGPIO1_INT5_IRQnGPIO1_INT6_IRQnGPIO1_INT7_IRQnGPIO1_Combined_0_15_IRQnGPIO1_Combined_16_31_IRQnGPIO2_Combined_0_15_IRQnGPIO2_Combined_16_31_IRQnGPIO3_Combined_0_15_IRQnGPIO3_Combined_16_31_IRQnReserved102_IRQnReserved103_IRQnGPIO5_Combined_0_15_IRQnGPIO5_Combined_16_31_IRQnFLEXIO1_IRQnReserved107_IRQnWDOG1_IRQnRTWDOG_IRQnEWM_IRQnCCM_1_IRQnCCM_2_IRQnGPC_IRQnSRC_IRQnReserved115_IRQnGPT1_IRQnGPT2_IRQnPWM1_0_IRQnPWM1_1_IRQnPWM1_2_IRQnPWM1_3_IRQnPWM1_FAULT_IRQnReserved123_IRQnFLEXSPI_IRQnSEMC_IRQnUSDHC1_IRQnUSDHC2_IRQnReserved128_IRQnUSB_OTG1_IRQnENET_IRQnENET_1588_Timer_IRQnXBAR1_IRQ_0_1_IRQnXBAR1_IRQ_2_3_IRQnADC_ETC_IRQ0_IRQnADC_ETC_IRQ1_IRQnADC_ETC_IRQ2_IRQnADC_ETC_ERROR_IRQ_IRQnPIT_IRQnACMP1_IRQnACMP2_IRQnACMP3_IRQnACMP4_IRQnReserved143_IRQnReserved144_IRQnENC1_IRQnENC2_IRQnReserved147_IRQnReserved148_IRQnTMR1_IRQnTMR2_IRQnReserved151_IRQnReserved152_IRQnPWM2_0_IRQnPWM2_1_IRQnPWM2_2_IRQnPWM2_3_IRQnPWM2_FAULT_IRQnPIRQn_Type,_dma_request_sourcekDmaRequestMuxFlexIO1Request0Request1kDmaRequestMuxFlexIO1Request4Request5kDmaRequestMuxLPUART1TxkDmaRequestMuxLPUART1RxkDmaRequestMuxLPUART3TxkDmaRequestMuxLPUART3RxkDmaRequestMuxLPUART5TxkDmaRequestMuxLPUART5RxkDmaRequestMuxLPUART7TxkDmaRequestMuxLPUART7Rx kDmaRequestMuxLPSPI1Rx kDmaRequestMuxLPSPI1TxkDmaRequestMuxLPSPI3RxkDmaRequestMuxLPSPI3TxkDmaRequestMuxLPI2C1kDmaRequestMuxLPI2C3kDmaRequestMuxSai1RxkDmaRequestMuxSai1TxkDmaRequestMuxSai2RxkDmaRequestMuxSai2TxkDmaRequestMuxADC_ETCkDmaRequestMuxADC1kDmaRequestMuxACMP1kDmaRequestMuxACMP2kDmaRequestMuxFlexSPIRxkDmaRequestMuxFlexSPITxkDmaRequestMuxXBAR1Request0kDmaRequestMuxXBAR1Request1kDmaRequestMuxFlexPWM1CaptureSub0 kDmaRequestMuxFlexPWM1CaptureSub1!kDmaRequestMuxFlexPWM1CaptureSub2"kDmaRequestMuxFlexPWM1CaptureSub3#kDmaRequestMuxFlexPWM1ValueSub0$kDmaRequestMuxFlexPWM1ValueSub1%kDmaRequestMuxFlexPWM1ValueSub2&kDmaRequestMuxFlexPWM1ValueSub3'kDmaRequestMuxQTIMER1CaptTimer00kDmaRequestMuxQTIMER1CaptTimer11kDmaRequestMuxQTIMER1CaptTimer22kDmaRequestMuxQTIMER1CaptTimer33kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer14kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer05kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer36kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer27kDmaRequestMuxFlexIO1Request2Request3@kDmaRequestMuxFlexIO1Request6Request7AkDmaRequestMuxLPUART2TxBkDmaRequestMuxLPUART2RxCkDmaRequestMuxLPUART4TxDkDmaRequestMuxLPUART4RxEkDmaRequestMuxLPUART6TxFkDmaRequestMuxLPUART6RxGkDmaRequestMuxLPUART8TxHkDmaRequestMuxLPUART8RxIkDmaRequestMuxLPSPI2RxMkDmaRequestMuxLPSPI2TxNkDmaRequestMuxLPSPI4RxOkDmaRequestMuxLPSPI4TxPkDmaRequestMuxLPI2C2QkDmaRequestMuxLPI2C4RkDmaRequestMuxSai3RxSkDmaRequestMuxSai3TxTkDmaRequestMuxSpdifRxUkDmaRequestMuxSpdifTxVkDmaRequestMuxADC2XkDmaRequestMuxACMP3YkDmaRequestMuxACMP4ZkDmaRequestMuxEnetTimer0\kDmaRequestMuxEnetTimer1]kDmaRequestMuxXBAR1Request2^kDmaRequestMuxXBAR1Request3_kDmaRequestMuxFlexPWM2CaptureSub0`kDmaRequestMuxFlexPWM2CaptureSub1akDmaRequestMuxFlexPWM2CaptureSub2bkDmaRequestMuxFlexPWM2CaptureSub3ckDmaRequestMuxFlexPWM2ValueSub0dkDmaRequestMuxFlexPWM2ValueSub1ekDmaRequestMuxFlexPWM2ValueSub2fkDmaRequestMuxFlexPWM2ValueSub3gkDmaRequestMuxQTIMER2CaptTimer0pkDmaRequestMuxQTIMER2CaptTimer1qkDmaRequestMuxQTIMER2CaptTimer2rkDmaRequestMuxQTIMER2CaptTimer3skDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1tkDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0ukDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3vkDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2wPdma_request_source_tG I_iomuxc_sw_mux_ctl_padkIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 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5kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 6kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 7kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 8kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 9kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 :kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 ;kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 <kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 =kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 >kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 ?kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 @kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 AkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 BkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 CkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 DkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 EkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 FkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 GkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 HkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 IkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 JkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 KkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 LkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 MkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 NkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 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kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 !kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 "kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 #kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 $kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 %kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 &kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 'kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 (kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 )kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 *kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 +kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 ,kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 -kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 .kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 /kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 0kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 1kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 2kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 3kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 4kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 5kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 6kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 7kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 8kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 9kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 :kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 ;kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 <kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 =kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 >kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 ?kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 @kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 AkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 BkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 CkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 DkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 EkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 FkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 GkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 HkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 IkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 JkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 KkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 LkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 MkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 NkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 OkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_06 PkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 QkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 RkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 SkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 TkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 UkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 VkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 WkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 XkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 YkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 ZkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 [kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 \Piomuxc_sw_pad_ctl_pad_t$_iomuxc_select_inputkIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT kIOMUXC_CCM_PMIC_READY_SELECT_INPUT kIOMUXC_ENET_RMII_SELECT_INPUT kIOMUXC_ENET_MDIO_SELECT_INPUT kIOMUXC_ENET_RX_DATA0_SELECT_INPUT kIOMUXC_ENET_RX_DATA1_SELECT_INPUT kIOMUXC_ENET_RX_EN_SELECT_INPUT kIOMUXC_ENET_RX_ERR_SELECT_INPUT kIOMUXC_ENET_TX_CLK_SELECT_INPUT kIOMUXC_FLEXCAN1_RX_SELECT_INPUT kIOMUXC_FLEXCAN2_RX_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT kIOMUXC_LPI2C1_SCL_SELECT_INPUT kIOMUXC_LPI2C1_SDA_SELECT_INPUT !kIOMUXC_LPI2C2_SCL_SELECT_INPUT "kIOMUXC_LPI2C2_SDA_SELECT_INPUT #kIOMUXC_LPI2C3_SCL_SELECT_INPUT $kIOMUXC_LPI2C3_SDA_SELECT_INPUT %kIOMUXC_LPI2C4_SCL_SELECT_INPUT &kIOMUXC_LPI2C4_SDA_SELECT_INPUT 'kIOMUXC_LPSPI1_PCS0_SELECT_INPUT (kIOMUXC_LPSPI1_SCK_SELECT_INPUT )kIOMUXC_LPSPI1_SDI_SELECT_INPUT *kIOMUXC_LPSPI1_SDO_SELECT_INPUT +kIOMUXC_LPSPI2_PCS0_SELECT_INPUT ,kIOMUXC_LPSPI2_SCK_SELECT_INPUT -kIOMUXC_LPSPI2_SDI_SELECT_INPUT .kIOMUXC_LPSPI2_SDO_SELECT_INPUT /kIOMUXC_LPSPI4_PCS0_SELECT_INPUT 0kIOMUXC_LPSPI4_SCK_SELECT_INPUT 1kIOMUXC_LPSPI4_SDI_SELECT_INPUT 2kIOMUXC_LPSPI4_SDO_SELECT_INPUT 3kIOMUXC_LPUART2_CTS_B_SELECT_INPUT 4kIOMUXC_LPUART2_RX_SELECT_INPUT 5kIOMUXC_LPUART2_TX_SELECT_INPUT 6kIOMUXC_LPUART3_RX_SELECT_INPUT 7kIOMUXC_LPUART3_TX_SELECT_INPUT 8kIOMUXC_LPUART4_CTS_B_SELECT_INPUT 9kIOMUXC_LPUART4_RX_SELECT_INPUT :kIOMUXC_LPUART4_TX_SELECT_INPUT ;kIOMUXC_LPUART5_RX_SELECT_INPUT <kIOMUXC_LPUART5_TX_SELECT_INPUT =kIOMUXC_LPUART6_RX_SELECT_INPUT >kIOMUXC_LPUART6_TX_SELECT_INPUT ?kIOMUXC_LPUART7_RX_SELECT_INPUT @kIOMUXC_LPUART7_TX_SELECT_INPUT AkIOMUXC_LPUART8_RX_SELECT_INPUT BkIOMUXC_LPUART8_TX_SELECT_INPUT CkIOMUXC_NMI_SELECT_INPUT DkIOMUXC_QTIMER1_TIMER0_INPUT_SELECT_INPUT EkIOMUXC_QTIMER1_TIMER1_INPUT_SELECT_INPUT FkIOMUXC_QTIMER1_TIMER2_INPUT_SELECT_INPUT GkIOMUXC_QTIMER1_TIMER3_INPUT_SELECT_INPUT HkIOMUXC_QTIMER2_TIMER0_INPUT_SELECT_INPUT IkIOMUXC_QTIMER2_TIMER1_INPUT_SELECT_INPUT JkIOMUXC_QTIMER2_TIMER2_INPUT_SELECT_INPUT KkIOMUXC_QTIMER2_TIMER3_INPUT_SELECT_INPUT LkIOMUXC_SAI1_MCLK_SELECT_INPUT MkIOMUXC_SAI1_RX_BCLK_SELECT_INPUT NkIOMUXC_SAI1_RX_DATA0_SELECT_INPUT OkIOMUXC_SAI1_RX_DATA1_SELECT_INPUT PkIOMUXC_SAI1_RX_DATA2_SELECT_INPUT QkIOMUXC_SAI1_RX_DATA3_SELECT_INPUT RkIOMUXC_SAI1_RX_SYNC_SELECT_INPUT SkIOMUXC_SAI1_TX_BCLK_SELECT_INPUT TkIOMUXC_SAI1_TX_SYNC_SELECT_INPUT UkIOMUXC_SAI2_MCLK_SELECT_INPUT VkIOMUXC_SAI2_RX_BCLK_SELECT_INPUT WkIOMUXC_SAI2_RX_DATA0_SELECT_INPUT XkIOMUXC_SAI2_RX_SYNC_SELECT_INPUT YkIOMUXC_SAI2_TX_BCLK_SELECT_INPUT ZkIOMUXC_SAI2_TX_SYNC_SELECT_INPUT [kIOMUXC_SAI3_MCLK_SELECT_INPUT \kIOMUXC_SAI3_RX_BCLK_SELECT_INPUT ]kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT ^kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT _kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT `kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT akIOMUXC_SEMC_READY_SELECT_INPUT bkIOMUXC_SPDIF_IN_SELECT_INPUT ckIOMUXC_USB_OTG_OC_SELECT_INPUT dkIOMUXC_USDHC1_CD_B_SELECT_INPUT ekIOMUXC_USDHC1_WP_SELECT_INPUT fkIOMUXC_USDHC2_CD_B_SELECT_INPUT gkIOMUXC_USDHC2_WP_SELECT_INPUT hkIOMUXC_XBAR1_IN14_SELECT_INPUT ikIOMUXC_XBAR1_IN15_SELECT_INPUT jkIOMUXC_XBAR1_IN16_SELECT_INPUT kkIOMUXC_XBAR1_IN17_SELECT_INPUT lkIOMUXC_XBAR1_IN10_SELECT_INPUT mkIOMUXC_XBAR1_IN12_SELECT_INPUT nkIOMUXC_XBAR1_IN13_SELECT_INPUT okIOMUXC_XBAR1_IN18_SELECT_INPUT pkIOMUXC_XBAR1_IN19_SELECT_INPUT qPiomuxc_select_input_te3_xbar_input_signalkXBARA_InputLogicLowkXBARA_InputLogicHighkXBARA_InputRESERVED2kXBARA_InputRESERVED3kXBARA_InputIomuxXbarInout04kXBARA_InputIomuxXbarInout05kXBARA_InputIomuxXbarInout06kXBARA_InputIomuxXbarInout07kXBARA_InputIomuxXbarInout08kXBARA_InputIomuxXbarInout09 kXBARA_InputIomuxXbarInout10 kXBARA_InputIomuxXbarInout11 kXBARA_InputIomuxXbarInout12 kXBARA_InputIomuxXbarInout13 kXBARA_InputIomuxXbarInout14kXBARA_InputIomuxXbarInout15kXBARA_InputIomuxXbarInout16kXBARA_InputIomuxXbarInout17kXBARA_InputIomuxXbarInout18kXBARA_InputIomuxXbarInout19kXBARA_InputRESERVED20kXBARA_InputRESERVED21kXBARA_InputRESERVED22kXBARA_InputRESERVED23kXBARA_InputRESERVED24kXBARA_InputRESERVED25kXBARA_InputAcmp1OutkXBARA_InputAcmp2OutkXBARA_InputAcmp3OutkXBARA_InputAcmp4OutkXBARA_InputRESERVED30kXBARA_InputRESERVED31kXBARA_InputQtimer1Tmr0 kXBARA_InputQtimer1Tmr1!kXBARA_InputQtimer1Tmr2"kXBARA_InputQtimer1Tmr3#kXBARA_InputQtimer2Tmr0$kXBARA_InputQtimer2Tmr1%kXBARA_InputQtimer2Tmr2&kXBARA_InputQtimer2Tmr3'kXBARA_InputFlexpwm1Pwm1OutTrig01(kXBARA_InputFlexpwm1Pwm2OutTrig01)kXBARA_InputFlexpwm1Pwm3OutTrig01*kXBARA_InputFlexpwm1Pwm4OutTrig01+kXBARA_InputFlexpwm2Pwm1OutTrig01,kXBARA_InputFlexpwm2Pwm2OutTrig01-kXBARA_InputFlexpwm2Pwm3OutTrig01.kXBARA_InputFlexpwm2Pwm4OutTrig01/kXBARA_InputRESERVED480kXBARA_InputRESERVED491kXBARA_InputRESERVED502kXBARA_InputRESERVED513kXBARA_InputRESERVED524kXBARA_InputRESERVED535kXBARA_InputRESERVED546kXBARA_InputRESERVED557kXBARA_InputPitTrigger08kXBARA_InputPitTrigger19kXBARA_InputPitTrigger2:kXBARA_InputPitTrigger3;kXBARA_InputEnc1PosMatch<kXBARA_InputEnc2PosMatch=kXBARA_InputRESERVED62>kXBARA_InputRESERVED63?kXBARA_InputDmaDone0@kXBARA_InputDmaDone1AkXBARA_InputDmaDone2BkXBARA_InputDmaDone3CkXBARA_InputDmaDone4DkXBARA_InputDmaDone5EkXBARA_InputDmaDone6FkXBARA_InputDmaDone7GkXBARA_InputAoi1Out0HkXBARA_InputAoi1Out1IkXBARA_InputAoi1Out2JkXBARA_InputAoi1Out3KkXBARA_InputRESERVED76LkXBARA_InputRESERVED77MkXBARA_InputRESERVED78NkXBARA_InputRESERVED79OkXBARA_InputAdcEtc0Coco0PkXBARA_InputAdcEtc0Coco1QkXBARA_InputAdcEtc0Coco2RkXBARA_InputAdcEtc0Coco3SkXBARA_InputAdcEtc1Coco0TkXBARA_InputAdcEtc1Coco1UkXBARA_InputAdcEtc1Coco2VkXBARA_InputAdcEtc1Coco3WkXBARB_InputLogicLowkXBARB_InputLogicHighkXBARB_InputRESERVED2kXBARB_InputRESERVED3kXBARB_InputRESERVED4kXBARB_InputRESERVED5kXBARB_InputAcmp1OutkXBARB_InputAcmp2OutkXBARB_InputAcmp3OutkXBARB_InputAcmp4Out kXBARB_InputRESERVED10 kXBARB_InputRESERVED11 kXBARB_InputQtimer1Tmr0 kXBARB_InputQtimer1Tmr1 kXBARB_InputQtimer1Tmr2kXBARB_InputQtimer1Tmr3kXBARB_InputQtimer2Tmr0kXBARB_InputQtimer2Tmr1kXBARB_InputQtimer2Tmr2kXBARB_InputQtimer2Tmr3kXBARB_InputFlexpwm1Pwm1OutTrig01kXBARB_InputFlexpwm1Pwm2OutTrig01kXBARB_InputFlexpwm1Pwm3OutTrig01kXBARB_InputFlexpwm1Pwm4OutTrig01kXBARB_InputFlexpwm2Pwm1OutTrig01kXBARB_InputFlexpwm2Pwm2OutTrig01kXBARB_InputFlexpwm2Pwm3OutTrig01kXBARB_InputFlexpwm2Pwm4OutTrig01kXBARB_InputRESERVED28kXBARB_InputRESERVED29kXBARB_InputRESERVED30kXBARB_InputRESERVED31kXBARB_InputRESERVED32 kXBARB_InputRESERVED33!kXBARB_InputRESERVED34"kXBARB_InputRESERVED35#kXBARB_InputPitTrigger0$kXBARB_InputPitTrigger1%kXBARB_InputAdcEtc0Coco0&kXBARB_InputAdcEtc0Coco1'kXBARB_InputAdcEtc0Coco2(kXBARB_InputAdcEtc0Coco3)kXBARB_InputAdcEtc1Coco0*kXBARB_InputAdcEtc1Coco1+kXBARB_InputAdcEtc1Coco2,kXBARB_InputAdcEtc1Coco3-kXBARB_InputEnc1PosMatch.kXBARB_InputEnc2PosMatch/kXBARB_InputRESERVED480kXBARB_InputRESERVED491kXBARB_InputDmaDone02kXBARB_InputDmaDone13kXBARB_InputDmaDone24kXBARB_InputDmaDone35kXBARB_InputDmaDone46kXBARB_InputDmaDone57kXBARB_InputDmaDone68kXBARB_InputDmaDone79Pxbar_input_signal_tD_xbar_output_signalkXBARA_OutputDmaChMuxReq30kXBARA_OutputDmaChMuxReq31kXBARA_OutputDmaChMuxReq94kXBARA_OutputDmaChMuxReq95kXBARA_OutputIomuxXbarInout04kXBARA_OutputIomuxXbarInout05kXBARA_OutputIomuxXbarInout06kXBARA_OutputIomuxXbarInout07kXBARA_OutputIomuxXbarInout08kXBARA_OutputIomuxXbarInout09 kXBARA_OutputIomuxXbarInout10 kXBARA_OutputIomuxXbarInout11 kXBARA_OutputIomuxXbarInout12 kXBARA_OutputIomuxXbarInout13 kXBARA_OutputIomuxXbarInout14kXBARA_OutputIomuxXbarInout15kXBARA_OutputIomuxXbarInout16kXBARA_OutputIomuxXbarInout17kXBARA_OutputIomuxXbarInout18kXBARA_OutputIomuxXbarInout19kXBARA_OutputAcmp1SamplekXBARA_OutputAcmp2SamplekXBARA_OutputAcmp3SamplekXBARA_OutputAcmp4SamplekXBARA_OutputRESERVED24kXBARA_OutputRESERVED25kXBARA_OutputFlexpwm1Exta0kXBARA_OutputFlexpwm1Exta1kXBARA_OutputFlexpwm1Exta2kXBARA_OutputFlexpwm1Exta3kXBARA_OutputFlexpwm1ExtSync0kXBARA_OutputFlexpwm1ExtSync1kXBARA_OutputFlexpwm1ExtSync2 kXBARA_OutputFlexpwm1ExtSync3!kXBARA_OutputFlexpwm1ExtClk"kXBARA_OutputFlexpwm1Fault0#kXBARA_OutputFlexpwm1Fault1$kXBARA_OutputFlexpwm1Fault2%flexpwm2Fault2%kXBARA_OutputFlexpwm1Fault3&flexpwm2Fault3&kXBARA_OutputFlexpwm1ExtForce'kXBARA_OutputFlexpwm2Exta0(kXBARA_OutputFlexpwm2Exta1)kXBARA_OutputFlexpwm2Exta2*kXBARA_OutputFlexpwm2Exta3+kXBARA_OutputFlexpwm2ExtSync0,kXBARA_OutputFlexpwm2ExtSync1-kXBARA_OutputFlexpwm2ExtSync2.kXBARA_OutputFlexpwm2ExtSync3/kXBARA_OutputFlexpwm2ExtClk0kXBARA_OutputFlexpwm2Fault01kXBARA_OutputFlexpwm2Fault12kXBARA_OutputFlexpwm2ExtForce3kXBARA_OutputRESERVED524kXBARA_OutputRESERVED535kXBARA_OutputRESERVED546kXBARA_OutputRESERVED557kXBARA_OutputRESERVED568kXBARA_OutputRESERVED579kXBARA_OutputRESERVED58:kXBARA_OutputRESERVED59;kXBARA_OutputRESERVED60<kXBARA_OutputRESERVED61=kXBARA_OutputRESERVED62>kXBARA_OutputRESERVED63?kXBARA_OutputRESERVED64@kXBARA_OutputRESERVED65AkXBARA_OutputEnc1PhaseAInputBkXBARA_OutputEnc1PhaseBInputCkXBARA_OutputEnc1IndexDkXBARA_OutputEnc1HomeEkXBARA_OutputEnc1TriggerFkXBARA_OutputEnc2PhaseAInputGkXBARA_OutputEnc2PhaseBInputHkXBARA_OutputEnc2IndexIkXBARA_OutputEnc2HomeJkXBARA_OutputEnc2TriggerKkXBARA_OutputRESERVED76LkXBARA_OutputRESERVED77MkXBARA_OutputRESERVED78NkXBARA_OutputRESERVED79OkXBARA_OutputRESERVED80PkXBARA_OutputRESERVED81QkXBARA_OutputRESERVED82RkXBARA_OutputRESERVED83SkXBARA_OutputRESERVED84TkXBARA_OutputRESERVED85UkXBARA_OutputQtimer1Tmr0VkXBARA_OutputQtimer1Tmr1WkXBARA_OutputQtimer1Tmr2XkXBARA_OutputQtimer1Tmr3YkXBARA_OutputQtimer2Tmr0ZkXBARA_OutputQtimer2Tmr1[kXBARA_OutputQtimer2Tmr2\kXBARA_OutputQtimer2Tmr3]kXBARA_OutputRESERVED94^kXBARA_OutputRESERVED95_kXBARA_OutputRESERVED96`kXBARA_OutputRESERVED97akXBARA_OutputRESERVED98bkXBARA_OutputRESERVED99ckXBARA_OutputRESERVED100dkXBARA_OutputRESERVED101ekXBARA_OutputEwmEwmInfkXBARA_OutputAdcEtcTrig00gkXBARA_OutputAdcEtcTrig01hkXBARA_OutputAdcEtcTrig02ikXBARA_OutputAdcEtcTrig03jkXBARA_OutputAdcEtcTrig10kkXBARA_OutputAdcEtcTrig11lkXBARA_OutputAdcEtcTrig12mkXBARA_OutputAdcEtcTrig13nkXBARA_OutputLpi2c1TrgInputokXBARA_OutputLpi2c2TrgInputpkXBARA_OutputLpi2c3TrgInputqkXBARA_OutputLpi2c4TrgInputrkXBARA_OutputLpspi1TrgInputskXBARA_OutputLpspi2TrgInputtkXBARA_OutputLpspi3TrgInputukXBARA_OutputLpspi4TrgInputvkXBARA_OutputLpuart1TrgInputwkXBARA_OutputLpuart2TrgInputxkXBARA_OutputLpuart3TrgInputykXBARA_OutputLpuart4TrgInputzkXBARA_OutputLpuart5TrgInput{kXBARA_OutputLpuart6TrgInput|kXBARA_OutputLpuart7TrgInput}kXBARA_OutputLpuart8TrgInput~kXBARA_OutputFlexio1TriggerIn0kXBARA_OutputFlexio1TriggerIn1kXBARA_OutputRESERVED129kXBARA_OutputRESERVED130kXBARA_OutputRESERVED131kXBARB_OutputAoi1In00kXBARB_OutputAoi1In01kXBARB_OutputAoi1In02kXBARB_OutputAoi1In03kXBARB_OutputAoi1In04kXBARB_OutputAoi1In05kXBARB_OutputAoi1In06kXBARB_OutputAoi1In07kXBARB_OutputAoi1In08kXBARB_OutputAoi1In09 kXBARB_OutputAoi1In10 kXBARB_OutputAoi1In11 kXBARB_OutputAoi1In12 kXBARB_OutputAoi1In13 kXBARB_OutputAoi1In14kXBARB_OutputAoi1In15Pxbar_output_signal_tT*\gHCf#HSg# gRf#$CFGg#DGCg#HGSg#LCVg#POFSg#TCALg#XtYYt gPADC_Typef*(TRIGn_CTRLg#TRIGn_COUNTERg#TRIGn_CHAIN_1_0g#TRIGn_CHAIN_3_2g# TRIGn_CHAIN_5_4g#TRIGn_CHAIN_7_6g#TRIGn_RESULT_1_0g#TRIGn_RESULT_3_2g#TRIGn_RESULT_5_4g# TRIGn_RESULT_7_6g#$*CTRLg#DONE0_1_IRQg#DONE2_ERR_IRQg#DMA_CTRLg# $gTRIGWh#PADC_ETC_Type h *TMPRg#:;RESERVED_0h#OPACRg#@OPACR1g#DOPACR2g#HOPACR3g#LOPACR4g#PPAIPSTZ_Typeh *BFCRT01/i#BFCRT23/i#tI* iBFCRT:i#PAOI_Type5i*CSg#IDg#WORD0g#WORD1g# *MCRg#CTRL1g#TIMERg#:RESERVED_0i# RXMGMASKg#RX14MASKg#RX15MASKg#ECRg#ESR1g# IMASK2g#$IMASK1g#(IFLAG2g#,IFLAG1g#0CTRL2g#4ESR2g#8:RESERVED_1xj#<CRCRg#DRXFGMASKg#HRXFIRg#L:/RESERVED_2j#Pci?MBj#:RESERVED_3j# g?RXIMRk#:_RESERVED_4*k#GFWRg#PCAN_Typei*CCRg#:RESERVED_0yk#CSRg#CCSRg# CACRRg#CBCDRg#CBCMRg#CSCMR1g#CSCMR2g# CSCDR1g#$CS1CDRg#(CS2CDRg#,CDCDRg#0:RESERVED_1(l#4CSCDR2g#8CSCDR3Y#<:RESERVED_2dl#@CDHIPRg#H:RESERVED_3l#LCLPCRg#TCISRg#XCIMRg#\CCOSRg#`CGPRg#dCCGR0g#hCCGR1g#lCCGR2g#pCCGR3g#tCCGR4g#xCCGR5g#|CCGR6g#:RESERVED_4Hm#CMEORg#PCCM_Typehk*:RESERVED_0m#PLL_USB1g#PLL_USB1_SETg#PLL_USB1_CLRg#PLL_USB1_TOGg#:RESERVED_1m# PLL_SYSg#0PLL_SYS_SETg#4PLL_SYS_CLRg#8PLL_SYS_TOGg#<PLL_SYS_SSg#@: RESERVED_2on#DPLL_SYS_NUMg#P: RESERVED_3n#TPLL_SYS_DENOMg#`: RESERVED_4n#dPLL_AUDIOg#pPLL_AUDIO_SETg#tPLL_AUDIO_CLRg#xPLL_AUDIO_TOGg#|PLL_AUDIO_NUMg#: RESERVED_5Wo#PLL_AUDIO_DENOMg#:KRESERVED_6o#PLL_ENETg#PLL_ENET_SETg#PLL_ENET_CLRg#PLL_ENET_TOGg#PFD_480g#PFD_480_SETg#PFD_480_CLRg#PFD_480_TOGg#PFD_528g#PFD_528_SETg#PFD_528_CLRg#PFD_528_TOGg#:?RESERVED_7p#MISC0g#MISC0_SETg#MISC0_CLRg#MISC0_TOGg#MISC1g#MISC1_SETg#MISC1_CLRg#MISC1_TOGg#MISC2g#MISC2_SETg#MISC2_CLRg#MISC2_TOGg#PCCM_ANALOG_Typem*CR0q#CR1q#FPRq#SCRq#DACCRq#MUXCRq#t:PCMP_Typeq%*REG0g#REG1g#REG2g#REG3g# PDCDC_Typeq'*CTRLg#: RESERVED_0Vr#STATg#: RESERVED_1r#CHANNELCTRLg# : RESERVED_2r#$CAPABILITY0g#0: RESERVED_3r#4CAPABILITY1g#@: RESERVED_4s#DCONTEXTg#P: RESERVED_5@s#TKEYg#`: RESERVED_6is#dKEYDATAg#p: RESERVED_7s#tPACKET0g#: RESERVED_8s#PACKET1g#: RESERVED_9s#PACKET2g#: RESERVED_10"t#PACKET3g#: RESERVED_11Rt#PACKET4g#: RESERVED_12t#PACKET5g#: RESERVED_13t#PACKET6g#:RESERVED_14t#CH0CMDPTRg#: RESERVED_15u#CH0SEMAg#: RESERVED_16Du#CH0STATg#: RESERVED_17tu#CH0OPTSg#: RESERVED_18u#CH1CMDPTRg#: RESERVED_19u#CH1SEMAg#: RESERVED_20v#CH1STATg#: RESERVED_216v#CH1OPTSg#: RESERVED_22fv#CH2CMDPTRg#: RESERVED_23v#CH2SEMAg#: RESERVED_24v#CH2STATg#: RESERVED_25v#CH2OPTSg#: RESERVED_26(w#CH3CMDPTRg#: RESERVED_27Zw#CH3SEMAg#: RESERVED_28w#CH3STATg#: RESERVED_29w#CH3OPTSg#:RESERVED_30w#DBGSELECTg#: RESERVED_31x#DBGDATAg#: RESERVED_32Mx#PAGETABLEg#: RESERVED_33x#VERSIONg#PDCP_TypeDr)SNBYTES_MLNOgNBYTES_MLOFFNOgNBYTES_MLOFFYESgSCITER_ELINKNO/iCITER_ELINKYES/iSBITER_ELINKNO/iBITER_ELINKYES/i* SADDRg#SOFF/i#ATTR/i#x#SLASTg# DADDRg#DOFF/i#x#DLAST_SGAg#CSR/i#)y#*(CRg#ESg#:RESERVED_0y#ERQg# :RESERVED_1z#EEIg#CEEIq#SEEIq#CERQq#SERQq#CDNEq#SSRTq#CERRq#CINTq#:RESERVED_2z# INTg#$:RESERVED_3z#(ERRg#,:RESERVED_4z#0HRSg#4: RESERVED_5 {#8EARSg#D:RESERVED_6J{#HDCHPRI3q#DCHPRI2q#DCHPRI1q#DCHPRI0q#DCHPRI7q#DCHPRI6q#DCHPRI5q#DCHPRI4q#DCHPRI11q#DCHPRI10q#DCHPRI9q#DCHPRI8q#DCHPRI15q#DCHPRI14q#DCHPRI13q#DCHPRI12q#DCHPRI19q#DCHPRI18q#DCHPRI17q#DCHPRI16q#DCHPRI23q#DCHPRI22q#DCHPRI21q#DCHPRI20q#DCHPRI27q#DCHPRI26q#DCHPRI25q#DCHPRI24q#DCHPRI31q#DCHPRI30q#DCHPRI29q#DCHPRI28q#:RESERVED_7}#qDCHMID}#:RESERVED_8}#TyTCD}# PDMA_Typey.*gCHCFG~#PDMAMUX_Type}:*(CTRL/i#FILT/i#WTR/i#POSD/i#POSDH1#REV/i# REVH1# UPOS/i#LPOS/i#UPOSH1#LPOSH1#UINIT/i#LINIT/i#IMR1#TST/i#CTRL2/i#UMOD/i# LMOD/i#"UCOMP/i#$LCOMP/i#&It+PENC_Type1~;*TCSRg#TCCRg#* :RESERVED_0j#EIRg#EIMRg#:RESERVED_1# RDARg#TDARg#: RESERVED_2#ECRg#$:RESERVED_3#(MMFRg#@MSCRg#D:RESERVED_44#HMIBCg#d:RESERVED_5^#hRCRg#:;RESERVED_6#TCRg#:RESERVED_7#PALRg#PAURg#OPDg#TXICg#: RESERVED_8#RXICg#:RESERVED_91#IAURg#IALRg#GAURg#GALRg#:RESERVED_10#TFWRg#:7RESERVED_11#RDSRg#TDSRg#MRBRg#:RESERVED_12#RSFLg#RSEMg#RAEMg#RAFLg#TSEMg#TAEMg#TAFLg#TIPGg#FTRLg#: RESERVED_13#TACCg#RACCg#Ӆ:7RESERVED_14ǂ#RMON_T_DROPY#RMON_T_PACKETSg#RMON_T_BC_PKTg#RMON_T_MC_PKTg#RMON_T_CRC_ALIGNg#RMON_T_UNDERSIZEg#RMON_T_OVERSIZEg#RMON_T_FRAGg#RMON_T_JABg#RMON_T_COLg#RMON_T_P64g#RMON_T_P65TO127g#RMON_T_P128TO255g#RMON_T_P256TO511g#RMON_T_P512TO1023g#RMON_T_P1024TO2047g#RMON_T_P_GTE2048g#RMON_T_OCTETSg#IEEE_T_DROPY#IEEE_T_FRAME_OKg#IEEE_T_1COLg#IEEE_T_MCOLg#IEEE_T_DEFg#IEEE_T_LCOLg#IEEE_T_EXCOLg#IEEE_T_MACERRg#IEEE_T_CSERRg#IEEE_T_SQEg#IEEE_T_FDXFCg#IEEE_T_OCTETS_OKg#: RESERVED_15#RMON_R_PACKETSg#RMON_R_BC_PKTg#RMON_R_MC_PKTg#RMON_R_CRC_ALIGNg#RMON_R_UNDERSIZEg#RMON_R_OVERSIZEg#RMON_R_FRAGg#RMON_R_JABg#RMON_R_RESVD_0Y#RMON_R_P64g#RMON_R_P65TO127g#RMON_R_P128TO255g#RMON_R_P256TO511g#RMON_R_P512TO1023g#RMON_R_P1024TO2047g#RMON_R_P_GTE2048g#RMON_R_OCTETSg#IEEE_R_DROPg#IEEE_R_FRAME_OKg#IEEE_R_CRCg#IEEE_R_ALIGNg#IEEE_R_MACERRg#IEEE_R_FDXFCg#IEEE_R_OCTETS_OKg#֏:RESERVED_16ɇ#ATCRg#ATVRg#ATOFFg#ATPERg#ATCORg#ATINCg#ATSTMPg#ؐ:RESERVED_17K#TGSRg# FCHANNELy# PENET_Typed>*CTRLq#SERVq#CMPLq#CMPHq#CLKCTRLq#CLKPRESCALERq#PEWM_TypeF*VERIDg#PARAMg#CTRLg#PINg# SHIFTSTATg#SHIFTERRg#TIMSTATg#:RESERVED_0w#SHIFTSIENg# SHIFTEIENg#$TIMIENg#(ѓ:RESERVED_1ʼn#,SHIFTSDENg#0: RESERVED_2#4SHIFTSTATEg#@:;RESERVED_3$#D̔gSHIFTCTLB#:oRESERVED_4]#gSHIFTCFG|#:RESERVED_5#gSHIFTBUF#ޕ:oRESERVED_6Ҋ#gSHIFTBUFBIS#:oRESERVED_7#gSHIFTBUFBYS.#ؖ:oRESERVED_8L#gSHIFTBUFBBSk#:oRESERVED_9#gTIMCTL#͗:oRESERVED_10#gTIMCFG# :oRESERVED_11# gTIMCMP# :RESERVED_123# ޘgSHIFTBUFNBST# :oRESERVED_13r# gSHIFTBUFHWS#:oRESERVED_14#ڙgSHIFTBUFNISЌ#PFLEXIO_TypeG*TCM_CTRLg#OCRAM_MAGIC_ADDRg#DTCM_MAGIC_ADDRg#ITCM_MAGIC_ADDRg# INT_STATUSg#INT_STAT_ENg#INT_SIG_ENg#PFLEXRAM_TypeJ*MCR0g#MCR1g#MCR2g#AHBCRg# INTENg#INTRg#LUTKEYg#LUTCRg#gAHBRXBUFCR0# :/RESERVED_03#0ۜgFLSHCR0Q#`gFLSHCR1j#pgFLSHCR2#:RESERVED_1#FLSHCR4g#؝:RESERVED_2̎#IPCR0g#IPCR1g#:RESERVED_3#IPCMDg#:RESERVED_44#IPRXFCRg#IPTXFCRg#gDLLCRs#:RESERVED_5#STS0g#STS1g#STS2g#AHBSPNDSTSg#IPRXFSTSg#IPTXFSTSg#:RESERVED_6#gRFDR%#ƠgTFDR<#ݠg?LUTS#PFLEXSPI_TypeK*<CNTRg#:RESERVED_0#gIMR#͡gISRÐ#: RESERVED_1ؐ#(IMR5g#4ISR5g#8PGPC_TypeP*֣DRg#GDIRg#PSRg#ICR1g# ICR2g#IMRg#ISRg#EDGE_SELg#:cRESERVED_0# DR_SETg#DR_CLEARg#DR_TOGGLEg#PGPIO_Type Q*ˤ(CRg#PRg#SRg#IRg# gOCR#gICR*#CNTg#$PGPT_TypeR*VERIDg#PARAMg#TCSRg#TCR1g# TCR2g#TCR3g#TCR4g#TCR5g#ΥgTDRĒ# :RESERVED_0ْ#0gTFR#@:RESERVED_1 #PTMRg#`:#RESERVED_25#dRCSRg#RCR1g#RCR2g#RCR3g#RCR4g#RCR5g#gRDR#ç:RESERVED_3#gRFR֓#:RESERVED_4#RMRg#PI2S_Type\T* :RESERVED_0/#רg\SW_MUX_CTL_PADM#g\SW_PAD_CTL_PADm#gqSELECT_INPUT#PIOMUXC_Type)X*hGPR0Y#GPR1g#GPR2g#GPR3g# GPR4g#GPR5g#GPR6g#GPR7g#GPR8g# GPR9Y#$GPR10g#(GPR11g#,GPR12g#0GPR13g#4GPR14g#8GPR15Y#<GPR16g#@GPR17g#DGPR18g#HGPR19g#LGPR20g#PGPR21g#TGPR22g#XGPR23g#\GPR24g#`GPR25g#dPIOMUXC_GPR_Type”Y*Ү$SW_MUX_CTL_PAD_WAKEUPg#SW_MUX_CTL_PAD_PMIC_ON_REQg#SW_MUX_CTL_PAD_PMIC_STBY_REQg#SW_PAD_CTL_PAD_TEST_MODEg# SW_PAD_CTL_PAD_POR_Bg#SW_PAD_CTL_PAD_ONOFFg#SW_PAD_CTL_PAD_WAKEUPg#SW_PAD_CTL_PAD_PMIC_ON_REQg#SW_PAD_CTL_PAD_PMIC_STBY_REQg# PIOMUXC_SNVS_Type._*GPR0Y#GPR1Y#GPR2Y#GPR3g# PIOMUXC_SNVS_GPR_Typeka*KPCR/i#KPSR/i#KDDR/i#KPDR/i#PKPP_Typeėa*VERIDg#PARAMg#:RESERVED_0+#MCRg#MSRg#MIERg#MDERg#MCFGR0g# MCFGR1g#$MCFGR2g#(MCFGR3g#,:RESERVED_1#0MDMRg#@:RESERVED_2٘#DMCCR0g#H:RESERVED_3#LMCCR1g#P:RESERVED_4/#TMFCRg#XMFSRg#\MTDRg#`: RESERVED_5q#dMRDRg#p:RESERVED_6#tSCRg#SSRg#SIERg#SDERg#:RESERVED_7#SCFGR1g#SCFGR2g#:RESERVED_8)#SAMRg#: RESERVED_9U#SASRg#STARg#:RESERVED_10#STDRg#ǵ: RESERVED_11#SRDRg#PLPI2C_Type b*۸xVERIDg#PARAMg#:RESERVED_0#CRg#SRg#IERg#DERg#CFGR0g# CFGR1g#$:RESERVED_1}#(DMR0g#0DMR1g#4:RESERVED_2#8CCRg#@:RESERVED_3ܛ#DFCRg#XFSRg#\TCRg#`TDRg#d:RESERVED_4&#hRSRg#pRDRg#tPLPSPI_Typeg*0VERIDg#PARAMg#GLOBALg#PINCFGg# BAUDg#STATg#CTRLg#DATAg#MATCHg# MODIRg#$FIFOg#(WATERg#,PLPUART_Typeni* CTRLg#CTRL_SETg#CTRL_CLRg#CTRL_TOGg# TIMINGg#: RESERVED_0q#DATAg# : RESERVED_1#$READ_CTRLg#0ֻ: RESERVED_2ʝ#4READ_FUSE_DATAg#@: RESERVED_3#DSW_STICKYg#P: RESERVED_4-#TSCSg#`SCS_SETg#dSCS_CLRg#hSCS_TOGg#l:RESERVED_5#pVERSIONg#:kRESERVED_6#TIMING2g#:RESERVED_7#LOCKg#: RESERVED_8 #CFG0g#ž: RESERVED_99#CFG1g#: RESERVED_10e#CFG2g#: RESERVED_11#CFG3g#˿: RESERVED_12#CFG4g#: RESERVED_13#CFG5g#: RESERVED_14#CFG6g#: RESERVED_15F#MEM0g# : RESERVED_16s# MEM1g# : RESERVED_17# MEM2g# : RESERVED_18͠# MEM3g# : RESERVED_19# MEM4g# : RESERVED_20'# ANA0g# : RESERVED_21T# ANA1g# : RESERVED_22# ANA2g# :RESERVED_23# SRK0g# : RESERVED_24ܡ# SRK1g# : RESERVED_25 # SRK2g# : RESERVED_266# SRK3g# : RESERVED_27c# SRK4g# : RESERVED_28# SRK5g# : RESERVED_29# SRK6g# : RESERVED_30# SRK7g# : RESERVED_31# SJC_RESP0g# : RESERVED_32I# SJC_RESP1g# : RESERVED_33{# MAC0g# : RESERVED_34# MAC1g# : RESERVED_35գ# GP3g# :RESERVED_36# GP1g# : RESERVED_37-# GP2g# : RESERVED_38Y# SW_GP1g# : RESERVED_39# SW_GP20g# : RESERVED_40# SW_GP21g# : RESERVED_41# SW_GP22g# : RESERVED_42# SW_GP23g# : RESERVED_43H# MISC_CONF0g# : RESERVED_44{# MISC_CONF1g# : RESERVED_45# SRK_REVOKEg# POCOTP_Type!n*:RESERVED_0#MEGA_CTRLg#MEGA_PUPSCRg#MEGA_PDNSCRg#MEGA_SRg#:oRESERVED_1d#CPU_CTRLg#CPU_PUPSCRg#CPU_PDNSCRg#CPU_SRg#PPGC_Typer*LDVALg#CVALg#TCTRLg#TFLGg# *MCRg#:RESERVED_0$#LTMR64Hg#LTMR64Lg#:RESERVED_1c#ۦCHANNEL#PPIT_Types*:RESERVED_0#REG_1P1g#REG_1P1_SETg#REG_1P1_CLRg#REG_1P1_TOGg#REG_3P0g#REG_3P0_SETg#REG_3P0_CLRg#REG_3P0_TOGg#REG_2P5g#REG_2P5_SETg#REG_2P5_CLRg#REG_2P5_TOGg#REG_COREg#REG_CORE_SETg#REG_CORE_CLRg#REG_CORE_TOGg#MISC0g#MISC0_SETg#MISC0_CLRg#MISC0_TOGg#MISC1g#MISC1_SETg#MISC1_CLRg#MISC1_TOGg#MISC2g#MISC2_SETg#MISC2_CLRg#MISC2_TOGg#PPMU_Typet*`CNT1#INIT/i#CTRL2/i#CTRL/i#:RESERVED_0#VAL0/i# FRACVAL1/i# VAL1/i#FRACVAL2/i#VAL2/i#FRACVAL3/i#VAL3/i#FRACVAL4/i#VAL4/i#FRACVAL5/i#VAL5/i#FRCTRL/i# OCTRL/i#"STS/i#$INTEN/i#&DMAEN/i#(TCTRL/i#*/iDISMAP#,DTCNT0/i#0DTCNT1/i#2CAPTCTRLA/i#4CAPTCOMPA/i#6CAPTCTRLB/i#8CAPTCOMPB/i#:CAPTCTRLX/i#<CAPTCOMPX/i#>CVAL01#@CVAL0CYC1#BCVAL11#DCVAL1CYC1#FCVAL21#HCVAL2CYC1#JCVAL31#LCVAL3CYC1#NCVAL41#PCVAL4CYC1#RCVAL51#TCVAL5CYC1#V:RESERVED_1e#X*SM#OUTEN/i#MASK/i#SWCOUT/i#DTSRCSEL/i#MCTRL/i#MCTRL2/i#FCTRL/i#FSTS/i#FFILT/i#FTST/i#FCTRL2/i#PPWM_Type}*:RESERVED_0S#gROMPATCHDr#ROMPATCHCNTLg#ROMPATCHENHY#ROMPATCHENLg#gROMPATCHAͭ#:RESERVED_1#ROMPATCHSRg#PROMC_TypeM*CSg#CNTg#TOVALg#WINg# PRTWDOG_Type0*MCRg#IOCRg#BMCR0g#BMCR1g# gBR#:RESERVED_0î#4INTENg#8INTRg#<SDRAMCR0g#@SDRAMCR1g#DSDRAMCR2g#HSDRAMCR3g#LNANDCR0g#PNANDCR1g#TNANDCR2g#XNANDCR3g#\NORCR0g#`NORCR1g#dNORCR2g#hNORCR3Y#lSRAMCR0g#pSRAMCR1g#tSRAMCR2g#xSRAMCR3Y#|DBICR0g#DBICR1g#:RESERVED_1 #IPCR0g#IPCR1g#IPCR2g#IPCMDg#IPTXDATg#: RESERVED_2s#IPRXDATg#: RESERVED_3#STS0g#STS1Y#STS2g#STS3Y#STS4Y#STS5Y#STS6Y#STS7Y#STS8Y#STS9Y#STS10Y#STS11Y#STS12g#STS13Y#STS14Y#STS15Y#PSEMC_Typex*HPLRg#HPCOMRg#HPCRg#HPSICRg# HPSVCRg#HPSRg#HPSVSRg#HPHACIVRg#HPHACRg# HPRTCMRg#$HPRTCLRg#(HPTAMRg#,HPTALRg#0LPLRg#4LPCRg#8LPMKCRg#<LPSVCRg#@:RESERVED_0#DLPTDCRg#HLPSRg#LLPSRTCMRg#PLPSRTCLRg#TLPTARg#XLPSMCMRg#\LPSMCLRg#`LPPGDRg#dLPGPR0_LEGACY_ALIASg#hgLPZMKR_#l:RESERVED_1w#gLPGPR_ALIAS#:_RESERVED_2#gLPGPRӳ#:RESERVED_3#HPVIDR1g#HPVIDR2g#PSNVS_TypeűSSICgSISg*TSCRg#SRCDg#SRPCg#SIEg# ?#SRLg#SRRg#SRCSHg#SRCSLg# SRUg#$SRQg#(STLg#,STRg#0STCSCHg#4STCSCLg#8:RESERVED_0#<SRFMg#D:RESERVED_12#HSTCg#PPSPDIF_TypeU*HSCRg#SBMR1g#SRSRg#:RESERVED_0# SBMR2g#g GPRĵ# PSRC_Typep*:RESERVED_0#TEMPSENSE0g#TEMPSENSE0_SETg#TEMPSENSE0_CLRg#TEMPSENSE0_TOGg#TEMPSENSE1g#TEMPSENSE1_SETg#TEMPSENSE1_CLRg#TEMPSENSE1_TOGg#:RESERVED_1#TEMPSENSE2g#TEMPSENSE2_SETg#TEMPSENSE2_CLRg#TEMPSENSE2_TOGg#PTEMPMON_Typeו* COMP1/i#COMP2/i#CAPT/i#LOAD/i#HOLD/i#CNTR/i# CTRL/i# SCTRL/i#CMPLD1/i#CMPLD2/i#CSCTRL/i#FILT/i#DMA/i#:RESERVED_0#ENBL/i#*PCHANNEL*#PTMR_Type$SPKRMAXgPKRSQgSSBLIMgTOTSAMgSFRQCNTgFRQMAXgSSCMCgSCMLgSSCR1CgSCR1LgSSCR2CgSCR2LgSSCR3CgSCR3LgSSCR4CgSCR4LgSSCR5CgSCR5LgSSCR6PCgSCR6PLg*MCTLg#SCMISCg#PKRRNGg#V# SDCTLg#q#FRQMINg### #$ڸ#(#,#0(#4B#8STATUSg#<gENT#@PKRCNT10g#PKRCNT32g#PKRCNT54g#PKRCNT76g#PKRCNT98g#PKRCNTBAg#PKRCNTDCg#PKRCNTFEg#SEC_CFGg#INT_CTRLg#INT_MASKg#INT_STATUSg#:?RESERVED_0#VID1g#VID2g#PTRNG_Type^SDEVICEADDRgPERIODICLISTBASEgSASYNCLISTADDRgENDPTLISTADDRg*IDg#HWGENERALg#HWHOSTg#HWDEVICEg# HWTXBUFg#HWRXBUFg#:gRESERVED_0#GPTIMER0LDg#GPTIMER0CTRLg#GPTIMER1LDg#GPTIMER1CTRLg#SBUSCFGg#:kRESERVED_1c#CAPLENGTH_#:RESERVED_2#HCIVERSION1#HCSPARAMSg#HCCPARAMSg#:RESERVED_3#DCIVERSION1#:RESERVED_4#DCCPARAMSg#:RESERVED_5M#USBCMDg#USBSTSg#USBINTRg#FRINDEXg#:RESERVED_6#4#^#:RESERVED_7۽#BURSTSIZEg#TXFILLTUNINGg#:RESERVED_8!#ENDPTNAKg#ENDPTNAKENg#CONFIGFLAGg#PORTSC1g#:RESERVED_9#OTGSCg#USBMODEg#ENDPTSETUPSTATg#ENDPTPRIMEg#ENDPTFLUSHg#ENDPTSTATg#ENDPTCOMPLETEg#ENDPTCTRL0g#gENDPTCTRL<#:tYPUSB_TypeҞ*:RESERVED_0{#USB_OTGn_CTRLg#:RESERVED_1#USB_OTGn_PHY_CTRL_0g#PUSBNC_Typeu*׃PWDg#PWD_SETg#PWD_CLRg#PWD_TOGg# TXg#TX_SETg#TX_CLRg#TX_TOGg#RXg# RX_SETg#$RX_CLRg#(RX_TOGg#,CTRLg#0CTRL_SETg#4CTRL_CLRg#8CTRL_TOGg#<STATUSg#@: RESERVED_0#DDEBUGrg#PDEBUG_SETg#TDEBUG_CLRg#XDEBUG_TOGg#\DEBUG0_STATUSg#`: RESERVED_1d#dDEBUG1g#pDEBUG1_SETg#tDEBUG1_CLRg#xDEBUG1_TOGg#|VERSIONg#PUSBPHY_Type*ʆ`VBUS_DETECTg#VBUS_DETECT_SETg#VBUS_DETECT_CLRg#VBUS_DETECT_TOGg# CHRG_DETECTg#CHRG_DETECT_SETg#CHRG_DETECT_CLRg#CHRG_DETECT_TOGg#VBUS_DETECT_STATg# Ņ: RESERVED_0#$CHRG_DETECT_STATg#0:RESERVED_1#4MISCg#PMISC_SETg#TMISC_CLRg#XMISC_TOGg#\*݆:RESERVED_0P#INSTANCEo#DIGPROGg#PUSB_ANALOG_TypeJ˲*DS_ADDRg#BLK_ATTg#CMD_ARGg#CMD_XFR_TYPg# CMD_RSP0g#CMD_RSP1g#CMD_RSP2g#CMD_RSP3g#DATA_BUFF_ACC_PORTg# PRES_STATEg#$PROT_CTRLg#(SYS_CTRLg#,INT_STATUSg#0INT_STATUS_ENg#4INT_SIGNAL_ENg#8AUTOCMD12_ERR_STATUSg#<HOST_CTRL_CAPg#@WTMK_LVLg#DMIX_CTRLg#H:RESERVED_0#LFORCE_EVENTg#PADMA_ERR_STATUSg#TADMA_SYS_ADDRg#X:RESERVED_1q#\DLL_CTRLg#`DLL_STATUSg#dCLK_TUNE_CTRL_STATUSg#hً:SRESERVED_2#lVEND_SPECg#MMC_BOOTg#VEND_SPEC2g#TUNING_CTRLg#PUSDHC_Type* WCR/i#WSR/i#WRSR1#WICR/i#WMCR/i#PWDOG_TypeJ*SEL0/i#SEL1/i#SEL2/i#SEL3/i#SEL4/i#SEL5/i# SEL6/i# SEL7/i#SEL8/i#SEL9/i#SEL10/i#SEL11/i#SEL12/i#SEL13/i#SEL14/i#SEL15/i#SEL16/i# SEL17/i#"SEL18/i#$SEL19/i#&SEL20/i#(SEL21/i#*SEL22/i#,SEL23/i#.SEL24/i#0SEL25/i#2SEL26/i#4SEL27/i#6SEL28/i#8SEL29/i#:SEL30/i#<SEL31/i#>SEL32/i#@SEL33/i#BSEL34/i#DSEL35/i#FSEL36/i#HSEL37/i#JSEL38/i#LSEL39/i#NSEL40/i#PSEL41/i#RSEL42/i#TSEL43/i#VSEL44/i#XSEL45/i#ZSEL46/i#\SEL47/i#^SEL48/i#`SEL49/i#bSEL50/i#dSEL51/i#fSEL52/i#hSEL53/i#jSEL54/i#lSEL55/i#nSEL56/i#pSEL57/i#rSEL58/i#tSEL59/i#vSEL60/i#xSEL61/i#zSEL62/i#|SEL63/i#~SEL64/i#SEL65/i#CTRL0/i#CTRL1/i#PXBARA_Type*SEL0/i#SEL1/i#SEL2/i#SEL3/i#SEL4/i#SEL5/i# SEL6/i# SEL7/i#PXBARB_Type&*:RESERVED_0#MISC0g#MISC0_SETg#MISC0_CLRg#MISC0_TOGg#:RESERVED_1 #LOWPWR_CTRLg#LOWPWR_CTRL_SETg#LOWPWR_CTRL_CLRg#LOWPWR_CTRL_TOGg#:RESERVED_2#OSC_CONFIG0g#OSC_CONFIG0_SETg#OSC_CONFIG0_CLRg#OSC_CONFIG0_TOGg#OSC_CONFIG1g#OSC_CONFIG1_SETg#OSC_CONFIG1_CLRg#OSC_CONFIG1_TOGg#OSC_CONFIG2g#OSC_CONFIG2_SETg#OSC_CONFIG2_CLRg#OSC_CONFIG2_TOGg#PXTALOSC24M_Typex .\middleware\flexspi/fsl_flexspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash >|=_Bool"YPflexspi_serial_clk_freq_tpPflexspi_read_sample_clk_tPflexspi_ipcmd_error_tPflexspi_lut_seq_tPflexspi_dll_time_t Pflexspi_mem_config_t Pflexspi_operation_t$Pflexspi_xfer_tkFlexSpiClock_CoreClock kFlexSpiClock_AhbClock kFlexSpiClock_SerialRootClock kFlexSpiClock_IpgClock Pflexspi_clock_type_t_FlexSpiSerialClockFreqkFlexSpiSerialClk_30MHz kFlexSpiSerialClk_50MHz kFlexSpiSerialClk_60MHz kFlexSpiSerialClk_75MHz kFlexSpiSerialClk_80MHz kFlexSpiSerialClk_100MHz kFlexSpiSerialClk_133MHz kFlexSpiSerialClk_166MHz kFlexSpiSerialClk_200MHz kFlexSpiClk_SDR kFlexSpiClk_DDR  _FlashReadSampleClkSourcekFlexSPIReadSampleClk_LoopbackInternally kFlexSPIReadSampleClk_LoopbackFromDqsPad kFlexSPIReadSampleClk_LoopbackFromSckPad kFlexSPIReadSampleClk_ExternalInputFromDqsPad  _FlexSpiIpCmdErrorkFlexSpiIpCmdError_NoError kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode kFlexSpiIpCmdError_JumpOnCsInIpCmd kFlexSpiIpCmdError_UnknownOpCode kFlexSpiIpCmdError_SdrDummyInDdrSequence kFlexSpiIpCmdError_DDRDummyInSdrSequence kFlexSpiIpCmdError_InvalidAddress kFlexSpiIpCmdError_SequenceExecutionTimeout kFlexSpiIpCmdError_FlashBoundaryAcrosss  _flexspi_statuskStatus_FLEXSPI_SequenceExecutionTimeoutXkStatus_FLEXSPI_InvalidSequenceYkStatus_FLEXSPI_DeviceTimeoutZkFlexSpiMiscOffset_DiffClkEnable kFlexSpiMiscOffset_Ck2Enable kFlexSpiMiscOffset_ParallelEnable kFlexSpiMiscOffset_WordAddressableEnable kFlexSpiMiscOffset_SafeConfigFreqEnable kFlexSpiMiscOffset_PadSettingOverrideEnable kFlexSpiMiscOffset_DdrModeEnable kFlexSpiMiscOffset_UseValidTimeForAllFreq kFlexSpiDeviceType_SerialNOR kFlexSpiDeviceType_SerialNAND kFlexSpiDeviceType_SerialRAM kFlexSpiDeviceType_MCP_NOR_NAND kFlexSpiDeviceType_MCP_NOR_RAM kSerialFlash_1Pad kSerialFlash_2Pads kSerialFlash_4Pads kSerialFlash_8Pads )_lut_sequenceseqNum:#seqId:#reservedI#kDeviceConfigCmdType_Generic kDeviceConfigCmdType_QuadEnable kDeviceConfigCmdType_Spi2Xpi kDeviceConfigCmdType_Xpi2Spi kDeviceConfigCmdType_Spi2NoCmd kDeviceConfigCmdType_Reset *time_100ps:#delay_cells:#)_FlexSPIConfigtagY#versionY#reserved0Y#readSampleClkSrc:# dataHoldTime:# dataSetupTime:#columnAddressWidth:#deviceModeCfgEnable:#deviceModeType:#waitTimeCfgCommandsI#deviceModeSeqY#deviceModeArgY#configCmdEnable:#:configModeType^ #YconfigCmdSeqs # reserved1Y#,YconfigCmdArgs #0reserved2Y#<controllerMiscOptionY#@deviceType:#DsflashPadType:#EserialClkFreq:#FlutCustomSeqEnable:#GYreserved3_ #HsflashA1SizeY#PsflashA2SizeY#TsflashB1SizeY#XsflashB2SizeY#\csPadSettingOverrideY#`sclkPadSettingOverrideY#ddataPadSettingOverrideY#hdqsPadSettingOverrideY#ltimeoutInMsY#pcommandIntervalY#tsdataValidTime~ #xbusyOffsetI#|busyBitPolarityI#~Y?lookupTable #Y lutCustomSeq #Yreserved4#_FlexSPIOperationTypekFlexSpiOperation_Command kFlexSpiOperation_Config kFlexSpiOperation_Write kFlexSpiOperation_Read kFlexSpiOperation_End )_FlexSpiXfer$operation#baseAddressY#seqIdY#seqNumY# isParallelModeEnable#txBuffer#txSizeY#rxBuffer#rxSizeY#  devices\MIMXRT1021\MIMXRT1021.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashIRQnNotAvail_IRQnNonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnDMA0_DMA16_IRQnDMA1_DMA17_IRQnDMA2_DMA18_IRQnDMA3_DMA19_IRQnDMA4_DMA20_IRQnDMA5_DMA21_IRQnDMA6_DMA22_IRQnDMA7_DMA23_IRQnDMA8_DMA24_IRQnDMA9_DMA25_IRQn DMA10_DMA26_IRQn DMA11_DMA27_IRQn DMA12_DMA28_IRQn DMA13_DMA29_IRQn DMA14_DMA30_IRQnDMA15_DMA31_IRQnDMA_ERROR_IRQnCTI0_ERROR_IRQnCTI1_ERROR_IRQnCORE_IRQnLPUART1_IRQnLPUART2_IRQnLPUART3_IRQnLPUART4_IRQnLPUART5_IRQnLPUART6_IRQnLPUART7_IRQnLPUART8_IRQnLPI2C1_IRQnLPI2C2_IRQnLPI2C3_IRQnLPI2C4_IRQnLPSPI1_IRQn LPSPI2_IRQn!LPSPI3_IRQn"LPSPI4_IRQn#CAN1_IRQn$CAN2_IRQn%FLEXRAM_IRQn&KPP_IRQn'Reserved56_IRQn(GPR_IRQ_IRQn)Reserved58_IRQn*Reserved59_IRQn+Reserved60_IRQn,WDOG2_IRQn-SNVS_HP_WRAPPER_IRQn.SNVS_HP_WRAPPER_TZ_IRQn/SNVS_LP_WRAPPER_IRQn0Reserved65_IRQn1DCP_IRQn2DCP_VMI_IRQn3Reserved68_IRQn4TRNG_IRQn5Reserved70_IRQn6Reserved71_IRQn7SAI1_IRQn8SAI2_IRQn9SAI3_RX_IRQn:SAI3_TX_IRQn;SPDIF_IRQn<PMU_IRQn=Reserved78_IRQn>TEMP_LOW_HIGH_IRQn?TEMP_PANIC_IRQnUSB_PHY1_IRQnReserved82_IRQnADC1_IRQnADC2_IRQnDCDC_IRQnReserved86_IRQnReserved87_IRQnGPIO1_INT0_IRQnGPIO1_INT1_IRQnGPIO1_INT2_IRQnGPIO1_INT3_IRQnGPIO1_INT4_IRQnGPIO1_INT5_IRQnGPIO1_INT6_IRQnGPIO1_INT7_IRQnGPIO1_Combined_0_15_IRQnGPIO1_Combined_16_31_IRQnGPIO2_Combined_0_15_IRQnGPIO2_Combined_16_31_IRQnGPIO3_Combined_0_15_IRQnGPIO3_Combined_16_31_IRQnReserved102_IRQnReserved103_IRQnGPIO5_Combined_0_15_IRQnGPIO5_Combined_16_31_IRQnFLEXIO1_IRQnReserved107_IRQnWDOG1_IRQnRTWDOG_IRQnEWM_IRQnCCM_1_IRQnCCM_2_IRQnGPC_IRQnSRC_IRQnReserved115_IRQnGPT1_IRQnGPT2_IRQnPWM1_0_IRQnPWM1_1_IRQnPWM1_2_IRQnPWM1_3_IRQnPWM1_FAULT_IRQnReserved123_IRQnFLEXSPI_IRQnSEMC_IRQnUSDHC1_IRQnUSDHC2_IRQnReserved128_IRQnUSB_OTG1_IRQnENET_IRQnENET_1588_Timer_IRQnXBAR1_IRQ_0_1_IRQnXBAR1_IRQ_2_3_IRQnADC_ETC_IRQ0_IRQnADC_ETC_IRQ1_IRQnADC_ETC_IRQ2_IRQnADC_ETC_ERROR_IRQ_IRQnPIT_IRQnACMP1_IRQnACMP2_IRQnACMP3_IRQnACMP4_IRQnReserved143_IRQnReserved144_IRQnENC1_IRQnENC2_IRQnReserved147_IRQnReserved148_IRQnTMR1_IRQnTMR2_IRQnReserved151_IRQnReserved152_IRQnPWM2_0_IRQnPWM2_1_IRQnPWM2_2_IRQnPWM2_3_IRQnPWM2_FAULT_IRQnPIRQn_Type,_dma_request_sourcekDmaRequestMuxFlexIO1Request0Request1kDmaRequestMuxFlexIO1Request4Request5kDmaRequestMuxLPUART1TxkDmaRequestMuxLPUART1RxkDmaRequestMuxLPUART3TxkDmaRequestMuxLPUART3RxkDmaRequestMuxLPUART5TxkDmaRequestMuxLPUART5RxkDmaRequestMuxLPUART7TxkDmaRequestMuxLPUART7Rx kDmaRequestMuxLPSPI1Rx kDmaRequestMuxLPSPI1TxkDmaRequestMuxLPSPI3RxkDmaRequestMuxLPSPI3TxkDmaRequestMuxLPI2C1kDmaRequestMuxLPI2C3kDmaRequestMuxSai1RxkDmaRequestMuxSai1TxkDmaRequestMuxSai2RxkDmaRequestMuxSai2TxkDmaRequestMuxADC_ETCkDmaRequestMuxADC1kDmaRequestMuxACMP1kDmaRequestMuxACMP2kDmaRequestMuxFlexSPIRxkDmaRequestMuxFlexSPITxkDmaRequestMuxXBAR1Request0kDmaRequestMuxXBAR1Request1kDmaRequestMuxFlexPWM1CaptureSub0 kDmaRequestMuxFlexPWM1CaptureSub1!kDmaRequestMuxFlexPWM1CaptureSub2"kDmaRequestMuxFlexPWM1CaptureSub3#kDmaRequestMuxFlexPWM1ValueSub0$kDmaRequestMuxFlexPWM1ValueSub1%kDmaRequestMuxFlexPWM1ValueSub2&kDmaRequestMuxFlexPWM1ValueSub3'kDmaRequestMuxQTIMER1CaptTimer00kDmaRequestMuxQTIMER1CaptTimer11kDmaRequestMuxQTIMER1CaptTimer22kDmaRequestMuxQTIMER1CaptTimer33kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer14kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer05kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer36kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer27kDmaRequestMuxFlexIO1Request2Request3@kDmaRequestMuxFlexIO1Request6Request7AkDmaRequestMuxLPUART2TxBkDmaRequestMuxLPUART2RxCkDmaRequestMuxLPUART4TxDkDmaRequestMuxLPUART4RxEkDmaRequestMuxLPUART6TxFkDmaRequestMuxLPUART6RxGkDmaRequestMuxLPUART8TxHkDmaRequestMuxLPUART8RxIkDmaRequestMuxLPSPI2RxMkDmaRequestMuxLPSPI2TxNkDmaRequestMuxLPSPI4RxOkDmaRequestMuxLPSPI4TxPkDmaRequestMuxLPI2C2QkDmaRequestMuxLPI2C4RkDmaRequestMuxSai3RxSkDmaRequestMuxSai3TxTkDmaRequestMuxSpdifRxUkDmaRequestMuxSpdifTxVkDmaRequestMuxADC2XkDmaRequestMuxACMP3YkDmaRequestMuxACMP4ZkDmaRequestMuxEnetTimer0\kDmaRequestMuxEnetTimer1]kDmaRequestMuxXBAR1Request2^kDmaRequestMuxXBAR1Request3_kDmaRequestMuxFlexPWM2CaptureSub0`kDmaRequestMuxFlexPWM2CaptureSub1akDmaRequestMuxFlexPWM2CaptureSub2bkDmaRequestMuxFlexPWM2CaptureSub3ckDmaRequestMuxFlexPWM2ValueSub0dkDmaRequestMuxFlexPWM2ValueSub1ekDmaRequestMuxFlexPWM2ValueSub2fkDmaRequestMuxFlexPWM2ValueSub3gkDmaRequestMuxQTIMER2CaptTimer0pkDmaRequestMuxQTIMER2CaptTimer1qkDmaRequestMuxQTIMER2CaptTimer2rkDmaRequestMuxQTIMER2CaptTimer3skDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1tkDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0ukDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3vkDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2wPdma_request_source_tE I_iomuxc_sw_mux_ctl_padkIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 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\Piomuxc_sw_pad_ctl_pad_t$_iomuxc_select_inputkIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT kIOMUXC_CCM_PMIC_READY_SELECT_INPUT kIOMUXC_ENET_RMII_SELECT_INPUT kIOMUXC_ENET_MDIO_SELECT_INPUT kIOMUXC_ENET_RX_DATA0_SELECT_INPUT kIOMUXC_ENET_RX_DATA1_SELECT_INPUT kIOMUXC_ENET_RX_EN_SELECT_INPUT kIOMUXC_ENET_RX_ERR_SELECT_INPUT kIOMUXC_ENET_TX_CLK_SELECT_INPUT kIOMUXC_FLEXCAN1_RX_SELECT_INPUT kIOMUXC_FLEXCAN2_RX_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT kIOMUXC_LPI2C1_SCL_SELECT_INPUT kIOMUXC_LPI2C1_SDA_SELECT_INPUT !kIOMUXC_LPI2C2_SCL_SELECT_INPUT "kIOMUXC_LPI2C2_SDA_SELECT_INPUT #kIOMUXC_LPI2C3_SCL_SELECT_INPUT $kIOMUXC_LPI2C3_SDA_SELECT_INPUT %kIOMUXC_LPI2C4_SCL_SELECT_INPUT &kIOMUXC_LPI2C4_SDA_SELECT_INPUT 'kIOMUXC_LPSPI1_PCS0_SELECT_INPUT (kIOMUXC_LPSPI1_SCK_SELECT_INPUT )kIOMUXC_LPSPI1_SDI_SELECT_INPUT *kIOMUXC_LPSPI1_SDO_SELECT_INPUT +kIOMUXC_LPSPI2_PCS0_SELECT_INPUT ,kIOMUXC_LPSPI2_SCK_SELECT_INPUT -kIOMUXC_LPSPI2_SDI_SELECT_INPUT .kIOMUXC_LPSPI2_SDO_SELECT_INPUT /kIOMUXC_LPSPI4_PCS0_SELECT_INPUT 0kIOMUXC_LPSPI4_SCK_SELECT_INPUT 1kIOMUXC_LPSPI4_SDI_SELECT_INPUT 2kIOMUXC_LPSPI4_SDO_SELECT_INPUT 3kIOMUXC_LPUART2_CTS_B_SELECT_INPUT 4kIOMUXC_LPUART2_RX_SELECT_INPUT 5kIOMUXC_LPUART2_TX_SELECT_INPUT 6kIOMUXC_LPUART3_RX_SELECT_INPUT 7kIOMUXC_LPUART3_TX_SELECT_INPUT 8kIOMUXC_LPUART4_CTS_B_SELECT_INPUT 9kIOMUXC_LPUART4_RX_SELECT_INPUT :kIOMUXC_LPUART4_TX_SELECT_INPUT ;kIOMUXC_LPUART5_RX_SELECT_INPUT <kIOMUXC_LPUART5_TX_SELECT_INPUT =kIOMUXC_LPUART6_RX_SELECT_INPUT >kIOMUXC_LPUART6_TX_SELECT_INPUT ?kIOMUXC_LPUART7_RX_SELECT_INPUT @kIOMUXC_LPUART7_TX_SELECT_INPUT AkIOMUXC_LPUART8_RX_SELECT_INPUT BkIOMUXC_LPUART8_TX_SELECT_INPUT CkIOMUXC_NMI_SELECT_INPUT DkIOMUXC_QTIMER1_TIMER0_INPUT_SELECT_INPUT EkIOMUXC_QTIMER1_TIMER1_INPUT_SELECT_INPUT FkIOMUXC_QTIMER1_TIMER2_INPUT_SELECT_INPUT GkIOMUXC_QTIMER1_TIMER3_INPUT_SELECT_INPUT HkIOMUXC_QTIMER2_TIMER0_INPUT_SELECT_INPUT IkIOMUXC_QTIMER2_TIMER1_INPUT_SELECT_INPUT JkIOMUXC_QTIMER2_TIMER2_INPUT_SELECT_INPUT KkIOMUXC_QTIMER2_TIMER3_INPUT_SELECT_INPUT LkIOMUXC_SAI1_MCLK_SELECT_INPUT MkIOMUXC_SAI1_RX_BCLK_SELECT_INPUT NkIOMUXC_SAI1_RX_DATA0_SELECT_INPUT OkIOMUXC_SAI1_RX_DATA1_SELECT_INPUT PkIOMUXC_SAI1_RX_DATA2_SELECT_INPUT QkIOMUXC_SAI1_RX_DATA3_SELECT_INPUT RkIOMUXC_SAI1_RX_SYNC_SELECT_INPUT SkIOMUXC_SAI1_TX_BCLK_SELECT_INPUT TkIOMUXC_SAI1_TX_SYNC_SELECT_INPUT UkIOMUXC_SAI2_MCLK_SELECT_INPUT VkIOMUXC_SAI2_RX_BCLK_SELECT_INPUT WkIOMUXC_SAI2_RX_DATA0_SELECT_INPUT XkIOMUXC_SAI2_RX_SYNC_SELECT_INPUT YkIOMUXC_SAI2_TX_BCLK_SELECT_INPUT ZkIOMUXC_SAI2_TX_SYNC_SELECT_INPUT [kIOMUXC_SAI3_MCLK_SELECT_INPUT \kIOMUXC_SAI3_RX_BCLK_SELECT_INPUT ]kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT ^kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT _kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT `kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT akIOMUXC_SEMC_READY_SELECT_INPUT bkIOMUXC_SPDIF_IN_SELECT_INPUT ckIOMUXC_USB_OTG_OC_SELECT_INPUT dkIOMUXC_USDHC1_CD_B_SELECT_INPUT ekIOMUXC_USDHC1_WP_SELECT_INPUT fkIOMUXC_USDHC2_CD_B_SELECT_INPUT gkIOMUXC_USDHC2_WP_SELECT_INPUT hkIOMUXC_XBAR1_IN14_SELECT_INPUT ikIOMUXC_XBAR1_IN15_SELECT_INPUT jkIOMUXC_XBAR1_IN16_SELECT_INPUT kkIOMUXC_XBAR1_IN17_SELECT_INPUT lkIOMUXC_XBAR1_IN10_SELECT_INPUT mkIOMUXC_XBAR1_IN12_SELECT_INPUT nkIOMUXC_XBAR1_IN13_SELECT_INPUT okIOMUXC_XBAR1_IN18_SELECT_INPUT pkIOMUXC_XBAR1_IN19_SELECT_INPUT qPiomuxc_select_input_tc3_xbar_input_signalkXBARA_InputLogicLowkXBARA_InputLogicHighkXBARA_InputRESERVED2kXBARA_InputRESERVED3kXBARA_InputIomuxXbarInout04kXBARA_InputIomuxXbarInout05kXBARA_InputIomuxXbarInout06kXBARA_InputIomuxXbarInout07kXBARA_InputIomuxXbarInout08kXBARA_InputIomuxXbarInout09 kXBARA_InputIomuxXbarInout10 kXBARA_InputIomuxXbarInout11 kXBARA_InputIomuxXbarInout12 kXBARA_InputIomuxXbarInout13 kXBARA_InputIomuxXbarInout14kXBARA_InputIomuxXbarInout15kXBARA_InputIomuxXbarInout16kXBARA_InputIomuxXbarInout17kXBARA_InputIomuxXbarInout18kXBARA_InputIomuxXbarInout19kXBARA_InputRESERVED20kXBARA_InputRESERVED21kXBARA_InputRESERVED22kXBARA_InputRESERVED23kXBARA_InputRESERVED24kXBARA_InputRESERVED25kXBARA_InputAcmp1OutkXBARA_InputAcmp2OutkXBARA_InputAcmp3OutkXBARA_InputAcmp4OutkXBARA_InputRESERVED30kXBARA_InputRESERVED31kXBARA_InputQtimer1Tmr0 kXBARA_InputQtimer1Tmr1!kXBARA_InputQtimer1Tmr2"kXBARA_InputQtimer1Tmr3#kXBARA_InputQtimer2Tmr0$kXBARA_InputQtimer2Tmr1%kXBARA_InputQtimer2Tmr2&kXBARA_InputQtimer2Tmr3'kXBARA_InputFlexpwm1Pwm1OutTrig01(kXBARA_InputFlexpwm1Pwm2OutTrig01)kXBARA_InputFlexpwm1Pwm3OutTrig01*kXBARA_InputFlexpwm1Pwm4OutTrig01+kXBARA_InputFlexpwm2Pwm1OutTrig01,kXBARA_InputFlexpwm2Pwm2OutTrig01-kXBARA_InputFlexpwm2Pwm3OutTrig01.kXBARA_InputFlexpwm2Pwm4OutTrig01/kXBARA_InputRESERVED480kXBARA_InputRESERVED491kXBARA_InputRESERVED502kXBARA_InputRESERVED513kXBARA_InputRESERVED524kXBARA_InputRESERVED535kXBARA_InputRESERVED546kXBARA_InputRESERVED557kXBARA_InputPitTrigger08kXBARA_InputPitTrigger19kXBARA_InputPitTrigger2:kXBARA_InputPitTrigger3;kXBARA_InputEnc1PosMatch<kXBARA_InputEnc2PosMatch=kXBARA_InputRESERVED62>kXBARA_InputRESERVED63?kXBARA_InputDmaDone0@kXBARA_InputDmaDone1AkXBARA_InputDmaDone2BkXBARA_InputDmaDone3CkXBARA_InputDmaDone4DkXBARA_InputDmaDone5EkXBARA_InputDmaDone6FkXBARA_InputDmaDone7GkXBARA_InputAoi1Out0HkXBARA_InputAoi1Out1IkXBARA_InputAoi1Out2JkXBARA_InputAoi1Out3KkXBARA_InputRESERVED76LkXBARA_InputRESERVED77MkXBARA_InputRESERVED78NkXBARA_InputRESERVED79OkXBARA_InputAdcEtc0Coco0PkXBARA_InputAdcEtc0Coco1QkXBARA_InputAdcEtc0Coco2RkXBARA_InputAdcEtc0Coco3SkXBARA_InputAdcEtc1Coco0TkXBARA_InputAdcEtc1Coco1UkXBARA_InputAdcEtc1Coco2VkXBARA_InputAdcEtc1Coco3WkXBARB_InputLogicLowkXBARB_InputLogicHighkXBARB_InputRESERVED2kXBARB_InputRESERVED3kXBARB_InputRESERVED4kXBARB_InputRESERVED5kXBARB_InputAcmp1OutkXBARB_InputAcmp2OutkXBARB_InputAcmp3OutkXBARB_InputAcmp4Out kXBARB_InputRESERVED10 kXBARB_InputRESERVED11 kXBARB_InputQtimer1Tmr0 kXBARB_InputQtimer1Tmr1 kXBARB_InputQtimer1Tmr2kXBARB_InputQtimer1Tmr3kXBARB_InputQtimer2Tmr0kXBARB_InputQtimer2Tmr1kXBARB_InputQtimer2Tmr2kXBARB_InputQtimer2Tmr3kXBARB_InputFlexpwm1Pwm1OutTrig01kXBARB_InputFlexpwm1Pwm2OutTrig01kXBARB_InputFlexpwm1Pwm3OutTrig01kXBARB_InputFlexpwm1Pwm4OutTrig01kXBARB_InputFlexpwm2Pwm1OutTrig01kXBARB_InputFlexpwm2Pwm2OutTrig01kXBARB_InputFlexpwm2Pwm3OutTrig01kXBARB_InputFlexpwm2Pwm4OutTrig01kXBARB_InputRESERVED28kXBARB_InputRESERVED29kXBARB_InputRESERVED30kXBARB_InputRESERVED31kXBARB_InputRESERVED32 kXBARB_InputRESERVED33!kXBARB_InputRESERVED34"kXBARB_InputRESERVED35#kXBARB_InputPitTrigger0$kXBARB_InputPitTrigger1%kXBARB_InputAdcEtc0Coco0&kXBARB_InputAdcEtc0Coco1'kXBARB_InputAdcEtc0Coco2(kXBARB_InputAdcEtc0Coco3)kXBARB_InputAdcEtc1Coco0*kXBARB_InputAdcEtc1Coco1+kXBARB_InputAdcEtc1Coco2,kXBARB_InputAdcEtc1Coco3-kXBARB_InputEnc1PosMatch.kXBARB_InputEnc2PosMatch/kXBARB_InputRESERVED480kXBARB_InputRESERVED491kXBARB_InputDmaDone02kXBARB_InputDmaDone13kXBARB_InputDmaDone24kXBARB_InputDmaDone35kXBARB_InputDmaDone46kXBARB_InputDmaDone57kXBARB_InputDmaDone68kXBARB_InputDmaDone79Pxbar_input_signal_tD_xbar_output_signalkXBARA_OutputDmaChMuxReq30kXBARA_OutputDmaChMuxReq31kXBARA_OutputDmaChMuxReq94kXBARA_OutputDmaChMuxReq95kXBARA_OutputIomuxXbarInout04kXBARA_OutputIomuxXbarInout05kXBARA_OutputIomuxXbarInout06kXBARA_OutputIomuxXbarInout07kXBARA_OutputIomuxXbarInout08kXBARA_OutputIomuxXbarInout09 kXBARA_OutputIomuxXbarInout10 kXBARA_OutputIomuxXbarInout11 kXBARA_OutputIomuxXbarInout12 kXBARA_OutputIomuxXbarInout13 kXBARA_OutputIomuxXbarInout14kXBARA_OutputIomuxXbarInout15kXBARA_OutputIomuxXbarInout16kXBARA_OutputIomuxXbarInout17kXBARA_OutputIomuxXbarInout18kXBARA_OutputIomuxXbarInout19kXBARA_OutputAcmp1SamplekXBARA_OutputAcmp2SamplekXBARA_OutputAcmp3SamplekXBARA_OutputAcmp4SamplekXBARA_OutputRESERVED24kXBARA_OutputRESERVED25kXBARA_OutputFlexpwm1Exta0kXBARA_OutputFlexpwm1Exta1kXBARA_OutputFlexpwm1Exta2kXBARA_OutputFlexpwm1Exta3kXBARA_OutputFlexpwm1ExtSync0kXBARA_OutputFlexpwm1ExtSync1kXBARA_OutputFlexpwm1ExtSync2 kXBARA_OutputFlexpwm1ExtSync3!kXBARA_OutputFlexpwm1ExtClk"kXBARA_OutputFlexpwm1Fault0#kXBARA_OutputFlexpwm1Fault1$kXBARA_OutputFlexpwm1Fault2%flexpwm2Fault2%kXBARA_OutputFlexpwm1Fault3&flexpwm2Fault3&kXBARA_OutputFlexpwm1ExtForce'kXBARA_OutputFlexpwm2Exta0(kXBARA_OutputFlexpwm2Exta1)kXBARA_OutputFlexpwm2Exta2*kXBARA_OutputFlexpwm2Exta3+kXBARA_OutputFlexpwm2ExtSync0,kXBARA_OutputFlexpwm2ExtSync1-kXBARA_OutputFlexpwm2ExtSync2.kXBARA_OutputFlexpwm2ExtSync3/kXBARA_OutputFlexpwm2ExtClk0kXBARA_OutputFlexpwm2Fault01kXBARA_OutputFlexpwm2Fault12kXBARA_OutputFlexpwm2ExtForce3kXBARA_OutputRESERVED524kXBARA_OutputRESERVED535kXBARA_OutputRESERVED546kXBARA_OutputRESERVED557kXBARA_OutputRESERVED568kXBARA_OutputRESERVED579kXBARA_OutputRESERVED58:kXBARA_OutputRESERVED59;kXBARA_OutputRESERVED60<kXBARA_OutputRESERVED61=kXBARA_OutputRESERVED62>kXBARA_OutputRESERVED63?kXBARA_OutputRESERVED64@kXBARA_OutputRESERVED65AkXBARA_OutputEnc1PhaseAInputBkXBARA_OutputEnc1PhaseBInputCkXBARA_OutputEnc1IndexDkXBARA_OutputEnc1HomeEkXBARA_OutputEnc1TriggerFkXBARA_OutputEnc2PhaseAInputGkXBARA_OutputEnc2PhaseBInputHkXBARA_OutputEnc2IndexIkXBARA_OutputEnc2HomeJkXBARA_OutputEnc2TriggerKkXBARA_OutputRESERVED76LkXBARA_OutputRESERVED77MkXBARA_OutputRESERVED78NkXBARA_OutputRESERVED79OkXBARA_OutputRESERVED80PkXBARA_OutputRESERVED81QkXBARA_OutputRESERVED82RkXBARA_OutputRESERVED83SkXBARA_OutputRESERVED84TkXBARA_OutputRESERVED85UkXBARA_OutputQtimer1Tmr0VkXBARA_OutputQtimer1Tmr1WkXBARA_OutputQtimer1Tmr2XkXBARA_OutputQtimer1Tmr3YkXBARA_OutputQtimer2Tmr0ZkXBARA_OutputQtimer2Tmr1[kXBARA_OutputQtimer2Tmr2\kXBARA_OutputQtimer2Tmr3]kXBARA_OutputRESERVED94^kXBARA_OutputRESERVED95_kXBARA_OutputRESERVED96`kXBARA_OutputRESERVED97akXBARA_OutputRESERVED98bkXBARA_OutputRESERVED99ckXBARA_OutputRESERVED100dkXBARA_OutputRESERVED101ekXBARA_OutputEwmEwmInfkXBARA_OutputAdcEtcTrig00gkXBARA_OutputAdcEtcTrig01hkXBARA_OutputAdcEtcTrig02ikXBARA_OutputAdcEtcTrig03jkXBARA_OutputAdcEtcTrig10kkXBARA_OutputAdcEtcTrig11lkXBARA_OutputAdcEtcTrig12mkXBARA_OutputAdcEtcTrig13nkXBARA_OutputLpi2c1TrgInputokXBARA_OutputLpi2c2TrgInputpkXBARA_OutputLpi2c3TrgInputqkXBARA_OutputLpi2c4TrgInputrkXBARA_OutputLpspi1TrgInputskXBARA_OutputLpspi2TrgInputtkXBARA_OutputLpspi3TrgInputukXBARA_OutputLpspi4TrgInputvkXBARA_OutputLpuart1TrgInputwkXBARA_OutputLpuart2TrgInputxkXBARA_OutputLpuart3TrgInputykXBARA_OutputLpuart4TrgInputzkXBARA_OutputLpuart5TrgInput{kXBARA_OutputLpuart6TrgInput|kXBARA_OutputLpuart7TrgInput}kXBARA_OutputLpuart8TrgInput~kXBARA_OutputFlexio1TriggerIn0kXBARA_OutputFlexio1TriggerIn1kXBARA_OutputRESERVED129kXBARA_OutputRESERVED130kXBARA_OutputRESERVED131kXBARB_OutputAoi1In00kXBARB_OutputAoi1In01kXBARB_OutputAoi1In02kXBARB_OutputAoi1In03kXBARB_OutputAoi1In04kXBARB_OutputAoi1In05kXBARB_OutputAoi1In06kXBARB_OutputAoi1In07kXBARB_OutputAoi1In08kXBARB_OutputAoi1In09 kXBARB_OutputAoi1In10 kXBARB_OutputAoi1In11 kXBARB_OutputAoi1In12 kXBARB_OutputAoi1In13 kXBARB_OutputAoi1In14kXBARB_OutputAoi1In15Pxbar_output_signal_tT*\gHCf#HS g#  gRf#$CFGg#DGCg#HGSg#LCVg#POFSg#TCALg#XtYYtgPADC_Typef*(TRIGn_CTRLg#TRIGn_COUNTERg#TRIGn_CHAIN_1_0g#TRIGn_CHAIN_3_2g# TRIGn_CHAIN_5_4g#TRIGn_CHAIN_7_6g#TRIGn_RESULT_1_0 g#TRIGn_RESULT_3_2 g#TRIGn_RESULT_5_4 g# TRIGn_RESULT_7_6 g#$*CTRLg#DONE0_1_IRQg#DONE2_ERR_IRQg#DMA_CTRLg# "gTRIGUh#PADC_ETC_Type h *TMPRg#:;RESERVED_0h#OPACRg#@OPACR1g#DOPACR2g#HOPACR3g#LOPACR4g#PPAIPSTZ_Typeh *BFCRT01-i#BFCRT23-i#tI* iBFCRT8i#PAOI_Type3i*CSg#IDg#WORD0g#WORD1g# *MCRg#CTRL1g#TIMERg#:RESERVED_0i# RXMGMASKg#RX14MASKg#RX15MASKg#ECRg#ESR1g# IMASK2g#$IMASK1g#(IFLAG2g#,IFLAG1g#0CTRL2g#4ESR2 g#8:RESERVED_1vj#<CRCR g#DRXFGMASKg#HRXFIR g#L:/RESERVED_2j#Pai?MBj#:RESERVED_3j# g?RXIMRk#:_RESERVED_4(k#GFWRg#PCAN_Typei*CCRg#:RESERVED_0wk#CSR g#CCSRg# CACRRg#CBCDRg#CBCMRg#CSCMR1g#CSCMR2g# CSCDR1g#$CS1CDRg#(CS2CDRg#,CDCDRg#0:RESERVED_1&l#4CSCDR2g#8CSCDR3Y#<:RESERVED_2bl#@CDHIPR g#H:RESERVED_3l#LCLPCRg#TCISRg#XCIMRg#\CCOSRg#`CGPRg#dCCGR0g#hCCGR1g#lCCGR2g#pCCGR3g#tCCGR4g#xCCGR5g#|CCGR6g#:RESERVED_4Fm#CMEORg#PCCM_Typefk*:RESERVED_0m#PLL_USB1g#PLL_USB1_SETg#PLL_USB1_CLRg#PLL_USB1_TOGg#:RESERVED_1m# PLL_SYSg#0PLL_SYS_SETg#4PLL_SYS_CLRg#8PLL_SYS_TOGg#<PLL_SYS_SSg#@: RESERVED_2mn#DPLL_SYS_NUMg#P: RESERVED_3n#TPLL_SYS_DENOMg#`: RESERVED_4n#dPLL_AUDIOg#pPLL_AUDIO_SETg#tPLL_AUDIO_CLRg#xPLL_AUDIO_TOGg#|PLL_AUDIO_NUMg#: RESERVED_5Uo#PLL_AUDIO_DENOMg#:KRESERVED_6o#PLL_ENETg#PLL_ENET_SETg#PLL_ENET_CLRg#PLL_ENET_TOGg#PFD_480g#PFD_480_SETg#PFD_480_CLRg#PFD_480_TOGg#PFD_528g#PFD_528_SETg#PFD_528_CLRg#PFD_528_TOGg#:?RESERVED_7p#MISC0g#MISC0_SETg#MISC0_CLRg#MISC0_TOGg#MISC1g#MISC1_SETg#MISC1_CLRg#MISC1_TOGg#MISC2g#MISC2_SETg#MISC2_CLRg#MISC2_TOGg#PCCM_ANALOG_Typem*CR0q#CR1q#FPRq#SCRq#DACCRq#MUXCRq#t:PCMP_Typeq%*REG0g#REG1g#REG2g#REG3g# PDCDC_Typeq'*CTRLg#: RESERVED_0Tr#STATg#: RESERVED_1~r#CHANNELCTRLg# : RESERVED_2r#$CAPABILITY0g#0: RESERVED_3r#4CAPABILITY1 g#@: RESERVED_4s#DCONTEXTg#P: RESERVED_5>s#TKEYg#`: RESERVED_6gs#dKEYDATAg#p: RESERVED_7s#tPACKET0 g#: RESERVED_8s#PACKET1 g#: RESERVED_9s#PACKET2 g#: RESERVED_10 t#PACKET3 g#: RESERVED_11Pt#PACKET4 g#: RESERVED_12t#PACKET5 g#: RESERVED_13t#PACKET6 g#:RESERVED_14t#CH0CMDPTRg#: RESERVED_15u#CH0SEMAg#: RESERVED_16Bu#CH0STATg#: RESERVED_17ru#CH0OPTSg#: RESERVED_18u#CH1CMDPTRg#: RESERVED_19u#CH1SEMAg#: RESERVED_20v#CH1STATg#: RESERVED_214v#CH1OPTSg#: RESERVED_22dv#CH2CMDPTRg#: RESERVED_23v#CH2SEMAg#: RESERVED_24v#CH2STATg#: RESERVED_25v#CH2OPTSg#: RESERVED_26&w#CH3CMDPTRg#: RESERVED_27Xw#CH3SEMAg#: RESERVED_28w#CH3STATg#: RESERVED_29w#CH3OPTSg#:RESERVED_30w#DBGSELECTg#: RESERVED_31x#DBGDATA g#: RESERVED_32Kx#PAGETABLEg#: RESERVED_33}x#VERSION g#PDCP_TypeBr)SNBYTES_MLNOgNBYTES_MLOFFNOgNBYTES_MLOFFYESgSCITER_ELINKNO-iCITER_ELINKYES-iSBITER_ELINKNO-iBITER_ELINKYES-i* SADDRg#SOFF-i#ATTR-i#x#SLASTg# DADDRg#DOFF-i#x#DLAST_SGAg#CSR-i#'y#*(CRg#ES g#:RESERVED_0y#ERQg# :RESERVED_1z#EEIg#CEEIq#SEEIq#CERQq#SERQq#CDNEq#SSRTq#CERRq#CINTq#:RESERVED_2z# INTg#$:RESERVED_3z#(ERRg#,:RESERVED_4z#0HRS g#4: RESERVED_5{#8EARSg#D:RESERVED_6H{#HDCHPRI3q#DCHPRI2q#DCHPRI1q#DCHPRI0q#DCHPRI7q#DCHPRI6q#DCHPRI5q#DCHPRI4q#DCHPRI11q#DCHPRI10q#DCHPRI9q#DCHPRI8q#DCHPRI15q#DCHPRI14q#DCHPRI13q#DCHPRI12q#DCHPRI19q#DCHPRI18q#DCHPRI17q#DCHPRI16q#DCHPRI23q#DCHPRI22q#DCHPRI21q#DCHPRI20q#DCHPRI27q#DCHPRI26q#DCHPRI25q#DCHPRI24q#DCHPRI31q#DCHPRI30q#DCHPRI29q#DCHPRI28q#:RESERVED_7}}#qDCHMID}#:RESERVED_8}#RyTCD}# PDMA_Typey.*gCHCFG~#PDMAMUX_Type}:*(CTRL-i#FILT-i#WTR-i#POSD-i#POSDH/#REV-i# REVH/# UPOS-i#LPOS-i#UPOSH/#LPOSH/#UINIT-i#LINIT-i#IMR/#TST-i#CTRL2-i#UMOD-i# LMOD-i#"UCOMP-i#$LCOMP-i#&It)PENC_Type/~;*TCSRg#TCCRg#* :RESERVED_0h#EIRg#EIMRg#:RESERVED_1# RDARg#TDARg#: RESERVED_2#ECRg#$:RESERVED_3#(MMFRg#@MSCRg#D:RESERVED_42#HMIBCg#d:RESERVED_5\#hRCRg#:;RESERVED_6#TCRg#:RESERVED_7#PALRg#PAURg#OPDg#TXICg#: RESERVED_8#RXICg#:RESERVED_9/#IAURg#IALRg#GAURg#GALRg#:RESERVED_10#TFWRg#:7RESERVED_11#RDSRg#TDSRg#MRBRg#:RESERVED_12#RSFLg#RSEMg#RAEMg#RAFLg#TSEMg#TAEMg#TAFLg#TIPGg#FTRLg#: RESERVED_13#TACCg#RACCg#х:7RESERVED_14ł#RMON_T_DROPY#RMON_T_PACKETS g#RMON_T_BC_PKT g#RMON_T_MC_PKT g#RMON_T_CRC_ALIGN g#RMON_T_UNDERSIZE g#RMON_T_OVERSIZE g#RMON_T_FRAG g#RMON_T_JAB g#RMON_T_COL g#RMON_T_P64 g#RMON_T_P65TO127 g#RMON_T_P128TO255 g#RMON_T_P256TO511 g#RMON_T_P512TO1023 g#RMON_T_P1024TO2047 g#RMON_T_P_GTE2048 g#RMON_T_OCTETS g#IEEE_T_DROPY#IEEE_T_FRAME_OK g#IEEE_T_1COL g#IEEE_T_MCOL g#IEEE_T_DEF g#IEEE_T_LCOL g#IEEE_T_EXCOL g#IEEE_T_MACERR g#IEEE_T_CSERR g#IEEE_T_SQE g#IEEE_T_FDXFC g#IEEE_T_OCTETS_OK g#: RESERVED_15#RMON_R_PACKETS g#RMON_R_BC_PKT g#RMON_R_MC_PKT g#RMON_R_CRC_ALIGN g#RMON_R_UNDERSIZE g#RMON_R_OVERSIZE g#RMON_R_FRAG g#RMON_R_JAB g#RMON_R_RESVD_0Y#RMON_R_P64 g#RMON_R_P65TO127 g#RMON_R_P128TO255 g#RMON_R_P256TO511 g#RMON_R_P512TO1023 g#RMON_R_P1024TO2047 g#RMON_R_P_GTE2048 g#RMON_R_OCTETS g#IEEE_R_DROP g#IEEE_R_FRAME_OK g#IEEE_R_CRC g#IEEE_R_ALIGN g#IEEE_R_MACERR g#IEEE_R_FDXFC g#IEEE_R_OCTETS_OK g#ԏ:RESERVED_16LJ#ATCRg#ATVRg#ATOFFg#ATPERg#ATCORg#ATINCg#ATSTMP g#֐:RESERVED_17I#TGSRg# DCHANNELw# PENET_Typeb>*CTRLq#SERVq#CMPLq#CMPHq#CLKCTRLq#CLKPRESCALERq#PEWM_TypeF*VERID g#PARAM g#CTRLg#PIN g# SHIFTSTATg#SHIFTERRg#TIMSTATg#:RESERVED_0u#SHIFTSIENg# SHIFTEIENg#$TIMIENg#(ϓ:RESERVED_1É#,SHIFTSDENg#0: RESERVED_2#4SHIFTSTATEg#@:;RESERVED_3"#DʔgSHIFTCTL@#:oRESERVED_4[#gSHIFTCFGz#:RESERVED_5#gSHIFTBUF#ܕ:oRESERVED_6Њ#gSHIFTBUFBIS#:oRESERVED_7 #gSHIFTBUFBYS,#֖:oRESERVED_8J#gSHIFTBUFBBSi#:oRESERVED_9#gTIMCTL#˗:oRESERVED_10#gTIMCFGߋ# :oRESERVED_11# gTIMCMP# :RESERVED_121# ܘgSHIFTBUFNBSR# :oRESERVED_13p# gSHIFTBUFHWS#:oRESERVED_14#ؙgSHIFTBUFNISΌ#PFLEXIO_TypeG*TCM_CTRLg#OCRAM_MAGIC_ADDRg#DTCM_MAGIC_ADDRg#ITCM_MAGIC_ADDRg# INT_STATUSg#INT_STAT_ENg#INT_SIG_ENg#PFLEXRAM_TypeJ*MCR0g#MCR1g#MCR2g#AHBCRg# INTENg#INTRg#LUTKEYg#LUTCRg#gAHBRXBUFCR0# :/RESERVED_01#0ٜgFLSHCR0O#`gFLSHCR1h#pgFLSHCR2#:RESERVED_1#FLSHCR4g#֝:RESERVED_2ʎ#IPCR0g#IPCR1g#:RESERVED_3#IPCMDg#:RESERVED_42#IPRXFCRg#IPTXFCRg#gDLLCRq#:RESERVED_5#STS0 g#STS1 g#STS2 g#AHBSPNDSTS g#IPRXFSTS g#IPTXFSTS g#:RESERVED_6# gRFDR##ĠgTFDR:#۠g?LUTQ#PFLEXSPI_TypeK*<CNTRg#:RESERVED_0#gIMR#ˡ gISR#: RESERVED_1֐#(IMR5g#4ISR5 g#8PGPC_Type}P*ԣDRg#GDIRg#PSR g#ICR1g# ICR2g#IMRg#ISRg#EDGE_SELg#:cRESERVED_0# DR_SETg#DR_CLEARg#DR_TOGGLEg#PGPIO_TypeQ*ɤ(CRg#PRg#SRg#IRg# gOCR# gICR(#CNT g#$PGPT_TypeR*VERID g#PARAM g#TCSRg#TCR1g# TCR2g#TCR3g#TCR4g#TCR5g#̥gTDR’# :RESERVED_0ג#0 gTFR#@:RESERVED_1 #PTMRg#`:#RESERVED_23#dRCSRg#RCR1g#RCR2g#RCR3g#RCR4g#RCR5g# gRDR#:RESERVED_3#ާ gRFRԓ#:RESERVED_4#RMRg#PI2S_TypeZT* :RESERVED_0-#ըg\SW_MUX_CTL_PADK#g\SW_PAD_CTL_PADk#gqSELECT_INPUT#PIOMUXC_Type'X*hGPR0Y#GPR1g#GPR2g#GPR3g# GPR4g#GPR5g#GPR6g#GPR7g#GPR8g# GPR9Y#$GPR10g#(GPR11g#,GPR12g#0GPR13g#4GPR14g#8GPR15Y#<GPR16g#@GPR17g#DGPR18g#HGPR19g#LGPR20g#PGPR21g#TGPR22g#XGPR23g#\GPR24g#`GPR25g#dPIOMUXC_GPR_TypeY*Ю$SW_MUX_CTL_PAD_WAKEUPg#SW_MUX_CTL_PAD_PMIC_ON_REQg#SW_MUX_CTL_PAD_PMIC_STBY_REQg#SW_PAD_CTL_PAD_TEST_MODEg# SW_PAD_CTL_PAD_POR_Bg#SW_PAD_CTL_PAD_ONOFFg#SW_PAD_CTL_PAD_WAKEUPg#SW_PAD_CTL_PAD_PMIC_ON_REQg#SW_PAD_CTL_PAD_PMIC_STBY_REQg# PIOMUXC_SNVS_Type,_*GPR0Y#GPR1Y#GPR2Y#GPR3g# PIOMUXC_SNVS_GPR_Typeia*KPCR-i#KPSR-i#KDDR-i#KPDR-i#PKPP_Type—a*VERID g#PARAM g#:RESERVED_0)#MCRg#MSRg#MIERg#MDERg#MCFGR0g# MCFGR1g#$MCFGR2g#(MCFGR3g#,:RESERVED_1#0MDMRg#@:RESERVED_2ט#DMCCR0g#H:RESERVED_3#LMCCR1g#P:RESERVED_4-#TMFCRg#XMFSR g#\MTDRg#`: RESERVED_5o#dMRDR g#p:RESERVED_6#tSCRg#SSRg#SIERg#SDERg#:RESERVED_7#SCFGR1g#SCFGR2g#:RESERVED_8'#SAMRg#ߴ: RESERVED_9S#SASR g#STARg#:RESERVED_10#STDRg#ŵ: RESERVED_11#SRDR g#PLPI2C_Type b*ٸxVERID g#PARAM g#:RESERVED_0#CRg#SRg#IERg#DERg#CFGR0g# CFGR1g#$:RESERVED_1{#(DMR0g#0DMR1g#4:RESERVED_2#8CCRg#@:RESERVED_3ڛ#DFCRg#XFSR g#\TCRg#`TDRg#d:RESERVED_4$#hRSR g#pRDR g#tPLPSPI_Typeg*0VERID g#PARAM g#GLOBALg#PINCFGg# BAUDg#STATg#CTRLg#DATAg#MATCHg# MODIRg#$FIFOg#(WATERg#,PLPUART_Typeli* CTRLg#CTRL_SETg#CTRL_CLRg#CTRL_TOGg# TIMINGg#: RESERVED_0o#DATAg# : RESERVED_1#$READ_CTRLg#0Ի: RESERVED_2ȝ#4READ_FUSE_DATAg#@: RESERVED_3#DSW_STICKYg#P: RESERVED_4+#TSCSg#`SCS_SETg#dSCS_CLRg#hSCS_TOGg#l:RESERVED_5#pVERSION g#:kRESERVED_6#TIMING2g#:RESERVED_7ޞ#LOCKg#: RESERVED_8 #CFG0g#þ: RESERVED_97#CFG1g#: RESERVED_10c#CFG2g#: RESERVED_11#CFG3g#ɿ: RESERVED_12#CFG4g#: RESERVED_13#CFG5g#: RESERVED_14#CFG6g#: RESERVED_15D#MEM0g# : RESERVED_16q# MEM1g# : RESERVED_17# MEM2g# : RESERVED_18ˠ# MEM3g# : RESERVED_19# MEM4g# : RESERVED_20%# ANA0g# : RESERVED_21R# ANA1g# : RESERVED_22# ANA2g# :RESERVED_23# SRK0g# : RESERVED_24ڡ# SRK1g# : RESERVED_25# SRK2g# : RESERVED_264# SRK3g# : RESERVED_27a# SRK4g# : RESERVED_28# SRK5g# : RESERVED_29# SRK6g# : RESERVED_30# SRK7g# : RESERVED_31# SJC_RESP0g# : RESERVED_32G# SJC_RESP1g# : RESERVED_33y# MAC0g# : RESERVED_34# MAC1g# : RESERVED_35ӣ# GP3g# :RESERVED_36# GP1g# : RESERVED_37+# GP2g# : RESERVED_38W# SW_GP1g# : RESERVED_39# SW_GP20g# : RESERVED_40# SW_GP21g# : RESERVED_41# SW_GP22g# : RESERVED_42# SW_GP23g# : RESERVED_43F# MISC_CONF0g# : RESERVED_44y# MISC_CONF1g# : RESERVED_45# SRK_REVOKEg# POCOTP_Typen*:RESERVED_0#MEGA_CTRLg#MEGA_PUPSCRg#MEGA_PDNSCRg#MEGA_SRg#:oRESERVED_1b#CPU_CTRLg#CPU_PUPSCRg#CPU_PDNSCRg#CPU_SRg#PPGC_Typer*LDVALg#CVAL g#TCTRLg#TFLGg# *MCRg#:RESERVED_0"#LTMR64H g#LTMR64L g#:RESERVED_1a#٦CHANNEL#PPIT_Types*:RESERVED_0#REG_1P1g#REG_1P1_SETg#REG_1P1_CLRg#REG_1P1_TOGg#REG_3P0g#REG_3P0_SETg#REG_3P0_CLRg#REG_3P0_TOGg#REG_2P5g#REG_2P5_SETg#REG_2P5_CLRg#REG_2P5_TOGg#REG_COREg#REG_CORE_SETg#REG_CORE_CLRg#REG_CORE_TOGg#MISC0g#MISC0_SETg#MISC0_CLRg#MISC0_TOGg#MISC1g#MISC1_SETg#MISC1_CLRg#MISC1_TOGg#MISC2g#MISC2_SETg#MISC2_CLRg#MISC2_TOGg#PPMU_Typet*`CNT/#INIT-i#CTRL2-i#CTRL-i#:RESERVED_0#VAL0-i# FRACVAL1-i# VAL1-i#FRACVAL2-i#VAL2-i#FRACVAL3-i#VAL3-i#FRACVAL4-i#VAL4-i#FRACVAL5-i#VAL5-i#FRCTRL-i# OCTRL-i#"STS-i#$INTEN-i#&DMAEN-i#(TCTRL-i#*-iDISMAP#,DTCNT0-i#0DTCNT1-i#2CAPTCTRLA-i#4CAPTCOMPA-i#6CAPTCTRLB-i#8CAPTCOMPB-i#:CAPTCTRLX-i#<CAPTCOMPX-i#>CVAL0/#@CVAL0CYC/#BCVAL1/#DCVAL1CYC/#FCVAL2/#HCVAL2CYC/#JCVAL3/#LCVAL3CYC/#NCVAL4/#PCVAL4CYC/#RCVAL5/#TCVAL5CYC/#V:RESERVED_1c#X*SM#OUTEN-i#MASK-i#SWCOUT-i#DTSRCSEL-i#MCTRL-i#MCTRL2-i#FCTRL-i#FSTS-i#FFILT-i#FTST-i#FCTRL2-i#PPWM_Type}*:RESERVED_0Q#gROMPATCHDp#ROMPATCHCNTLg#ROMPATCHENHY#ROMPATCHENLg#gROMPATCHA˭#:RESERVED_1#ROMPATCHSRg#PROMC_TypeK*CSg#CNTg#TOVALg#WINg# PRTWDOG_Type.*MCRg#IOCRg#BMCR0g#BMCR1g# gBR#:RESERVED_0#4INTENg#8INTRg#<SDRAMCR0g#@SDRAMCR1g#DSDRAMCR2g#HSDRAMCR3g#LNANDCR0g#PNANDCR1g#TNANDCR2g#XNANDCR3g#\NORCR0g#`NORCR1g#dNORCR2g#hNORCR3Y#lSRAMCR0g#pSRAMCR1g#tSRAMCR2g#xSRAMCR3Y#|DBICR0g#DBICR1g#:RESERVED_1 #IPCR0g#IPCR1g#IPCR2g#IPCMDg#IPTXDATg#: RESERVED_2q#IPRXDAT g#: RESERVED_3#STS0 g#STS1Y#STS2 g#STS3Y#STS4Y#STS5Y#STS6Y#STS7Y#STS8Y#STS9Y#STS10Y#STS11Y#STS12 g#STS13Y#STS14Y#STS15Y#PSEMC_Typev*HPLRg#HPCOMRg#HPCRg#HPSICRg# HPSVCRg#HPSRg#HPSVSRg#HPHACIVRg#HPHACR g# HPRTCMRg#$HPRTCLRg#(HPTAMRg#,HPTALRg#0LPLRg#4LPCRg#8LPMKCRg#<LPSVCRg#@:RESERVED_0#DLPTDCRg#HLPSRg#LLPSRTCMRg#PLPSRTCLRg#TLPTARg#XLPSMCMR g#\LPSMCLR g#`LPPGDRg#dLPGPR0_LEGACY_ALIASg#hgLPZMKR]#l:RESERVED_1u#gLPGPR_ALIAS#:_RESERVED_2#gLPGPRѳ#:RESERVED_3#HPVIDR1 g#HPVIDR2 g#PSNVS_TypeñSSICgSIS g*TSCRg#SRCDg#SRPCg#SIEg# =#SRL g#SRR g#SRCSH g#SRCSL g# SRU g#$SRQ g#(STLg#,STRg#0STCSCHg#4STCSCLg#8:RESERVED_0#<SRFM g#D:RESERVED_10#HSTCg#PPSPDIF_TypeS*HSCRg#SBMR1 g#SRSRg#:RESERVED_0# SBMR2 g#g GPRµ# PSRC_Typen*:RESERVED_0#TEMPSENSE0g#TEMPSENSE0_SETg#TEMPSENSE0_CLRg#TEMPSENSE0_TOGg#TEMPSENSE1g#TEMPSENSE1_SETg#TEMPSENSE1_CLRg#TEMPSENSE1_TOGg#:RESERVED_1#TEMPSENSE2g#TEMPSENSE2_SETg#TEMPSENSE2_CLRg#TEMPSENSE2_TOGg#PTEMPMON_Typeו* COMP1-i#COMP2-i#CAPT-i#LOAD-i#HOLD-i#CNTR-i# CTRL-i# SCTRL-i#CMPLD1-i#CMPLD2-i#CSCTRL-i#FILT-i#DMA-i#:RESERVED_0#ENBL-i#*NCHANNEL(#PTMR_Type"SPKRMAXgPKRSQ gSSBLIMgTOTSAM gSFRQCNT gFRQMAXgSSCMC gSCMLgSSCR1C gSCR1LgSSCR2C gSCR2LgSSCR3C gSCR3LgSSCR4C gSCR4LgSSCR5C gSCR5LgSSCR6PC gSCR6PLg*MCTLg#SCMISCg#PKRRNGg#T# SDCTLg#o#FRQMINg### #$ظ#(#, #0&#4@#8STATUS g#< gENT#@PKRCNT10 g#PKRCNT32 g#PKRCNT54 g#PKRCNT76 g#PKRCNT98 g#PKRCNTBA g#PKRCNTDC g#PKRCNTFE g#SEC_CFGg#INT_CTRLg#INT_MASKg#INT_STATUS g#:?RESERVED_0#VID1 g#VID2 g#PTRNG_Type\SDEVICEADDRgPERIODICLISTBASEgSASYNCLISTADDRgENDPTLISTADDRg*ID g#HWGENERAL g#HWHOST g#HWDEVICE g# HWTXBUF g#HWRXBUF g#:gRESERVED_0#GPTIMER0LDg#GPTIMER0CTRLg#GPTIMER1LDg#GPTIMER1CTRLg#SBUSCFGg#:kRESERVED_1a#CAPLENGTH]#:RESERVED_2#HCIVERSION/#HCSPARAMS g#HCCPARAMS g#:RESERVED_3#DCIVERSION/#:RESERVED_4#DCCPARAMS g#:RESERVED_5K#USBCMDg#USBSTSg#USBINTRg#FRINDEXg#:RESERVED_6#2#\#:RESERVED_7ٽ#BURSTSIZEg#TXFILLTUNINGg#:RESERVED_8#ENDPTNAKg#ENDPTNAKENg#CONFIGFLAG g#PORTSC1g#:RESERVED_9#OTGSCg#USBMODEg#ENDPTSETUPSTATg#ENDPTPRIMEg#ENDPTFLUSHg#ENDPTSTAT g#ENDPTCOMPLETEg#ENDPTCTRL0g#gENDPTCTRL:#:tWPUSB_TypeҞ*:RESERVED_0y#USB_OTGn_CTRLg#:RESERVED_1#USB_OTGn_PHY_CTRL_0g#PUSBNC_Types*ՃPWDg#PWD_SETg#PWD_CLRg#PWD_TOGg# TXg#TX_SETg#TX_CLRg#TX_TOGg#RXg# RX_SETg#$RX_CLRg#(RX_TOGg#,CTRLg#0CTRL_SETg#4CTRL_CLRg#8CTRL_TOGg#<STATUSg#@: RESERVED_0#DDEBUGrg#PDEBUG_SETg#TDEBUG_CLRg#XDEBUG_TOGg#\DEBUG0_STATUS g#`: RESERVED_1b#dDEBUG1g#pDEBUG1_SETg#tDEBUG1_CLRg#xDEBUG1_TOGg#|VERSION g#PUSBPHY_Type*Ȇ`VBUS_DETECTg#VBUS_DETECT_SETg#VBUS_DETECT_CLRg#VBUS_DETECT_TOGg# CHRG_DETECTg#CHRG_DETECT_SETg#CHRG_DETECT_CLRg#CHRG_DETECT_TOGg#VBUS_DETECT_STAT g# Å: RESERVED_0#$CHRG_DETECT_STAT g#0:RESERVED_1#4MISCg#PMISC_SETg#TMISC_CLRg#XMISC_TOGg#\*ۆ:RESERVED_0N#INSTANCEm#DIGPROG g#PUSB_ANALOG_TypeH˲*DS_ADDRg#BLK_ATTg#CMD_ARGg#CMD_XFR_TYPg# CMD_RSP0 g#CMD_RSP1 g#CMD_RSP2 g#CMD_RSP3 g#DATA_BUFF_ACC_PORTg# PRES_STATE g#$PROT_CTRLg#(SYS_CTRLg#,INT_STATUSg#0INT_STATUS_ENg#4INT_SIGNAL_ENg#8AUTOCMD12_ERR_STATUSg#<HOST_CTRL_CAPg#@WTMK_LVLg#DMIX_CTRLg#H:RESERVED_0#LFORCE_EVENTg#PADMA_ERR_STATUS g#TADMA_SYS_ADDRg#X:RESERVED_1o#\DLL_CTRLg#`DLL_STATUS g#dCLK_TUNE_CTRL_STATUSg#h׋:SRESERVED_2#lVEND_SPECg#MMC_BOOTg#VEND_SPEC2g#TUNING_CTRLg#PUSDHC_Type* WCR-i#WSR-i#WRSR/#WICR-i#WMCR-i#PWDOG_TypeH*SEL0-i#SEL1-i#SEL2-i#SEL3-i#SEL4-i#SEL5-i# SEL6-i# SEL7-i#SEL8-i#SEL9-i#SEL10-i#SEL11-i#SEL12-i#SEL13-i#SEL14-i#SEL15-i#SEL16-i# SEL17-i#"SEL18-i#$SEL19-i#&SEL20-i#(SEL21-i#*SEL22-i#,SEL23-i#.SEL24-i#0SEL25-i#2SEL26-i#4SEL27-i#6SEL28-i#8SEL29-i#:SEL30-i#<SEL31-i#>SEL32-i#@SEL33-i#BSEL34-i#DSEL35-i#FSEL36-i#HSEL37-i#JSEL38-i#LSEL39-i#NSEL40-i#PSEL41-i#RSEL42-i#TSEL43-i#VSEL44-i#XSEL45-i#ZSEL46-i#\SEL47-i#^SEL48-i#`SEL49-i#bSEL50-i#dSEL51-i#fSEL52-i#hSEL53-i#jSEL54-i#lSEL55-i#nSEL56-i#pSEL57-i#rSEL58-i#tSEL59-i#vSEL60-i#xSEL61-i#zSEL62-i#|SEL63-i#~SEL64-i#SEL65-i#CTRL0-i#CTRL1-i#PXBARA_Type*SEL0-i#SEL1-i#SEL2-i#SEL3-i#SEL4-i#SEL5-i# SEL6-i# SEL7-i#PXBARB_Type$*:RESERVED_0#MISC0g#MISC0_SETg#MISC0_CLRg#MISC0_TOGg#:RESERVED_1#LOWPWR_CTRLg#LOWPWR_CTRL_SETg#LOWPWR_CTRL_CLRg#LOWPWR_CTRL_TOGg#:RESERVED_2#OSC_CONFIG0g#OSC_CONFIG0_SETg#OSC_CONFIG0_CLRg#OSC_CONFIG0_TOGg#OSC_CONFIG1g#OSC_CONFIG1_SETg#OSC_CONFIG1_CLRg#OSC_CONFIG1_TOGg#OSC_CONFIG2g#OSC_CONFIG2_SETg#OSC_CONFIG2_CLRg#OSC_CONFIG2_TOGg#PXTALOSC24M_Type .\devices\MIMXRT1021\drivers\fsl_common.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashC= _status_groupskStatusGroup_Generic kStatusGroup_FLASH kStatusGroup_LPSPI kStatusGroup_FLEXIO_SPI kStatusGroup_DSPI kStatusGroup_FLEXIO_UART kStatusGroup_FLEXIO_I2C kStatusGroup_LPI2C kStatusGroup_UART kStatusGroup_I2C kStatusGroup_LPSCI kStatusGroup_LPUART kStatusGroup_SPI kStatusGroup_XRDC kStatusGroup_SEMA42 kStatusGroup_SDHC kStatusGroup_SDMMC kStatusGroup_SAI kStatusGroup_MCG kStatusGroup_SCG kStatusGroup_SDSPI kStatusGroup_FLEXIO_I2S kStatusGroup_FLEXIO_MCULCD kStatusGroup_FLASHIAP kStatusGroup_FLEXCOMM_I2C kStatusGroup_I2S kStatusGroup_IUART kStatusGroup_CSI kStatusGroup_MIPI_DSI kStatusGroup_SDRAMC #kStatusGroup_POWER 'kStatusGroup_ENET (kStatusGroup_PHY )kStatusGroup_TRGMUX *kStatusGroup_SMARTCARD +kStatusGroup_LMEM ,kStatusGroup_QSPI -kStatusGroup_DMA 2kStatusGroup_EDMA 3kStatusGroup_DMAMGR 4kStatusGroup_FLEXCAN 5kStatusGroup_LTC 6kStatusGroup_FLEXIO_CAMERA 7kStatusGroup_LPC_SPI 8kStatusGroup_LPC_USART 9kStatusGroup_DMIC :kStatusGroup_SDIF ;kStatusGroup_SPIFI <kStatusGroup_OTP =kStatusGroup_MCAN >kStatusGroup_CAAM ?kStatusGroup_ECSPI @kStatusGroup_USDHC AkStatusGroup_LPC_I2C BkStatusGroup_DCP CkStatusGroup_MSCAN DkStatusGroup_ESAI EkStatusGroup_FLEXSPI FkStatusGroup_MMDC GkStatusGroup_MICFIL HkStatusGroup_SDMA IkStatusGroup_ICS JkStatusGroup_SPDIF KkStatusGroup_NOTIFIER bkStatusGroup_DebugConsole ckStatusGroup_SEMC dkStatusGroup_ApplicationRangeStart e_generic_statuskStatus_Success kStatus_Fail kStatus_ReadOnly kStatus_OutOfRange kStatus_InvalidArgument kStatus_Timeout kStatus_NoTransferInProgress Pstatus_t ; EnableIRQ$Ainterrupta__result; DisableIRQ$Ainterrupta__result; DisableGlobalIRQYa__resultY\regPrimaskY< EnableGlobalIRQ$Yprimaskx middleware\flexspi\fsl_flexspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flasht_Bool"YPflexspi_serial_clk_freq_tnPflexspi_read_sample_clk_tPflexspi_ipcmd_error_tPflexspi_lut_seq_tPflexspi_dll_time_t Pflexspi_mem_config_t Pflexspi_operation_t"Pflexspi_xfer_tkFlexSpiClock_CoreClock kFlexSpiClock_AhbClock kFlexSpiClock_SerialRootClock kFlexSpiClock_IpgClock Pflexspi_clock_type_t_FlexSpiSerialClockFreqkFlexSpiSerialClk_30MHz kFlexSpiSerialClk_50MHz kFlexSpiSerialClk_60MHz kFlexSpiSerialClk_75MHz kFlexSpiSerialClk_80MHz kFlexSpiSerialClk_100MHz kFlexSpiSerialClk_133MHz kFlexSpiSerialClk_166MHz kFlexSpiSerialClk_200MHz kFlexSpiClk_SDR kFlexSpiClk_DDR  _FlashReadSampleClkSourcekFlexSPIReadSampleClk_LoopbackInternally kFlexSPIReadSampleClk_LoopbackFromDqsPad kFlexSPIReadSampleClk_LoopbackFromSckPad kFlexSPIReadSampleClk_ExternalInputFromDqsPad  _FlexSpiIpCmdErrorkFlexSpiIpCmdError_NoError kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode kFlexSpiIpCmdError_JumpOnCsInIpCmd kFlexSpiIpCmdError_UnknownOpCode kFlexSpiIpCmdError_SdrDummyInDdrSequence kFlexSpiIpCmdError_DDRDummyInSdrSequence kFlexSpiIpCmdError_InvalidAddress kFlexSpiIpCmdError_SequenceExecutionTimeout kFlexSpiIpCmdError_FlashBoundaryAcrosss  _flexspi_statuskStatus_FLEXSPI_SequenceExecutionTimeoutXkStatus_FLEXSPI_InvalidSequenceYkStatus_FLEXSPI_DeviceTimeoutZkFlexSpiMiscOffset_DiffClkEnable kFlexSpiMiscOffset_Ck2Enable kFlexSpiMiscOffset_ParallelEnable kFlexSpiMiscOffset_WordAddressableEnable kFlexSpiMiscOffset_SafeConfigFreqEnable kFlexSpiMiscOffset_PadSettingOverrideEnable kFlexSpiMiscOffset_DdrModeEnable kFlexSpiMiscOffset_UseValidTimeForAllFreq kFlexSpiDeviceType_SerialNOR kFlexSpiDeviceType_SerialNAND kFlexSpiDeviceType_SerialRAM kFlexSpiDeviceType_MCP_NOR_NAND kFlexSpiDeviceType_MCP_NOR_RAM kSerialFlash_1Pad kSerialFlash_2Pads kSerialFlash_4Pads kSerialFlash_8Pads )_lut_sequenceseqNum:#seqId:#reservedI#kDeviceConfigCmdType_Generic kDeviceConfigCmdType_QuadEnable kDeviceConfigCmdType_Spi2Xpi kDeviceConfigCmdType_Xpi2Spi kDeviceConfigCmdType_Spi2NoCmd kDeviceConfigCmdType_Reset *time_100ps:#delay_cells:#)_FlexSPIConfigtagY#versionY#reserved0Y#readSampleClkSrc:# dataHoldTime:# dataSetupTime:#columnAddressWidth:#deviceModeCfgEnable:#deviceModeType:#waitTimeCfgCommandsI#deviceModeSeqW#deviceModeArgY#configCmdEnable:#:configModeType\ #WconfigCmdSeqs} # reserved1Y#,YconfigCmdArgs #0reserved2Y#<controllerMiscOptionY#@deviceType:#DsflashPadType:#EserialClkFreq:#FlutCustomSeqEnable:#GYreserved3] #HsflashA1SizeY#PsflashA2SizeY#TsflashB1SizeY#XsflashB2SizeY#\csPadSettingOverrideY#`sclkPadSettingOverrideY#ddataPadSettingOverrideY#hdqsPadSettingOverrideY#ltimeoutInMsY#pcommandIntervalY#tqdataValidTime| #xbusyOffsetI#|busyBitPolarityI#~Y?lookupTable #W lutCustomSeq #Yreserved4#_FlexSPIOperationTypekFlexSpiOperation_Command kFlexSpiOperation_Config kFlexSpiOperation_Write kFlexSpiOperation_Read kFlexSpiOperation_End )_FlexSpiXfer$operation#baseAddressY#seqIdY#seqNumY# isParallelModeEnable#txBuffer#txSizeY#rxBuffer#rxSizeY#  middleware\flexspi_nor\flexspi_nor_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash_flexspi_nor_statuskStatusGroup_FLEXSPINOR kStatus_FLEXSPINOR_ProgramFail NkStatus_FLEXSPINOR_EraseSectorFail!NkStatus_FLEXSPINOR_EraseAllFail"NkStatus_FLEXSPINOR_WaitTimeout#NkStatus_FlexSPINOR_NotSupported$NkStatus_FlexSPINOR_WriteAlignmentError%NkStatus_FlexSPINOR_CommandFailure&NkStatus_FlexSPINOR_SFDP_NotFound'NkStatus_FLEXSPINOR_Unsupported_SFDP_Version(NkStatus_FLEXSPINOR_Flash_NotFound)NkStatus_FLEXSPINOR_DTRRead_DummyProbeFailed*N kSerialNorCfgOption_Tag kSerialNorCfgOption_DeviceType_ReadSFDP_SDR kSerialNorCfgOption_DeviceType_ReadSFDP_DDR kSerialNorCfgOption_DeviceType_HyperFLASH1V8 kSerialNorCfgOption_DeviceType_HyperFLASH3V0 kSerialNorCfgOption_DeviceType_MacronixOctalDDR kSerialNorCfgOption_DeviceType_MacronixOctalSDR kSerialNorCfgOption_DeviceType_MicronOctalDDR kSerialNorCfgOption_DeviceType_MicronOctalSDR kSerialNorCfgOption_DeviceType_AdestoOctalDDR kSerialNorCfgOption_DeviceType_AdestoOctalSDR  kSerialNorQuadMode_NotConfig kSerialNorQuadMode_StatusReg1_Bit6 kSerialNorQuadMode_StatusReg2_Bit1 kSerialNorQuadMode_StatusReg2_Bit7 kSerialNorQuadMode_StatusReg2_Bit1_0x31  kSerialNorEnhanceMode_Disabled kSerialNorEnhanceMode_0_4_4_Mode kSerialNorEnhanceMode_0_8_8_Mode kSerialNorEnhanceMode_DataOrderSwapped kSerialNorEnhanceMode_2ndPinMux *!max_freqY#!misc_modeY#!quad_mode_settingY#!cmd_padsY#!query_padsY# !device_typeY#!option_sizeY#!tagY#SB[UY*!dummy_cyclesY#!status_overrideY#!reservedY#SB(UY)_serial_nor_config_optionoption0#option1w#Pserial_nor_config_option_t*por_mode:#current_mode:#exit_no_cmd_sequence:#restore_sequence:#SBUYPflash_run_context_tOkRestoreSequence_None kRestoreSequence_HW_Reset kRestoreSequence_4QPI_FF kRestoreSequence_5QPI_FF kRestoreSequence_8QPI_FF kRestoreSequence_Send_F0 kRestoreSequence_Send_66_99 kRestoreSequence_Send_6699_9966 kRestoreSequence_Send_06_FF kFlashInstMode_ExtendedSpi kFlashInstMode_0_4_4_SDR kFlashInstMode_0_4_4_DDR kFlashInstMode_QPI_SDR AkFlashInstMode_QPI_DDR BkFlashInstMode_OPI_SDR kFlashInstMode_OPI_DDR )_flexspi_nor_configmemConfign#pageSizeY#sectorSizeY#ipcmdSerialClkFreq:#isUniformBlockSize:#isDataOrderSwapped:#:reserved0 #serialNorType:#needExitNoCmdMode:#halfClkForNonReadCmd:#needRestoreNoCmdMode:#blockSizeY#Y reserve2 #Pflexspi_nor_config_tM \ devices\MIMXRT1021\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash-5_BoolPclock_name_tPclock_ip_name_t Pclock_osc_tPclock_gate_value_t Pclock_mode_tsPclock_mux_tPclock_div_tPclock_arm_pll_config_tPclock_usb_pll_config_tKPclock_sys_pll_config_t{Pclock_audio_pll_config_tPclock_video_pll_config_tBPclock_enet_pll_config_t_clock_pllkCLOCK_PllSys 0kCLOCK_PllUsb1 kCLOCK_PllAudio pkCLOCK_PllEnet_Enet0 kCLOCK_PllEnet_Enet1kCLOCK_PllEnet_25MkCLOCK_PllEnetPclock_pll_tM_clock_pfdkCLOCK_Pfd0 kCLOCK_Pfd1 kCLOCK_Pfd2 kCLOCK_Pfd3 Pclock_pfd_t_clock_usb_srckCLOCK_Usb480M kCLOCK_UsbSrcUnusedPclock_usb_src_tt_clock_usb_phy_srckCLOCK_Usbphy480M Pclock_usb_phy_src_t<CLOCK_SetMux$fmux$Yvalue\busyShiftY; CLOCK_GetMuxY$fmuxa__resultY< CLOCK_SetDiv$zdivider$Yvalue\busyShiftY; CLOCK_GetDivY$zdividera__resultY< CLOCK_ControlGate$ name$6value\indexY\shiftY\regKtY"E< CLOCK_EnableClock$ name< CLOCK_DisableClock$ name< CLOCK_SetMode$Qmode< CLOCK_SetPllBypass$base$pll$bypass"t< CLOCK_SetPllBypassRefClkSrc$base$pll$Ysrc; CLOCK_GetCpuClkFreqYa__resultY< CLOCK_SetXtalFreq$Yfreq< CLOCK_SetRtcXtalFreq$Yfreq8 CLOCK_IsPllBypassed$base$plla__result8CLOCK_IsPllEnabled$base$plla__result8CLOCK_GetOscFreqYa__resultY8CLOCK_GetPllBypassRefClkY$base$plla__resultY8CLOCK_GetRtcFreqYa__resultY_clock_namekCLOCK_CpuClk kCLOCK_AhbClk kCLOCK_SemcClk kCLOCK_IpgClk kCLOCK_OscClk kCLOCK_RtcClk kCLOCK_ArmPllClk kCLOCK_Usb1PllClk kCLOCK_Usb1PllPfd0Clk kCLOCK_Usb1PllPfd1Clk kCLOCK_Usb1PllPfd2Clk kCLOCK_Usb1PllPfd3Clk kCLOCK_Usb2PllClk kCLOCK_SysPllClk kCLOCK_SysPllPfd0Clk kCLOCK_SysPllPfd1Clk kCLOCK_SysPllPfd2Clk kCLOCK_SysPllPfd3Clk kCLOCK_EnetPllEnet0Clk kCLOCK_EnetPllEnet1Clk kCLOCK_EnetPll25MClk kCLOCK_EnetPllClk kCLOCK_AudioPllClk _clock_ip_namekCLOCK_IpInvalidkCLOCK_Aips_tz1kCLOCK_Aips_tz2kCLOCK_MqskCLOCK_Sim_m_clk_rkCLOCK_Dcp kCLOCK_Lpuart3 kCLOCK_Can1kCLOCK_Can1SkCLOCK_Can2kCLOCK_Can2SkCLOCK_TracekCLOCK_Gpt2kCLOCK_Gpt2SkCLOCK_Lpuart2kCLOCK_Gpio2kCLOCK_Lpspi1kCLOCK_Lpspi2kCLOCK_Lpspi3kCLOCK_Lpspi4kCLOCK_Adc2kCLOCK_EnetkCLOCK_PitkCLOCK_Adc1kCLOCK_Gpt1kCLOCK_Gpt1SkCLOCK_Lpuart4kCLOCK_Gpio1kCLOCK_CsukCLOCK_Gpio5kCLOCK_IomuxcSnvskCLOCK_Lpi2c1kCLOCK_Lpi2c2kCLOCK_Lpi2c3kCLOCK_OcotpkCLOCK_Xbar1kCLOCK_Xbar2kCLOCK_Gpio3kCLOCK_Lpuart5kCLOCK_SemckCLOCK_Lpuart6kCLOCK_Aoi1kCLOCK_Ewm0kCLOCK_Wdog1kCLOCK_FlexRamkCLOCK_Acmp1kCLOCK_Acmp2kCLOCK_Acmp3kCLOCK_Acmp4kCLOCK_IomuxcSnvsGprkCLOCK_Sim_m7_clk_rkCLOCK_IomuxckCLOCK_IomuxcGprkCLOCK_BeekCLOCK_SimM7kCLOCK_TsckCLOCK_SimMkCLOCK_SimEmskCLOCK_Pwm1kCLOCK_Pwm2kCLOCK_Enc1kCLOCK_Enc2kCLOCK_Rom kCLOCK_Flexio1 kCLOCK_Wdog3 kCLOCK_Dma kCLOCK_Kpp kCLOCK_Wdog2 kCLOCK_Aips_tz4 kCLOCK_Spdif kCLOCK_Sai1 kCLOCK_Sai2 kCLOCK_Sai3 kCLOCK_Lpuart1 kCLOCK_Lpuart7 kCLOCK_SnvsHp kCLOCK_SnvsLp kCLOCK_UsbOh3 kCLOCK_Usdhc1 kCLOCK_Usdhc2 kCLOCK_Dcdc kCLOCK_Ipmux4 kCLOCK_FlexSpi kCLOCK_Trng kCLOCK_Lpuart8 kCLOCK_Timer4 kCLOCK_Aips_tz3 kCLOCK_SimPer kCLOCK_Anadig kCLOCK_Lpi2c4 kCLOCK_Timer1 kCLOCK_Timer2  _clock_osckCLOCK_RcOsc kCLOCK_XtalOsc  _clock_gate_valuekCLOCK_ClockNotNeeded kCLOCK_ClockNeededRun kCLOCK_ClockNeededRunWait !_clock_mode_tkCLOCK_ModeRun kCLOCK_ModeWait kCLOCK_ModeStop %_clock_muxkCLOCK_Pll3SwMux kCLOCK_PeriphMux9kCLOCK_SemcAltMux'kCLOCK_SemcMux&kCLOCK_PrePeriphMuxrkCLOCK_TraceMuxnkCLOCK_PeriphClk2MuxlkCLOCK_LpspiMuxdkCLOCK_FlexspiMux}kCLOCK_Usdhc2Mux1kCLOCK_Usdhc1Mux0kCLOCK_Sai3MuxnkCLOCK_Sai2MuxlkCLOCK_Sai1MuxjkCLOCK_PerclkMux&kCLOCK_Flexio1Mux skCLOCK_CanMux hkCLOCK_UartMux$&kCLOCK_SpdifMux0tkCLOCK_Lpi2cMux82)_clock_divkCLOCK_ArmDiv@kCLOCK_PeriphClk2DivkCLOCK_SemcDivkCLOCK_AhbDivkCLOCK_IpgDivhkCLOCK_LpspiDivkCLOCK_FlexspiDivkCLOCK_PerclkDivkCLOCK_CanDiv kCLOCK_TraceDiv$ykCLOCK_Usdhc2Div$kCLOCK_Usdhc1Div$kCLOCK_UartDiv$kCLOCK_Flexio1Div(kCLOCK_Sai3PreDiv(kCLOCK_Sai3Div(kCLOCK_Flexio1PreDiv(kCLOCK_Sai1PreDiv(kCLOCK_Sai1Div(kCLOCK_Sai2PreDiv,kCLOCK_Sai2Div,kCLOCK_Spdif0PreDiv0kCLOCK_Spdif0Div0kCLOCK_Lpi2cDiv8*_clock_pll_bypass_clk_srckCLOCK_PllBypassClkSrc24M kCLOCK_PllBypassClkSrcClkPN )*_clock_arm_pll_configloopDividerY#)*_clock_usb_pll_configloopDivider:#)+_clock_sys_pll_config loopDivider:#numeratorY#denominatorY#),_clock_audio_pll_config loopDivider:#postDivider:#numeratorY#denominatorY#)-_clock_video_pll_config loopDivider:#postDivider:#numeratorY#denominatorY#)._clock_enet_pll_configenableClkOutput0#enableClkOutput1#enableClkOutput25M#enableClkOutput500M#loopDivider0:#loopDivider1:# FlashOS.HComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash!?unsigned longunsigned shortcharunsigned char)FlashDevice!Vers#DevName(#DevType#DevAdr#szDev#szPage#Res#valEmpty#toProg#toErase#sectors#)FlashSectorsszSector#AddrSector# .\CMSIS\Include\core_cm7.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flashx|*!_reserved0Y#!GEY# !_reserved1Y#!QY#!VY#!CY#!ZY#!NY#SbwYPAPSR_Typeh*!ISRY# !_reserved0Y#SbwYPIPSR_Type*!ISRY# !_reserved0Y#!ICI_IT_1Y#!GEY# !_reserved1Y#!TY#!ICI_IT_2Y#!QY#!VY#!CY#!ZY#!NY#SbwYPxPSR_Type*!nPRIVY#!SPSELY#!FPCAY#!_reserved0Y#SbwYPCONTROL_Type$* ISERQ#YRESERVED0f# ICER#YRSERVED1#ISPR#YRESERVED2#ICPR#YRESERVED3#IABR#Y7RESERVED40#IPM#YRESERVED5b#STIR#tYt:PNVIC_TypeL*CPUID#ICSR#VTOR#AIRCR# SCR#CCR#  SHPR#SHCSR#$CFSR#(HFSR#,DFSR#0MMFAR#4BFAR#8AFSR#< ID_PFRd#@ID_DFR#HID_AFR#L ID_MFR#P ID_ISAR#` YRESERVED0#tCLIDR#xCTR#|CCSIDR#CSSELR#CPACR# Y\RESERVED3&#STIR# YRESERVED4P#MVFR0#MVFR1#MVFR2# YRESERVED5#ICIALLU# YRESERVED6#ICIMVAU#DCIMVAC#DCISW#DCCMVAU#DCCMVAC#DCCSW#DCCIMVAC#DCCISW#YRESERVED7]#ITCMCR#DTCMCR#AHBPCR#CACR#AHBSCR#YRESERVED8#ABFSR#YtPSCB_Type* YRESERVED0#ICTR#ACTLR#PSCnSCB_Type *CTRL#LOAD#VAL#CALIB# PSysTick_TypeXSu8u16u32tI*  PORT#YRESERVED0#TER#YRESERVED1 #TPR#YRESERVED21 #TCR#YRESERVED3Z #IWR#IRR#IMCR#Y*RESERVED4 #LAR#LSR#YRESERVED5 #PID4#PID5#PID6#PID7#PID0#PID1#PID2#PID3#CID0#CID1#CID2#CID3#tPITM_Type*CTRL#CYCCNT#CPICNT#EXCCNT# SLEEPCNT#LSUCNT#FOLDCNT#PCSR#COMP0# MASK0#$FUNCTION0#(YRESERVED0? #,COMP1#0MASK1#4FUNCTION1#8YRESERVED1 #<COMP2#@MASK2#DFUNCTION2#HYRESERVED2 #LCOMP3#PMASK3#TFUNCTION3#XYRESERVED3 #\LAR#LSR#PDWT_Type *SSPSR#CSPSR#YRESERVED0z #ACPR#Y6RESERVED1 #SPPR#YRESERVED2 #FFSR#FFCR#FSCR#YRESERVED3 #TRIGGER#FIFO0#ITATBCTR2#YRESERVED4^ #ITATBCTR0#FIFO1#ITCTRL#Y&RESERVED5 #CLAIMSET#CLAIMCLR#YRESERVED7 #DEVID#DEVTYPE#PTPI_Type[  *,TYPE#CTRL#RNR#RBAR# RASR#RBAR_A1#RASR_A1#RBAR_A2#RASR_A2# RBAR_A3#$RASR_A3#(PMPU_Type6 *YRESERVED0#FPCCR#FPCAR#FPDSCR# MVFR0#MVFR1#MVFR2#PFPU_Type *DHCSR#DCRSR#DCRDR#DEMCR# PCoreDebug_Typeb tqITM_RxBuffer< __NVIC_SetPriorityGrouping$YPriorityGroup\reg_valueY\PriorityGroupTmpY; __NVIC_GetPriorityGroupingYa__resultYkSerialNorCmd_PageProgram_1_1_4_4B 4kSerialNorCmd_Read_SDR_1_4_4_3B kSerialNorCmd_Read_DDR_1_4_4_3B kSerialNorCmd_Read_SDR_1_4_4_4B kSerialNorCmd_Read_SDR_1_1_4_4B lkSerialNorCmd_Read_DDR_1_4_4_4B kSerialNorCmd_ChipErase `kSerialNorCmd_WriteEnable kSerialNorCmd_WriteStatusReg1 kSerialNorCmd_ReadStatusReg1 kSerialNorCmd_WriteStatusReg2 >kSerialNorCmd_ReadStatusReg2 ?kSerialNorCmd_ReadFlagReg pkSerialNorCmd_SE4K_3B kSerialNorCmd_SE4K_4B !kSerialNorCmd_SE64K_3B kSerialNorCmd_SE64K_4B kSerialNorQpiMode_NotConfig kSerialNorQpiMode_Cmd_0x38 kSerialNorQpiMode_Cmd_0x38_QE kSerialNorQpiMode_Cmd_0x35 kSerialNorQpiMode_Cmd_0x71 kSerialNorQpiMode_Cmd_0x61 kSerialNorType_StandardSPI kSerialNorType_HyperBus kSerialNorType_XPI kSerialNorType_NoCmd )_lut_seqYlut#kSerialNOR_IndividualMode kSerialNOR_ParallelMode kFlexSpiSerialClk_Update kFlexSpiSerialClk_Restore kSerialFlash_ReadSFDP ZkSerialFlash_ReadManufacturerId kSfdp_Version_Major_1_0 kSfdp_Version_Minor_0 kSfdp_Version_Minor_A kSfdp_Version_Minor_B kSfdp_Version_Minor_C kSfdp_BasicProtocolTableSize_Rev0 $kSfdp_BasicProtocolTableSize_RevA @kSfdp_BasicProtocolTableSize_RevB @kSfdp_BasicProtocolTableSize_RevC P)_sfdp_headersignatureY#minor_rev:#major_rev:#param_hdr_num:#sfdp_access_protocol:#kParameterID_BasicSpiProtocolkParameterID_SectorMapkParameterID_4ByteAddressInstructionTablekParameterID_xSpiProfile1_0kParameterID_xSpiOrofile2_0kParameterID_StaCtrlCfgRegMapkParameterID_OpiEnableSeq )_sfdp_parameter_headerparameter_id_lsb:#minor_rev:#major_rev:#table_length_in_32bit:#:parameter_table_pointer #parameter_id_msb:#*!erase_sizeY#!write_granularityY#!reserved0Y#!unused0Y#!erase4k_instY#!support_1_1_2_fast_readY#!address_bitsY# !support_ddr_clockingY# !support_1_2_2_fast_readY# !supports_1_4_4_fast_readY# !support_1_1_4_fast_readY# !unused1Y# *!dummy_clocks_1_4_4_readY#!mode_clocks_1_4_4_readY#!inst_1_4_4_readY#!dummy_clocks_1_1_4_readY# !mode_clocks_1_1_4_readY#!inst_1_1_4_readY#*!dummy_clocks_1_2_2_readY#!mode_clocks_1_2_2_readY#!inst_1_2_2_readY#!dummy_clocks_1_1_2_readY# !mode_clocks_1_1_2_readY#!inst_1_1_2_readY#* !support_2_2_2_fast_readY#!reserved0Y#!support_4_4_4_fast_readY#!reserved1Y#*!!reserved0Y#!dummy_clocks_2_2_2_readY# !mode_clocks_2_2_2_readY#!inst_2_2_2_readY#*"!reserved0Y#!dummy_clocks_4_4_4_readY# !mode_clocks_4_4_4_readY#!inst_4_4_4_readY#*"size:#inst:#*#!reserved0Y#!page_sizeY#!reserved1Y#*#suspend_resume_specY#suspend_resume_instY#*$!reserved0Y#!busy_status_pollingY#!reserved1Y#*&!mode_4_4_4_disable_seqY#!mode_4_4_4_enable_seqY#!support_mode_0_4_4Y#!mode_0_4_4_exit_methodY#!mode_0_4_4_entry_methodY# !quad_enable_requirementY# !hold_reset_disableY#!reserved0Y#*'!status_reg_write_enableY#!reserved0Y#!soft_reset_rescue_supportY#!exit_4_byte_addressingY# !enter_4_byte_addrssingY#*)!dummy_clocks_1_8_8_readY#!mode_clocks_1_8_8_readY#!inst_1_8_8_readY#!dummy_clocks_1_1_8_readY# !mode_clocks_1_1_8_readY#!inst_1_1_8_readY#*+!reservedY#!output_driver_strengthY# !jedec_spi_protocol_resetY#!dqs_waveform_type_sdrY#!dqs_support_in_qpi_sdrY#!dqs_support_in_qpi_ddrY#!dqs_support_in_opi_strY#!cmd_and_extension_in_opi_ddrY#!byte_order_in_opi_ddrY#*-!opi_sdr_disable_seqY#!opi_sdr_enable_deqY#!support_mode_0_8_8Y#!mode_0_8_8_exit_methodY#!mode_0_8_8_entry_methodY# !octal_enable_requirementY# !reservedY# */!qpi_sdr_no_dqsY#!qpi_sdr_with_dqsY#!qpi_ddr_no_dqsY#!qpi_ddr_with_dqsY#!opi_sdr_no_dqsY# !opi_sdr_with_dqsY#!opi_ddr_no_dqsY#!opi_ddr_with_dqsY#)2_jedec_flash_param_tablePmisc #flash_densityY#read_1_4_info%#read_1_2_info# read_22_44_check#read_2_2_info4#read_4_4_info#00erase_infoT#erase_timingY#$chip_erase_progrm_infoQ#(suspend_resume_info#,busy_status_info#4mode_4_4_info(#8mode_config_info1#<read_1_8_info#@xpi_misc_info#Dmode_octal_info#Hmax_speed_info_xpi#L*9!support_1_1_1_readY#!support_1_1_1_fast_readY#!support_1_1_2_fast_readY#!support_1_2_2_fast_readY#!support_1_1_4_fast_readY#!support_1_4_4_fast_readY#!support_1_1_1_page_programY#!support_1_1_4_page_programY#!support_1_4_4_page_programY#!support_erase_type1_sizeY#!support_erase_type2_sizeY#!support_erase_type3_sizeY#!support_erase_type4_sizeY#!support_1_1_1_dtr_readY#!support_1_2_2_dtr_readY#!support_1_4_4_dtr_readY#!support_volatile_sector_lock_read_cmdY#!support_volatile_sector_lock_write_cmdY#!support_nonvolatile_sector_lock_read_cmdY# !support_nonvolatile_sector_lock_write_cmdY# !reservedY# *99:erase_inst#):_jedec_4byte_addressing_inst_tablecmd_4byte_support_info_#erase_inst_info#);_jdec_query_tabledstandard_versionY#flash_param_tbl_sizeY#flash_param_tbl@#has_4b_addressing_inst_table#Xflash_4b_inst_tblb#\ .\devices\MIMXRT1021\drivers\fsl_common.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash(/ _status_groupskStatusGroup_Generic kStatusGroup_FLASH kStatusGroup_LPSPI kStatusGroup_FLEXIO_SPI kStatusGroup_DSPI kStatusGroup_FLEXIO_UART kStatusGroup_FLEXIO_I2C kStatusGroup_LPI2C kStatusGroup_UART kStatusGroup_I2C kStatusGroup_LPSCI kStatusGroup_LPUART kStatusGroup_SPI kStatusGroup_XRDC kStatusGroup_SEMA42 kStatusGroup_SDHC kStatusGroup_SDMMC kStatusGroup_SAI kStatusGroup_MCG kStatusGroup_SCG kStatusGroup_SDSPI kStatusGroup_FLEXIO_I2S kStatusGroup_FLEXIO_MCULCD kStatusGroup_FLASHIAP kStatusGroup_FLEXCOMM_I2C kStatusGroup_I2S kStatusGroup_IUART kStatusGroup_CSI kStatusGroup_MIPI_DSI kStatusGroup_SDRAMC #kStatusGroup_POWER 'kStatusGroup_ENET (kStatusGroup_PHY )kStatusGroup_TRGMUX *kStatusGroup_SMARTCARD +kStatusGroup_LMEM ,kStatusGroup_QSPI -kStatusGroup_DMA 2kStatusGroup_EDMA 3kStatusGroup_DMAMGR 4kStatusGroup_FLEXCAN 5kStatusGroup_LTC 6kStatusGroup_FLEXIO_CAMERA 7kStatusGroup_LPC_SPI 8kStatusGroup_LPC_USART 9kStatusGroup_DMIC :kStatusGroup_SDIF ;kStatusGroup_SPIFI <kStatusGroup_OTP =kStatusGroup_MCAN >kStatusGroup_CAAM ?kStatusGroup_ECSPI @kStatusGroup_USDHC AkStatusGroup_LPC_I2C BkStatusGroup_DCP CkStatusGroup_MSCAN DkStatusGroup_ESAI EkStatusGroup_FLEXSPI FkStatusGroup_MMDC GkStatusGroup_MICFIL HkStatusGroup_SDMA IkStatusGroup_ICS JkStatusGroup_SPDIF KkStatusGroup_NOTIFIER bkStatusGroup_DebugConsole ckStatusGroup_SEMC dkStatusGroup_ApplicationRangeStart e_generic_statuskStatus_Success kStatus_Fail kStatus_ReadOnly kStatus_OutOfRange kStatus_InvalidArgument kStatus_Timeout kStatus_NoTransferInProgress Pstatus_t;EnableIRQ$Ainterrupta__result;DisableIRQ$Ainterrupta__result;DisableGlobalIRQYa__resultY\regPrimaskY<EnableGlobalIRQ$Yprimask bsp\src\hardware_init_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash @+"nY"Y bsp\src\clock_config_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash\.kMaxAHBClockD"YtY9flexspi_clock_gate_enable$Yinstance9flexspi_clock_gate_disable$Yinstance8 get_core_clockYa__resultY .\devices\MIMXRT1021\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash 0_BoolPclock_name_tPclock_ip_name_t Pclock_osc_tPclock_gate_value_t4Pclock_mode_tPclock_mux_tPclock_div_tPclock_arm_pll_config_tBPclock_usb_pll_config_trPclock_sys_pll_config_tPclock_audio_pll_config_tPclock_video_pll_config_tiPclock_enet_pll_config_t_clock_pllkCLOCK_PllSys 0kCLOCK_PllUsb1 kCLOCK_PllAudio pkCLOCK_PllEnet_Enet0 kCLOCK_PllEnet_Enet1kCLOCK_PllEnet_25MkCLOCK_PllEnetPclock_pll_tO_clock_pfdkCLOCK_Pfd0 kCLOCK_Pfd1 kCLOCK_Pfd2 kCLOCK_Pfd3 Pclock_pfd_t_clock_usb_srckCLOCK_Usb480M kCLOCK_UsbSrcUnusedPclock_usb_src_tv_clock_usb_phy_srckCLOCK_Usbphy480M Pclock_usb_phy_src_tqg_xtalFreqYqg_rtcXtalFreqY<CLOCK_SetMux$hmux$Yvalue\busyShiftY; CLOCK_GetMuxY$hmuxa__resultY< CLOCK_SetDiv$|divider$Yvalue\busyShiftY; CLOCK_GetDivY$|dividera__resultY< CLOCK_ControlGate$ name$8value\indexY\shiftY\regvtY"p< CLOCK_EnableClock$ name< CLOCK_DisableClock$ name< CLOCK_SetMode$Smode< CLOCK_SetPllBypass$base$pll$bypass"t; CLOCK_IsPllBypassed$base$plla__result; CLOCK_IsPllEnabled$base$plla__result< CLOCK_SetPllBypassRefClkSrc$base$pll$Ysrc;CLOCK_GetOscFreqYa__resultY;CLOCK_GetPllBypassRefClkY$base$plla__resultY;CLOCK_GetCpuClkFreqYa__resultY;CLOCK_GetRtcFreqYa__resultY<CLOCK_SetRtcXtalFreq$Yfreq9CLOCK_SetXtalFreq$Yfreq_clock_namekCLOCK_CpuClk kCLOCK_AhbClk kCLOCK_SemcClk kCLOCK_IpgClk kCLOCK_OscClk kCLOCK_RtcClk kCLOCK_ArmPllClk kCLOCK_Usb1PllClk kCLOCK_Usb1PllPfd0Clk kCLOCK_Usb1PllPfd1Clk kCLOCK_Usb1PllPfd2Clk kCLOCK_Usb1PllPfd3Clk kCLOCK_Usb2PllClk kCLOCK_SysPllClk kCLOCK_SysPllPfd0Clk kCLOCK_SysPllPfd1Clk kCLOCK_SysPllPfd2Clk kCLOCK_SysPllPfd3Clk kCLOCK_EnetPllEnet0Clk kCLOCK_EnetPllEnet1Clk kCLOCK_EnetPll25MClk kCLOCK_EnetPllClk kCLOCK_AudioPllClk  _clock_ip_namekCLOCK_IpInvalidkCLOCK_Aips_tz1kCLOCK_Aips_tz2kCLOCK_MqskCLOCK_Sim_m_clk_rkCLOCK_Dcp kCLOCK_Lpuart3 kCLOCK_Can1kCLOCK_Can1SkCLOCK_Can2kCLOCK_Can2SkCLOCK_TracekCLOCK_Gpt2kCLOCK_Gpt2SkCLOCK_Lpuart2kCLOCK_Gpio2kCLOCK_Lpspi1kCLOCK_Lpspi2kCLOCK_Lpspi3kCLOCK_Lpspi4kCLOCK_Adc2kCLOCK_EnetkCLOCK_PitkCLOCK_Adc1kCLOCK_Gpt1kCLOCK_Gpt1SkCLOCK_Lpuart4kCLOCK_Gpio1kCLOCK_CsukCLOCK_Gpio5kCLOCK_IomuxcSnvskCLOCK_Lpi2c1kCLOCK_Lpi2c2kCLOCK_Lpi2c3kCLOCK_OcotpkCLOCK_Xbar1kCLOCK_Xbar2kCLOCK_Gpio3kCLOCK_Lpuart5kCLOCK_SemckCLOCK_Lpuart6kCLOCK_Aoi1kCLOCK_Ewm0kCLOCK_Wdog1kCLOCK_FlexRamkCLOCK_Acmp1kCLOCK_Acmp2kCLOCK_Acmp3kCLOCK_Acmp4kCLOCK_IomuxcSnvsGprkCLOCK_Sim_m7_clk_rkCLOCK_IomuxckCLOCK_IomuxcGprkCLOCK_BeekCLOCK_SimM7kCLOCK_TsckCLOCK_SimMkCLOCK_SimEmskCLOCK_Pwm1kCLOCK_Pwm2kCLOCK_Enc1kCLOCK_Enc2kCLOCK_Rom kCLOCK_Flexio1 kCLOCK_Wdog3 kCLOCK_Dma kCLOCK_Kpp kCLOCK_Wdog2 kCLOCK_Aips_tz4 kCLOCK_Spdif kCLOCK_Sai1 kCLOCK_Sai2 kCLOCK_Sai3 kCLOCK_Lpuart1 kCLOCK_Lpuart7 kCLOCK_SnvsHp kCLOCK_SnvsLp kCLOCK_UsbOh3 kCLOCK_Usdhc1 kCLOCK_Usdhc2 kCLOCK_Dcdc kCLOCK_Ipmux4 kCLOCK_FlexSpi kCLOCK_Trng kCLOCK_Lpuart8 kCLOCK_Timer4 kCLOCK_Aips_tz3 kCLOCK_SimPer kCLOCK_Anadig kCLOCK_Lpi2c4 kCLOCK_Timer1 kCLOCK_Timer2  _clock_osckCLOCK_RcOsc kCLOCK_XtalOsc !_clock_gate_valuekCLOCK_ClockNotNeeded kCLOCK_ClockNeededRun kCLOCK_ClockNeededRunWait !_clock_mode_tkCLOCK_ModeRun kCLOCK_ModeWait kCLOCK_ModeStop %_clock_muxkCLOCK_Pll3SwMux kCLOCK_PeriphMux9kCLOCK_SemcAltMux'kCLOCK_SemcMux&kCLOCK_PrePeriphMuxrkCLOCK_TraceMuxnkCLOCK_PeriphClk2MuxlkCLOCK_LpspiMuxdkCLOCK_FlexspiMux}kCLOCK_Usdhc2Mux1kCLOCK_Usdhc1Mux0kCLOCK_Sai3MuxnkCLOCK_Sai2MuxlkCLOCK_Sai1MuxjkCLOCK_PerclkMux&kCLOCK_Flexio1Mux skCLOCK_CanMux hkCLOCK_UartMux$&kCLOCK_SpdifMux0tkCLOCK_Lpi2cMux82)_clock_divkCLOCK_ArmDiv@kCLOCK_PeriphClk2DivkCLOCK_SemcDivkCLOCK_AhbDivkCLOCK_IpgDivhkCLOCK_LpspiDivkCLOCK_FlexspiDivkCLOCK_PerclkDivkCLOCK_CanDiv kCLOCK_TraceDiv$ykCLOCK_Usdhc2Div$kCLOCK_Usdhc1Div$kCLOCK_UartDiv$kCLOCK_Flexio1Div(kCLOCK_Sai3PreDiv(kCLOCK_Sai3Div(kCLOCK_Flexio1PreDiv(kCLOCK_Sai1PreDiv(kCLOCK_Sai1Div(kCLOCK_Sai2PreDiv,kCLOCK_Sai2Div,kCLOCK_Spdif0PreDiv0kCLOCK_Spdif0Div0kCLOCK_Lpi2cDiv8*_clock_pll_bypass_clk_srckCLOCK_PllBypassClkSrc24M kCLOCK_PllBypassClkSrcClkPN )*_clock_arm_pll_configloopDividerY#)+_clock_usb_pll_configloopDivider:#)+_clock_sys_pll_config loopDivider:#numeratorY#denominatorY#),_clock_audio_pll_config loopDivider:#postDivider:#numeratorY#denominatorY#)-_clock_video_pll_config loopDivider:#postDivider:#numeratorY#denominatorY#)/_clock_enet_pll_configenableClkOutput0#enableClkOutput1#enableClkOutput25M#enableClkOutput500M#loopDivider0:#loopDivider1:#l devices\MIMXRT1021\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash-t4_Bool""" E"YtY9CLOCK_InitUsb1Pll$config9CLOCK_DeinitUsb1Pll FlashDev.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash:<  .\middleware\flexspi_nor/flexspi_nor_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash:<_flexspi_nor_statuskStatusGroup_FLEXSPINOR kStatus_FLEXSPINOR_ProgramFail NkStatus_FLEXSPINOR_EraseSectorFail!NkStatus_FLEXSPINOR_EraseAllFail"NkStatus_FLEXSPINOR_WaitTimeout#NkStatus_FlexSPINOR_NotSupported$NkStatus_FlexSPINOR_WriteAlignmentError%NkStatus_FlexSPINOR_CommandFailure&NkStatus_FlexSPINOR_SFDP_NotFound'NkStatus_FLEXSPINOR_Unsupported_SFDP_Version(NkStatus_FLEXSPINOR_Flash_NotFound)NkStatus_FLEXSPINOR_DTRRead_DummyProbeFailed*N kSerialNorCfgOption_Tag kSerialNorCfgOption_DeviceType_ReadSFDP_SDR kSerialNorCfgOption_DeviceType_ReadSFDP_DDR kSerialNorCfgOption_DeviceType_HyperFLASH1V8 kSerialNorCfgOption_DeviceType_HyperFLASH3V0 kSerialNorCfgOption_DeviceType_MacronixOctalDDR kSerialNorCfgOption_DeviceType_MacronixOctalSDR kSerialNorCfgOption_DeviceType_MicronOctalDDR kSerialNorCfgOption_DeviceType_MicronOctalSDR kSerialNorCfgOption_DeviceType_AdestoOctalDDR kSerialNorCfgOption_DeviceType_AdestoOctalSDR  kSerialNorQuadMode_NotConfig kSerialNorQuadMode_StatusReg1_Bit6 kSerialNorQuadMode_StatusReg2_Bit1 kSerialNorQuadMode_StatusReg2_Bit7 kSerialNorQuadMode_StatusReg2_Bit1_0x31  kSerialNorEnhanceMode_Disabled kSerialNorEnhanceMode_0_4_4_Mode kSerialNorEnhanceMode_0_8_8_Mode kSerialNorEnhanceMode_DataOrderSwapped kSerialNorEnhanceMode_2ndPinMux *!max_freqY#!misc_modeY#!quad_mode_settingY#!cmd_padsY#!query_padsY# !device_typeY#!option_sizeY#!tagY#SB]UY*!dummy_cyclesY#!status_overrideY#!reservedY#SB*UY)_serial_nor_config_optionoption0#option1y#Pserial_nor_config_option_t*por_mode:#current_mode:#exit_no_cmd_sequence:#restore_sequence:#SBUYPflash_run_context_tQkRestoreSequence_None kRestoreSequence_HW_Reset kRestoreSequence_4QPI_FF kRestoreSequence_5QPI_FF kRestoreSequence_8QPI_FF kRestoreSequence_Send_F0 kRestoreSequence_Send_66_99 kRestoreSequence_Send_6699_9966 kRestoreSequence_Send_06_FF kFlashInstMode_ExtendedSpi kFlashInstMode_0_4_4_SDR kFlashInstMode_0_4_4_DDR kFlashInstMode_QPI_SDR AkFlashInstMode_QPI_DDR BkFlashInstMode_OPI_SDR kFlashInstMode_OPI_DDR )_flexspi_nor_configmemConfign#pageSizeY#sectorSizeY#ipcmdSerialClkFreq:#isUniformBlockSize:#isDataOrderSwapped:#:reserved0 #serialNorType:#needExitNoCmdMode:#halfClkForNonReadCmd:#needRestoreNoCmdMode:#blockSizeY#Y reserve2 #Pflexspi_nor_config_tO devices\MIMXRT1021\system_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash2J4$?SystemInitHook22@?]SystemInit2l3 F.2(3zFI(3f3}cccpc{?SystemCoreClockUpdatel3J4ZfreqYTZPLL2MainClockYZPLL3MainClockYrdevices\MIMXRT1021\system_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashpSystemCoreClockY y",devices\\MIMXRT1021\\system_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flashlp__asm___19_system_MIMXRT1021_c_5d646a67____REVSHlp,devices\\MIMXRT1021\\system_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashPTl__asm___19_system_MIMXRT1021_c_5d646a67____REV16PTmiddleware\flexspi\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash'2_BoolI''no5=c@>flexspi_is_padsetting_override_enable'(Ziconfig{ ___resultIO((FobPI( (2ocI (.(oc yI.(<( o@fcKH> flexspi_configure_dll߳<(b)iinstanceYiconfig{^__result߳PZstatus߳ZmdisConfigRequired<(^)Zbase\isUnifiedConfigYflexspiRootClkY\YYflexspiDllPZdllValueYZtempY0<(\)\useDLL<( )ZiYl( )ZdataValidTimeHYY\dataValidTimeLY( )YmaxFreqYXZis_ddr_enabled >  flexspi_get_ticks߳b))iticksiintervalNsYifreqYiunitYi^__result߳P<Zstatus߳V l))XcalculatedTicksP(ZcycleNsY8>  flexspi_config_mcr1߳)*niinstanceYiconfig{___result߳YseqWaitTicksYXYahbBusWaitTicksY\YserialRootClockFreqY`YahbBusClockFreqYdZbase>  flexspi_config_flash_control_registers߳**6iinstanceY~iconfig{J^__result߳PZstatus߳, **ZindexYYflashSizeYZtempYYserialClockFrequencyYXYcsIntervalTicksYHZbaseZflashSizeStart> flexspi_config_ahb_buffers߳**+ibase}iconfig{j^__result߳PNZtempYDZindexY1Zstatus߳WI[*+N+oc ,+L+bP> flexspi_command_xfer߳N+0-iinstanceYixfer___result߳L Zstatus߳wZbase8N+0-ZtempY%ZisParallelModeN+h,ZxferRemainingSizeYZxferBufferPtr\rx_fifo_sizeY\watermarkYZburst_rx_sizeYN+V,Zrx_fifo_reg+,,Zburst_rx_roundY{N+V,YbufYdZsrc]ZdstJN+N,XindexYSh,0-ZxferRemainingSize!ZxferBufferPtr \tx_fifo_sizeY\watermarkYZburst_tx_sizeY Zis_transfer_started ,,Ztx_fifo_reg} ,,Zburst_tx_roundY_ F-~++ fQF++ fFx,, f> flexspi_update_lut߳0--iinstanceY9 iseqIndexY ilutBase iseqNumberY ^__result߳P^Zstatus߳ :--Zbase Zstart_indexY Zend_indexY ZflexspiLutPtrs F^-f- fF-- f> flexspi_device_write_enable߳--~iinstanceYU iconfig{B iisParallelMode/ ibaseAddrY ^__result߳PVZstatus߳ --YflashXferH> flexspi_device_wait_busy߳-.8iinstanceY iconfig{ iisParallelModee ibaseAddrYR ___result߳h Zstatus߳ -.YYstatusDataBuffer HZbusyMaskY ZbusyPolarityY ZisBusy{ Ystatus0Y@Ystatus1YDYflashXferZenableTimeoutChecks ZremainingMsi? F.. o, o o o ed ..c c, c9 > flexspi_device_cmd_config߳./iinstanceY= iconfig{ ibaseAddrY^__result߳PZstatus߳//ZbaseYflashXferZindexYc2//Yread_cmd_padsY>! flexspi_init߳/1iinstanceYiconfig{^__result߳PZmcr0Y Zstatus߳/1ZbasemZneed_safe_freq)F 00 o#o2e=cM 00Zc]clbxLcF!1N1 omoOec<!1N1 c(cb+LcB?! flexspi_wait_idle11iinstanceY!11Zbase?" flexspi_clear_cache11iinstanceY"11XbaseP?# flexspi_half_clock_control11siinstanceYioptionY#11ZbaseI#11_orI$Z11Ko~TbPcAI$127o#.I%G22otoobPc%22cbbH middleware\flexspi\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashYg_flexSpiInstances y" middleware\\flexspi\\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flashhl__asm___13_fsl_flexspi_c_c729c902____REVSHhl middleware\\flexspi\\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashLPl__asm___13_fsl_flexspi_c_c729c902____REV16LPmiddleware\flexspi_nor\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashH 'l_BoolI H r ,o 9o 9b P(b U> flexspi_nor_exit_no_cmd_mode߳r iinstanceYm9iconfigU Z9iisParallelModeG9ibaseAddrY49^__result߳P2YflashXferH> flexspi_nor_write_enable߳ iinstanceY9iconfigU 8iisParallelMode8ibaseAddrY8^__result߳P`Zstatus߳8YZlut_tmp8>flexspi_nor_restore_no_cmd_mode߳ N iinstanceYh8iconfigU J8iisParallelMode,8ibaseAddrY8^__result߳P>Zstatus߳7 J YflashXfer> flexspi_nor_wait_busy߳N WiinstanceY7iconfigU 7iisParallMode7ibaseAddrY7^__result߳PNZstatus߳E7YZlut_tmp c7? flexspi_change_serial_clock P iinstanceY7iconfigU 6ioperationY6 L YisClockChangeRequiredZisDdrModeEnabled6Yserial_clockYXYcore_clockY\\dummy_cntY>  flexspi_nor_flash_page_program߳P iinstanceY6iconfigU a6idstAddrY86isrca 6^__result߳PZstatus߳5YflashXferYmemCfge ZisParallelMode5>  flexspi_nor_flash_erase_all߳iinstanceY5iconfigU 5^__result߳PZflashSizeStartk 5YcurrentFlashSizeY\YbaseAddrY\ZindexY-5Zstatus߳i5YflashXferZmemCfge V5> flexspi_nor_flash_erase_sector߳iinstanceY4iconfigU 4iaddressY4^__result߳PZstatus߳V4YflashXferZisParallelModei4YmemCfge > flexspi_nor_flash_erase_block߳bkiinstanceY+4iconfigU 4iaddressY3^__result߳PZstatus߳3YflashXferZisParallelMode3YmemCfge > flexspi_nor_read_sfdp߳b3iinstanceY3iaddrYl3ibufferk N3ibytesY03^__result߳P2YflashXferHZstatus߳3> prepare_quad_mode_enable_sequence߳iinstanceY2iconfigU 2itblq g2ioptionu 2___result߳1Ystatus߳Zenter_quad_mode_optionY1YYlut_seq HYxferYstatus_valY> probe_dtr_quad_read_dummy_cycles߳RiinstanceY1iconfigU k1idummy_cyclesk 41___result߳|0Zstatus߳0Zdummy_cycle_detected1YflashXferYYlut_seq DR[ Yprobe_pattern' YYbufferH \need_program_patternZmax_probe_tryY0Zprobe_cntY0Zprobe_dummy_cyclesY0> get_page_sector_block_size_from_sfdp߳RhciconfigU Q0itblq (0isector_erase_cmdk /iblock_erase_cmdk /___result߳.Zparam_tbl{ ?/Zflash_4b_tbl /Yflash_sizeYZflash_densityY/Zpage_sizeY.Zsector_sizeY.Zblock_sizeY.Zblock_erase_typeY/Zsector_erase_typeYh/RhZindexY.hZcurrent_erase_sizeY.> parse_sfdp߳hiinstanceY.iconfigU -itblq ,ioptionu m,___result߳(Zstatus߳+pZparam_tbl{ ?+Zflash_4b_tbl *Zsupport_ddr_moded*Yread_cmd:Ydummy_cyclesYZmode_cycles:)Ysector_erase_cmdYPYblock_erase_cmdYTZaddress_bitsY)Zaddress_padsY)Ycmd_padsYZenhance_modeY(Zentry_methodY(Zexit_methodY(LZmode_instYr(>" flexspi_nor_read_sfdp_info߳iinstanceY;(itblq (iaddress_shift_enable'^__result߳PZstatus߳'"Ysfdp_header ZaddressYS'Yparameter_header_numberY   Ysfdp_param_hdrsdZmax_hdr_countY'"XiYVh"DZparameter_idY5'"`Xtable_sizeYW"bpZindex"'>$ flexspi_nor_generate_config_block_hyperflash߳iinstanceY&iconfigU &iis_1v8&___result߳h&Zstatus߳&$#YYlut_seq@YdataYX#YYbufferP>& flexspi_nor_restore_spi_protocol߳,qiinstanceY1&iconfigU %irun_ctx %^__result߳PZstatus߳%Yxfer&(ZpadY%Zcmd_instYz%%YYlut_seq&$Ywait_cnt \>* flexspi_nor_generate_config_block_mxic_octalflash߳,8iinstanceYC%iconfigU $ioptionu $^__result߳PZstatus߳2#Yxfer~'YYmfg_idZis_sdr_mode?$' Yk_rdid_lut*LZcmd_padsY#Zquery_padsY#ZindexY#\mfg_id_buffer ZenableDTR")rYrun_ctx~)fYrun_ctx~*|Zcmd_instY"Zaddr_instY"Zdummy_instY"Zread_instY"Ywrite_instY~>- flexspi_nor_generate_config_block_micron_octalflash߳!iinstanceY}"iconfigU T"ioptionu +"^__result߳PZstatus߳!+ Yk_sdfp_lutZis_sdr_mode!-!Yjedec_info_tbl: ~Ysector_erase_cmdY~Yblock_erase_cmdY~\opi_mode_enable-~!Yrun_ctx~- @!Zaddress_bitsY!Ypage_program_cmdY-@!~!Yrun_ctx~>3 flexspi_nor_generate_config_block_adesto_octalflash߳!$iinstanceYg!iconfigU !ioptionu  ___result߳0kSfdp_LutIndex_Sdr_1_1 kSfdp_LutIndex_Sdr_4_4 kSfdp_LutIndex_Sdr_8_8 kSfdp_LutIndex_Ddr_4_4 kSfdp_LutIndex_Ddr_8_8 Zstatus߳y Zis_sdr_mode/ 0 Yk_sdfp_lut'3!$Zaddress_shift_enable Zquery_padsYZcmd_padsYZlutIndexYqYjedec_info_tbl: ~Ysector_erase_cmdYXYblock_erase_cmdY\Zaddr_padsY^\dummy_padsY\write_padsY\read_padsYZaddr_instYKZdummy_instY8Zread_instY#Ywrite_instY~Yrun_ctx~3!$Yrun_ctx~>4 flexspi_nor_get_config߳$d%iinstanceYiconfigU ioptionu ^__result߳PZstatus߳>6 flexspi_nor_flash_erase߳d%%UiinstanceYliconfigU NistartY;ilengthY(___result߳Zaligned_startYZaligned_endYZstatus߳6%%Zis_addr_block_alignedZremaining_sizeY>8 flexspi_nor_flash_read߳%N&iinstanceYTiconfigU Aidstk istartYibytesY^__result߳PVZstatus߳8%J&YflashXferYisParallelModeYmemCfge 8"&J&XreadLengthYUI9 N&&o' o6 oA \oI obT Plbd b| `9V&& b 6b 6I: &'o >o  o b Pc b/  :&'> bA ~NI;V ''~o~ o o o b P$b Pb I; ''Po o ro _o& Lb2 P"bB PbM 0middleware\\flexspi_nor\\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flashdh*__asm___19_flexspi_nor_flash_c_93f2e184____REVSHdh0middleware\\flexspi_nor\\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashHL*__asm___19_flexspi_nor_flash_c_93f2e184____REV16HLbsp\src\hardware_init_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash 4 ,?qflexspi_iomux_config 9iinstanceY;iconfig/:ZcsPadCtlValueY:ZdqsPadCtlValueY:ZsclkPadCtlValueY:ZdataPadCtlValueYo:> flexspi_set_failsafe_setting. " 9iconfig/\:^__result.P(Zstatus.>:> flexspi_nor_write_persistent." * 9idata/+:^__result.P> flexspi_nor_read_persistent.* 4 9idata/:^__result.P,bsp\\src\\hardware_init_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash`d-__asm___26_hardware_init_MIMXRT1021_c_753bbbb7____REVSH`d,bsp\\src\\hardware_init_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashDH.__asm___26_hardware_init_MIMXRT1021_c_753bbbb7____REV16DHbsp\src\clock_config_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flashx 0?>clock_init<Xahb_dividerYUrFs9@f9I0<o1e>I.1;oR1R>?flexspi_clock_config;iinstanceY3>ifreq >isampleClkModeY=)_flexspi_clock_paramfrac:#podf:#Pflexspi_clock_param_tZpfd480Y=Zcscmr1Y=ZfracYt=ZpodfYa= h Yk_sdr_clock_configlh Yk_ddr_clock_configL0Zflexspi_config_array="h> flexspi_get_clock. ;iinstanceYN=itype3;=ifreq0=___result.<ZclockFrequencyY<Zstatus.<YahbBusDividerYYseralRootClkDividerYZarm_clockY<YpfdFracYXpfdClkYP,\flexspi_clk_srcY>  flexspi_get_max_supported_freq.  y;iinstanceY<ifreq0<iclkModeYw<^__result.PZstatus.d<I b1 e;b1P>  get_bus_clockY 8 E;^__resultYPYahbBusDividerY? flexspi_sw_delay_us8 x $;iusi;<XticksPerUsYV N b YticksCount0hF b1> D e1,bsp\\src\\clock_config_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash\`3__asm___25_clock_config_MIMXRT1021_c_efd8dd31____REVSH\`,bsp\\src\\clock_config_MIMXRT1021.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash@D 4__asm___25_clock_config_MIMXRT1021_c_efd8dd31____REV16@Ddevices\MIMXRT1021\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashL5_Bool> CLOCK_GetPllFreqYL`@ipllJE___resultYDZfreqYEZdivSelectYDZfreqTmpioD9JYenetRefClkFreqzXF^nf.n7e?F~pffeF|ffe> CLOCK_GetSysPfdFreqY`@ipfdxQD___resultY DZfreqY3D> CLOCK_GetUsb1PfdFreqY@ipfdxD___resultYCZfreqYC>9CLOCK_GetPeriphClkFreqY`@___resultYtCZfreqYC?zCLOCK_InitExternalClk`g@ibypassXtalOscaC?CLOCK_DeinitExternalClkS@?CLOCK_SwitchOsc?@iosc:NC?CLOCK_InitRcOsc24M+@?CLOCK_DeinitRcOsc24M@> CLOCK_GetFreqY?iname ;C___resultYBZfreqYCF8< e? CLOCK_InitSysPll?iconfigJB? CLOCK_DeinitSysPll?I EJ?o`JBI lJ?? CLOCK_InitAudioPllp?iconfig+JBZpllAudioYqBZmisc2YSB? CLOCK_DeinitAudioPllpzs?? CLOCK_InitEnetPllz_?iconfig5J@BZenet_pllY-B? CLOCK_DeinitEnetPllK?? CLOCK_InitSysPfd+?ipfdxBipfdFrac:BZpfdIndexYAXpfd528YR? CLOCK_DeinitSysPfd?ipfdxA?CLOCK_InitUsb1Pfd,>ipfdxAipfdFrac:AZpfdIndexYAXpfd480YR?CLOCK_DeinitUsb1Pfd,>>ipfdxA>CLOCK_EnableUsbhs0Clock>|>isrcAifreqYoA^__resultP<>zYi?Jx>CLOCK_EnableUsbhs0PhyPllClock|>isrc\AifreqYIA^__resultP,Yg_ccmConfigUsbPllJx?CLOCK_DisableUsbhs0PhyPllClock>FlJINx>cm+Adevices\MIMXRT1021\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flashpg_xtalFreqY y"pg_rtcXtalFreqY y"$devices\\MIMXRT1021\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashX\<__asm___11_fsl_clock_c_07a918fd____REVSHX\$devices\\MIMXRT1021\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash<@T<__asm___11_fsl_clock_c_07a918fd____REV16<@FlashDev.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashpFlashDevice\K y"FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flashp.?intunsigned longunsigned char">InitpEiadriFiclkVFifncCF^__resultPj\status߳Yoption-Sp>IUnInitEifnc0F^__resultP>UEraseChipE^__resultPYstatus߳>iEraseSectorE$adr^__resultPYstatus߳>ProgramPage.hE$adriszFibufE^__resultPYstatus߳FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashpconfigW y"FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_FlashTXA__asm___10_FlashPrg_c_Init____REVSHTXFlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2018\RT1020\flashloader\MDK_QSPI_flashloader\_Template_Flash8<TA__asm___10_FlashPrg_c_Init____REV168<xm devices\MIMXRT1021\.\CMSIS\Include\MIMXRT1021.hcore_cm7.hsystem_MIMXRT1021.h .\CMSIS\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm7.hstdint.hcmsis_version.hcmsis_compiler.hmpu_armv7.h] devices\MIMXRT1021\.\CMSIS\Include\system_MIMXRT1021.ccore_cm7.h2~ ~x   / &1 ~ 0 'o# ~#y  jpL} lr = n  # ]U;~-kkpP8 .\\CMSIS\\Include\\cmsis_armcc.hlP8 .\\CMSIS\\Include\\cmsis_armcc.hP middleware\flexspi\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\MIMXRT1021\middleware\flexspi\fsl_flexspi.cfsl_flexspi.hassert.hstdbool.hfsl_device_registers.hfsl_flexspi.cpf middleware\flexspi\.\devices\MIMXRT1021\drivers\fsl_flexspi.hfsl_common.h 8 middleware\flexspi\fsl_flexspi.c'  ~  ~   ~  ~  ~   7 %*m! -   %&Q7 4  !1U ! %w! y -I{ %  %  (   |!/ -  !&&,-  - k-" u     !"d/"d/ j4~K' &- /%'/ !] & y   "'   $~ ~+   ~1|~ ) 2  y "{ ! }{ L $ $ {   96~# ~(0~&-2~7X />% $ z, & 99~6 ~!# w  #X .  "  n} z~ ! 6 <y & ~y | |  +% - ?* { ,'-H + - !?,   }+   )w  $!& vz     (4&88?& 3U+1$ !  ?!: 9 %   x " G   !  " %' *"""""~ "~  !~{ &v%   ~  ~{ 01 &v%   !A!       z u  ~ o &  % 0 -?, n 0 ;)P8 .\\CMSIS\\Include\\cmsis_armcc.hhP8 .\\CMSIS\\Include\\cmsis_armcc.hL C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\middleware\middleware\flexspi_nor\middleware\flexspi_nor\flexspi_nor_flash.cstring.hstdlib.hstdbool.hflexspi/fsl_flexspi.hflexspi_nor_flash.hflexspi_nor_flash.c middleware\flexspi_nor\.\devices\MIMXRT1021\drivers\.\middleware\flexspi_nor_flash.hfsl_common.hflexspi/fsl_flexspi.h(B middleware\flexspi_nor\flexspi_nor_flash.cH  . /&) {   /&   ~[. 1 * @)4 z   ! ~  Z % x%"($ 2  . ! &  %( 8 Y! ! !~$ *2+ + ! F,2 '6'ws'  -/  2E& i H v2'2 k'$# )2+ - @,2 ' 1'$# )2+ - @,2 ' 1'~ *{   *  w   o r  ! G}  - 2!  z *1  v&fczv  s) ':&,J  7, 4&,      %} & - &3 &   |qg7 ,` .+i7~7*{*y  }x  0 znj h &8> )'  7!sZ;%  -  )" z. @  {& +.{.; v+     | v% 3 '   ,!&0  H>Bp z$\n|!  A).1 (~T0'   &  ! h 8I+!!| !##!^ 0 B= C= C=B % }8',&& ! x 9 ]~6+ 1O 3P 9w"  2 y   ! * "A   3! # 4 $)}%",,V5   |u    ) ~|.  1 ,,~+ ' ~,   , u %! ( t !! +! % z   ! | E  E  ! o }1l"|+ V2!   &,)(C+ C~w{{%# ,j . e7 ,     ! ~  ~  & x    9&  ~  z  ',   cu n p%&| ~#    u   u- e7* .:!/; .9!/; EQ553?|9~/7zC@ #}#  / %h  ,  !&# ~ +,-  9b e@ < '/||" n%< " t t t #  } I $ &    ,J   "  ~|  ~  & ( ( :&.,8-9,7-9 ]Y|1G3/~ ~ , (; #* ~   " q+  ~   m {"  %&|/&&&  !| x  2},#&y',g) /&,w &wu { {"3& !; 2~r n  t  ~2 &#} # $, (2 n' ?,35~)(~(P8 .\\CMSIS\\Include\\cmsis_armcc.hdP8 .\\CMSIS\\Include\\cmsis_armcc.hH .\devices\MIMXRT1021\.\middleware\bsp\src\hardware_init_MIMXRT1021.cfsl_device_registers.hflexspi/fsl_flexspi.hflexspi_nor/flexspi_nor_flash.h9 bsp\src\hardware_init_MIMXRT1021.c z .     ![% (   # '      !Q/ |  ' P8 .\\CMSIS\\Include\\cmsis_armcc.h`P8 .\\CMSIS\\Include\\cmsis_armcc.hD .\devices\MIMXRT1021\.\devices\MIMXRT1021\drivers\.\middleware\bsp\src\clock_config_MIMXRT1021.cfsl_device_registers.hfsl_clock.hflexspi/fsl_flexspi.h .\devices\MIMXRT1021\drivers\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\MIMXRT1021\fsl_common.hassert.hstdbool.hstdint.hstring.hstdlib.hfsl_device_registers.hfsl_clock.h .\devices\MIMXRT1021\drivers\.\devices\MIMXRT1021\C:\Keil_v5\ARM\ARMCC\Bin\..\include\fsl_clock.hfsl_device_registers.hstdint.hstdbool.hassert.he .\devices\MIMXRT1021\drivers\bsp\src\clock_config_MIMXRT1021.cfsl_clock.h>xx - = %7 1`)(5=';&&R tR  4 %    }~    Y7{|x x % _ d & &'  d  |!  ,u u  & ! ~ | 7P8 .\\CMSIS\\Include\\cmsis_armcc.h\P8 .\\CMSIS\\Include\\cmsis_armcc.h@ devices\MIMXRT1021\drivers\devices\MIMXRT1021\drivers\fsl_clock.cfsl_common.hfsl_clock.hfsl_clock.c devices\MIMXRT1021\drivers\.\devices\MIMXRT1021\C:\Keil_v5\ARM\ARMCC\Bin\..\include\fsl_clock.hfsl_device_registers.hstdint.hstdbool.hassert.h,M devices\MIMXRT1021\drivers\fsl_clock.cfsl_clock.hL%{%|7 {| {   A| +~Kn= L% % E  \bM! g o t ) } 7 j j+ s  w  $} 7 j j+ s  w{ _ = " ^"L { U zglq~       }    z  $  D%< C= C< E8z N& ] l { :  <~,'~  xf  s 1.  bd  4|     &|("&,|("&,  #/~#/25  !*}!N[P8 .\\CMSIS\\Include\\cmsis_armcc.hXP8 .\\CMSIS\\Include\\cmsis_armcc.h<8. FlashDev.cFlashOS.H .\middleware\.\devices\MIMXRT1021\drivers\flexspi_nor/flexspi_nor_flash.hfsl_common.hflexspi/fsl_flexspi.hth .\middleware\.\devices\MIMXRT1021\drivers\flexspi/fsl_flexspi.hfsl_common.h .\devices\MIMXRT1021\drivers\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\MIMXRT1021\fsl_common.hassert.hstdbool.hstdint.hstring.hstdlib.hfsl_device_registers.hfsl_clock.hdrivers\fsl_common.hxo .\devices\MIMXRT1021\.\CMSIS\Include\MIMXRT1021.hcore_cm7.hsystem_MIMXRT1021.hPD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h,  FlashOS.H! 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ADC_HC_ADCH_MASK)ADC_HC_AIEN_MASK (0x80U)ADC_HC_AIEN_SHIFT (7U)ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)ADC_HC_COUNT (8U)ADC_HS_COCO0_MASK (0x1U)ADC_HS_COCO0_SHIFT (0U)ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)ADC_R_CDATA_MASK (0xFFFU)ADC_R_CDATA_SHIFT (0U)ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)ADC_R_COUNT (8U) ADC_CFG_ADICLK_MASK (0x3U) ADC_CFG_ADICLK_SHIFT (0U) ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) ADC_CFG_MODE_MASK (0xCU) ADC_CFG_MODE_SHIFT (2U) ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) ADC_CFG_ADLSMP_MASK (0x10U) ADC_CFG_ADLSMP_SHIFT (4U) ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) ADC_CFG_ADIV_MASK (0x60U) ADC_CFG_ADIV_SHIFT (5U) ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) ADC_CFG_ADLPC_MASK (0x80U) ADC_CFG_ADLPC_SHIFT (7U) ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) ADC_CFG_ADSTS_MASK (0x300U) ADC_CFG_ADSTS_SHIFT (8U) ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) ADC_CFG_ADHSC_MASK (0x400U) ADC_CFG_ADHSC_SHIFT (10U) ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) ADC_CFG_REFSEL_MASK (0x1800U) ADC_CFG_REFSEL_SHIFT (11U) ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) ADC_CFG_ADTRG_MASK (0x2000U) ADC_CFG_ADTRG_SHIFT (13U) ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) ADC_CFG_AVGS_MASK (0xC000U) ADC_CFG_AVGS_SHIFT (14U) ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) ADC_CFG_OVWREN_MASK (0x10000U) ADC_CFG_OVWREN_SHIFT (16U) ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) ADC_GC_ADACKEN_MASK (0x1U) ADC_GC_ADACKEN_SHIFT (0U) ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) ADC_GC_DMAEN_MASK (0x2U) ADC_GC_DMAEN_SHIFT (1U) ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) ADC_GC_ACREN_MASK (0x4U) ADC_GC_ACREN_SHIFT (2U) ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) ADC_GC_ACFGT_MASK (0x8U) ADC_GC_ACFGT_SHIFT (3U) ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) ADC_GC_ACFE_MASK (0x10U) ADC_GC_ACFE_SHIFT (4U) ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) ADC_GC_AVGE_MASK (0x20U) ADC_GC_AVGE_SHIFT (5U) ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) ADC_GC_ADCO_MASK (0x40U) ADC_GC_ADCO_SHIFT (6U) ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) ADC_GC_CAL_MASK (0x80U) ADC_GC_CAL_SHIFT (7U) ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) ADC_GS_ADACT_MASK (0x1U) ADC_GS_ADACT_SHIFT (0U) ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) ADC_GS_CALF_MASK (0x2U) ADC_GS_CALF_SHIFT (1U) ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) ADC_GS_AWKST_MASK (0x4U) ADC_GS_AWKST_SHIFT (2U) ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) ADC_CV_CV1_MASK (0xFFFU) ADC_CV_CV1_SHIFT (0U) ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) ADC_CV_CV2_MASK (0xFFF0000U) ADC_CV_CV2_SHIFT (16U) ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) ADC_OFS_OFS_MASK (0xFFFU) ADC_OFS_OFS_SHIFT (0U) ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) ADC_OFS_SIGN_MASK (0x1000U) ADC_OFS_SIGN_SHIFT (12U) ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) ADC_CAL_CAL_CODE_MASK (0xFU) ADC_CAL_CAL_CODE_SHIFT (0U) ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) ADC1_BASE (0x400C4000u) ADC1 ((ADC_Type *)ADC1_BASE) ADC2_BASE (0x400C8000u) ADC2 ((ADC_Type *)ADC2_BASE) ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) ADC_ETC_CTRL_SOFTRST_SHIFT (31U) ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) ADC_ETC_TRIGn_CTRL_COUNT (8U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) ADC_ETC_TRIGn_COUNTER_COUNT (8U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) ADC_ETC_BASE (0x403B0000u) ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } ADC_ETC_BASE_PTRS { ADC_ETC } ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } AIPSTZ_MPR_MPROT5_MASK (0xF00U) AIPSTZ_MPR_MPROT5_SHIFT (8U) AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) AIPSTZ_MPR_MPROT3_MASK (0xF0000U) AIPSTZ_MPR_MPROT3_SHIFT (16U) AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) AIPSTZ_MPR_MPROT2_MASK (0xF00000U) AIPSTZ_MPR_MPROT2_SHIFT (20U) AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) AIPSTZ_MPR_MPROT1_MASK (0xF000000U) AIPSTZ_MPR_MPROT1_SHIFT (24U) AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) AIPSTZ_MPR_MPROT0_SHIFT (28U) AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) AIPSTZ_OPACR_OPAC7_MASK (0xFU)AIPSTZ_OPACR_OPAC7_SHIFT (0U)AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)AIPSTZ_OPACR_OPAC6_MASK (0xF0U)AIPSTZ_OPACR_OPAC6_SHIFT (4U)AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)AIPSTZ_OPACR_OPAC5_MASK (0xF00U)AIPSTZ_OPACR_OPAC5_SHIFT (8U)AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)AIPSTZ_OPACR_OPAC4_MASK (0xF000U)AIPSTZ_OPACR_OPAC4_SHIFT (12U)AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)AIPSTZ_OPACR_OPAC3_SHIFT (16U)AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)AIPSTZ_OPACR_OPAC2_SHIFT (20U)AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)AIPSTZ_OPACR_OPAC1_SHIFT (24U)AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)AIPSTZ_OPACR_OPAC0_SHIFT (28U)AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)AIPSTZ_OPACR1_OPAC15_MASK (0xFU)AIPSTZ_OPACR1_OPAC15_SHIFT (0U)AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)AIPSTZ_OPACR1_OPAC14_SHIFT (4U)AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)AIPSTZ_OPACR1_OPAC13_SHIFT (8U)AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)AIPSTZ_OPACR1_OPAC12_SHIFT (12U)AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)AIPSTZ_OPACR1_OPAC11_SHIFT (16U)AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)AIPSTZ_OPACR1_OPAC10_SHIFT (20U)AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)AIPSTZ_OPACR1_OPAC9_SHIFT (24U)AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)AIPSTZ_OPACR1_OPAC8_SHIFT (28U)AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)AIPSTZ_OPACR2_OPAC23_MASK (0xFU)AIPSTZ_OPACR2_OPAC23_SHIFT (0U)AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)AIPSTZ_OPACR2_OPAC22_SHIFT (4U)AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)AIPSTZ_OPACR2_OPAC21_SHIFT (8U)AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)AIPSTZ_OPACR2_OPAC20_SHIFT (12U)AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)AIPSTZ_OPACR2_OPAC19_SHIFT (16U)AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)AIPSTZ_OPACR2_OPAC18_SHIFT (20U)AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)AIPSTZ_OPACR2_OPAC17_SHIFT (24U)AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)AIPSTZ_OPACR2_OPAC16_SHIFT (28U)AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)AIPSTZ_OPACR3_OPAC31_MASK (0xFU)AIPSTZ_OPACR3_OPAC31_SHIFT (0U)AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)AIPSTZ_OPACR3_OPAC30_SHIFT (4U)AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)AIPSTZ_OPACR3_OPAC29_SHIFT (8U)AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)AIPSTZ_OPACR3_OPAC28_SHIFT (12U)AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)AIPSTZ_OPACR3_OPAC27_SHIFT (16U)AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)AIPSTZ_OPACR3_OPAC26_SHIFT (20U)AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)AIPSTZ_OPACR3_OPAC25_SHIFT (24U)AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)AIPSTZ_OPACR3_OPAC24_SHIFT (28U)AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)AIPSTZ_OPACR4_OPAC33_SHIFT (24U)AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)AIPSTZ_OPACR4_OPAC32_SHIFT (28U)AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)AIPSTZ1_BASE (0x4007C000u)AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)AIPSTZ2_BASE (0x4017C000u)AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)AIPSTZ3_BASE (0x4027C000u)AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)AIPSTZ4_BASE (0x4037C000u)AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }AOI_BFCRT01_PT1_DC_MASK (0x3U)AOI_BFCRT01_PT1_DC_SHIFT (0U)AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)AOI_BFCRT01_PT1_CC_MASK (0xCU)AOI_BFCRT01_PT1_CC_SHIFT (2U)AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)AOI_BFCRT01_PT1_BC_MASK (0x30U)AOI_BFCRT01_PT1_BC_SHIFT (4U)AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)AOI_BFCRT01_PT1_AC_MASK (0xC0U)AOI_BFCRT01_PT1_AC_SHIFT (6U)AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)AOI_BFCRT01_PT0_DC_MASK (0x300U)AOI_BFCRT01_PT0_DC_SHIFT (8U)AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)AOI_BFCRT01_PT0_CC_MASK (0xC00U)AOI_BFCRT01_PT0_CC_SHIFT (10U)AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)AOI_BFCRT01_PT0_BC_MASK (0x3000U)AOI_BFCRT01_PT0_BC_SHIFT (12U)AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)AOI_BFCRT01_PT0_AC_MASK (0xC000U)AOI_BFCRT01_PT0_AC_SHIFT (14U)AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)AOI_BFCRT01_COUNT (4U)AOI_BFCRT23_PT3_DC_MASK (0x3U)AOI_BFCRT23_PT3_DC_SHIFT (0U)AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)AOI_BFCRT23_PT3_CC_MASK (0xCU)AOI_BFCRT23_PT3_CC_SHIFT (2U)AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)AOI_BFCRT23_PT3_BC_MASK (0x30U)AOI_BFCRT23_PT3_BC_SHIFT (4U)AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)AOI_BFCRT23_PT3_AC_MASK (0xC0U)AOI_BFCRT23_PT3_AC_SHIFT (6U)AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)AOI_BFCRT23_PT2_DC_MASK (0x300U)AOI_BFCRT23_PT2_DC_SHIFT (8U)AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)AOI_BFCRT23_PT2_CC_MASK (0xC00U)AOI_BFCRT23_PT2_CC_SHIFT (10U)AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)AOI_BFCRT23_PT2_BC_MASK (0x3000U)AOI_BFCRT23_PT2_BC_SHIFT (12U)AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)AOI_BFCRT23_PT2_AC_MASK (0xC000U)AOI_BFCRT23_PT2_AC_SHIFT (14U)AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)AOI_BFCRT23_COUNT (4U)AOI_BASE (0x403B4000u)AOI ((AOI_Type *)AOI_BASE)AOI_BASE_ADDRS { AOI_BASE }AOI_BASE_PTRS { AOI }CAN_MCR_MAXMB_MASK (0x7FU)CAN_MCR_MAXMB_SHIFT (0U)CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)CAN_MCR_IDAM_MASK (0x300U)CAN_MCR_IDAM_SHIFT (8U)CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)CAN_MCR_AEN_MASK (0x1000U)CAN_MCR_AEN_SHIFT (12U)CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)CAN_MCR_LPRIOEN_MASK (0x2000U)CAN_MCR_LPRIOEN_SHIFT (13U)CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)CAN_MCR_IRMQ_MASK (0x10000U)CAN_MCR_IRMQ_SHIFT (16U)CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)CAN_MCR_SRXDIS_MASK (0x20000U)CAN_MCR_SRXDIS_SHIFT (17U)CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)CAN_MCR_WAKSRC_MASK (0x80000U)CAN_MCR_WAKSRC_SHIFT (19U)CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)CAN_MCR_LPMACK_MASK (0x100000U)CAN_MCR_LPMACK_SHIFT (20U)CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)CAN_MCR_WRNEN_MASK (0x200000U)CAN_MCR_WRNEN_SHIFT (21U)CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)CAN_MCR_SLFWAK_MASK (0x400000U)CAN_MCR_SLFWAK_SHIFT (22U)CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)CAN_MCR_SUPV_MASK (0x800000U)CAN_MCR_SUPV_SHIFT (23U)CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)CAN_MCR_FRZACK_MASK (0x1000000U)CAN_MCR_FRZACK_SHIFT (24U)CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)CAN_MCR_SOFTRST_MASK (0x2000000U)CAN_MCR_SOFTRST_SHIFT (25U)CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)CAN_MCR_WAKMSK_MASK (0x4000000U)CAN_MCR_WAKMSK_SHIFT (26U)CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)CAN_MCR_NOTRDY_MASK (0x8000000U)CAN_MCR_NOTRDY_SHIFT (27U)CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)CAN_MCR_HALT_MASK (0x10000000U)CAN_MCR_HALT_SHIFT (28U)CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)CAN_MCR_RFEN_MASK (0x20000000U)CAN_MCR_RFEN_SHIFT (29U)CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)CAN_MCR_FRZ_MASK (0x40000000U)CAN_MCR_FRZ_SHIFT (30U)CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)CAN_MCR_MDIS_MASK (0x80000000U)CAN_MCR_MDIS_SHIFT (31U)CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)CAN_CTRL1_PROPSEG_MASK (0x7U)CAN_CTRL1_PROPSEG_SHIFT (0U)CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)CAN_CTRL1_LOM_MASK (0x8U)CAN_CTRL1_LOM_SHIFT (3U)CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)CAN_CTRL1_LBUF_MASK (0x10U)CAN_CTRL1_LBUF_SHIFT (4U)CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)CAN_CTRL1_TSYN_MASK (0x20U)CAN_CTRL1_TSYN_SHIFT (5U)CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)CAN_CTRL1_BOFFREC_MASK (0x40U)CAN_CTRL1_BOFFREC_SHIFT (6U)CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)CAN_CTRL1_SMP_MASK (0x80U)CAN_CTRL1_SMP_SHIFT (7U)CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)CAN_CTRL1_RWRNMSK_MASK (0x400U)CAN_CTRL1_RWRNMSK_SHIFT (10U)CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)CAN_CTRL1_TWRNMSK_MASK (0x800U)CAN_CTRL1_TWRNMSK_SHIFT (11U)CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)CAN_CTRL1_LPB_MASK (0x1000U)CAN_CTRL1_LPB_SHIFT (12U)CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)CAN_CTRL1_ERRMSK_MASK (0x4000U)CAN_CTRL1_ERRMSK_SHIFT (14U)CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)CAN_CTRL1_BOFFMSK_MASK (0x8000U)CAN_CTRL1_BOFFMSK_SHIFT (15U)CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)CAN_CTRL1_PSEG2_MASK (0x70000U)CAN_CTRL1_PSEG2_SHIFT (16U)CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)CAN_CTRL1_PSEG1_MASK (0x380000U)CAN_CTRL1_PSEG1_SHIFT (19U)CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)CAN_CTRL1_RJW_MASK (0xC00000U)CAN_CTRL1_RJW_SHIFT (22U)CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)CAN_CTRL1_PRESDIV_MASK (0xFF000000U)CAN_CTRL1_PRESDIV_SHIFT (24U)CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)CAN_TIMER_TIMER_MASK (0xFFFFU)CAN_TIMER_TIMER_SHIFT (0U)CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)CAN_RXMGMASK_MG_SHIFT (0U)CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)CAN_RX14MASK_RX14M_SHIFT (0U)CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)CAN_RX15MASK_RX15M_SHIFT (0U)CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)CAN_ESR1_WAKINT_MASK (0x1U)CAN_ESR1_WAKINT_SHIFT (0U)CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)CAN_ESR1_ERRINT_MASK (0x2U)CAN_ESR1_ERRINT_SHIFT (1U)CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)CAN_ESR1_BOFFINT_MASK (0x4U)CAN_ESR1_BOFFINT_SHIFT (2U)CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)CAN_ESR1_RX_MASK (0x8U)CAN_ESR1_RX_SHIFT (3U)CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)CAN_ESR1_FLTCONF_MASK (0x30U)CAN_ESR1_FLTCONF_SHIFT (4U)CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)CAN_ESR1_TX_MASK (0x40U)CAN_ESR1_TX_SHIFT (6U)CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)CAN_ESR1_IDLE_MASK (0x80U)CAN_ESR1_IDLE_SHIFT (7U)CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)CAN_ESR1_RXWRN_MASK (0x100U)CAN_ESR1_RXWRN_SHIFT (8U)CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)CAN_ESR1_TXWRN_MASK (0x200U)CAN_ESR1_TXWRN_SHIFT (9U)CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)CAN_ESR1_STFERR_MASK (0x400U)CAN_ESR1_STFERR_SHIFT (10U)CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)CAN_ESR1_FRMERR_MASK (0x800U)CAN_ESR1_FRMERR_SHIFT (11U)CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)CAN_ESR1_CRCERR_MASK (0x1000U)CAN_ESR1_CRCERR_SHIFT (12U)CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)CAN_ESR1_ACKERR_MASK (0x2000U)CAN_ESR1_ACKERR_SHIFT (13U)CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)CAN_ESR1_BIT0ERR_MASK (0x4000U)CAN_ESR1_BIT0ERR_SHIFT (14U)CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)CAN_ESR1_BIT1ERR_MASK (0x8000U)CAN_ESR1_BIT1ERR_SHIFT (15U)CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)CAN_ESR1_RWRNINT_MASK (0x10000U)CAN_ESR1_RWRNINT_SHIFT (16U)CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)CAN_ESR1_TWRNINT_MASK (0x20000U)CAN_ESR1_TWRNINT_SHIFT (17U)CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)CAN_ESR1_SYNCH_MASK (0x40000U)CAN_ESR1_SYNCH_SHIFT (18U)CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)CAN_IMASK2_BUFHM_SHIFT (0U)CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)CAN_IMASK1_BUFLM_SHIFT (0U)CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)CAN_IFLAG2_BUFHI_SHIFT (0U)CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)CAN_IFLAG1_BUF4TO0I_SHIFT (0U)CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)CAN_IFLAG1_BUF5I_MASK (0x20U)CAN_IFLAG1_BUF5I_SHIFT (5U)CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)CAN_IFLAG1_BUF6I_MASK (0x40U)CAN_IFLAG1_BUF6I_SHIFT (6U)CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)CAN_IFLAG1_BUF7I_MASK (0x80U)CAN_IFLAG1_BUF7I_SHIFT (7U)CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)CAN_IFLAG1_BUF31TO8I_SHIFT (8U)CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)CAN_CTRL2_EACEN_MASK (0x10000U)CAN_CTRL2_EACEN_SHIFT (16U)CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)CAN_CTRL2_RRS_MASK (0x20000U)CAN_CTRL2_RRS_SHIFT (17U)CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)CAN_CTRL2_MRP_MASK (0x40000U)CAN_CTRL2_MRP_SHIFT (18U)CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)CAN_CTRL2_TASD_MASK (0xF80000U)CAN_CTRL2_TASD_SHIFT (19U)CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)CAN_CTRL2_RFFN_MASK (0xF000000U)CAN_CTRL2_RFFN_SHIFT (24U)CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)CAN_CTRL2_WRMFRZ_MASK (0x10000000U)CAN_CTRL2_WRMFRZ_SHIFT (28U)CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)CAN_ESR2_IMB_MASK (0x2000U)CAN_ESR2_IMB_SHIFT (13U)CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)CAN_ESR2_VPS_MASK (0x4000U)CAN_ESR2_VPS_SHIFT (14U)CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)CAN_ESR2_LPTM_MASK (0x7F0000U)CAN_ESR2_LPTM_SHIFT (16U)CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)CAN_CRCR_TXCRC_MASK (0x7FFFU)CAN_CRCR_TXCRC_SHIFT (0U)CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)CAN_CRCR_MBCRC_MASK (0x7F0000U)CAN_CRCR_MBCRC_SHIFT (16U)CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)CAN_RXFGMASK_FGM_SHIFT (0U)CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)CAN_RXFIR_IDHIT_MASK (0x1FFU)CAN_RXFIR_IDHIT_SHIFT (0U)CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)CAN_CS_TIME_STAMP_MASK (0xFFFFU)CAN_CS_TIME_STAMP_SHIFT (0U)CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)CAN_CS_DLC_MASK (0xF0000U)CAN_CS_DLC_SHIFT (16U)CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)CAN_CS_RTR_MASK (0x100000U)CAN_CS_RTR_SHIFT (20U)CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)CAN_CS_IDE_MASK (0x200000U)CAN_CS_IDE_SHIFT (21U)CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)CAN_CS_SRR_MASK (0x400000U)CAN_CS_SRR_SHIFT (22U)CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)CAN_CS_CODE_MASK (0xF000000U)CAN_CS_CODE_SHIFT (24U)CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)CAN_CS_COUNT (64U)CAN_ID_EXT_MASK (0x3FFFFU)CAN_ID_EXT_SHIFT (0U)CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)CAN_ID_STD_MASK (0x1FFC0000U)CAN_ID_STD_SHIFT (18U)CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)CAN_ID_PRIO_MASK (0xE0000000U)CAN_ID_PRIO_SHIFT (29U)CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)CAN_ID_COUNT (64U)CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)CAN_WORD0_DATA_BYTE_3_SHIFT (0U)CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)CAN_WORD0_DATA_BYTE_2_SHIFT (8U)CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)CAN_WORD0_DATA_BYTE_1_SHIFT (16U)CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)CAN_WORD0_DATA_BYTE_0_SHIFT (24U)CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)CAN_WORD0_COUNT (64U)CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)CAN_WORD1_DATA_BYTE_7_SHIFT (0U)CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)CAN_WORD1_DATA_BYTE_6_SHIFT (8U)CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)CAN_WORD1_DATA_BYTE_5_SHIFT (16U)CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)CAN_WORD1_DATA_BYTE_4_SHIFT (24U)CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)CAN_WORD1_COUNT (64U)CAN_RXIMR_MI_MASK (0xFFFFFFFFU)CAN_RXIMR_MI_SHIFT (0U)CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)CAN_RXIMR_COUNT (64U)CAN_GFWR_GFWR_MASK (0xFFU)CAN_GFWR_GFWR_SHIFT (0U)CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)CAN1_BASE (0x401D0000u)CAN1 ((CAN_Type *)CAN1_BASE)CAN2_BASE (0x401D4000u)CAN2 ((CAN_Type *)CAN2_BASE)CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASKCAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFTCAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASKCAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFTCAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)CCM_CCR_OSCNT_MASK (0xFFU)CCM_CCR_OSCNT_SHIFT (0U)CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)CCM_CCR_COSC_EN_MASK (0x1000U)CCM_CCR_COSC_EN_SHIFT (12U)CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)CCM_CCR_RBC_EN_MASK (0x8000000U)CCM_CCR_RBC_EN_SHIFT (27U)CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)CCM_CSR_REF_EN_B_MASK (0x1U)CCM_CSR_REF_EN_B_SHIFT (0U)CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)CCM_CSR_CAMP2_READY_MASK (0x8U)CCM_CSR_CAMP2_READY_SHIFT (3U)CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)CCM_CSR_COSC_READY_MASK (0x20U)CCM_CSR_COSC_READY_SHIFT (5U)CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)CCM_CACRR_ARM_PODF_MASK (0x7U)CCM_CACRR_ARM_PODF_SHIFT (0U)CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)CCM_CBCDR_IPG_PODF_MASK (0x300U)CCM_CBCDR_IPG_PODF_SHIFT (8U)CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)CCM_CBCDR_AHB_PODF_MASK (0x1C00U)CCM_CBCDR_AHB_PODF_SHIFT (10U)CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)CCM_CBCDR_SEMC_PODF_MASK (0x70000U)CCM_CBCDR_SEMC_PODF_SHIFT (16U)CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)CCM_CBCMR_LPSPI_PODF_SHIFT (26U)CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U)CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U)CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK)CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)CCM_CSCDR1_TRACE_PODF_SHIFT (25U)CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U)CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U)CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK)CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0xE000000U)CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U)CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)CCM_CLPCR_LPM_MASK (0x3U)CCM_CLPCR_LPM_SHIFT (0U)CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)CCM_CLPCR_SBYOS_MASK (0x40U)CCM_CLPCR_SBYOS_SHIFT (6U)CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)CCM_CLPCR_VSTBY_MASK (0x100U)CCM_CLPCR_VSTBY_SHIFT (8U)CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)CCM_CLPCR_STBY_COUNT_MASK (0x600U)CCM_CLPCR_STBY_COUNT_SHIFT (9U)CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)CCM_CISR_LRF_PLL_MASK (0x1U)CCM_CISR_LRF_PLL_SHIFT (0U)CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)CCM_CISR_COSC_READY_MASK (0x40U)CCM_CISR_COSC_READY_SHIFT (6U)CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)CCM_CIMR_MASK_COSC_READY_MASK (0x40U)CCM_CIMR_MASK_COSC_READY_SHIFT (6U)CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)CCM_CCOSR_CLKO1_SEL_MASK (0xFU)CCM_CCOSR_CLKO1_SEL_SHIFT (0U)CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)CCM_CCOSR_CLKO1_DIV_MASK (0x70U)CCM_CCOSR_CLKO1_DIV_SHIFT (4U)CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)CCM_CCOSR_CLKO1_EN_MASK (0x80U)CCM_CCOSR_CLKO1_EN_SHIFT (7U)CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)CCM_CCOSR_CLKO2_SEL_SHIFT (16U)CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)CCM_CCOSR_CLKO2_DIV_SHIFT (21U)CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)CCM_CCOSR_CLKO2_EN_SHIFT (24U)CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)CCM_CGPR_FPL_MASK (0x10000U)CCM_CGPR_FPL_SHIFT (16U)CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)CCM_CCGR0_CG0_MASK (0x3U)CCM_CCGR0_CG0_SHIFT (0U)CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)CCM_CCGR0_CG1_MASK (0xCU)CCM_CCGR0_CG1_SHIFT (2U)CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)CCM_CCGR0_CG2_MASK (0x30U)CCM_CCGR0_CG2_SHIFT (4U)CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)CCM_CCGR0_CG3_MASK (0xC0U)CCM_CCGR0_CG3_SHIFT (6U)CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)CCM_CCGR0_CG4_MASK (0x300U)CCM_CCGR0_CG4_SHIFT (8U)CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)CCM_CCGR0_CG5_MASK (0xC00U)CCM_CCGR0_CG5_SHIFT (10U)CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)CCM_CCGR0_CG6_MASK (0x3000U)CCM_CCGR0_CG6_SHIFT (12U)CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)CCM_CCGR0_CG7_MASK (0xC000U)CCM_CCGR0_CG7_SHIFT (14U)CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)CCM_CCGR0_CG8_MASK (0x30000U)CCM_CCGR0_CG8_SHIFT (16U)CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)CCM_CCGR0_CG9_MASK (0xC0000U)CCM_CCGR0_CG9_SHIFT (18U)CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)CCM_CCGR0_CG10_MASK (0x300000U)CCM_CCGR0_CG10_SHIFT (20U)CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)CCM_CCGR0_CG11_MASK (0xC00000U)CCM_CCGR0_CG11_SHIFT (22U)CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)CCM_CCGR0_CG12_MASK (0x3000000U)CCM_CCGR0_CG12_SHIFT (24U)CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)CCM_CCGR0_CG13_MASK (0xC000000U)CCM_CCGR0_CG13_SHIFT (26U)CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)CCM_CCGR0_CG14_MASK (0x30000000U)CCM_CCGR0_CG14_SHIFT (28U)CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)CCM_CCGR0_CG15_MASK (0xC0000000U)CCM_CCGR0_CG15_SHIFT (30U)CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)CCM_CCGR1_CG0_MASK (0x3U)CCM_CCGR1_CG0_SHIFT (0U)CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)CCM_CCGR1_CG1_MASK (0xCU)CCM_CCGR1_CG1_SHIFT (2U)CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)CCM_CCGR1_CG2_MASK (0x30U)CCM_CCGR1_CG2_SHIFT (4U)CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)CCM_CCGR1_CG3_MASK (0xC0U)CCM_CCGR1_CG3_SHIFT (6U)CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)CCM_CCGR1_CG4_MASK (0x300U)CCM_CCGR1_CG4_SHIFT (8U)CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)CCM_CCGR1_CG5_MASK (0xC00U)CCM_CCGR1_CG5_SHIFT (10U)CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)CCM_CCGR1_CG6_MASK (0x3000U)CCM_CCGR1_CG6_SHIFT (12U)CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)CCM_CCGR1_CG7_MASK (0xC000U)CCM_CCGR1_CG7_SHIFT (14U)CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)CCM_CCGR1_CG8_MASK (0x30000U)CCM_CCGR1_CG8_SHIFT (16U)CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)CCM_CCGR1_CG9_MASK (0xC0000U)CCM_CCGR1_CG9_SHIFT (18U)CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)CCM_CCGR1_CG10_MASK (0x300000U)CCM_CCGR1_CG10_SHIFT (20U)CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)CCM_CCGR1_CG11_MASK (0xC00000U)CCM_CCGR1_CG11_SHIFT (22U)CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)CCM_CCGR1_CG12_MASK (0x3000000U)CCM_CCGR1_CG12_SHIFT (24U)CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)CCM_CCGR1_CG13_MASK (0xC000000U)CCM_CCGR1_CG13_SHIFT (26U)CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)CCM_CCGR1_CG14_MASK (0x30000000U)CCM_CCGR1_CG14_SHIFT (28U)CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)CCM_CCGR1_CG15_MASK (0xC0000000U)CCM_CCGR1_CG15_SHIFT (30U)CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)CCM_CCGR2_CG0_MASK (0x3U)CCM_CCGR2_CG0_SHIFT (0U)CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)CCM_CCGR2_CG1_MASK (0xCU)CCM_CCGR2_CG1_SHIFT (2U)CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)CCM_CCGR2_CG2_MASK (0x30U)CCM_CCGR2_CG2_SHIFT (4U)CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)CCM_CCGR2_CG3_MASK (0xC0U)CCM_CCGR2_CG3_SHIFT (6U)CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)CCM_CCGR2_CG4_MASK (0x300U)CCM_CCGR2_CG4_SHIFT (8U)CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)CCM_CCGR2_CG5_MASK (0xC00U)CCM_CCGR2_CG5_SHIFT (10U)CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)CCM_CCGR2_CG6_MASK (0x3000U)CCM_CCGR2_CG6_SHIFT (12U)CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)CCM_CCGR2_CG7_MASK (0xC000U)CCM_CCGR2_CG7_SHIFT (14U)CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)CCM_CCGR2_CG8_MASK (0x30000U)CCM_CCGR2_CG8_SHIFT (16U)CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)CCM_CCGR2_CG9_MASK (0xC0000U)CCM_CCGR2_CG9_SHIFT (18U)CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)CCM_CCGR2_CG10_MASK (0x300000U)CCM_CCGR2_CG10_SHIFT (20U)CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)CCM_CCGR2_CG11_MASK (0xC00000U)CCM_CCGR2_CG11_SHIFT (22U)CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)CCM_CCGR2_CG12_MASK (0x3000000U)CCM_CCGR2_CG12_SHIFT (24U)CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)CCM_CCGR2_CG13_MASK (0xC000000U)CCM_CCGR2_CG13_SHIFT (26U)CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)CCM_CCGR2_CG14_MASK (0x30000000U)CCM_CCGR2_CG14_SHIFT (28U)CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)CCM_CCGR2_CG15_MASK (0xC0000000U)CCM_CCGR2_CG15_SHIFT (30U)CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)CCM_CCGR3_CG0_MASK (0x3U)CCM_CCGR3_CG0_SHIFT (0U)CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)CCM_CCGR3_CG1_MASK (0xCU)CCM_CCGR3_CG1_SHIFT (2U)CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)CCM_CCGR3_CG2_MASK (0x30U)CCM_CCGR3_CG2_SHIFT (4U)CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)CCM_CCGR3_CG3_MASK (0xC0U)CCM_CCGR3_CG3_SHIFT (6U)CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)CCM_CCGR3_CG4_MASK (0x300U)CCM_CCGR3_CG4_SHIFT (8U)CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)CCM_CCGR3_CG5_MASK (0xC00U)CCM_CCGR3_CG5_SHIFT (10U)CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)CCM_CCGR3_CG6_MASK (0x3000U)CCM_CCGR3_CG6_SHIFT (12U)CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)CCM_CCGR3_CG7_MASK (0xC000U)CCM_CCGR3_CG7_SHIFT (14U)CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)CCM_CCGR3_CG8_MASK (0x30000U)CCM_CCGR3_CG8_SHIFT (16U)CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)CCM_CCGR3_CG9_MASK (0xC0000U)CCM_CCGR3_CG9_SHIFT (18U)CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)CCM_CCGR3_CG10_MASK (0x300000U)CCM_CCGR3_CG10_SHIFT (20U)CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)CCM_CCGR3_CG11_MASK (0xC00000U)CCM_CCGR3_CG11_SHIFT (22U)CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)CCM_CCGR3_CG12_MASK (0x3000000U)CCM_CCGR3_CG12_SHIFT (24U)CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)CCM_CCGR3_CG13_MASK (0xC000000U)CCM_CCGR3_CG13_SHIFT (26U)CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)CCM_CCGR3_CG14_MASK (0x30000000U)CCM_CCGR3_CG14_SHIFT (28U)CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)CCM_CCGR3_CG15_MASK (0xC0000000U)CCM_CCGR3_CG15_SHIFT (30U)CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)CCM_CCGR4_CG0_MASK (0x3U)CCM_CCGR4_CG0_SHIFT (0U)CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)CCM_CCGR4_CG1_MASK (0xCU)CCM_CCGR4_CG1_SHIFT (2U)CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)CCM_CCGR4_CG2_MASK (0x30U)CCM_CCGR4_CG2_SHIFT (4U)CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)CCM_CCGR4_CG3_MASK (0xC0U)CCM_CCGR4_CG3_SHIFT (6U)CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)CCM_CCGR4_CG4_MASK (0x300U)CCM_CCGR4_CG4_SHIFT (8U)CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)CCM_CCGR4_CG5_MASK (0xC00U)CCM_CCGR4_CG5_SHIFT (10U)CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)CCM_CCGR4_CG6_MASK (0x3000U)CCM_CCGR4_CG6_SHIFT (12U)CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)CCM_CCGR4_CG7_MASK (0xC000U)CCM_CCGR4_CG7_SHIFT (14U)CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)CCM_CCGR4_CG8_MASK (0x30000U)CCM_CCGR4_CG8_SHIFT (16U)CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)CCM_CCGR4_CG9_MASK (0xC0000U)CCM_CCGR4_CG9_SHIFT (18U)CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)CCM_CCGR4_CG10_MASK (0x300000U)CCM_CCGR4_CG10_SHIFT (20U)CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)CCM_CCGR4_CG11_MASK (0xC00000U)CCM_CCGR4_CG11_SHIFT (22U)CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)CCM_CCGR4_CG12_MASK (0x3000000U)CCM_CCGR4_CG12_SHIFT (24U)CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)CCM_CCGR4_CG13_MASK (0xC000000U)CCM_CCGR4_CG13_SHIFT (26U)CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)CCM_CCGR4_CG14_MASK (0x30000000U)CCM_CCGR4_CG14_SHIFT (28U)CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)CCM_CCGR4_CG15_MASK (0xC0000000U)CCM_CCGR4_CG15_SHIFT (30U)CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)CCM_CCGR5_CG0_MASK (0x3U)CCM_CCGR5_CG0_SHIFT (0U)CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)CCM_CCGR5_CG1_MASK (0xCU)CCM_CCGR5_CG1_SHIFT (2U)CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)CCM_CCGR5_CG2_MASK (0x30U)CCM_CCGR5_CG2_SHIFT (4U)CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)CCM_CCGR5_CG3_MASK (0xC0U)CCM_CCGR5_CG3_SHIFT (6U)CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)CCM_CCGR5_CG4_MASK (0x300U)CCM_CCGR5_CG4_SHIFT (8U)CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)CCM_CCGR5_CG5_MASK (0xC00U)CCM_CCGR5_CG5_SHIFT (10U)CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)CCM_CCGR5_CG6_MASK (0x3000U)CCM_CCGR5_CG6_SHIFT (12U)CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)CCM_CCGR5_CG7_MASK (0xC000U)CCM_CCGR5_CG7_SHIFT (14U)CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)CCM_CCGR5_CG8_MASK (0x30000U)CCM_CCGR5_CG8_SHIFT (16U)CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)CCM_CCGR5_CG9_MASK (0xC0000U)CCM_CCGR5_CG9_SHIFT (18U)CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)CCM_CCGR5_CG10_MASK (0x300000U)CCM_CCGR5_CG10_SHIFT (20U)CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)CCM_CCGR5_CG11_MASK (0xC00000U)CCM_CCGR5_CG11_SHIFT (22U)CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)CCM_CCGR5_CG12_MASK (0x3000000U)CCM_CCGR5_CG12_SHIFT (24U)CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)CCM_CCGR5_CG13_MASK (0xC000000U)CCM_CCGR5_CG13_SHIFT (26U)CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)CCM_CCGR5_CG14_MASK (0x30000000U)CCM_CCGR5_CG14_SHIFT (28U)CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)CCM_CCGR5_CG15_MASK (0xC0000000U)CCM_CCGR5_CG15_SHIFT (30U)CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)CCM_CCGR6_CG0_MASK (0x3U)CCM_CCGR6_CG0_SHIFT (0U)CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)CCM_CCGR6_CG1_MASK (0xCU)CCM_CCGR6_CG1_SHIFT (2U)CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)CCM_CCGR6_CG2_MASK (0x30U)CCM_CCGR6_CG2_SHIFT (4U)CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)CCM_CCGR6_CG3_MASK (0xC0U)CCM_CCGR6_CG3_SHIFT (6U)CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)CCM_CCGR6_CG4_MASK (0x300U)CCM_CCGR6_CG4_SHIFT (8U)CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)CCM_CCGR6_CG5_MASK (0xC00U)CCM_CCGR6_CG5_SHIFT (10U)CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)CCM_CCGR6_CG6_MASK (0x3000U)CCM_CCGR6_CG6_SHIFT (12U)CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)CCM_CCGR6_CG7_MASK (0xC000U)CCM_CCGR6_CG7_SHIFT (14U)CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)CCM_CCGR6_CG8_MASK (0x30000U)CCM_CCGR6_CG8_SHIFT (16U)CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)CCM_CCGR6_CG9_MASK (0xC0000U)CCM_CCGR6_CG9_SHIFT (18U)CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)CCM_CCGR6_CG10_MASK (0x300000U)CCM_CCGR6_CG10_SHIFT (20U)CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)CCM_CCGR6_CG11_MASK (0xC00000U)CCM_CCGR6_CG11_SHIFT (22U)CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)CCM_CCGR6_CG12_MASK (0x3000000U)CCM_CCGR6_CG12_SHIFT (24U)CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)CCM_CCGR6_CG13_MASK (0xC000000U)CCM_CCGR6_CG13_SHIFT (26U)CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)CCM_CCGR6_CG14_MASK (0x30000000U)CCM_CCGR6_CG14_SHIFT (28U)CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)CCM_CCGR6_CG15_MASK (0xC0000000U)CCM_CCGR6_CG15_SHIFT (30U)CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)CCM_BASE (0x400FC000u)CCM ((CCM_Type *)CCM_BASE)CCM_BASE_ADDRS { CCM_BASE }CCM_BASE_PTRS { CCM }CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU)CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U)CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U)CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U)CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK)CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U)CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U)CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK)CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U)CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U)CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK)CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK (0x400000U)CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT (22U)CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU)CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U)CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U)CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U)CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK)CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U)CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U)CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK)CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U)CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U)CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK)CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK (0x400000U)CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT (22U)CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU)CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U)CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U)CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U)CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U)CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U)CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U)CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U)CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK (0x400000U)CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT (22U)CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU)CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U)CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U)CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U)CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U)CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U)CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U)CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U)CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK (0x400000U)CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT (22U)CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)!CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)!CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)!CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)!CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)!CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)!CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)!CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)!CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)!CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)!CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)!CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)!CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)!CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)!CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)!CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)!CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)!CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)!CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)!CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)!CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)!CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)!CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)!CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)!CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)!CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)!CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)!CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)!CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)!CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)!CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)!CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)!CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)!CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)!CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)!CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)!CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)!CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)!CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)!CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)!CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)!CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)!CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)!CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)!CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)!CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)!CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)!CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)!CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)!CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)!CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)!CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)!CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)!CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)!CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)!CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)!CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)!CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)!CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)!CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)!CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)!CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)!CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)!CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)!CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)!CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)!CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)!CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)!CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)!CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)!CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)!CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)!CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)!CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)!CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)!CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)!CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)!CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)!CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)!CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)!CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)!CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)!CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)!CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)!CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)!CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)!CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)!CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)!CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)!CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)!CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)!CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)!CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)!CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)!CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)!CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)!CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)!CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)!CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)!CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)!CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)!CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)!CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)!CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)"CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)"CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)"CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)"CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)"CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)"CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)"CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)"CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)"CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)"CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)"CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)"CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)"CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)"CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)"CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)"CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)"CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)"CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)"CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)"CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)"CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)"CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)"CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)"CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)"CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)"CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)"CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)"CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)"CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)"CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)"CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)"CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)"CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)"CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)"CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)"CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)"CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)"CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)"CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)"CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)"CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)"CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)"CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)"CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)"CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)"CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)"CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)"CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)"CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)"CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)"CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)"CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)"CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)"CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)"CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)"CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)"CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)"CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)"CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)"CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)"CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)"CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)"CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)"CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)"CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)"CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)"CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)"CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)"CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)"CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)"CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)"CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)"CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)"CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)"CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)"CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)"CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)"CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)"CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)"CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)"CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)"CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)"CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)"CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)"CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)"CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)"CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)"CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)#CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)#CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)#CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)#CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)#CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)#CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)#CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)#CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)#CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)#CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)#CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)#CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)#CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)#CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)#CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)#CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)#CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)#CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)#CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)#CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)#CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)#CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)#CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)#CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)#CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)#CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)#CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)#CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)#CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)#CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)#CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)#CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)#CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)#CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)#CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)#CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)#CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)#CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)#CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)#CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)#CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)#CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)#CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)#CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)#CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)#CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)#CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)#CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)#CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)#CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)#CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)#CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)#CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)#CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)#CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)#CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)#CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)#CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)#CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U)#CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U)#CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)#CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)#CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)#CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)#CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)#CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)#CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)#CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)#CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)#CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)#CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)#CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)$CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)$CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)$CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)$CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)$CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)$CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)$CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)$CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)$CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)$CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)$CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)$CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)$CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)$CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)$CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)$CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)$CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)$CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)$CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)$CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)$CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)$CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)$CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)$CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)$CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)$CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)$CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)$CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)$CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)$CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)$CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)$CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)$CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)$CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)$CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)$CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)$CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)$CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)$CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)$CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U)$CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U)$CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)$CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)$CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)$CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)$CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)$CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)$CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)$CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)$CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)$CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)$CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)$CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)$CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)$CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)$CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)$CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)$CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)$CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)$CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)$CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)$CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)$CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)$CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)$CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)$CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)$CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)$CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)$CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)$CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)$CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)$CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)$CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)$CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)$CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)$CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)$CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)$CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)$CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)$CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)$CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)$CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)$CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)$CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)$CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U)$CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U)$CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK)$CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)$CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)$CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)$CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)$CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)$CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)$CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)$CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)$CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)$CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)$CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)$CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)$CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)$CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)$CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)%CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)%CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)%CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)%CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)%CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)%CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)%CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)%CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)%CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)%CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)%CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)%CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)%CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)%CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)%CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)%CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)%CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)%CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)%CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)%CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)%CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)%CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)%CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)%CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)%CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)%CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)%CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)%CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)%CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)%CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)%CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)%CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)%CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)%CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)%CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)%CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)%CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)%CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U)%CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U)%CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK)%CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)%CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)%CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)%CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)%CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)%CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)%CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)%CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)%CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)%CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)%CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)%CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)%CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)%CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)%CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)%CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)%CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)%CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)%CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)%CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)%CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)%CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)%CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)%CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)%CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)%CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)%CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)%CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)%CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)%CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)%CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)%CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)%CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)%CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)%CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)%CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)%CCM_ANALOG_BASE (0x400D8000u)%CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)%CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }%CCM_ANALOG_BASE_PTRS { CCM_ANALOG }&CMP_CR0_HYSTCTR_MASK (0x3U)&CMP_CR0_HYSTCTR_SHIFT (0U)&CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)&CMP_CR0_FILTER_CNT_MASK (0x70U)&CMP_CR0_FILTER_CNT_SHIFT (4U)&CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)&CMP_CR1_EN_MASK (0x1U)&CMP_CR1_EN_SHIFT (0U)&CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)&CMP_CR1_OPE_MASK (0x2U)&CMP_CR1_OPE_SHIFT (1U)&CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)&CMP_CR1_COS_MASK (0x4U)&CMP_CR1_COS_SHIFT (2U)&CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)&CMP_CR1_INV_MASK (0x8U)&CMP_CR1_INV_SHIFT (3U)&CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)&CMP_CR1_PMODE_MASK (0x10U)&CMP_CR1_PMODE_SHIFT (4U)&CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)&CMP_CR1_WE_MASK (0x40U)&CMP_CR1_WE_SHIFT (6U)&CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)&CMP_CR1_SE_MASK (0x80U)&CMP_CR1_SE_SHIFT (7U)&CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)&CMP_FPR_FILT_PER_MASK (0xFFU)&CMP_FPR_FILT_PER_SHIFT (0U)&CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)&CMP_SCR_COUT_MASK (0x1U)&CMP_SCR_COUT_SHIFT (0U)&CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)&CMP_SCR_CFF_MASK (0x2U)&CMP_SCR_CFF_SHIFT (1U)&CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)&CMP_SCR_CFR_MASK (0x4U)&CMP_SCR_CFR_SHIFT (2U)&CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)&CMP_SCR_IEF_MASK (0x8U)&CMP_SCR_IEF_SHIFT (3U)&CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)&CMP_SCR_IER_MASK (0x10U)&CMP_SCR_IER_SHIFT (4U)&CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)&CMP_SCR_DMAEN_MASK (0x40U)&CMP_SCR_DMAEN_SHIFT (6U)&CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)&CMP_DACCR_VOSEL_MASK (0x3FU)&CMP_DACCR_VOSEL_SHIFT (0U)&CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)&CMP_DACCR_VRSEL_MASK (0x40U)&CMP_DACCR_VRSEL_SHIFT (6U)&CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)&CMP_DACCR_DACEN_MASK (0x80U)&CMP_DACCR_DACEN_SHIFT (7U)&CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)&CMP_MUXCR_MSEL_MASK (0x7U)&CMP_MUXCR_MSEL_SHIFT (0U)&CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)&CMP_MUXCR_PSEL_MASK (0x38U)&CMP_MUXCR_PSEL_SHIFT (3U)&CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)&CMP1_BASE (0x40094000u)&CMP1 ((CMP_Type *)CMP1_BASE)&CMP2_BASE (0x40094008u)&CMP2 ((CMP_Type *)CMP2_BASE)&CMP3_BASE (0x40094010u)&CMP3 ((CMP_Type *)CMP3_BASE)&CMP4_BASE (0x40094018u)&CMP4 ((CMP_Type *)CMP4_BASE)&CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }&CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }&CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }'DCDC_REG0_PWD_ZCD_MASK (0x1U)'DCDC_REG0_PWD_ZCD_SHIFT (0U)'DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)'DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)'DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)'DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)'DCDC_REG0_SEL_CLK_MASK (0x4U)'DCDC_REG0_SEL_CLK_SHIFT (2U)'DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)'DCDC_REG0_PWD_OSC_INT_MASK (0x8U)'DCDC_REG0_PWD_OSC_INT_SHIFT (3U)'DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)'DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)'DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)'DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)'DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)'DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)'DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)'DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)'DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)'DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)'DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)'DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)'DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)'DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)'DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)'DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)'DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)'DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)'DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)'DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)'DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)'DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)'DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)'DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)'DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)'DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)'DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)'DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)'DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)'DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)'DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)'DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)'DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)'DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)'DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)'DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)'DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)'DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)'DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)'DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)'DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)'DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)'DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)'DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)'DCDC_REG0_XTAL_24M_OK_SHIFT (29U)'DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)'DCDC_REG0_STS_DC_OK_MASK (0x80000000U)'DCDC_REG0_STS_DC_OK_SHIFT (31U)'DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)'DCDC_REG1_REG_FBK_SEL_MASK (0x180U)'DCDC_REG1_REG_FBK_SEL_SHIFT (7U)'DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)'DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)'DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)'DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)'DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)'DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)'DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)'DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)'DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)'DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)'DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)'DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)'DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)'DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)'DCDC_REG1_VBG_TRIM_SHIFT (24U)'DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)'DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)'DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)'DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)'DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)'DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)'DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)'DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)'DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)'DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)'DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)'DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)(DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)(DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)(DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)(DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)(DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)(DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)(DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)(DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)(DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)(DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)(DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)(DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)(DCDC_REG3_TRG_MASK (0x1FU)(DCDC_REG3_TRG_SHIFT (0U)(DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)(DCDC_REG3_TARGET_LP_MASK (0x700U)(DCDC_REG3_TARGET_LP_SHIFT (8U)(DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)(DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)(DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)(DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)(DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)(DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)(DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)(DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)(DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)(DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)(DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)(DCDC_REG3_DISABLE_STEP_SHIFT (30U)(DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)(DCDC_BASE (0x40080000u)(DCDC ((DCDC_Type *)DCDC_BASE)(DCDC_BASE_ADDRS { DCDC_BASE }(DCDC_BASE_PTRS { DCDC }(DCDC_IRQS { DCDC_IRQn })DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU))DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U))DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK))DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U))DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U))DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK))DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U))DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U))DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK))DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U))DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U))DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK))DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U))DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U))DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK))DCP_CTRL_PRESENT_SHA_MASK (0x10000000U))DCP_CTRL_PRESENT_SHA_SHIFT (28U))DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK))DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U))DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U))DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK))DCP_CTRL_CLKGATE_MASK (0x40000000U))DCP_CTRL_CLKGATE_SHIFT (30U))DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK))DCP_CTRL_SFTRST_MASK (0x80000000U))DCP_CTRL_SFTRST_SHIFT (31U))DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK))DCP_STAT_IRQ_MASK (0xFU))DCP_STAT_IRQ_SHIFT (0U))DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK))DCP_STAT_RSVD_IRQ_MASK (0x100U))DCP_STAT_RSVD_IRQ_SHIFT (8U))DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK))DCP_STAT_READY_CHANNELS_MASK (0xFF0000U))DCP_STAT_READY_CHANNELS_SHIFT (16U))DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK))DCP_STAT_CUR_CHANNEL_MASK (0xF000000U))DCP_STAT_CUR_CHANNEL_SHIFT (24U))DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK))DCP_STAT_OTP_KEY_READY_MASK (0x10000000U))DCP_STAT_OTP_KEY_READY_SHIFT (28U))DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK))DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU))DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U))DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK))DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U))DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U))DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK))DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U))DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U))DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK))DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U))DCP_CHANNELCTRL_RSVD_SHIFT (17U))DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK))DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU))DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U))DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK))DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U))DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U))DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK))DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U))DCP_CAPABILITY0_RSVD_SHIFT (12U))DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK))DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U))DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U))DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK))DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U))DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U))DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK))DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU))DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U))DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK))DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U))DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U))DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK))DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU))DCP_CONTEXT_ADDR_SHIFT (0U))DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK))DCP_KEY_SUBWORD_MASK (0x3U)*DCP_KEY_SUBWORD_SHIFT (0U)*DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)*DCP_KEY_RSVD_SUBWORD_MASK (0xCU)*DCP_KEY_RSVD_SUBWORD_SHIFT (2U)*DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)*DCP_KEY_INDEX_MASK (0x30U)*DCP_KEY_INDEX_SHIFT (4U)*DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)*DCP_KEY_RSVD_INDEX_MASK (0xC0U)*DCP_KEY_RSVD_INDEX_SHIFT (6U)*DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)*DCP_KEY_RSVD_MASK (0xFFFFFF00U)*DCP_KEY_RSVD_SHIFT (8U)*DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)*DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)*DCP_KEYDATA_DATA_SHIFT (0U)*DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)*DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)*DCP_PACKET0_ADDR_SHIFT (0U)*DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)*DCP_PACKET1_INTERRUPT_MASK (0x1U)*DCP_PACKET1_INTERRUPT_SHIFT (0U)*DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)*DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)*DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)*DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)*DCP_PACKET1_CHAIN_MASK (0x4U)*DCP_PACKET1_CHAIN_SHIFT (2U)*DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)*DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)*DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)*DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)*DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)*DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)*DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)*DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)*DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)*DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)*DCP_PACKET1_ENABLE_HASH_MASK (0x40U)*DCP_PACKET1_ENABLE_HASH_SHIFT (6U)*DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)*DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)*DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)*DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)*DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)*DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)*DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)*DCP_PACKET1_CIPHER_INIT_MASK (0x200U)*DCP_PACKET1_CIPHER_INIT_SHIFT (9U)*DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)*DCP_PACKET1_OTP_KEY_MASK (0x400U)*DCP_PACKET1_OTP_KEY_SHIFT (10U)*DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)*DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)*DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)*DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)*DCP_PACKET1_HASH_INIT_MASK (0x1000U)*DCP_PACKET1_HASH_INIT_SHIFT (12U)*DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)*DCP_PACKET1_HASH_TERM_MASK (0x2000U)*DCP_PACKET1_HASH_TERM_SHIFT (13U)*DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)*DCP_PACKET1_CHECK_HASH_MASK (0x4000U)*DCP_PACKET1_CHECK_HASH_SHIFT (14U)*DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)*DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)*DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)*DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)*DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)*DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)*DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)*DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)*DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)*DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)*DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)*DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)*DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)*DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)*DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)*DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)*DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)*DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)*DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)*DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)*DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)*DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)*DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)*DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)*DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)*DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)*DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)*DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)*DCP_PACKET1_TAG_MASK (0xFF000000U)*DCP_PACKET1_TAG_SHIFT (24U)*DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)*DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)*DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)*DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)*DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)*DCP_PACKET2_CIPHER_MODE_SHIFT (4U)*DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)*DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)*DCP_PACKET2_KEY_SELECT_SHIFT (8U)*DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)*DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)*DCP_PACKET2_HASH_SELECT_SHIFT (16U)*DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)*DCP_PACKET2_RSVD_MASK (0xF00000U)*DCP_PACKET2_RSVD_SHIFT (20U)*DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)*DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)*DCP_PACKET2_CIPHER_CFG_SHIFT (24U)+DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)+DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)+DCP_PACKET3_ADDR_SHIFT (0U)+DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)+DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)+DCP_PACKET4_ADDR_SHIFT (0U)+DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)+DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)+DCP_PACKET5_COUNT_SHIFT (0U)+DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)+DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)+DCP_PACKET6_ADDR_SHIFT (0U)+DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)+DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)+DCP_CH0CMDPTR_ADDR_SHIFT (0U)+DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)+DCP_CH0SEMA_INCREMENT_MASK (0xFFU)+DCP_CH0SEMA_INCREMENT_SHIFT (0U)+DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)+DCP_CH0SEMA_VALUE_MASK (0xFF0000U)+DCP_CH0SEMA_VALUE_SHIFT (16U)+DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)+DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)+DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)+DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)+DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)+DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)+DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)+DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)+DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)+DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)+DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)+DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)+DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)+DCP_CH0STAT_ERROR_SRC_MASK (0x10U)+DCP_CH0STAT_ERROR_SRC_SHIFT (4U)+DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)+DCP_CH0STAT_ERROR_DST_MASK (0x20U)+DCP_CH0STAT_ERROR_DST_SHIFT (5U)+DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)+DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)+DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)+DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)+DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)+DCP_CH0STAT_ERROR_CODE_SHIFT (16U)+DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)+DCP_CH0STAT_TAG_MASK (0xFF000000U)+DCP_CH0STAT_TAG_SHIFT (24U)+DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)+DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)+DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)+DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)+DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)+DCP_CH0OPTS_RSVD_SHIFT (16U)+DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)+DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)+DCP_CH1CMDPTR_ADDR_SHIFT (0U)+DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)+DCP_CH1SEMA_INCREMENT_MASK (0xFFU)+DCP_CH1SEMA_INCREMENT_SHIFT (0U)+DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)+DCP_CH1SEMA_VALUE_MASK (0xFF0000U)+DCP_CH1SEMA_VALUE_SHIFT (16U)+DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)+DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)+DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)+DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)+DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)+DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)+DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)+DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)+DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)+DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)+DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)+DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)+DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)+DCP_CH1STAT_ERROR_SRC_MASK (0x10U)+DCP_CH1STAT_ERROR_SRC_SHIFT (4U)+DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)+DCP_CH1STAT_ERROR_DST_MASK (0x20U)+DCP_CH1STAT_ERROR_DST_SHIFT (5U)+DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)+DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)+DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U),DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK),DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U),DCP_CH1STAT_ERROR_CODE_SHIFT (16U),DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK),DCP_CH1STAT_TAG_MASK (0xFF000000U),DCP_CH1STAT_TAG_SHIFT (24U),DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK),DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU),DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U),DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK),DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U),DCP_CH1OPTS_RSVD_SHIFT (16U),DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK),DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU),DCP_CH2CMDPTR_ADDR_SHIFT (0U),DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK),DCP_CH2SEMA_INCREMENT_MASK (0xFFU),DCP_CH2SEMA_INCREMENT_SHIFT (0U),DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK),DCP_CH2SEMA_VALUE_MASK (0xFF0000U),DCP_CH2SEMA_VALUE_SHIFT (16U),DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK),DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U),DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U),DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK),DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U),DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U),DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK),DCP_CH2STAT_ERROR_SETUP_MASK (0x4U),DCP_CH2STAT_ERROR_SETUP_SHIFT (2U),DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK),DCP_CH2STAT_ERROR_PACKET_MASK (0x8U),DCP_CH2STAT_ERROR_PACKET_SHIFT (3U),DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK),DCP_CH2STAT_ERROR_SRC_MASK (0x10U),DCP_CH2STAT_ERROR_SRC_SHIFT (4U),DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK),DCP_CH2STAT_ERROR_DST_MASK (0x20U),DCP_CH2STAT_ERROR_DST_SHIFT (5U),DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK),DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U),DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U),DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK),DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U),DCP_CH2STAT_ERROR_CODE_SHIFT (16U),DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK),DCP_CH2STAT_TAG_MASK (0xFF000000U),DCP_CH2STAT_TAG_SHIFT (24U),DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK),DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU),DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U),DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK),DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U),DCP_CH2OPTS_RSVD_SHIFT (16U),DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK),DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU),DCP_CH3CMDPTR_ADDR_SHIFT (0U),DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK),DCP_CH3SEMA_INCREMENT_MASK (0xFFU),DCP_CH3SEMA_INCREMENT_SHIFT (0U),DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK),DCP_CH3SEMA_VALUE_MASK (0xFF0000U),DCP_CH3SEMA_VALUE_SHIFT (16U),DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK),DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U),DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U),DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK),DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U),DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U),DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK),DCP_CH3STAT_ERROR_SETUP_MASK (0x4U),DCP_CH3STAT_ERROR_SETUP_SHIFT (2U),DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK),DCP_CH3STAT_ERROR_PACKET_MASK (0x8U),DCP_CH3STAT_ERROR_PACKET_SHIFT (3U),DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK),DCP_CH3STAT_ERROR_SRC_MASK (0x10U),DCP_CH3STAT_ERROR_SRC_SHIFT (4U),DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK),DCP_CH3STAT_ERROR_DST_MASK (0x20U),DCP_CH3STAT_ERROR_DST_SHIFT (5U),DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK),DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U),DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U),DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK),DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U),DCP_CH3STAT_ERROR_CODE_SHIFT (16U),DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK),DCP_CH3STAT_TAG_MASK (0xFF000000U),DCP_CH3STAT_TAG_SHIFT (24U),DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK),DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)-DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)-DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)-DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)-DCP_CH3OPTS_RSVD_SHIFT (16U)-DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)-DCP_DBGSELECT_INDEX_MASK (0xFFU)-DCP_DBGSELECT_INDEX_SHIFT (0U)-DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)-DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)-DCP_DBGSELECT_RSVD_SHIFT (8U)-DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)-DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)-DCP_DBGDATA_DATA_SHIFT (0U)-DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)-DCP_PAGETABLE_ENABLE_MASK (0x1U)-DCP_PAGETABLE_ENABLE_SHIFT (0U)-DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)-DCP_PAGETABLE_FLUSH_MASK (0x2U)-DCP_PAGETABLE_FLUSH_SHIFT (1U)-DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)-DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)-DCP_PAGETABLE_BASE_SHIFT (2U)-DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)-DCP_VERSION_STEP_MASK (0xFFFFU)-DCP_VERSION_STEP_SHIFT (0U)-DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)-DCP_VERSION_MINOR_MASK (0xFF0000U)-DCP_VERSION_MINOR_SHIFT (16U)-DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)-DCP_VERSION_MAJOR_MASK (0xFF000000U)-DCP_VERSION_MAJOR_SHIFT (24U)-DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)-DCP_BASE (0x402FC000u)-DCP ((DCP_Type *)DCP_BASE)-DCP_BASE_ADDRS { DCP_BASE }-DCP_BASE_PTRS { DCP }-DCP_IRQS { DCP_IRQn }-DCP_VMI_IRQS { DCP_VMI_IRQn }.DMA_CR_EDBG_MASK (0x2U).DMA_CR_EDBG_SHIFT (1U).DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK).DMA_CR_ERCA_MASK (0x4U).DMA_CR_ERCA_SHIFT (2U).DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK).DMA_CR_ERGA_MASK (0x8U).DMA_CR_ERGA_SHIFT (3U).DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK).DMA_CR_HOE_MASK (0x10U).DMA_CR_HOE_SHIFT (4U).DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK).DMA_CR_HALT_MASK (0x20U).DMA_CR_HALT_SHIFT (5U).DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK).DMA_CR_CLM_MASK (0x40U).DMA_CR_CLM_SHIFT (6U).DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK).DMA_CR_EMLM_MASK (0x80U).DMA_CR_EMLM_SHIFT (7U).DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK).DMA_CR_GRP0PRI_MASK (0x100U).DMA_CR_GRP0PRI_SHIFT (8U).DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK).DMA_CR_GRP1PRI_MASK (0x400U).DMA_CR_GRP1PRI_SHIFT (10U).DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK).DMA_CR_ECX_MASK (0x10000U).DMA_CR_ECX_SHIFT (16U).DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK).DMA_CR_CX_MASK (0x20000U).DMA_CR_CX_SHIFT (17U).DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK).DMA_CR_ACTIVE_MASK (0x80000000U).DMA_CR_ACTIVE_SHIFT (31U).DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK).DMA_ES_DBE_MASK (0x1U).DMA_ES_DBE_SHIFT (0U).DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK).DMA_ES_SBE_MASK (0x2U).DMA_ES_SBE_SHIFT (1U).DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK).DMA_ES_SGE_MASK (0x4U).DMA_ES_SGE_SHIFT (2U).DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK).DMA_ES_NCE_MASK (0x8U).DMA_ES_NCE_SHIFT (3U).DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK).DMA_ES_DOE_MASK (0x10U).DMA_ES_DOE_SHIFT (4U).DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK).DMA_ES_DAE_MASK (0x20U).DMA_ES_DAE_SHIFT (5U).DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK).DMA_ES_SOE_MASK (0x40U).DMA_ES_SOE_SHIFT (6U).DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK).DMA_ES_SAE_MASK (0x80U).DMA_ES_SAE_SHIFT (7U).DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK).DMA_ES_ERRCHN_MASK (0x1F00U).DMA_ES_ERRCHN_SHIFT (8U).DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK).DMA_ES_CPE_MASK (0x4000U).DMA_ES_CPE_SHIFT (14U).DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK).DMA_ES_GPE_MASK (0x8000U).DMA_ES_GPE_SHIFT (15U).DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK).DMA_ES_ECX_MASK (0x10000U).DMA_ES_ECX_SHIFT (16U).DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK).DMA_ES_VLD_MASK (0x80000000U)/DMA_ES_VLD_SHIFT (31U)/DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)/DMA_ERQ_ERQ0_MASK (0x1U)/DMA_ERQ_ERQ0_SHIFT (0U)/DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)/DMA_ERQ_ERQ1_MASK (0x2U)/DMA_ERQ_ERQ1_SHIFT (1U)/DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)/DMA_ERQ_ERQ2_MASK (0x4U)/DMA_ERQ_ERQ2_SHIFT (2U)/DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)/DMA_ERQ_ERQ3_MASK (0x8U)/DMA_ERQ_ERQ3_SHIFT (3U)/DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)/DMA_ERQ_ERQ4_MASK (0x10U)/DMA_ERQ_ERQ4_SHIFT (4U)/DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)/DMA_ERQ_ERQ5_MASK (0x20U)/DMA_ERQ_ERQ5_SHIFT (5U)/DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)/DMA_ERQ_ERQ6_MASK (0x40U)/DMA_ERQ_ERQ6_SHIFT (6U)/DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)/DMA_ERQ_ERQ7_MASK (0x80U)/DMA_ERQ_ERQ7_SHIFT (7U)/DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)/DMA_ERQ_ERQ8_MASK (0x100U)/DMA_ERQ_ERQ8_SHIFT (8U)/DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)/DMA_ERQ_ERQ9_MASK (0x200U)/DMA_ERQ_ERQ9_SHIFT (9U)/DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)/DMA_ERQ_ERQ10_MASK (0x400U)/DMA_ERQ_ERQ10_SHIFT (10U)/DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)/DMA_ERQ_ERQ11_MASK (0x800U)/DMA_ERQ_ERQ11_SHIFT (11U)/DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)/DMA_ERQ_ERQ12_MASK (0x1000U)/DMA_ERQ_ERQ12_SHIFT (12U)/DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)/DMA_ERQ_ERQ13_MASK (0x2000U)/DMA_ERQ_ERQ13_SHIFT (13U)/DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)/DMA_ERQ_ERQ14_MASK (0x4000U)/DMA_ERQ_ERQ14_SHIFT (14U)/DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)/DMA_ERQ_ERQ15_MASK (0x8000U)/DMA_ERQ_ERQ15_SHIFT (15U)/DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)/DMA_ERQ_ERQ16_MASK (0x10000U)/DMA_ERQ_ERQ16_SHIFT (16U)/DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)/DMA_ERQ_ERQ17_MASK (0x20000U)/DMA_ERQ_ERQ17_SHIFT (17U)/DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)/DMA_ERQ_ERQ18_MASK (0x40000U)/DMA_ERQ_ERQ18_SHIFT (18U)/DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)/DMA_ERQ_ERQ19_MASK (0x80000U)/DMA_ERQ_ERQ19_SHIFT (19U)/DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)/DMA_ERQ_ERQ20_MASK (0x100000U)/DMA_ERQ_ERQ20_SHIFT (20U)/DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)/DMA_ERQ_ERQ21_MASK (0x200000U)/DMA_ERQ_ERQ21_SHIFT (21U)/DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)/DMA_ERQ_ERQ22_MASK (0x400000U)/DMA_ERQ_ERQ22_SHIFT (22U)/DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)/DMA_ERQ_ERQ23_MASK (0x800000U)/DMA_ERQ_ERQ23_SHIFT (23U)/DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)/DMA_ERQ_ERQ24_MASK (0x1000000U)/DMA_ERQ_ERQ24_SHIFT (24U)/DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)/DMA_ERQ_ERQ25_MASK (0x2000000U)/DMA_ERQ_ERQ25_SHIFT (25U)/DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)/DMA_ERQ_ERQ26_MASK (0x4000000U)/DMA_ERQ_ERQ26_SHIFT (26U)/DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)/DMA_ERQ_ERQ27_MASK (0x8000000U)/DMA_ERQ_ERQ27_SHIFT (27U)/DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)/DMA_ERQ_ERQ28_MASK (0x10000000U)/DMA_ERQ_ERQ28_SHIFT (28U)/DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)/DMA_ERQ_ERQ29_MASK (0x20000000U)/DMA_ERQ_ERQ29_SHIFT (29U)/DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)/DMA_ERQ_ERQ30_MASK (0x40000000U)/DMA_ERQ_ERQ30_SHIFT (30U)/DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)/DMA_ERQ_ERQ31_MASK (0x80000000U)/DMA_ERQ_ERQ31_SHIFT (31U)/DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)/DMA_EEI_EEI0_MASK (0x1U)/DMA_EEI_EEI0_SHIFT (0U)/DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)/DMA_EEI_EEI1_MASK (0x2U)/DMA_EEI_EEI1_SHIFT (1U)/DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)/DMA_EEI_EEI2_MASK (0x4U)/DMA_EEI_EEI2_SHIFT (2U)/DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)/DMA_EEI_EEI3_MASK (0x8U)/DMA_EEI_EEI3_SHIFT (3U)/DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)/DMA_EEI_EEI4_MASK (0x10U)/DMA_EEI_EEI4_SHIFT (4U)/DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)/DMA_EEI_EEI5_MASK (0x20U)/DMA_EEI_EEI5_SHIFT (5U)/DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)/DMA_EEI_EEI6_MASK (0x40U)/DMA_EEI_EEI6_SHIFT (6U)/DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)/DMA_EEI_EEI7_MASK (0x80U)0DMA_EEI_EEI7_SHIFT (7U)0DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)0DMA_EEI_EEI8_MASK (0x100U)0DMA_EEI_EEI8_SHIFT (8U)0DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)0DMA_EEI_EEI9_MASK (0x200U)0DMA_EEI_EEI9_SHIFT (9U)0DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)0DMA_EEI_EEI10_MASK (0x400U)0DMA_EEI_EEI10_SHIFT (10U)0DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)0DMA_EEI_EEI11_MASK (0x800U)0DMA_EEI_EEI11_SHIFT (11U)0DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)0DMA_EEI_EEI12_MASK (0x1000U)0DMA_EEI_EEI12_SHIFT (12U)0DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)0DMA_EEI_EEI13_MASK (0x2000U)0DMA_EEI_EEI13_SHIFT (13U)0DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)0DMA_EEI_EEI14_MASK (0x4000U)0DMA_EEI_EEI14_SHIFT (14U)0DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)0DMA_EEI_EEI15_MASK (0x8000U)0DMA_EEI_EEI15_SHIFT (15U)0DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)0DMA_EEI_EEI16_MASK (0x10000U)0DMA_EEI_EEI16_SHIFT (16U)0DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)0DMA_EEI_EEI17_MASK (0x20000U)0DMA_EEI_EEI17_SHIFT (17U)0DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)0DMA_EEI_EEI18_MASK (0x40000U)0DMA_EEI_EEI18_SHIFT (18U)0DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)0DMA_EEI_EEI19_MASK (0x80000U)0DMA_EEI_EEI19_SHIFT (19U)0DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)0DMA_EEI_EEI20_MASK (0x100000U)0DMA_EEI_EEI20_SHIFT (20U)0DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)0DMA_EEI_EEI21_MASK (0x200000U)0DMA_EEI_EEI21_SHIFT (21U)0DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)0DMA_EEI_EEI22_MASK (0x400000U)0DMA_EEI_EEI22_SHIFT (22U)0DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)0DMA_EEI_EEI23_MASK (0x800000U)0DMA_EEI_EEI23_SHIFT (23U)0DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)0DMA_EEI_EEI24_MASK (0x1000000U)0DMA_EEI_EEI24_SHIFT (24U)0DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)0DMA_EEI_EEI25_MASK (0x2000000U)0DMA_EEI_EEI25_SHIFT (25U)0DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)0DMA_EEI_EEI26_MASK (0x4000000U)0DMA_EEI_EEI26_SHIFT (26U)0DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)0DMA_EEI_EEI27_MASK (0x8000000U)0DMA_EEI_EEI27_SHIFT (27U)0DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)0DMA_EEI_EEI28_MASK (0x10000000U)0DMA_EEI_EEI28_SHIFT (28U)0DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)0DMA_EEI_EEI29_MASK (0x20000000U)0DMA_EEI_EEI29_SHIFT (29U)0DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)0DMA_EEI_EEI30_MASK (0x40000000U)0DMA_EEI_EEI30_SHIFT (30U)0DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)0DMA_EEI_EEI31_MASK (0x80000000U)0DMA_EEI_EEI31_SHIFT (31U)0DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)0DMA_CEEI_CEEI_MASK (0x1FU)0DMA_CEEI_CEEI_SHIFT (0U)0DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)0DMA_CEEI_CAEE_MASK (0x40U)0DMA_CEEI_CAEE_SHIFT (6U)0DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)0DMA_CEEI_NOP_MASK (0x80U)0DMA_CEEI_NOP_SHIFT (7U)0DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)0DMA_SEEI_SEEI_MASK (0x1FU)0DMA_SEEI_SEEI_SHIFT (0U)0DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)0DMA_SEEI_SAEE_MASK (0x40U)0DMA_SEEI_SAEE_SHIFT (6U)0DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)0DMA_SEEI_NOP_MASK (0x80U)0DMA_SEEI_NOP_SHIFT (7U)0DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)0DMA_CERQ_CERQ_MASK (0x1FU)0DMA_CERQ_CERQ_SHIFT (0U)0DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)0DMA_CERQ_CAER_MASK (0x40U)0DMA_CERQ_CAER_SHIFT (6U)0DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)0DMA_CERQ_NOP_MASK (0x80U)0DMA_CERQ_NOP_SHIFT (7U)0DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)0DMA_SERQ_SERQ_MASK (0x1FU)0DMA_SERQ_SERQ_SHIFT (0U)0DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)0DMA_SERQ_SAER_MASK (0x40U)0DMA_SERQ_SAER_SHIFT (6U)0DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)0DMA_SERQ_NOP_MASK (0x80U)0DMA_SERQ_NOP_SHIFT (7U)0DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)1DMA_CDNE_CDNE_MASK (0x1FU)1DMA_CDNE_CDNE_SHIFT (0U)1DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)1DMA_CDNE_CADN_MASK (0x40U)1DMA_CDNE_CADN_SHIFT (6U)1DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)1DMA_CDNE_NOP_MASK (0x80U)1DMA_CDNE_NOP_SHIFT (7U)1DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)1DMA_SSRT_SSRT_MASK (0x1FU)1DMA_SSRT_SSRT_SHIFT (0U)1DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)1DMA_SSRT_SAST_MASK (0x40U)1DMA_SSRT_SAST_SHIFT (6U)1DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)1DMA_SSRT_NOP_MASK (0x80U)1DMA_SSRT_NOP_SHIFT (7U)1DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)1DMA_CERR_CERR_MASK (0x1FU)1DMA_CERR_CERR_SHIFT (0U)1DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)1DMA_CERR_CAEI_MASK (0x40U)1DMA_CERR_CAEI_SHIFT (6U)1DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)1DMA_CERR_NOP_MASK (0x80U)1DMA_CERR_NOP_SHIFT (7U)1DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)1DMA_CINT_CINT_MASK (0x1FU)1DMA_CINT_CINT_SHIFT (0U)1DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)1DMA_CINT_CAIR_MASK (0x40U)1DMA_CINT_CAIR_SHIFT (6U)1DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)1DMA_CINT_NOP_MASK (0x80U)1DMA_CINT_NOP_SHIFT (7U)1DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)1DMA_INT_INT0_MASK (0x1U)1DMA_INT_INT0_SHIFT (0U)1DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)1DMA_INT_INT1_MASK (0x2U)1DMA_INT_INT1_SHIFT (1U)1DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)1DMA_INT_INT2_MASK (0x4U)1DMA_INT_INT2_SHIFT (2U)1DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)1DMA_INT_INT3_MASK (0x8U)1DMA_INT_INT3_SHIFT (3U)1DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)1DMA_INT_INT4_MASK (0x10U)1DMA_INT_INT4_SHIFT (4U)1DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)1DMA_INT_INT5_MASK (0x20U)1DMA_INT_INT5_SHIFT (5U)1DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)1DMA_INT_INT6_MASK (0x40U)1DMA_INT_INT6_SHIFT (6U)1DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)1DMA_INT_INT7_MASK (0x80U)1DMA_INT_INT7_SHIFT (7U)1DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)1DMA_INT_INT8_MASK (0x100U)1DMA_INT_INT8_SHIFT (8U)1DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)1DMA_INT_INT9_MASK (0x200U)1DMA_INT_INT9_SHIFT (9U)1DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)1DMA_INT_INT10_MASK (0x400U)1DMA_INT_INT10_SHIFT (10U)1DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)1DMA_INT_INT11_MASK (0x800U)1DMA_INT_INT11_SHIFT (11U)1DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)1DMA_INT_INT12_MASK (0x1000U)1DMA_INT_INT12_SHIFT (12U)1DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)1DMA_INT_INT13_MASK (0x2000U)1DMA_INT_INT13_SHIFT (13U)1DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)1DMA_INT_INT14_MASK (0x4000U)1DMA_INT_INT14_SHIFT (14U)1DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)1DMA_INT_INT15_MASK (0x8000U)1DMA_INT_INT15_SHIFT (15U)1DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)1DMA_INT_INT16_MASK (0x10000U)1DMA_INT_INT16_SHIFT (16U)1DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)1DMA_INT_INT17_MASK (0x20000U)1DMA_INT_INT17_SHIFT (17U)1DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)1DMA_INT_INT18_MASK (0x40000U)1DMA_INT_INT18_SHIFT (18U)1DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)1DMA_INT_INT19_MASK (0x80000U)1DMA_INT_INT19_SHIFT (19U)1DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)1DMA_INT_INT20_MASK (0x100000U)1DMA_INT_INT20_SHIFT (20U)1DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)1DMA_INT_INT21_MASK (0x200000U)1DMA_INT_INT21_SHIFT (21U)1DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)1DMA_INT_INT22_MASK (0x400000U)1DMA_INT_INT22_SHIFT (22U)1DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)1DMA_INT_INT23_MASK (0x800000U)1DMA_INT_INT23_SHIFT (23U)1DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)1DMA_INT_INT24_MASK (0x1000000U)1DMA_INT_INT24_SHIFT (24U)2DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)2DMA_INT_INT25_MASK (0x2000000U)2DMA_INT_INT25_SHIFT (25U)2DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)2DMA_INT_INT26_MASK (0x4000000U)2DMA_INT_INT26_SHIFT (26U)2DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)2DMA_INT_INT27_MASK (0x8000000U)2DMA_INT_INT27_SHIFT (27U)2DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)2DMA_INT_INT28_MASK (0x10000000U)2DMA_INT_INT28_SHIFT (28U)2DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)2DMA_INT_INT29_MASK (0x20000000U)2DMA_INT_INT29_SHIFT (29U)2DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)2DMA_INT_INT30_MASK (0x40000000U)2DMA_INT_INT30_SHIFT (30U)2DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)2DMA_INT_INT31_MASK (0x80000000U)2DMA_INT_INT31_SHIFT (31U)2DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)2DMA_ERR_ERR0_MASK (0x1U)2DMA_ERR_ERR0_SHIFT (0U)2DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)2DMA_ERR_ERR1_MASK (0x2U)2DMA_ERR_ERR1_SHIFT (1U)2DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)2DMA_ERR_ERR2_MASK (0x4U)2DMA_ERR_ERR2_SHIFT (2U)2DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)2DMA_ERR_ERR3_MASK (0x8U)2DMA_ERR_ERR3_SHIFT (3U)2DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)2DMA_ERR_ERR4_MASK (0x10U)2DMA_ERR_ERR4_SHIFT (4U)2DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)2DMA_ERR_ERR5_MASK (0x20U)2DMA_ERR_ERR5_SHIFT (5U)2DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)2DMA_ERR_ERR6_MASK (0x40U)2DMA_ERR_ERR6_SHIFT (6U)2DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)2DMA_ERR_ERR7_MASK (0x80U)2DMA_ERR_ERR7_SHIFT (7U)2DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)2DMA_ERR_ERR8_MASK (0x100U)2DMA_ERR_ERR8_SHIFT (8U)2DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)2DMA_ERR_ERR9_MASK (0x200U)2DMA_ERR_ERR9_SHIFT (9U)2DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)2DMA_ERR_ERR10_MASK (0x400U)2DMA_ERR_ERR10_SHIFT (10U)2DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)2DMA_ERR_ERR11_MASK (0x800U)2DMA_ERR_ERR11_SHIFT (11U)2DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)2DMA_ERR_ERR12_MASK (0x1000U)2DMA_ERR_ERR12_SHIFT (12U)2DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)2DMA_ERR_ERR13_MASK (0x2000U)2DMA_ERR_ERR13_SHIFT (13U)2DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)2DMA_ERR_ERR14_MASK (0x4000U)2DMA_ERR_ERR14_SHIFT (14U)2DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)2DMA_ERR_ERR15_MASK (0x8000U)2DMA_ERR_ERR15_SHIFT (15U)2DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)2DMA_ERR_ERR16_MASK (0x10000U)2DMA_ERR_ERR16_SHIFT (16U)2DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)2DMA_ERR_ERR17_MASK (0x20000U)2DMA_ERR_ERR17_SHIFT (17U)2DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)2DMA_ERR_ERR18_MASK (0x40000U)2DMA_ERR_ERR18_SHIFT (18U)2DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)2DMA_ERR_ERR19_MASK (0x80000U)2DMA_ERR_ERR19_SHIFT (19U)2DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)2DMA_ERR_ERR20_MASK (0x100000U)2DMA_ERR_ERR20_SHIFT (20U)2DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)2DMA_ERR_ERR21_MASK (0x200000U)2DMA_ERR_ERR21_SHIFT (21U)2DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)2DMA_ERR_ERR22_MASK (0x400000U)2DMA_ERR_ERR22_SHIFT (22U)2DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)2DMA_ERR_ERR23_MASK (0x800000U)2DMA_ERR_ERR23_SHIFT (23U)2DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)2DMA_ERR_ERR24_MASK (0x1000000U)2DMA_ERR_ERR24_SHIFT (24U)2DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)2DMA_ERR_ERR25_MASK (0x2000000U)2DMA_ERR_ERR25_SHIFT (25U)2DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)2DMA_ERR_ERR26_MASK (0x4000000U)2DMA_ERR_ERR26_SHIFT (26U)2DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)2DMA_ERR_ERR27_MASK (0x8000000U)2DMA_ERR_ERR27_SHIFT (27U)2DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)2DMA_ERR_ERR28_MASK (0x10000000U)2DMA_ERR_ERR28_SHIFT (28U)2DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)2DMA_ERR_ERR29_MASK (0x20000000U)2DMA_ERR_ERR29_SHIFT (29U)2DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)2DMA_ERR_ERR30_MASK (0x40000000U)2DMA_ERR_ERR30_SHIFT (30U)2DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)2DMA_ERR_ERR31_MASK (0x80000000U)2DMA_ERR_ERR31_SHIFT (31U)2DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)2DMA_HRS_HRS0_MASK (0x1U)2DMA_HRS_HRS0_SHIFT (0U)3DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)3DMA_HRS_HRS1_MASK (0x2U)3DMA_HRS_HRS1_SHIFT (1U)3DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)3DMA_HRS_HRS2_MASK (0x4U)3DMA_HRS_HRS2_SHIFT (2U)3DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)3DMA_HRS_HRS3_MASK (0x8U)3DMA_HRS_HRS3_SHIFT (3U)3DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)3DMA_HRS_HRS4_MASK (0x10U)3DMA_HRS_HRS4_SHIFT (4U)3DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)3DMA_HRS_HRS5_MASK (0x20U)3DMA_HRS_HRS5_SHIFT (5U)3DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)3DMA_HRS_HRS6_MASK (0x40U)3DMA_HRS_HRS6_SHIFT (6U)3DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)3DMA_HRS_HRS7_MASK (0x80U)3DMA_HRS_HRS7_SHIFT (7U)3DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)3DMA_HRS_HRS8_MASK (0x100U)3DMA_HRS_HRS8_SHIFT (8U)3DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)3DMA_HRS_HRS9_MASK (0x200U)3DMA_HRS_HRS9_SHIFT (9U)3DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)3DMA_HRS_HRS10_MASK (0x400U)3DMA_HRS_HRS10_SHIFT (10U)3DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)3DMA_HRS_HRS11_MASK (0x800U)3DMA_HRS_HRS11_SHIFT (11U)3DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)3DMA_HRS_HRS12_MASK (0x1000U)3DMA_HRS_HRS12_SHIFT (12U)3DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)3DMA_HRS_HRS13_MASK (0x2000U)3DMA_HRS_HRS13_SHIFT (13U)3DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)3DMA_HRS_HRS14_MASK (0x4000U)3DMA_HRS_HRS14_SHIFT (14U)3DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)3DMA_HRS_HRS15_MASK (0x8000U)3DMA_HRS_HRS15_SHIFT (15U)3DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)3DMA_HRS_HRS16_MASK (0x10000U)3DMA_HRS_HRS16_SHIFT (16U)3DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)3DMA_HRS_HRS17_MASK (0x20000U)3DMA_HRS_HRS17_SHIFT (17U)3DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)3DMA_HRS_HRS18_MASK (0x40000U)3DMA_HRS_HRS18_SHIFT (18U)3DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)3DMA_HRS_HRS19_MASK (0x80000U)3DMA_HRS_HRS19_SHIFT (19U)3DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)3DMA_HRS_HRS20_MASK (0x100000U)3DMA_HRS_HRS20_SHIFT (20U)3DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)3DMA_HRS_HRS21_MASK (0x200000U)3DMA_HRS_HRS21_SHIFT (21U)3DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)3DMA_HRS_HRS22_MASK (0x400000U)3DMA_HRS_HRS22_SHIFT (22U)3DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)3DMA_HRS_HRS23_MASK (0x800000U)3DMA_HRS_HRS23_SHIFT (23U)3DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)3DMA_HRS_HRS24_MASK (0x1000000U)3DMA_HRS_HRS24_SHIFT (24U)3DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)3DMA_HRS_HRS25_MASK (0x2000000U)3DMA_HRS_HRS25_SHIFT (25U)3DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)3DMA_HRS_HRS26_MASK (0x4000000U)3DMA_HRS_HRS26_SHIFT (26U)3DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)3DMA_HRS_HRS27_MASK (0x8000000U)3DMA_HRS_HRS27_SHIFT (27U)3DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)3DMA_HRS_HRS28_MASK (0x10000000U)3DMA_HRS_HRS28_SHIFT (28U)3DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)3DMA_HRS_HRS29_MASK (0x20000000U)3DMA_HRS_HRS29_SHIFT (29U)3DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)3DMA_HRS_HRS30_MASK (0x40000000U)3DMA_HRS_HRS30_SHIFT (30U)3DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)3DMA_HRS_HRS31_MASK (0x80000000U)3DMA_HRS_HRS31_SHIFT (31U)3DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)3DMA_EARS_EDREQ_0_MASK (0x1U)3DMA_EARS_EDREQ_0_SHIFT (0U)3DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)3DMA_EARS_EDREQ_1_MASK (0x2U)3DMA_EARS_EDREQ_1_SHIFT (1U)3DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)3DMA_EARS_EDREQ_2_MASK (0x4U)3DMA_EARS_EDREQ_2_SHIFT (2U)3DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)3DMA_EARS_EDREQ_3_MASK (0x8U)3DMA_EARS_EDREQ_3_SHIFT (3U)3DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)3DMA_EARS_EDREQ_4_MASK (0x10U)3DMA_EARS_EDREQ_4_SHIFT (4U)3DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)3DMA_EARS_EDREQ_5_MASK (0x20U)3DMA_EARS_EDREQ_5_SHIFT (5U)3DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)3DMA_EARS_EDREQ_6_MASK (0x40U)3DMA_EARS_EDREQ_6_SHIFT (6U)3DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)3DMA_EARS_EDREQ_7_MASK (0x80U)3DMA_EARS_EDREQ_7_SHIFT (7U)3DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)3DMA_EARS_EDREQ_8_MASK (0x100U)3DMA_EARS_EDREQ_8_SHIFT (8U)3DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)3DMA_EARS_EDREQ_9_MASK (0x200U)3DMA_EARS_EDREQ_9_SHIFT (9U)3DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)4DMA_EARS_EDREQ_10_MASK (0x400U)4DMA_EARS_EDREQ_10_SHIFT (10U)4DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)4DMA_EARS_EDREQ_11_MASK (0x800U)4DMA_EARS_EDREQ_11_SHIFT (11U)4DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)4DMA_EARS_EDREQ_12_MASK (0x1000U)4DMA_EARS_EDREQ_12_SHIFT (12U)4DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)4DMA_EARS_EDREQ_13_MASK (0x2000U)4DMA_EARS_EDREQ_13_SHIFT (13U)4DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)4DMA_EARS_EDREQ_14_MASK (0x4000U)4DMA_EARS_EDREQ_14_SHIFT (14U)4DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)4DMA_EARS_EDREQ_15_MASK (0x8000U)4DMA_EARS_EDREQ_15_SHIFT (15U)4DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)4DMA_EARS_EDREQ_16_MASK (0x10000U)4DMA_EARS_EDREQ_16_SHIFT (16U)4DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)4DMA_EARS_EDREQ_17_MASK (0x20000U)4DMA_EARS_EDREQ_17_SHIFT (17U)4DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)4DMA_EARS_EDREQ_18_MASK (0x40000U)4DMA_EARS_EDREQ_18_SHIFT (18U)4DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)4DMA_EARS_EDREQ_19_MASK (0x80000U)4DMA_EARS_EDREQ_19_SHIFT (19U)4DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)4DMA_EARS_EDREQ_20_MASK (0x100000U)4DMA_EARS_EDREQ_20_SHIFT (20U)4DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)4DMA_EARS_EDREQ_21_MASK (0x200000U)4DMA_EARS_EDREQ_21_SHIFT (21U)4DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)4DMA_EARS_EDREQ_22_MASK (0x400000U)4DMA_EARS_EDREQ_22_SHIFT (22U)4DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)4DMA_EARS_EDREQ_23_MASK (0x800000U)4DMA_EARS_EDREQ_23_SHIFT (23U)4DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)4DMA_EARS_EDREQ_24_MASK (0x1000000U)4DMA_EARS_EDREQ_24_SHIFT (24U)4DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)4DMA_EARS_EDREQ_25_MASK (0x2000000U)4DMA_EARS_EDREQ_25_SHIFT (25U)4DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)4DMA_EARS_EDREQ_26_MASK (0x4000000U)4DMA_EARS_EDREQ_26_SHIFT (26U)4DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)4DMA_EARS_EDREQ_27_MASK (0x8000000U)4DMA_EARS_EDREQ_27_SHIFT (27U)4DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)4DMA_EARS_EDREQ_28_MASK (0x10000000U)4DMA_EARS_EDREQ_28_SHIFT (28U)4DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)4DMA_EARS_EDREQ_29_MASK (0x20000000U)4DMA_EARS_EDREQ_29_SHIFT (29U)4DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)4DMA_EARS_EDREQ_30_MASK (0x40000000U)4DMA_EARS_EDREQ_30_SHIFT (30U)4DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)4DMA_EARS_EDREQ_31_MASK (0x80000000U)4DMA_EARS_EDREQ_31_SHIFT (31U)4DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)4DMA_DCHPRI3_CHPRI_MASK (0xFU)4DMA_DCHPRI3_CHPRI_SHIFT (0U)4DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)4DMA_DCHPRI3_GRPPRI_MASK (0x30U)4DMA_DCHPRI3_GRPPRI_SHIFT (4U)4DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)4DMA_DCHPRI3_DPA_MASK (0x40U)4DMA_DCHPRI3_DPA_SHIFT (6U)4DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)4DMA_DCHPRI3_ECP_MASK (0x80U)4DMA_DCHPRI3_ECP_SHIFT (7U)4DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)4DMA_DCHPRI2_CHPRI_MASK (0xFU)4DMA_DCHPRI2_CHPRI_SHIFT (0U)4DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)4DMA_DCHPRI2_GRPPRI_MASK (0x30U)4DMA_DCHPRI2_GRPPRI_SHIFT (4U)4DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)4DMA_DCHPRI2_DPA_MASK (0x40U)4DMA_DCHPRI2_DPA_SHIFT (6U)4DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)4DMA_DCHPRI2_ECP_MASK (0x80U)4DMA_DCHPRI2_ECP_SHIFT (7U)4DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)4DMA_DCHPRI1_CHPRI_MASK (0xFU)4DMA_DCHPRI1_CHPRI_SHIFT (0U)4DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)4DMA_DCHPRI1_GRPPRI_MASK (0x30U)4DMA_DCHPRI1_GRPPRI_SHIFT (4U)4DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)4DMA_DCHPRI1_DPA_MASK (0x40U)4DMA_DCHPRI1_DPA_SHIFT (6U)4DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)4DMA_DCHPRI1_ECP_MASK (0x80U)4DMA_DCHPRI1_ECP_SHIFT (7U)4DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)4DMA_DCHPRI0_CHPRI_MASK (0xFU)4DMA_DCHPRI0_CHPRI_SHIFT (0U)4DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)4DMA_DCHPRI0_GRPPRI_MASK (0x30U)4DMA_DCHPRI0_GRPPRI_SHIFT (4U)4DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)4DMA_DCHPRI0_DPA_MASK (0x40U)4DMA_DCHPRI0_DPA_SHIFT (6U)4DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)4DMA_DCHPRI0_ECP_MASK (0x80U)5DMA_DCHPRI0_ECP_SHIFT (7U)5DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)5DMA_DCHPRI7_CHPRI_MASK (0xFU)5DMA_DCHPRI7_CHPRI_SHIFT (0U)5DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)5DMA_DCHPRI7_GRPPRI_MASK (0x30U)5DMA_DCHPRI7_GRPPRI_SHIFT (4U)5DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)5DMA_DCHPRI7_DPA_MASK (0x40U)5DMA_DCHPRI7_DPA_SHIFT (6U)5DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)5DMA_DCHPRI7_ECP_MASK (0x80U)5DMA_DCHPRI7_ECP_SHIFT (7U)5DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)5DMA_DCHPRI6_CHPRI_MASK (0xFU)5DMA_DCHPRI6_CHPRI_SHIFT (0U)5DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)5DMA_DCHPRI6_GRPPRI_MASK (0x30U)5DMA_DCHPRI6_GRPPRI_SHIFT (4U)5DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)5DMA_DCHPRI6_DPA_MASK (0x40U)5DMA_DCHPRI6_DPA_SHIFT (6U)5DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)5DMA_DCHPRI6_ECP_MASK (0x80U)5DMA_DCHPRI6_ECP_SHIFT (7U)5DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)5DMA_DCHPRI5_CHPRI_MASK (0xFU)5DMA_DCHPRI5_CHPRI_SHIFT (0U)5DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)5DMA_DCHPRI5_GRPPRI_MASK (0x30U)5DMA_DCHPRI5_GRPPRI_SHIFT (4U)5DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)5DMA_DCHPRI5_DPA_MASK (0x40U)5DMA_DCHPRI5_DPA_SHIFT (6U)5DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)5DMA_DCHPRI5_ECP_MASK (0x80U)5DMA_DCHPRI5_ECP_SHIFT (7U)5DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)5DMA_DCHPRI4_CHPRI_MASK (0xFU)5DMA_DCHPRI4_CHPRI_SHIFT (0U)5DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)5DMA_DCHPRI4_GRPPRI_MASK (0x30U)5DMA_DCHPRI4_GRPPRI_SHIFT (4U)5DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)5DMA_DCHPRI4_DPA_MASK (0x40U)5DMA_DCHPRI4_DPA_SHIFT (6U)5DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)5DMA_DCHPRI4_ECP_MASK (0x80U)5DMA_DCHPRI4_ECP_SHIFT (7U)5DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)5DMA_DCHPRI11_CHPRI_MASK (0xFU)5DMA_DCHPRI11_CHPRI_SHIFT (0U)5DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)5DMA_DCHPRI11_GRPPRI_MASK (0x30U)5DMA_DCHPRI11_GRPPRI_SHIFT (4U)5DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)5DMA_DCHPRI11_DPA_MASK (0x40U)5DMA_DCHPRI11_DPA_SHIFT (6U)5DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)5DMA_DCHPRI11_ECP_MASK (0x80U)5DMA_DCHPRI11_ECP_SHIFT (7U)5DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)5DMA_DCHPRI10_CHPRI_MASK (0xFU)5DMA_DCHPRI10_CHPRI_SHIFT (0U)5DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)5DMA_DCHPRI10_GRPPRI_MASK (0x30U)5DMA_DCHPRI10_GRPPRI_SHIFT (4U)5DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)5DMA_DCHPRI10_DPA_MASK (0x40U)5DMA_DCHPRI10_DPA_SHIFT (6U)5DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)5DMA_DCHPRI10_ECP_MASK (0x80U)5DMA_DCHPRI10_ECP_SHIFT (7U)5DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)5DMA_DCHPRI9_CHPRI_MASK (0xFU)5DMA_DCHPRI9_CHPRI_SHIFT (0U)5DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)5DMA_DCHPRI9_GRPPRI_MASK (0x30U)5DMA_DCHPRI9_GRPPRI_SHIFT (4U)5DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)5DMA_DCHPRI9_DPA_MASK (0x40U)5DMA_DCHPRI9_DPA_SHIFT (6U)5DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)5DMA_DCHPRI9_ECP_MASK (0x80U)5DMA_DCHPRI9_ECP_SHIFT (7U)5DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)5DMA_DCHPRI8_CHPRI_MASK (0xFU)5DMA_DCHPRI8_CHPRI_SHIFT (0U)5DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)5DMA_DCHPRI8_GRPPRI_MASK (0x30U)5DMA_DCHPRI8_GRPPRI_SHIFT (4U)5DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)5DMA_DCHPRI8_DPA_MASK (0x40U)5DMA_DCHPRI8_DPA_SHIFT (6U)5DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)5DMA_DCHPRI8_ECP_MASK (0x80U)6DMA_DCHPRI8_ECP_SHIFT (7U)6DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)6DMA_DCHPRI15_CHPRI_MASK (0xFU)6DMA_DCHPRI15_CHPRI_SHIFT (0U)6DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)6DMA_DCHPRI15_GRPPRI_MASK (0x30U)6DMA_DCHPRI15_GRPPRI_SHIFT (4U)6DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)6DMA_DCHPRI15_DPA_MASK (0x40U)6DMA_DCHPRI15_DPA_SHIFT (6U)6DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)6DMA_DCHPRI15_ECP_MASK (0x80U)6DMA_DCHPRI15_ECP_SHIFT (7U)6DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)6DMA_DCHPRI14_CHPRI_MASK (0xFU)6DMA_DCHPRI14_CHPRI_SHIFT (0U)6DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)6DMA_DCHPRI14_GRPPRI_MASK (0x30U)6DMA_DCHPRI14_GRPPRI_SHIFT (4U)6DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)6DMA_DCHPRI14_DPA_MASK (0x40U)6DMA_DCHPRI14_DPA_SHIFT (6U)6DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)6DMA_DCHPRI14_ECP_MASK (0x80U)6DMA_DCHPRI14_ECP_SHIFT (7U)6DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)6DMA_DCHPRI13_CHPRI_MASK (0xFU)6DMA_DCHPRI13_CHPRI_SHIFT (0U)6DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)6DMA_DCHPRI13_GRPPRI_MASK (0x30U)6DMA_DCHPRI13_GRPPRI_SHIFT (4U)6DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)6DMA_DCHPRI13_DPA_MASK (0x40U)6DMA_DCHPRI13_DPA_SHIFT (6U)6DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)6DMA_DCHPRI13_ECP_MASK (0x80U)6DMA_DCHPRI13_ECP_SHIFT (7U)6DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)6DMA_DCHPRI12_CHPRI_MASK (0xFU)6DMA_DCHPRI12_CHPRI_SHIFT (0U)6DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)6DMA_DCHPRI12_GRPPRI_MASK (0x30U)6DMA_DCHPRI12_GRPPRI_SHIFT (4U)6DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)6DMA_DCHPRI12_DPA_MASK (0x40U)6DMA_DCHPRI12_DPA_SHIFT (6U)6DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)6DMA_DCHPRI12_ECP_MASK (0x80U)6DMA_DCHPRI12_ECP_SHIFT (7U)6DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)6DMA_DCHPRI19_CHPRI_MASK (0xFU)6DMA_DCHPRI19_CHPRI_SHIFT (0U)6DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)6DMA_DCHPRI19_GRPPRI_MASK (0x30U)6DMA_DCHPRI19_GRPPRI_SHIFT (4U)6DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)6DMA_DCHPRI19_DPA_MASK (0x40U)6DMA_DCHPRI19_DPA_SHIFT (6U)6DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)6DMA_DCHPRI19_ECP_MASK (0x80U)6DMA_DCHPRI19_ECP_SHIFT (7U)6DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)6DMA_DCHPRI18_CHPRI_MASK (0xFU)6DMA_DCHPRI18_CHPRI_SHIFT (0U)6DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)6DMA_DCHPRI18_GRPPRI_MASK (0x30U)6DMA_DCHPRI18_GRPPRI_SHIFT (4U)6DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)6DMA_DCHPRI18_DPA_MASK (0x40U)6DMA_DCHPRI18_DPA_SHIFT (6U)6DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)6DMA_DCHPRI18_ECP_MASK (0x80U)6DMA_DCHPRI18_ECP_SHIFT (7U)6DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)6DMA_DCHPRI17_CHPRI_MASK (0xFU)6DMA_DCHPRI17_CHPRI_SHIFT (0U)6DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)6DMA_DCHPRI17_GRPPRI_MASK (0x30U)6DMA_DCHPRI17_GRPPRI_SHIFT (4U)6DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)6DMA_DCHPRI17_DPA_MASK (0x40U)6DMA_DCHPRI17_DPA_SHIFT (6U)6DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)6DMA_DCHPRI17_ECP_MASK (0x80U)6DMA_DCHPRI17_ECP_SHIFT (7U)6DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)6DMA_DCHPRI16_CHPRI_MASK (0xFU)6DMA_DCHPRI16_CHPRI_SHIFT (0U)6DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)6DMA_DCHPRI16_GRPPRI_MASK (0x30U)6DMA_DCHPRI16_GRPPRI_SHIFT (4U)6DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)6DMA_DCHPRI16_DPA_MASK (0x40U)6DMA_DCHPRI16_DPA_SHIFT (6U)6DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)6DMA_DCHPRI16_ECP_MASK (0x80U)7DMA_DCHPRI16_ECP_SHIFT (7U)7DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)7DMA_DCHPRI23_CHPRI_MASK (0xFU)7DMA_DCHPRI23_CHPRI_SHIFT (0U)7DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)7DMA_DCHPRI23_GRPPRI_MASK (0x30U)7DMA_DCHPRI23_GRPPRI_SHIFT (4U)7DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)7DMA_DCHPRI23_DPA_MASK (0x40U)7DMA_DCHPRI23_DPA_SHIFT (6U)7DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)7DMA_DCHPRI23_ECP_MASK (0x80U)7DMA_DCHPRI23_ECP_SHIFT (7U)7DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)7DMA_DCHPRI22_CHPRI_MASK (0xFU)7DMA_DCHPRI22_CHPRI_SHIFT (0U)7DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)7DMA_DCHPRI22_GRPPRI_MASK (0x30U)7DMA_DCHPRI22_GRPPRI_SHIFT (4U)7DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)7DMA_DCHPRI22_DPA_MASK (0x40U)7DMA_DCHPRI22_DPA_SHIFT (6U)7DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)7DMA_DCHPRI22_ECP_MASK (0x80U)7DMA_DCHPRI22_ECP_SHIFT (7U)7DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)7DMA_DCHPRI21_CHPRI_MASK (0xFU)7DMA_DCHPRI21_CHPRI_SHIFT (0U)7DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)7DMA_DCHPRI21_GRPPRI_MASK (0x30U)7DMA_DCHPRI21_GRPPRI_SHIFT (4U)7DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)7DMA_DCHPRI21_DPA_MASK (0x40U)7DMA_DCHPRI21_DPA_SHIFT (6U)7DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)7DMA_DCHPRI21_ECP_MASK (0x80U)7DMA_DCHPRI21_ECP_SHIFT (7U)7DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)7DMA_DCHPRI20_CHPRI_MASK (0xFU)7DMA_DCHPRI20_CHPRI_SHIFT (0U)7DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)7DMA_DCHPRI20_GRPPRI_MASK (0x30U)7DMA_DCHPRI20_GRPPRI_SHIFT (4U)7DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)7DMA_DCHPRI20_DPA_MASK (0x40U)7DMA_DCHPRI20_DPA_SHIFT (6U)7DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)7DMA_DCHPRI20_ECP_MASK (0x80U)7DMA_DCHPRI20_ECP_SHIFT (7U)7DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)7DMA_DCHPRI27_CHPRI_MASK (0xFU)7DMA_DCHPRI27_CHPRI_SHIFT (0U)7DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)7DMA_DCHPRI27_GRPPRI_MASK (0x30U)7DMA_DCHPRI27_GRPPRI_SHIFT (4U)7DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)7DMA_DCHPRI27_DPA_MASK (0x40U)7DMA_DCHPRI27_DPA_SHIFT (6U)7DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)7DMA_DCHPRI27_ECP_MASK (0x80U)7DMA_DCHPRI27_ECP_SHIFT (7U)7DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)7DMA_DCHPRI26_CHPRI_MASK (0xFU)7DMA_DCHPRI26_CHPRI_SHIFT (0U)7DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)7DMA_DCHPRI26_GRPPRI_MASK (0x30U)7DMA_DCHPRI26_GRPPRI_SHIFT (4U)7DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)7DMA_DCHPRI26_DPA_MASK (0x40U)7DMA_DCHPRI26_DPA_SHIFT (6U)7DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)7DMA_DCHPRI26_ECP_MASK (0x80U)7DMA_DCHPRI26_ECP_SHIFT (7U)7DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)7DMA_DCHPRI25_CHPRI_MASK (0xFU)7DMA_DCHPRI25_CHPRI_SHIFT (0U)7DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)7DMA_DCHPRI25_GRPPRI_MASK (0x30U)7DMA_DCHPRI25_GRPPRI_SHIFT (4U)7DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)7DMA_DCHPRI25_DPA_MASK (0x40U)7DMA_DCHPRI25_DPA_SHIFT (6U)7DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)7DMA_DCHPRI25_ECP_MASK (0x80U)7DMA_DCHPRI25_ECP_SHIFT (7U)7DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)7DMA_DCHPRI24_CHPRI_MASK (0xFU)7DMA_DCHPRI24_CHPRI_SHIFT (0U)7DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)7DMA_DCHPRI24_GRPPRI_MASK (0x30U)7DMA_DCHPRI24_GRPPRI_SHIFT (4U)7DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)7DMA_DCHPRI24_DPA_MASK (0x40U)7DMA_DCHPRI24_DPA_SHIFT (6U)7DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)7DMA_DCHPRI24_ECP_MASK (0x80U)8DMA_DCHPRI24_ECP_SHIFT (7U)8DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)8DMA_DCHPRI31_CHPRI_MASK (0xFU)8DMA_DCHPRI31_CHPRI_SHIFT (0U)8DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)8DMA_DCHPRI31_GRPPRI_MASK (0x30U)8DMA_DCHPRI31_GRPPRI_SHIFT (4U)8DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)8DMA_DCHPRI31_DPA_MASK (0x40U)8DMA_DCHPRI31_DPA_SHIFT (6U)8DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)8DMA_DCHPRI31_ECP_MASK (0x80U)8DMA_DCHPRI31_ECP_SHIFT (7U)8DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)8DMA_DCHPRI30_CHPRI_MASK (0xFU)8DMA_DCHPRI30_CHPRI_SHIFT (0U)8DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)8DMA_DCHPRI30_GRPPRI_MASK (0x30U)8DMA_DCHPRI30_GRPPRI_SHIFT (4U)8DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)8DMA_DCHPRI30_DPA_MASK (0x40U)8DMA_DCHPRI30_DPA_SHIFT (6U)8DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)8DMA_DCHPRI30_ECP_MASK (0x80U)8DMA_DCHPRI30_ECP_SHIFT (7U)8DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)8DMA_DCHPRI29_CHPRI_MASK (0xFU)8DMA_DCHPRI29_CHPRI_SHIFT (0U)8DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)8DMA_DCHPRI29_GRPPRI_MASK (0x30U)8DMA_DCHPRI29_GRPPRI_SHIFT (4U)8DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)8DMA_DCHPRI29_DPA_MASK (0x40U)8DMA_DCHPRI29_DPA_SHIFT (6U)8DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)8DMA_DCHPRI29_ECP_MASK (0x80U)8DMA_DCHPRI29_ECP_SHIFT (7U)8DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)8DMA_DCHPRI28_CHPRI_MASK (0xFU)8DMA_DCHPRI28_CHPRI_SHIFT (0U)8DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)8DMA_DCHPRI28_GRPPRI_MASK (0x30U)8DMA_DCHPRI28_GRPPRI_SHIFT (4U)8DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)8DMA_DCHPRI28_DPA_MASK (0x40U)8DMA_DCHPRI28_DPA_SHIFT (6U)8DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)8DMA_DCHPRI28_ECP_MASK (0x80U)8DMA_DCHPRI28_ECP_SHIFT (7U)8DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)8DMA_DCHMID_MID_MASK (0xFU)8DMA_DCHMID_MID_SHIFT (0U)8DMA_DCHMID_MID(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_MID_SHIFT)) & DMA_DCHMID_MID_MASK)8DMA_DCHMID_PAL_MASK (0x40U)8DMA_DCHMID_PAL_SHIFT (6U)8DMA_DCHMID_PAL(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_PAL_SHIFT)) & DMA_DCHMID_PAL_MASK)8DMA_DCHMID_EMI_MASK (0x80U)8DMA_DCHMID_EMI_SHIFT (7U)8DMA_DCHMID_EMI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_EMI_SHIFT)) & DMA_DCHMID_EMI_MASK)8DMA_DCHMID_COUNT (32U)8DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)8DMA_SADDR_SADDR_SHIFT (0U)8DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)8DMA_SADDR_COUNT (32U)8DMA_SOFF_SOFF_MASK (0xFFFFU)8DMA_SOFF_SOFF_SHIFT (0U)8DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)8DMA_SOFF_COUNT (32U)8DMA_ATTR_DSIZE_MASK (0x7U)8DMA_ATTR_DSIZE_SHIFT (0U)8DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)8DMA_ATTR_DMOD_MASK (0xF8U)8DMA_ATTR_DMOD_SHIFT (3U)8DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)8DMA_ATTR_SSIZE_MASK (0x700U)8DMA_ATTR_SSIZE_SHIFT (8U)8DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)8DMA_ATTR_SMOD_MASK (0xF800U)8DMA_ATTR_SMOD_SHIFT (11U)8DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)8DMA_ATTR_COUNT (32U)8DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)8DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)8DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)9DMA_NBYTES_MLNO_COUNT (32U)9DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)9DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)9DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)9DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)9DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)9DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)9DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)9DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)9DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)9DMA_NBYTES_MLOFFNO_COUNT (32U)9DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)9DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)9DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)9DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)9DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)9DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)9DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)9DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)9DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)9DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)9DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)9DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)9DMA_NBYTES_MLOFFYES_COUNT (32U)9DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)9DMA_SLAST_SLAST_SHIFT (0U)9DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)9DMA_SLAST_COUNT (32U)9DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)9DMA_DADDR_DADDR_SHIFT (0U)9DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)9DMA_DADDR_COUNT (32U)9DMA_DOFF_DOFF_MASK (0xFFFFU)9DMA_DOFF_DOFF_SHIFT (0U)9DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)9DMA_DOFF_COUNT (32U)9DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)9DMA_CITER_ELINKNO_CITER_SHIFT (0U)9DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)9DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)9DMA_CITER_ELINKNO_ELINK_SHIFT (15U)9DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)9DMA_CITER_ELINKNO_COUNT (32U)9DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)9DMA_CITER_ELINKYES_CITER_SHIFT (0U)9DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)9DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)9DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)9DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)9DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)9DMA_CITER_ELINKYES_ELINK_SHIFT (15U)9DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)9DMA_CITER_ELINKYES_COUNT (32U)9DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)9DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)9DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)9DMA_DLAST_SGA_COUNT (32U)9DMA_CSR_START_MASK (0x1U)9DMA_CSR_START_SHIFT (0U)9DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)9DMA_CSR_INTMAJOR_MASK (0x2U)9DMA_CSR_INTMAJOR_SHIFT (1U)9DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)9DMA_CSR_INTHALF_MASK (0x4U)9DMA_CSR_INTHALF_SHIFT (2U)9DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)9DMA_CSR_DREQ_MASK (0x8U)9DMA_CSR_DREQ_SHIFT (3U)9DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)9DMA_CSR_ESG_MASK (0x10U)9DMA_CSR_ESG_SHIFT (4U)9DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)9DMA_CSR_MAJORELINK_MASK (0x20U)9DMA_CSR_MAJORELINK_SHIFT (5U):DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK):DMA_CSR_ACTIVE_MASK (0x40U):DMA_CSR_ACTIVE_SHIFT (6U):DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK):DMA_CSR_DONE_MASK (0x80U):DMA_CSR_DONE_SHIFT (7U):DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK):DMA_CSR_MAJORLINKCH_MASK (0x1F00U):DMA_CSR_MAJORLINKCH_SHIFT (8U):DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK):DMA_CSR_BWC_MASK (0xC000U):DMA_CSR_BWC_SHIFT (14U):DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK):DMA_CSR_COUNT (32U):DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU):DMA_BITER_ELINKNO_BITER_SHIFT (0U):DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK):DMA_BITER_ELINKNO_ELINK_MASK (0x8000U):DMA_BITER_ELINKNO_ELINK_SHIFT (15U):DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK):DMA_BITER_ELINKNO_COUNT (32U):DMA_BITER_ELINKYES_BITER_MASK (0x1FFU):DMA_BITER_ELINKYES_BITER_SHIFT (0U):DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK):DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U):DMA_BITER_ELINKYES_LINKCH_SHIFT (9U):DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK):DMA_BITER_ELINKYES_ELINK_MASK (0x8000U):DMA_BITER_ELINKYES_ELINK_SHIFT (15U):DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK):DMA_BITER_ELINKYES_COUNT (32U):DMA0_BASE (0x400E8000u):DMA0 ((DMA_Type *)DMA0_BASE):DMA_BASE_ADDRS { DMA0_BASE }:DMA_BASE_PTRS { DMA0 }:DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }:DMA_ERROR_IRQS { DMA_ERROR_IRQn }:DMAMUX_CHCFG_SOURCE_MASK (0x7FU):DMAMUX_CHCFG_SOURCE_SHIFT (0U):DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK):DMAMUX_CHCFG_A_ON_MASK (0x20000000U):DMAMUX_CHCFG_A_ON_SHIFT (29U):DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK):DMAMUX_CHCFG_TRIG_MASK (0x40000000U):DMAMUX_CHCFG_TRIG_SHIFT (30U):DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK):DMAMUX_CHCFG_ENBL_MASK (0x80000000U):DMAMUX_CHCFG_ENBL_SHIFT (31U):DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK):DMAMUX_CHCFG_COUNT (32U):DMAMUX_BASE (0x400EC000u):DMAMUX ((DMAMUX_Type *)DMAMUX_BASE):DMAMUX_BASE_ADDRS { DMAMUX_BASE }:DMAMUX_BASE_PTRS { DMAMUX };ENC_CTRL_CMPIE_MASK (0x1U);ENC_CTRL_CMPIE_SHIFT (0U);ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK);ENC_CTRL_CMPIRQ_MASK (0x2U);ENC_CTRL_CMPIRQ_SHIFT (1U);ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK);ENC_CTRL_WDE_MASK (0x4U);ENC_CTRL_WDE_SHIFT (2U);ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK);ENC_CTRL_DIE_MASK (0x8U);ENC_CTRL_DIE_SHIFT (3U);ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK);ENC_CTRL_DIRQ_MASK (0x10U);ENC_CTRL_DIRQ_SHIFT (4U);ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK);ENC_CTRL_XNE_MASK (0x20U);ENC_CTRL_XNE_SHIFT (5U);ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK);ENC_CTRL_XIP_MASK (0x40U);ENC_CTRL_XIP_SHIFT (6U);ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK);ENC_CTRL_XIE_MASK (0x80U);ENC_CTRL_XIE_SHIFT (7U);ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK);ENC_CTRL_XIRQ_MASK (0x100U);ENC_CTRL_XIRQ_SHIFT (8U);ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK);ENC_CTRL_PH1_MASK (0x200U);ENC_CTRL_PH1_SHIFT (9U);ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK);ENC_CTRL_REV_MASK (0x400U);ENC_CTRL_REV_SHIFT (10U);ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK);ENC_CTRL_SWIP_MASK (0x800U);ENC_CTRL_SWIP_SHIFT (11U);ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK);ENC_CTRL_HNE_MASK (0x1000U);ENC_CTRL_HNE_SHIFT (12U);ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK);ENC_CTRL_HIP_MASK (0x2000U);ENC_CTRL_HIP_SHIFT (13U);ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK);ENC_CTRL_HIE_MASK (0x4000U);ENC_CTRL_HIE_SHIFT (14U);ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK);ENC_CTRL_HIRQ_MASK (0x8000U);ENC_CTRL_HIRQ_SHIFT (15U);ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK);ENC_FILT_FILT_PER_MASK (0xFFU);ENC_FILT_FILT_PER_SHIFT (0U);ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK);ENC_FILT_FILT_CNT_MASK (0x700U);ENC_FILT_FILT_CNT_SHIFT (8U);ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK);ENC_WTR_WDOG_MASK (0xFFFFU);ENC_WTR_WDOG_SHIFT (0U);ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK);ENC_POSD_POSD_MASK (0xFFFFU);ENC_POSD_POSD_SHIFT (0U);ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK);ENC_POSDH_POSDH_MASK (0xFFFFU);ENC_POSDH_POSDH_SHIFT (0U)ENET_EIR_TS_TIMER_MASK (0x8000U)>ENET_EIR_TS_TIMER_SHIFT (15U)>ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)>ENET_EIR_TS_AVAIL_MASK (0x10000U)>ENET_EIR_TS_AVAIL_SHIFT (16U)>ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)>ENET_EIR_WAKEUP_MASK (0x20000U)>ENET_EIR_WAKEUP_SHIFT (17U)>ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)>ENET_EIR_PLR_MASK (0x40000U)>ENET_EIR_PLR_SHIFT (18U)>ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)>ENET_EIR_UN_MASK (0x80000U)>ENET_EIR_UN_SHIFT (19U)>ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)>ENET_EIR_RL_MASK (0x100000U)>ENET_EIR_RL_SHIFT (20U)>ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)>ENET_EIR_LC_MASK (0x200000U)>ENET_EIR_LC_SHIFT (21U)>ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)>ENET_EIR_EBERR_MASK (0x400000U)>ENET_EIR_EBERR_SHIFT (22U)>ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)>ENET_EIR_MII_MASK (0x800000U)>ENET_EIR_MII_SHIFT (23U)>ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)>ENET_EIR_RXB_MASK (0x1000000U)>ENET_EIR_RXB_SHIFT (24U)>ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)>ENET_EIR_RXF_MASK (0x2000000U)>ENET_EIR_RXF_SHIFT (25U)>ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)>ENET_EIR_TXB_MASK (0x4000000U)>ENET_EIR_TXB_SHIFT (26U)>ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)>ENET_EIR_TXF_MASK (0x8000000U)?ENET_EIR_TXF_SHIFT (27U)?ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)?ENET_EIR_GRA_MASK (0x10000000U)?ENET_EIR_GRA_SHIFT (28U)?ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)?ENET_EIR_BABT_MASK (0x20000000U)?ENET_EIR_BABT_SHIFT (29U)?ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)?ENET_EIR_BABR_MASK (0x40000000U)?ENET_EIR_BABR_SHIFT (30U)?ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)?ENET_EIMR_TS_TIMER_MASK (0x8000U)?ENET_EIMR_TS_TIMER_SHIFT (15U)?ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)?ENET_EIMR_TS_AVAIL_MASK (0x10000U)?ENET_EIMR_TS_AVAIL_SHIFT (16U)?ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)?ENET_EIMR_WAKEUP_MASK (0x20000U)?ENET_EIMR_WAKEUP_SHIFT (17U)?ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)?ENET_EIMR_PLR_MASK (0x40000U)?ENET_EIMR_PLR_SHIFT (18U)?ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)?ENET_EIMR_UN_MASK (0x80000U)?ENET_EIMR_UN_SHIFT (19U)?ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)?ENET_EIMR_RL_MASK (0x100000U)?ENET_EIMR_RL_SHIFT (20U)?ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)?ENET_EIMR_LC_MASK (0x200000U)?ENET_EIMR_LC_SHIFT (21U)?ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)?ENET_EIMR_EBERR_MASK (0x400000U)?ENET_EIMR_EBERR_SHIFT (22U)?ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)?ENET_EIMR_MII_MASK (0x800000U)?ENET_EIMR_MII_SHIFT (23U)?ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)?ENET_EIMR_RXB_MASK (0x1000000U)?ENET_EIMR_RXB_SHIFT (24U)?ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)?ENET_EIMR_RXF_MASK (0x2000000U)?ENET_EIMR_RXF_SHIFT (25U)?ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)?ENET_EIMR_TXB_MASK (0x4000000U)?ENET_EIMR_TXB_SHIFT (26U)?ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)?ENET_EIMR_TXF_MASK (0x8000000U)?ENET_EIMR_TXF_SHIFT (27U)?ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)?ENET_EIMR_GRA_MASK (0x10000000U)?ENET_EIMR_GRA_SHIFT (28U)?ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)?ENET_EIMR_BABT_MASK (0x20000000U)?ENET_EIMR_BABT_SHIFT (29U)?ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)?ENET_EIMR_BABR_MASK (0x40000000U)?ENET_EIMR_BABR_SHIFT (30U)?ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)?ENET_RDAR_RDAR_MASK (0x1000000U)?ENET_RDAR_RDAR_SHIFT (24U)?ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)?ENET_TDAR_TDAR_MASK (0x1000000U)?ENET_TDAR_TDAR_SHIFT (24U)?ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)?ENET_ECR_RESET_MASK (0x1U)?ENET_ECR_RESET_SHIFT (0U)?ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)?ENET_ECR_ETHEREN_MASK (0x2U)?ENET_ECR_ETHEREN_SHIFT (1U)?ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)?ENET_ECR_MAGICEN_MASK (0x4U)?ENET_ECR_MAGICEN_SHIFT (2U)?ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)?ENET_ECR_SLEEP_MASK (0x8U)?ENET_ECR_SLEEP_SHIFT (3U)?ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)?ENET_ECR_EN1588_MASK (0x10U)?ENET_ECR_EN1588_SHIFT (4U)?ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)?ENET_ECR_DBGEN_MASK (0x40U)?ENET_ECR_DBGEN_SHIFT (6U)?ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)?ENET_ECR_DBSWP_MASK (0x100U)?ENET_ECR_DBSWP_SHIFT (8U)?ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)?ENET_MMFR_DATA_MASK (0xFFFFU)?ENET_MMFR_DATA_SHIFT (0U)?ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)?ENET_MMFR_TA_MASK (0x30000U)?ENET_MMFR_TA_SHIFT (16U)?ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)?ENET_MMFR_RA_MASK (0x7C0000U)?ENET_MMFR_RA_SHIFT (18U)?ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)?ENET_MMFR_PA_MASK (0xF800000U)?ENET_MMFR_PA_SHIFT (23U)?ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)?ENET_MMFR_OP_MASK (0x30000000U)?ENET_MMFR_OP_SHIFT (28U)?ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)?ENET_MMFR_ST_MASK (0xC0000000U)?ENET_MMFR_ST_SHIFT (30U)?ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)@ENET_MSCR_MII_SPEED_MASK (0x7EU)@ENET_MSCR_MII_SPEED_SHIFT (1U)@ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)@ENET_MSCR_DIS_PRE_MASK (0x80U)@ENET_MSCR_DIS_PRE_SHIFT (7U)@ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)@ENET_MSCR_HOLDTIME_MASK (0x700U)@ENET_MSCR_HOLDTIME_SHIFT (8U)@ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)@ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)@ENET_MIBC_MIB_CLEAR_SHIFT (29U)@ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)@ENET_MIBC_MIB_IDLE_MASK (0x40000000U)@ENET_MIBC_MIB_IDLE_SHIFT (30U)@ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)@ENET_MIBC_MIB_DIS_MASK (0x80000000U)@ENET_MIBC_MIB_DIS_SHIFT (31U)@ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)@ENET_RCR_LOOP_MASK (0x1U)@ENET_RCR_LOOP_SHIFT (0U)@ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)@ENET_RCR_DRT_MASK (0x2U)@ENET_RCR_DRT_SHIFT (1U)@ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)@ENET_RCR_MII_MODE_MASK (0x4U)@ENET_RCR_MII_MODE_SHIFT (2U)@ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)@ENET_RCR_PROM_MASK (0x8U)@ENET_RCR_PROM_SHIFT (3U)@ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)@ENET_RCR_BC_REJ_MASK (0x10U)@ENET_RCR_BC_REJ_SHIFT (4U)@ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)@ENET_RCR_FCE_MASK (0x20U)@ENET_RCR_FCE_SHIFT (5U)@ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)@ENET_RCR_RMII_MODE_MASK (0x100U)@ENET_RCR_RMII_MODE_SHIFT (8U)@ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)@ENET_RCR_RMII_10T_MASK (0x200U)@ENET_RCR_RMII_10T_SHIFT (9U)@ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)@ENET_RCR_PADEN_MASK (0x1000U)@ENET_RCR_PADEN_SHIFT (12U)@ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)@ENET_RCR_PAUFWD_MASK (0x2000U)@ENET_RCR_PAUFWD_SHIFT (13U)@ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)@ENET_RCR_CRCFWD_MASK (0x4000U)@ENET_RCR_CRCFWD_SHIFT (14U)@ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)@ENET_RCR_CFEN_MASK (0x8000U)@ENET_RCR_CFEN_SHIFT (15U)@ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)@ENET_RCR_MAX_FL_MASK (0x3FFF0000U)@ENET_RCR_MAX_FL_SHIFT (16U)@ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)@ENET_RCR_NLC_MASK (0x40000000U)@ENET_RCR_NLC_SHIFT (30U)@ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)@ENET_RCR_GRS_MASK (0x80000000U)@ENET_RCR_GRS_SHIFT (31U)@ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)@ENET_TCR_GTS_MASK (0x1U)@ENET_TCR_GTS_SHIFT (0U)@ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)@ENET_TCR_FDEN_MASK (0x4U)@ENET_TCR_FDEN_SHIFT (2U)@ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)@ENET_TCR_TFC_PAUSE_MASK (0x8U)@ENET_TCR_TFC_PAUSE_SHIFT (3U)@ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)@ENET_TCR_RFC_PAUSE_MASK (0x10U)@ENET_TCR_RFC_PAUSE_SHIFT (4U)@ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)@ENET_TCR_ADDSEL_MASK (0xE0U)@ENET_TCR_ADDSEL_SHIFT (5U)@ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)@ENET_TCR_ADDINS_MASK (0x100U)@ENET_TCR_ADDINS_SHIFT (8U)@ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)@ENET_TCR_CRCFWD_MASK (0x200U)@ENET_TCR_CRCFWD_SHIFT (9U)@ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)@ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)@ENET_PALR_PADDR1_SHIFT (0U)@ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)@ENET_PAUR_TYPE_MASK (0xFFFFU)@ENET_PAUR_TYPE_SHIFT (0U)@ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)@ENET_PAUR_PADDR2_MASK (0xFFFF0000U)@ENET_PAUR_PADDR2_SHIFT (16U)@ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)@ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)@ENET_OPD_PAUSE_DUR_SHIFT (0U)@ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)@ENET_OPD_OPCODE_MASK (0xFFFF0000U)@ENET_OPD_OPCODE_SHIFT (16U)@ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)@ENET_TXIC_ICTT_MASK (0xFFFFU)AENET_TXIC_ICTT_SHIFT (0U)AENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)AENET_TXIC_ICFT_MASK (0xFF00000U)AENET_TXIC_ICFT_SHIFT (20U)AENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)AENET_TXIC_ICCS_MASK (0x40000000U)AENET_TXIC_ICCS_SHIFT (30U)AENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)AENET_TXIC_ICEN_MASK (0x80000000U)AENET_TXIC_ICEN_SHIFT (31U)AENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)AENET_RXIC_ICTT_MASK (0xFFFFU)AENET_RXIC_ICTT_SHIFT (0U)AENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)AENET_RXIC_ICFT_MASK (0xFF00000U)AENET_RXIC_ICFT_SHIFT (20U)AENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)AENET_RXIC_ICCS_MASK (0x40000000U)AENET_RXIC_ICCS_SHIFT (30U)AENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)AENET_RXIC_ICEN_MASK (0x80000000U)AENET_RXIC_ICEN_SHIFT (31U)AENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)AENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)AENET_IAUR_IADDR1_SHIFT (0U)AENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)AENET_IALR_IADDR2_MASK (0xFFFFFFFFU)AENET_IALR_IADDR2_SHIFT (0U)AENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)AENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)AENET_GAUR_GADDR1_SHIFT (0U)AENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)AENET_GALR_GADDR2_MASK (0xFFFFFFFFU)AENET_GALR_GADDR2_SHIFT (0U)AENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)AENET_TFWR_TFWR_MASK (0x3FU)AENET_TFWR_TFWR_SHIFT (0U)AENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)AENET_TFWR_STRFWD_MASK (0x100U)AENET_TFWR_STRFWD_SHIFT (8U)AENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)AENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)AENET_RDSR_R_DES_START_SHIFT (3U)AENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)AENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)AENET_TDSR_X_DES_START_SHIFT (3U)AENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)AENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)AENET_MRBR_R_BUF_SIZE_SHIFT (4U)AENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)AENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)AENET_RSFL_RX_SECTION_FULL_SHIFT (0U)AENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)AENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)AENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)AENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)AENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)AENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)AENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)AENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)AENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)AENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)AENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)AENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)AENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)AENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)AENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)AENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)BENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)BENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)BENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)BENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)BENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)BENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)BENET_TIPG_IPG_MASK (0x1FU)BENET_TIPG_IPG_SHIFT (0U)BENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)BENET_FTRL_TRUNC_FL_MASK (0x3FFFU)BENET_FTRL_TRUNC_FL_SHIFT (0U)BENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)BENET_TACC_SHIFT16_MASK (0x1U)BENET_TACC_SHIFT16_SHIFT (0U)BENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)BENET_TACC_IPCHK_MASK (0x8U)BENET_TACC_IPCHK_SHIFT (3U)BENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)BENET_TACC_PROCHK_MASK (0x10U)BENET_TACC_PROCHK_SHIFT (4U)BENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)BENET_RACC_PADREM_MASK (0x1U)BENET_RACC_PADREM_SHIFT (0U)BENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)BENET_RACC_IPDIS_MASK (0x2U)BENET_RACC_IPDIS_SHIFT (1U)BENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)BENET_RACC_PRODIS_MASK (0x4U)BENET_RACC_PRODIS_SHIFT (2U)BENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)BENET_RACC_LINEDIS_MASK (0x40U)BENET_RACC_LINEDIS_SHIFT (6U)BENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)BENET_RACC_SHIFT16_MASK (0x80U)BENET_RACC_SHIFT16_SHIFT (7U)BENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)BENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)BENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)BENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)BENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)BENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)BENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)BENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)BENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)BENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)BENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)BENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)BENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)BENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)BENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)BENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_JAB_TXPKTS_SHIFT (0U)BENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)BENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_COL_TXPKTS_SHIFT (0U)BENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)BENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_P64_TXPKTS_SHIFT (0U)BENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)CENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)CENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)CENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)CENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)CENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)CENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)CENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)CENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)CENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)CENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)CENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)CENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)CENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)CENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)CENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)CENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)CENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)CENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)CENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)CENET_IEEE_T_1COL_COUNT_SHIFT (0U)CENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)CENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)CENET_IEEE_T_MCOL_COUNT_SHIFT (0U)CENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)CENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)CENET_IEEE_T_DEF_COUNT_SHIFT (0U)CENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)CENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)CENET_IEEE_T_LCOL_COUNT_SHIFT (0U)CENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)CENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)CENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)CENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)CENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)CENET_IEEE_T_MACERR_COUNT_SHIFT (0U)CENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)CENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)CENET_IEEE_T_CSERR_COUNT_SHIFT (0U)CENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)CENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)CENET_IEEE_T_SQE_COUNT_SHIFT (0U)CENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)CENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)CENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)CENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)CENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)CENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)CENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)DENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)DENET_RMON_R_PACKETS_COUNT_SHIFT (0U)DENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)DENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)DENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)DENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)DENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)DENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)DENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)DENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)DENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)DENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)DENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)DENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)DENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)DENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)DENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)DENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)DENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)DENET_RMON_R_FRAG_COUNT_SHIFT (0U)DENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)DENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)DENET_RMON_R_JAB_COUNT_SHIFT (0U)DENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)DENET_RMON_R_P64_COUNT_MASK (0xFFFFU)DENET_RMON_R_P64_COUNT_SHIFT (0U)DENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)DENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)DENET_RMON_R_P65TO127_COUNT_SHIFT (0U)DENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)DENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)DENET_RMON_R_P128TO255_COUNT_SHIFT (0U)DENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)DENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)DENET_RMON_R_P256TO511_COUNT_SHIFT (0U)DENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)DENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)DENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)DENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)DENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)DENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)DENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)DENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)DENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)DENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)DENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)DENET_RMON_R_OCTETS_COUNT_SHIFT (0U)DENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)DENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)DENET_IEEE_R_DROP_COUNT_SHIFT (0U)DENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)DENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)DENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)DENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)DENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)DENET_IEEE_R_CRC_COUNT_SHIFT (0U)EENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)EENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)EENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)EENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)EENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)EENET_IEEE_R_MACERR_COUNT_SHIFT (0U)EENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)EENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)EENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)EENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)EENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)EENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)EENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)EENET_ATCR_EN_MASK (0x1U)EENET_ATCR_EN_SHIFT (0U)EENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)EENET_ATCR_OFFEN_MASK (0x4U)EENET_ATCR_OFFEN_SHIFT (2U)EENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)EENET_ATCR_OFFRST_MASK (0x8U)EENET_ATCR_OFFRST_SHIFT (3U)EENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)EENET_ATCR_PEREN_MASK (0x10U)EENET_ATCR_PEREN_SHIFT (4U)EENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)EENET_ATCR_PINPER_MASK (0x80U)EENET_ATCR_PINPER_SHIFT (7U)EENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)EENET_ATCR_RESTART_MASK (0x200U)EENET_ATCR_RESTART_SHIFT (9U)EENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)EENET_ATCR_CAPTURE_MASK (0x800U)EENET_ATCR_CAPTURE_SHIFT (11U)EENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)EENET_ATCR_SLAVE_MASK (0x2000U)EENET_ATCR_SLAVE_SHIFT (13U)EENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)EENET_ATVR_ATIME_MASK (0xFFFFFFFFU)EENET_ATVR_ATIME_SHIFT (0U)EENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)EENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)EENET_ATOFF_OFFSET_SHIFT (0U)EENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)EENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)EENET_ATPER_PERIOD_SHIFT (0U)EENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)EENET_ATCOR_COR_MASK (0x7FFFFFFFU)EENET_ATCOR_COR_SHIFT (0U)EENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)EENET_ATINC_INC_MASK (0x7FU)EENET_ATINC_INC_SHIFT (0U)EENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)EENET_ATINC_INC_CORR_MASK (0x7F00U)EENET_ATINC_INC_CORR_SHIFT (8U)EENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)EENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)EENET_ATSTMP_TIMESTAMP_SHIFT (0U)EENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)EENET_TGSR_TF0_MASK (0x1U)EENET_TGSR_TF0_SHIFT (0U)EENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)EENET_TGSR_TF1_MASK (0x2U)EENET_TGSR_TF1_SHIFT (1U)EENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)EENET_TGSR_TF2_MASK (0x4U)EENET_TGSR_TF2_SHIFT (2U)EENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)EENET_TGSR_TF3_MASK (0x8U)EENET_TGSR_TF3_SHIFT (3U)EENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)EENET_TCSR_TDRE_MASK (0x1U)EENET_TCSR_TDRE_SHIFT (0U)EENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)EENET_TCSR_TMODE_MASK (0x3CU)EENET_TCSR_TMODE_SHIFT (2U)EENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)FENET_TCSR_TIE_MASK (0x40U)FENET_TCSR_TIE_SHIFT (6U)FENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)FENET_TCSR_TF_MASK (0x80U)FENET_TCSR_TF_SHIFT (7U)FENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)FENET_TCSR_TPWC_MASK (0xF800U)FENET_TCSR_TPWC_SHIFT (11U)FENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)FENET_TCSR_COUNT (4U)FENET_TCCR_TCC_MASK (0xFFFFFFFFU)FENET_TCCR_TCC_SHIFT (0U)FENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)FENET_TCCR_COUNT (4U)FENET_BASE (0x402D8000u)FENET ((ENET_Type *)ENET_BASE)FENET_BASE_ADDRS { ENET_BASE }FENET_BASE_PTRS { ENET }FENET_Transmit_IRQS { ENET_IRQn }FENET_Receive_IRQS { ENET_IRQn }FENET_Error_IRQS { ENET_IRQn }FENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }FENET_BUFF_ALIGNMENT (64U)FEWM_CTRL_EWMEN_MASK (0x1U)FEWM_CTRL_EWMEN_SHIFT (0U)FEWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)FEWM_CTRL_ASSIN_MASK (0x2U)FEWM_CTRL_ASSIN_SHIFT (1U)FEWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)FEWM_CTRL_INEN_MASK (0x4U)FEWM_CTRL_INEN_SHIFT (2U)FEWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)FEWM_CTRL_INTEN_MASK (0x8U)FEWM_CTRL_INTEN_SHIFT (3U)FEWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)FEWM_SERV_SERVICE_MASK (0xFFU)FEWM_SERV_SERVICE_SHIFT (0U)FEWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)FEWM_CMPL_COMPAREL_MASK (0xFFU)FEWM_CMPL_COMPAREL_SHIFT (0U)FEWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)FEWM_CMPH_COMPAREH_MASK (0xFFU)FEWM_CMPH_COMPAREH_SHIFT (0U)FEWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)FEWM_CLKCTRL_CLKSEL_MASK (0x3U)FEWM_CLKCTRL_CLKSEL_SHIFT (0U)FEWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)FEWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)GEWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)GEWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)GEWM_BASE (0x400B4000u)GEWM ((EWM_Type *)EWM_BASE)GEWM_BASE_ADDRS { EWM_BASE }GEWM_BASE_PTRS { EWM }GEWM_IRQS { EWM_IRQn }GFLEXIO_VERID_FEATURE_MASK (0xFFFFU)GFLEXIO_VERID_FEATURE_SHIFT (0U)GFLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)GFLEXIO_VERID_MINOR_MASK (0xFF0000U)GFLEXIO_VERID_MINOR_SHIFT (16U)GFLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)GFLEXIO_VERID_MAJOR_MASK (0xFF000000U)GFLEXIO_VERID_MAJOR_SHIFT (24U)GFLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)GFLEXIO_PARAM_SHIFTER_MASK (0xFFU)GFLEXIO_PARAM_SHIFTER_SHIFT (0U)GFLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)GFLEXIO_PARAM_TIMER_MASK (0xFF00U)GFLEXIO_PARAM_TIMER_SHIFT (8U)GFLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)GFLEXIO_PARAM_PIN_MASK (0xFF0000U)GFLEXIO_PARAM_PIN_SHIFT (16U)GFLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)GFLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)GFLEXIO_PARAM_TRIGGER_SHIFT (24U)GFLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)GFLEXIO_CTRL_FLEXEN_MASK (0x1U)GFLEXIO_CTRL_FLEXEN_SHIFT (0U)GFLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)GFLEXIO_CTRL_SWRST_MASK (0x2U)GFLEXIO_CTRL_SWRST_SHIFT (1U)GFLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)GFLEXIO_CTRL_FASTACC_MASK (0x4U)GFLEXIO_CTRL_FASTACC_SHIFT (2U)GFLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)HFLEXIO_CTRL_DBGE_MASK (0x40000000U)HFLEXIO_CTRL_DBGE_SHIFT (30U)HFLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)HFLEXIO_CTRL_DOZEN_MASK (0x80000000U)HFLEXIO_CTRL_DOZEN_SHIFT (31U)HFLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)HFLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)HFLEXIO_PIN_PDI_SHIFT (0U)HFLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)HFLEXIO_SHIFTSTAT_SSF_MASK (0xFU)HFLEXIO_SHIFTSTAT_SSF_SHIFT (0U)HFLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)HFLEXIO_SHIFTERR_SEF_MASK (0xFU)HFLEXIO_SHIFTERR_SEF_SHIFT (0U)HFLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)HFLEXIO_TIMSTAT_TSF_MASK (0xFU)HFLEXIO_TIMSTAT_TSF_SHIFT (0U)HFLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)HFLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)HFLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)HFLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)HFLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)HFLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)HFLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)HFLEXIO_TIMIEN_TEIE_MASK (0xFU)HFLEXIO_TIMIEN_TEIE_SHIFT (0U)HFLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)HFLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)HFLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)HFLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)HFLEXIO_SHIFTSTATE_STATE_MASK (0x7U)HFLEXIO_SHIFTSTATE_STATE_SHIFT (0U)HFLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)HFLEXIO_SHIFTCTL_SMOD_MASK (0x7U)HFLEXIO_SHIFTCTL_SMOD_SHIFT (0U)HFLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)HFLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)HFLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)HFLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)HFLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)HFLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)HFLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)HFLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)HFLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)HFLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)HFLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)HFLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)HFLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)HFLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)HFLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)HFLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)HFLEXIO_SHIFTCTL_COUNT (4U)HFLEXIO_SHIFTCFG_SSTART_MASK (0x3U)HFLEXIO_SHIFTCFG_SSTART_SHIFT (0U)HFLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)HFLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)HFLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)HFLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)HFLEXIO_SHIFTCFG_INSRC_MASK (0x100U)HFLEXIO_SHIFTCFG_INSRC_SHIFT (8U)HFLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)HFLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)HFLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)HFLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)HFLEXIO_SHIFTCFG_COUNT (4U)HFLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)HFLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)HFLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)HFLEXIO_SHIFTBUF_COUNT (4U)HFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)IFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)IFLEXIO_SHIFTBUFBIS_COUNT (4U)IFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)IFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)IFLEXIO_SHIFTBUFBYS_COUNT (4U)IFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)IFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)IFLEXIO_SHIFTBUFBBS_COUNT (4U)IFLEXIO_TIMCTL_TIMOD_MASK (0x3U)IFLEXIO_TIMCTL_TIMOD_SHIFT (0U)IFLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)IFLEXIO_TIMCTL_PINPOL_MASK (0x80U)IFLEXIO_TIMCTL_PINPOL_SHIFT (7U)IFLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)IFLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)IFLEXIO_TIMCTL_PINSEL_SHIFT (8U)IFLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)IFLEXIO_TIMCTL_PINCFG_MASK (0x30000U)IFLEXIO_TIMCTL_PINCFG_SHIFT (16U)IFLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)IFLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)IFLEXIO_TIMCTL_TRGSRC_SHIFT (22U)IFLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)IFLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)IFLEXIO_TIMCTL_TRGPOL_SHIFT (23U)IFLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)IFLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)IFLEXIO_TIMCTL_TRGSEL_SHIFT (24U)IFLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)IFLEXIO_TIMCTL_COUNT (4U)IFLEXIO_TIMCFG_TSTART_MASK (0x2U)IFLEXIO_TIMCFG_TSTART_SHIFT (1U)IFLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)IFLEXIO_TIMCFG_TSTOP_MASK (0x30U)IFLEXIO_TIMCFG_TSTOP_SHIFT (4U)IFLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)IFLEXIO_TIMCFG_TIMENA_MASK (0x700U)IFLEXIO_TIMCFG_TIMENA_SHIFT (8U)IFLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)IFLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)IFLEXIO_TIMCFG_TIMDIS_SHIFT (12U)IFLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)IFLEXIO_TIMCFG_TIMRST_MASK (0x70000U)IFLEXIO_TIMCFG_TIMRST_SHIFT (16U)IFLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)IFLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)IFLEXIO_TIMCFG_TIMDEC_SHIFT (20U)IFLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)IFLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)IFLEXIO_TIMCFG_TIMOUT_SHIFT (24U)IFLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)IFLEXIO_TIMCFG_COUNT (4U)IFLEXIO_TIMCMP_CMP_MASK (0xFFFFU)IFLEXIO_TIMCMP_CMP_SHIFT (0U)IFLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)IFLEXIO_TIMCMP_COUNT (4U)IFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)IFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)IFLEXIO_SHIFTBUFNBS_COUNT (4U)IFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)IFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)IFLEXIO_SHIFTBUFHWS_COUNT (4U)IFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)IFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)IFLEXIO_SHIFTBUFNIS_COUNT (4U)JFLEXIO1_BASE (0x401AC000u)JFLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)JFLEXIO2_BASE (0x401B0000u)JFLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)JFLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }JFLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }JFLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, NotAvail_IRQn }JFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)JFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)JFLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)JFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)JFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)JFLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)JFLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)JFLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)JFLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)JFLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U)JFLEXRAM_TCM_CTRL_Reserved_SHIFT (3U)JFLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)JFLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)JFLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U)JFLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)JFLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)JFLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U)JFLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)JFLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)JFLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U)JFLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)JFLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U)JFLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)JFLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)JFLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U)JFLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)JFLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)JFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)JFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)JFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)JFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)JFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)JFLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)JFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)JFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)JFLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)JFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)JFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)JFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)JFLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U)JFLEXRAM_INT_STATUS_Reserved_SHIFT (6U)KFLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)KFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)KFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)KFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)KFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)KFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)KFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)KFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)KFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)KFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)KFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)KFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)KFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)KFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U)KFLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U)KFLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)KFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U)KFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)KFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U)KFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)KFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)KFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)KFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)KFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)KFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)KFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)KFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)KFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)KFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U)KFLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U)KFLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)KFLEXRAM_BASE (0x400B0000u)KFLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)KFLEXRAM_BASE_ADDRS { FLEXRAM_BASE }KFLEXRAM_BASE_PTRS { FLEXRAM }KFLEXRAM_IRQS { FLEXRAM_IRQn }LFLEXSPI_MCR0_SWRESET_MASK (0x1U)LFLEXSPI_MCR0_SWRESET_SHIFT (0U)LFLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)LFLEXSPI_MCR0_MDIS_MASK (0x2U)LFLEXSPI_MCR0_MDIS_SHIFT (1U)LFLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)LFLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)LFLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)LFLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)LFLEXSPI_MCR0_ARDFEN_MASK (0x40U)LFLEXSPI_MCR0_ARDFEN_SHIFT (6U)LFLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)LFLEXSPI_MCR0_ATDFEN_MASK (0x80U)LFLEXSPI_MCR0_ATDFEN_SHIFT (7U)LFLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)LFLEXSPI_MCR0_HSEN_MASK (0x800U)LFLEXSPI_MCR0_HSEN_SHIFT (11U)LFLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)LFLEXSPI_MCR0_DOZEEN_MASK (0x1000U)LFLEXSPI_MCR0_DOZEEN_SHIFT (12U)LFLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)LFLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)LFLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)LFLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)LFLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)LFLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)LFLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)LFLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)LFLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)LFLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)LFLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)LFLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)LFLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)LFLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)LFLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)LFLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)LFLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)LFLEXSPI_MCR1_SEQWAIT_SHIFT (16U)LFLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)LFLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)LFLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)LFLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)LFLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)LFLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)LFLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)LFLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)LFLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)LFLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)LFLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)LFLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)LFLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)LFLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)LFLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)LFLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)LFLEXSPI_AHBCR_APAREN_MASK (0x1U)LFLEXSPI_AHBCR_APAREN_SHIFT (0U)LFLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)LFLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)LFLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)LFLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)LFLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)LFLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)LFLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)LFLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)LFLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)LFLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)LFLEXSPI_AHBCR_READADDROPT_MASK (0x40U)LFLEXSPI_AHBCR_READADDROPT_SHIFT (6U)LFLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)LFLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)LFLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)LFLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)LFLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)LFLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)LFLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)LFLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)LFLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)LFLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)LFLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)LFLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)LFLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)LFLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)LFLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)LFLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)LFLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)LFLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)LFLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)LFLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)LFLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)LFLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)LFLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)LFLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)LFLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)LFLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)LFLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)LFLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)LFLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)LFLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)LFLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)LFLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)LFLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)LFLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)MFLEXSPI_INTR_IPCMDDONE_MASK (0x1U)MFLEXSPI_INTR_IPCMDDONE_SHIFT (0U)MFLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)MFLEXSPI_INTR_IPCMDGE_MASK (0x2U)MFLEXSPI_INTR_IPCMDGE_SHIFT (1U)MFLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)MFLEXSPI_INTR_AHBCMDGE_MASK (0x4U)MFLEXSPI_INTR_AHBCMDGE_SHIFT (2U)MFLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)MFLEXSPI_INTR_IPCMDERR_MASK (0x8U)MFLEXSPI_INTR_IPCMDERR_SHIFT (3U)MFLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)MFLEXSPI_INTR_AHBCMDERR_MASK (0x10U)MFLEXSPI_INTR_AHBCMDERR_SHIFT (4U)MFLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)MFLEXSPI_INTR_IPRXWA_MASK (0x20U)MFLEXSPI_INTR_IPRXWA_SHIFT (5U)MFLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)MFLEXSPI_INTR_IPTXWE_MASK (0x40U)MFLEXSPI_INTR_IPTXWE_SHIFT (6U)MFLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)MFLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)MFLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)MFLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)MFLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)MFLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)MFLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)MFLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)MFLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)MFLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)MFLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)MFLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)MFLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)MFLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)MFLEXSPI_LUTKEY_KEY_SHIFT (0U)MFLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)MFLEXSPI_LUTCR_LOCK_MASK (0x1U)MFLEXSPI_LUTCR_LOCK_SHIFT (0U)MFLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)MFLEXSPI_LUTCR_UNLOCK_MASK (0x2U)MFLEXSPI_LUTCR_UNLOCK_SHIFT (1U)MFLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)MFLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)MFLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)MFLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)MFLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)MFLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)MFLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)MFLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)MFLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)MFLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)MFLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)MFLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)MFLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)MFLEXSPI_AHBRXBUFCR0_COUNT (4U)MFLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)MFLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)MFLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)MFLEXSPI_FLSHCR0_COUNT (4U)MFLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)MFLEXSPI_FLSHCR1_TCSS_SHIFT (0U)MFLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)MFLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)MFLEXSPI_FLSHCR1_TCSH_SHIFT (5U)MFLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)MFLEXSPI_FLSHCR1_WA_MASK (0x400U)MFLEXSPI_FLSHCR1_WA_SHIFT (10U)MFLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)MFLEXSPI_FLSHCR1_CAS_MASK (0x7800U)MFLEXSPI_FLSHCR1_CAS_SHIFT (11U)MFLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)MFLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)MFLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)MFLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)MFLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)MFLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)MFLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)MFLEXSPI_FLSHCR1_COUNT (4U)MFLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)MFLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)MFLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)MFLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)MFLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)MFLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)MFLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)MFLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)MFLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)MFLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)MFLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)MFLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)MFLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)MFLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)MFLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)MFLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)MFLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)MFLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)MFLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)NFLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)NFLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)NFLEXSPI_FLSHCR2_COUNT (4U)NFLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)NFLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)NFLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)NFLEXSPI_FLSHCR4_WMENA_MASK (0x4U)NFLEXSPI_FLSHCR4_WMENA_SHIFT (2U)NFLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)NFLEXSPI_FLSHCR4_WMENB_MASK (0x8U)NFLEXSPI_FLSHCR4_WMENB_SHIFT (3U)NFLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)NFLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)NFLEXSPI_IPCR0_SFAR_SHIFT (0U)NFLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)NFLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)NFLEXSPI_IPCR1_IDATSZ_SHIFT (0U)NFLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)NFLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)NFLEXSPI_IPCR1_ISEQID_SHIFT (16U)NFLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)NFLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)NFLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)NFLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)NFLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)NFLEXSPI_IPCR1_IPAREN_SHIFT (31U)NFLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)NFLEXSPI_IPCMD_TRG_MASK (0x1U)NFLEXSPI_IPCMD_TRG_SHIFT (0U)NFLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)NFLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)NFLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)NFLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)NFLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)NFLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)NFLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)NFLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)NFLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)NFLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)NFLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)NFLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)NFLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)NFLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)NFLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)NFLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)NFLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)NFLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)NFLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)NFLEXSPI_DLLCR_DLLEN_MASK (0x1U)NFLEXSPI_DLLCR_DLLEN_SHIFT (0U)NFLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)NFLEXSPI_DLLCR_DLLRESET_MASK (0x2U)NFLEXSPI_DLLCR_DLLRESET_SHIFT (1U)NFLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)NFLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)NFLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)NFLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)NFLEXSPI_DLLCR_OVRDEN_MASK (0x100U)NFLEXSPI_DLLCR_OVRDEN_SHIFT (8U)NFLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)NFLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)NFLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)NFLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)NFLEXSPI_DLLCR_COUNT (2U)NFLEXSPI_STS0_SEQIDLE_MASK (0x1U)NFLEXSPI_STS0_SEQIDLE_SHIFT (0U)NFLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)NFLEXSPI_STS0_ARBIDLE_MASK (0x2U)NFLEXSPI_STS0_ARBIDLE_SHIFT (1U)NFLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)NFLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)NFLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)NFLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)NFLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)NFLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)NFLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)NFLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)NFLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)NFLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)NFLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)NFLEXSPI_STS1_IPCMDERRID_SHIFT (16U)NFLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)NFLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)NFLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)NFLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)OFLEXSPI_STS2_ASLVLOCK_MASK (0x1U)OFLEXSPI_STS2_ASLVLOCK_SHIFT (0U)OFLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)OFLEXSPI_STS2_AREFLOCK_MASK (0x2U)OFLEXSPI_STS2_AREFLOCK_SHIFT (1U)OFLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)OFLEXSPI_STS2_ASLVSEL_MASK (0xFCU)OFLEXSPI_STS2_ASLVSEL_SHIFT (2U)OFLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)OFLEXSPI_STS2_AREFSEL_MASK (0x3F00U)OFLEXSPI_STS2_AREFSEL_SHIFT (8U)OFLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)OFLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)OFLEXSPI_STS2_BSLVLOCK_SHIFT (16U)OFLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)OFLEXSPI_STS2_BREFLOCK_MASK (0x20000U)OFLEXSPI_STS2_BREFLOCK_SHIFT (17U)OFLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)OFLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)OFLEXSPI_STS2_BSLVSEL_SHIFT (18U)OFLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)OFLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)OFLEXSPI_STS2_BREFSEL_SHIFT (24U)OFLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)OFLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)OFLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)OFLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)OFLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)OFLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)OFLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)OFLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)OFLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)OFLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)OFLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)OFLEXSPI_IPRXFSTS_FILL_SHIFT (0U)OFLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)OFLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)OFLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)OFLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)OFLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)OFLEXSPI_IPTXFSTS_FILL_SHIFT (0U)OFLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)OFLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)OFLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)OFLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)OFLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)OFLEXSPI_RFDR_RXDATA_SHIFT (0U)OFLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)OFLEXSPI_RFDR_COUNT (32U)OFLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)OFLEXSPI_TFDR_TXDATA_SHIFT (0U)OFLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)OFLEXSPI_TFDR_COUNT (32U)OFLEXSPI_LUT_OPERAND0_MASK (0xFFU)OFLEXSPI_LUT_OPERAND0_SHIFT (0U)OFLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)OFLEXSPI_LUT_NUM_PADS0_MASK (0x300U)OFLEXSPI_LUT_NUM_PADS0_SHIFT (8U)OFLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)OFLEXSPI_LUT_OPCODE0_MASK (0xFC00U)OFLEXSPI_LUT_OPCODE0_SHIFT (10U)OFLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)OFLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)OFLEXSPI_LUT_OPERAND1_SHIFT (16U)OFLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)OFLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)OFLEXSPI_LUT_NUM_PADS1_SHIFT (24U)OFLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)OFLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)OFLEXSPI_LUT_OPCODE1_SHIFT (26U)OFLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)OFLEXSPI_LUT_COUNT (64U)OFLEXSPI_BASE (0x402A8000u)OFLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)OFLEXSPI_BASE_ADDRS { FLEXSPI_BASE }OFLEXSPI_BASE_PTRS { FLEXSPI }OFLEXSPI_IRQS { FLEXSPI_IRQn }OFlexSPI_AMBA_BASE (0x60000000U)OFlexSPI_ASFM_BASE (0x00000000U)OFlexSPI_ARDF_BASE (0x7FC00000U)PFlexSPI_ATDF_BASE (0x7F800000U)PGPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)PGPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)PGPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)PGPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)PGPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)PGPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)PGPC_CNTR_PDRAM0_PGE_MASK (0x400000U)PGPC_CNTR_PDRAM0_PGE_SHIFT (22U)PGPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)PGPC_IMR_IMR1_MASK (0xFFFFFFFFU)PGPC_IMR_IMR1_SHIFT (0U)PGPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)PGPC_IMR_IMR2_MASK (0xFFFFFFFFU)PGPC_IMR_IMR2_SHIFT (0U)PGPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)PGPC_IMR_IMR3_MASK (0xFFFFFFFFU)PGPC_IMR_IMR3_SHIFT (0U)PGPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)PGPC_IMR_IMR4_MASK (0xFFFFFFFFU)PGPC_IMR_IMR4_SHIFT (0U)PGPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)PGPC_IMR_COUNT (4U)PGPC_ISR_ISR1_MASK (0xFFFFFFFFU)PGPC_ISR_ISR1_SHIFT (0U)PGPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)PGPC_ISR_ISR2_MASK (0xFFFFFFFFU)PGPC_ISR_ISR2_SHIFT (0U)PGPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)PGPC_ISR_ISR3_MASK (0xFFFFFFFFU)PGPC_ISR_ISR3_SHIFT (0U)PGPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)PGPC_ISR_ISR4_MASK (0xFFFFFFFFU)PGPC_ISR_ISR4_SHIFT (0U)PGPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)PGPC_ISR_COUNT (4U)PGPC_IMR5_IMR5_MASK (0xFFFFFFFFU)PGPC_IMR5_IMR5_SHIFT (0U)PGPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)PGPC_ISR5_ISR4_MASK (0xFFFFFFFFU)PGPC_ISR5_ISR4_SHIFT (0U)PGPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)PGPC_BASE (0x400F4000u)PGPC ((GPC_Type *)GPC_BASE)PGPC_BASE_ADDRS { GPC_BASE }PGPC_BASE_PTRS { GPC }PGPC_IRQS { GPC_IRQn }QGPIO_DR_DR_MASK (0xFFFFFFFFU)QGPIO_DR_DR_SHIFT (0U)QGPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)QGPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)QGPIO_GDIR_GDIR_SHIFT (0U)QGPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)QGPIO_PSR_PSR_MASK (0xFFFFFFFFU)QGPIO_PSR_PSR_SHIFT (0U)QGPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)QGPIO_ICR1_ICR0_MASK (0x3U)QGPIO_ICR1_ICR0_SHIFT (0U)QGPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)QGPIO_ICR1_ICR1_MASK (0xCU)QGPIO_ICR1_ICR1_SHIFT (2U)QGPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)QGPIO_ICR1_ICR2_MASK (0x30U)QGPIO_ICR1_ICR2_SHIFT (4U)QGPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)QGPIO_ICR1_ICR3_MASK (0xC0U)QGPIO_ICR1_ICR3_SHIFT (6U)QGPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)QGPIO_ICR1_ICR4_MASK (0x300U)QGPIO_ICR1_ICR4_SHIFT (8U)QGPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)QGPIO_ICR1_ICR5_MASK (0xC00U)QGPIO_ICR1_ICR5_SHIFT (10U)QGPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)QGPIO_ICR1_ICR6_MASK (0x3000U)QGPIO_ICR1_ICR6_SHIFT (12U)QGPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)QGPIO_ICR1_ICR7_MASK (0xC000U)QGPIO_ICR1_ICR7_SHIFT (14U)QGPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)QGPIO_ICR1_ICR8_MASK (0x30000U)QGPIO_ICR1_ICR8_SHIFT (16U)QGPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)QGPIO_ICR1_ICR9_MASK (0xC0000U)QGPIO_ICR1_ICR9_SHIFT (18U)QGPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)QGPIO_ICR1_ICR10_MASK (0x300000U)QGPIO_ICR1_ICR10_SHIFT (20U)QGPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)QGPIO_ICR1_ICR11_MASK (0xC00000U)QGPIO_ICR1_ICR11_SHIFT (22U)QGPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)QGPIO_ICR1_ICR12_MASK (0x3000000U)QGPIO_ICR1_ICR12_SHIFT (24U)QGPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)QGPIO_ICR1_ICR13_MASK (0xC000000U)QGPIO_ICR1_ICR13_SHIFT (26U)QGPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)QGPIO_ICR1_ICR14_MASK (0x30000000U)QGPIO_ICR1_ICR14_SHIFT (28U)QGPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)QGPIO_ICR1_ICR15_MASK (0xC0000000U)QGPIO_ICR1_ICR15_SHIFT (30U)QGPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)QGPIO_ICR2_ICR16_MASK (0x3U)QGPIO_ICR2_ICR16_SHIFT (0U)QGPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)QGPIO_ICR2_ICR17_MASK (0xCU)QGPIO_ICR2_ICR17_SHIFT (2U)QGPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)QGPIO_ICR2_ICR18_MASK (0x30U)QGPIO_ICR2_ICR18_SHIFT (4U)QGPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)QGPIO_ICR2_ICR19_MASK (0xC0U)QGPIO_ICR2_ICR19_SHIFT (6U)QGPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)QGPIO_ICR2_ICR20_MASK (0x300U)QGPIO_ICR2_ICR20_SHIFT (8U)QGPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)QGPIO_ICR2_ICR21_MASK (0xC00U)QGPIO_ICR2_ICR21_SHIFT (10U)QGPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)QGPIO_ICR2_ICR22_MASK (0x3000U)QGPIO_ICR2_ICR22_SHIFT (12U)QGPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)RGPIO_ICR2_ICR23_MASK (0xC000U)RGPIO_ICR2_ICR23_SHIFT (14U)RGPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)RGPIO_ICR2_ICR24_MASK (0x30000U)RGPIO_ICR2_ICR24_SHIFT (16U)RGPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)RGPIO_ICR2_ICR25_MASK (0xC0000U)RGPIO_ICR2_ICR25_SHIFT (18U)RGPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)RGPIO_ICR2_ICR26_MASK (0x300000U)RGPIO_ICR2_ICR26_SHIFT (20U)RGPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)RGPIO_ICR2_ICR27_MASK (0xC00000U)RGPIO_ICR2_ICR27_SHIFT (22U)RGPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)RGPIO_ICR2_ICR28_MASK (0x3000000U)RGPIO_ICR2_ICR28_SHIFT (24U)RGPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)RGPIO_ICR2_ICR29_MASK (0xC000000U)RGPIO_ICR2_ICR29_SHIFT (26U)RGPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)RGPIO_ICR2_ICR30_MASK (0x30000000U)RGPIO_ICR2_ICR30_SHIFT (28U)RGPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)RGPIO_ICR2_ICR31_MASK (0xC0000000U)RGPIO_ICR2_ICR31_SHIFT (30U)RGPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)RGPIO_IMR_IMR_MASK (0xFFFFFFFFU)RGPIO_IMR_IMR_SHIFT (0U)RGPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)RGPIO_ISR_ISR_MASK (0xFFFFFFFFU)RGPIO_ISR_ISR_SHIFT (0U)RGPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)RGPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)RGPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)RGPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)RGPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)RGPIO_DR_SET_DR_SET_SHIFT (0U)RGPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)RGPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)RGPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)RGPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)RGPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)RGPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)RGPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)RGPIO1_BASE (0x401B8000u)RGPIO1 ((GPIO_Type *)GPIO1_BASE)RGPIO2_BASE (0x401BC000u)RGPIO2 ((GPIO_Type *)GPIO2_BASE)RGPIO3_BASE (0x401C0000u)RGPIO3 ((GPIO_Type *)GPIO3_BASE)RGPIO5_BASE (0x400C0000u)RGPIO5 ((GPIO_Type *)GPIO5_BASE)RGPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, 0u, GPIO5_BASE }RGPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, (GPIO_Type *)0u, GPIO5 }RGPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }RGPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, NotAvail_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn }SGPT_CR_EN_MASK (0x1U)SGPT_CR_EN_SHIFT (0U)SGPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)SGPT_CR_ENMOD_MASK (0x2U)SGPT_CR_ENMOD_SHIFT (1U)SGPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)SGPT_CR_DBGEN_MASK (0x4U)SGPT_CR_DBGEN_SHIFT (2U)SGPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)SGPT_CR_WAITEN_MASK (0x8U)SGPT_CR_WAITEN_SHIFT (3U)SGPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)SGPT_CR_DOZEEN_MASK (0x10U)SGPT_CR_DOZEEN_SHIFT (4U)SGPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)SGPT_CR_STOPEN_MASK (0x20U)SGPT_CR_STOPEN_SHIFT (5U)SGPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)SGPT_CR_CLKSRC_MASK (0x1C0U)SGPT_CR_CLKSRC_SHIFT (6U)SGPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)SGPT_CR_FRR_MASK (0x200U)SGPT_CR_FRR_SHIFT (9U)SGPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)SGPT_CR_EN_24M_MASK (0x400U)SGPT_CR_EN_24M_SHIFT (10U)SGPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)SGPT_CR_SWR_MASK (0x8000U)SGPT_CR_SWR_SHIFT (15U)SGPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)SGPT_CR_IM1_MASK (0x30000U)SGPT_CR_IM1_SHIFT (16U)SGPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)SGPT_CR_IM2_MASK (0xC0000U)SGPT_CR_IM2_SHIFT (18U)SGPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)SGPT_CR_OM1_MASK (0x700000U)SGPT_CR_OM1_SHIFT (20U)SGPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)SGPT_CR_OM2_MASK (0x3800000U)SGPT_CR_OM2_SHIFT (23U)SGPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)SGPT_CR_OM3_MASK (0x1C000000U)SGPT_CR_OM3_SHIFT (26U)SGPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)SGPT_CR_FO1_MASK (0x20000000U)SGPT_CR_FO1_SHIFT (29U)SGPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)SGPT_CR_FO2_MASK (0x40000000U)SGPT_CR_FO2_SHIFT (30U)SGPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)SGPT_CR_FO3_MASK (0x80000000U)SGPT_CR_FO3_SHIFT (31U)SGPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)SGPT_PR_PRESCALER_MASK (0xFFFU)SGPT_PR_PRESCALER_SHIFT (0U)SGPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)SGPT_PR_PRESCALER24M_MASK (0xF000U)SGPT_PR_PRESCALER24M_SHIFT (12U)SGPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)SGPT_SR_OF1_MASK (0x1U)SGPT_SR_OF1_SHIFT (0U)SGPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)SGPT_SR_OF2_MASK (0x2U)SGPT_SR_OF2_SHIFT (1U)SGPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)SGPT_SR_OF3_MASK (0x4U)SGPT_SR_OF3_SHIFT (2U)SGPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)SGPT_SR_IF1_MASK (0x8U)SGPT_SR_IF1_SHIFT (3U)SGPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)SGPT_SR_IF2_MASK (0x10U)SGPT_SR_IF2_SHIFT (4U)SGPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)SGPT_SR_ROV_MASK (0x20U)SGPT_SR_ROV_SHIFT (5U)SGPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)SGPT_IR_OF1IE_MASK (0x1U)SGPT_IR_OF1IE_SHIFT (0U)SGPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)SGPT_IR_OF2IE_MASK (0x2U)SGPT_IR_OF2IE_SHIFT (1U)SGPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)SGPT_IR_OF3IE_MASK (0x4U)SGPT_IR_OF3IE_SHIFT (2U)SGPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)SGPT_IR_IF1IE_MASK (0x8U)SGPT_IR_IF1IE_SHIFT (3U)SGPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)SGPT_IR_IF2IE_MASK (0x10U)SGPT_IR_IF2IE_SHIFT (4U)SGPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)SGPT_IR_ROVIE_MASK (0x20U)SGPT_IR_ROVIE_SHIFT (5U)SGPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)SGPT_OCR_COMP_MASK (0xFFFFFFFFU)SGPT_OCR_COMP_SHIFT (0U)SGPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)TGPT_OCR_COUNT (3U)TGPT_ICR_CAPT_MASK (0xFFFFFFFFU)TGPT_ICR_CAPT_SHIFT (0U)TGPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)TGPT_ICR_COUNT (2U)TGPT_CNT_COUNT_MASK (0xFFFFFFFFU)TGPT_CNT_COUNT_SHIFT (0U)TGPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)TGPT1_BASE (0x401EC000u)TGPT1 ((GPT_Type *)GPT1_BASE)TGPT2_BASE (0x401F0000u)TGPT2 ((GPT_Type *)GPT2_BASE)TGPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }TGPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }TGPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }TI2S_VERID_FEATURE_MASK (0xFFFFU)TI2S_VERID_FEATURE_SHIFT (0U)TI2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)TI2S_VERID_MINOR_MASK (0xFF0000U)TI2S_VERID_MINOR_SHIFT (16U)TI2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)TI2S_VERID_MAJOR_MASK (0xFF000000U)TI2S_VERID_MAJOR_SHIFT (24U)TI2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)TI2S_PARAM_DATALINE_MASK (0xFU)TI2S_PARAM_DATALINE_SHIFT (0U)TI2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)TI2S_PARAM_FIFO_MASK (0xF00U)TI2S_PARAM_FIFO_SHIFT (8U)TI2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)TI2S_PARAM_FRAME_MASK (0xF0000U)TI2S_PARAM_FRAME_SHIFT (16U)TI2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)TI2S_TCSR_FRDE_MASK (0x1U)TI2S_TCSR_FRDE_SHIFT (0U)TI2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)TI2S_TCSR_FWDE_MASK (0x2U)TI2S_TCSR_FWDE_SHIFT (1U)TI2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)TI2S_TCSR_FRIE_MASK (0x100U)UI2S_TCSR_FRIE_SHIFT (8U)UI2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)UI2S_TCSR_FWIE_MASK (0x200U)UI2S_TCSR_FWIE_SHIFT (9U)UI2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)UI2S_TCSR_FEIE_MASK (0x400U)UI2S_TCSR_FEIE_SHIFT (10U)UI2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)UI2S_TCSR_SEIE_MASK (0x800U)UI2S_TCSR_SEIE_SHIFT (11U)UI2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)UI2S_TCSR_WSIE_MASK (0x1000U)UI2S_TCSR_WSIE_SHIFT (12U)UI2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)UI2S_TCSR_FRF_MASK (0x10000U)UI2S_TCSR_FRF_SHIFT (16U)UI2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)UI2S_TCSR_FWF_MASK (0x20000U)UI2S_TCSR_FWF_SHIFT (17U)UI2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)UI2S_TCSR_FEF_MASK (0x40000U)UI2S_TCSR_FEF_SHIFT (18U)UI2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)UI2S_TCSR_SEF_MASK (0x80000U)UI2S_TCSR_SEF_SHIFT (19U)UI2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)UI2S_TCSR_WSF_MASK (0x100000U)UI2S_TCSR_WSF_SHIFT (20U)UI2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)UI2S_TCSR_SR_MASK (0x1000000U)UI2S_TCSR_SR_SHIFT (24U)UI2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)UI2S_TCSR_FR_MASK (0x2000000U)UI2S_TCSR_FR_SHIFT (25U)UI2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)UI2S_TCSR_BCE_MASK (0x10000000U)UI2S_TCSR_BCE_SHIFT (28U)UI2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)UI2S_TCSR_DBGE_MASK (0x20000000U)UI2S_TCSR_DBGE_SHIFT (29U)UI2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)UI2S_TCSR_STOPE_MASK (0x40000000U)UI2S_TCSR_STOPE_SHIFT (30U)UI2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)UI2S_TCSR_TE_MASK (0x80000000U)UI2S_TCSR_TE_SHIFT (31U)UI2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)UI2S_TCR1_TFW_MASK (0x1FU)UI2S_TCR1_TFW_SHIFT (0U)UI2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)UI2S_TCR2_DIV_MASK (0xFFU)UI2S_TCR2_DIV_SHIFT (0U)UI2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)UI2S_TCR2_BCD_MASK (0x1000000U)UI2S_TCR2_BCD_SHIFT (24U)UI2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)UI2S_TCR2_BCP_MASK (0x2000000U)UI2S_TCR2_BCP_SHIFT (25U)UI2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)UI2S_TCR2_MSEL_MASK (0xC000000U)UI2S_TCR2_MSEL_SHIFT (26U)UI2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)UI2S_TCR2_BCI_MASK (0x10000000U)UI2S_TCR2_BCI_SHIFT (28U)UI2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)UI2S_TCR2_BCS_MASK (0x20000000U)UI2S_TCR2_BCS_SHIFT (29U)UI2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)UI2S_TCR2_SYNC_MASK (0xC0000000U)UI2S_TCR2_SYNC_SHIFT (30U)UI2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)UI2S_TCR3_WDFL_MASK (0x1FU)UI2S_TCR3_WDFL_SHIFT (0U)UI2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)UI2S_TCR3_TCE_MASK (0xF0000U)UI2S_TCR3_TCE_SHIFT (16U)UI2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)UI2S_TCR3_CFR_MASK (0xF000000U)UI2S_TCR3_CFR_SHIFT (24U)UI2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)UI2S_TCR4_FSD_MASK (0x1U)UI2S_TCR4_FSD_SHIFT (0U)UI2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)UI2S_TCR4_FSP_MASK (0x2U)UI2S_TCR4_FSP_SHIFT (1U)UI2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)UI2S_TCR4_ONDEM_MASK (0x4U)UI2S_TCR4_ONDEM_SHIFT (2U)UI2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)UI2S_TCR4_FSE_MASK (0x8U)UI2S_TCR4_FSE_SHIFT (3U)UI2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)UI2S_TCR4_MF_MASK (0x10U)UI2S_TCR4_MF_SHIFT (4U)UI2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)UI2S_TCR4_CHMOD_MASK (0x20U)UI2S_TCR4_CHMOD_SHIFT (5U)UI2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)UI2S_TCR4_SYWD_MASK (0x1F00U)UI2S_TCR4_SYWD_SHIFT (8U)UI2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)UI2S_TCR4_FRSZ_MASK (0x1F0000U)UI2S_TCR4_FRSZ_SHIFT (16U)UI2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)UI2S_TCR4_FPACK_MASK (0x3000000U)UI2S_TCR4_FPACK_SHIFT (24U)UI2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)UI2S_TCR4_FCOMB_MASK (0xC000000U)UI2S_TCR4_FCOMB_SHIFT (26U)UI2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)UI2S_TCR4_FCONT_MASK (0x10000000U)UI2S_TCR4_FCONT_SHIFT (28U)VI2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)VI2S_TCR5_FBT_MASK (0x1F00U)VI2S_TCR5_FBT_SHIFT (8U)VI2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)VI2S_TCR5_W0W_MASK (0x1F0000U)VI2S_TCR5_W0W_SHIFT (16U)VI2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)VI2S_TCR5_WNW_MASK (0x1F000000U)VI2S_TCR5_WNW_SHIFT (24U)VI2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)VI2S_TDR_TDR_MASK (0xFFFFFFFFU)VI2S_TDR_TDR_SHIFT (0U)VI2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)VI2S_TDR_COUNT (4U)VI2S_TFR_RFP_MASK (0x3FU)VI2S_TFR_RFP_SHIFT (0U)VI2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)VI2S_TFR_WFP_MASK (0x3F0000U)VI2S_TFR_WFP_SHIFT (16U)VI2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)VI2S_TFR_WCP_MASK (0x80000000U)VI2S_TFR_WCP_SHIFT (31U)VI2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)VI2S_TFR_COUNT (4U)VI2S_TMR_TWM_MASK (0xFFFFFFFFU)VI2S_TMR_TWM_SHIFT (0U)VI2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)VI2S_RCSR_FRDE_MASK (0x1U)VI2S_RCSR_FRDE_SHIFT (0U)VI2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)VI2S_RCSR_FWDE_MASK (0x2U)VI2S_RCSR_FWDE_SHIFT (1U)VI2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)VI2S_RCSR_FRIE_MASK (0x100U)VI2S_RCSR_FRIE_SHIFT (8U)VI2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)VI2S_RCSR_FWIE_MASK (0x200U)VI2S_RCSR_FWIE_SHIFT (9U)VI2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)VI2S_RCSR_FEIE_MASK (0x400U)VI2S_RCSR_FEIE_SHIFT (10U)VI2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)VI2S_RCSR_SEIE_MASK (0x800U)VI2S_RCSR_SEIE_SHIFT (11U)VI2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)VI2S_RCSR_WSIE_MASK (0x1000U)VI2S_RCSR_WSIE_SHIFT (12U)VI2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)VI2S_RCSR_FRF_MASK (0x10000U)VI2S_RCSR_FRF_SHIFT (16U)VI2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)VI2S_RCSR_FWF_MASK (0x20000U)VI2S_RCSR_FWF_SHIFT (17U)VI2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)VI2S_RCSR_FEF_MASK (0x40000U)VI2S_RCSR_FEF_SHIFT (18U)VI2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)VI2S_RCSR_SEF_MASK (0x80000U)VI2S_RCSR_SEF_SHIFT (19U)VI2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)VI2S_RCSR_WSF_MASK (0x100000U)VI2S_RCSR_WSF_SHIFT (20U)VI2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)VI2S_RCSR_SR_MASK (0x1000000U)VI2S_RCSR_SR_SHIFT (24U)VI2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)VI2S_RCSR_FR_MASK (0x2000000U)VI2S_RCSR_FR_SHIFT (25U)VI2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)VI2S_RCSR_BCE_MASK (0x10000000U)VI2S_RCSR_BCE_SHIFT (28U)VI2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)VI2S_RCSR_DBGE_MASK (0x20000000U)VI2S_RCSR_DBGE_SHIFT (29U)VI2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)VI2S_RCSR_STOPE_MASK (0x40000000U)VI2S_RCSR_STOPE_SHIFT (30U)VI2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)VI2S_RCSR_RE_MASK (0x80000000U)VI2S_RCSR_RE_SHIFT (31U)VI2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)VI2S_RCR1_RFW_MASK (0x1FU)VI2S_RCR1_RFW_SHIFT (0U)VI2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)VI2S_RCR2_DIV_MASK (0xFFU)VI2S_RCR2_DIV_SHIFT (0U)VI2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)VI2S_RCR2_BCD_MASK (0x1000000U)VI2S_RCR2_BCD_SHIFT (24U)VI2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)VI2S_RCR2_BCP_MASK (0x2000000U)VI2S_RCR2_BCP_SHIFT (25U)VI2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)VI2S_RCR2_MSEL_MASK (0xC000000U)VI2S_RCR2_MSEL_SHIFT (26U)VI2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)WI2S_RCR2_BCI_MASK (0x10000000U)WI2S_RCR2_BCI_SHIFT (28U)WI2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)WI2S_RCR2_BCS_MASK (0x20000000U)WI2S_RCR2_BCS_SHIFT (29U)WI2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)WI2S_RCR2_SYNC_MASK (0xC0000000U)WI2S_RCR2_SYNC_SHIFT (30U)WI2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)WI2S_RCR3_WDFL_MASK (0x1FU)WI2S_RCR3_WDFL_SHIFT (0U)WI2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)WI2S_RCR3_RCE_MASK (0xF0000U)WI2S_RCR3_RCE_SHIFT (16U)WI2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)WI2S_RCR3_CFR_MASK (0xF000000U)WI2S_RCR3_CFR_SHIFT (24U)WI2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)WI2S_RCR4_FSD_MASK (0x1U)WI2S_RCR4_FSD_SHIFT (0U)WI2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)WI2S_RCR4_FSP_MASK (0x2U)WI2S_RCR4_FSP_SHIFT (1U)WI2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)WI2S_RCR4_ONDEM_MASK (0x4U)WI2S_RCR4_ONDEM_SHIFT (2U)WI2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)WI2S_RCR4_FSE_MASK (0x8U)WI2S_RCR4_FSE_SHIFT (3U)WI2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)WI2S_RCR4_MF_MASK (0x10U)WI2S_RCR4_MF_SHIFT (4U)WI2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)WI2S_RCR4_SYWD_MASK (0x1F00U)WI2S_RCR4_SYWD_SHIFT (8U)WI2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)WI2S_RCR4_FRSZ_MASK (0x1F0000U)WI2S_RCR4_FRSZ_SHIFT (16U)WI2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)WI2S_RCR4_FPACK_MASK (0x3000000U)WI2S_RCR4_FPACK_SHIFT (24U)WI2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)WI2S_RCR4_FCOMB_MASK (0xC000000U)WI2S_RCR4_FCOMB_SHIFT (26U)WI2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)WI2S_RCR4_FCONT_MASK (0x10000000U)WI2S_RCR4_FCONT_SHIFT (28U)WI2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)WI2S_RCR5_FBT_MASK (0x1F00U)WI2S_RCR5_FBT_SHIFT (8U)WI2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)WI2S_RCR5_W0W_MASK (0x1F0000U)WI2S_RCR5_W0W_SHIFT (16U)WI2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)WI2S_RCR5_WNW_MASK (0x1F000000U)WI2S_RCR5_WNW_SHIFT (24U)WI2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)WI2S_RDR_RDR_MASK (0xFFFFFFFFU)WI2S_RDR_RDR_SHIFT (0U)WI2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)WI2S_RDR_COUNT (4U)WI2S_RFR_RFP_MASK (0x3FU)WI2S_RFR_RFP_SHIFT (0U)WI2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)WI2S_RFR_RCP_MASK (0x8000U)WI2S_RFR_RCP_SHIFT (15U)WI2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)WI2S_RFR_WFP_MASK (0x3F0000U)WI2S_RFR_WFP_SHIFT (16U)WI2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)WI2S_RFR_COUNT (4U)WI2S_RMR_RWM_MASK (0xFFFFFFFFU)WI2S_RMR_RWM_SHIFT (0U)WI2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)WSAI1_BASE (0x40384000u)WSAI1 ((I2S_Type *)SAI1_BASE)WSAI2_BASE (0x40388000u)WSAI2 ((I2S_Type *)SAI2_BASE)WSAI3_BASE (0x4038C000u)WSAI3 ((I2S_Type *)SAI3_BASE)WI2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }WI2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }XI2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }XI2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }XIOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)XIOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)XIOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)XIOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)XIOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)XIOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)XIOMUXC_SW_MUX_CTL_PAD_COUNT (93U)XIOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)XIOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)XIOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)XIOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)XIOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)XIOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)XIOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)XIOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)XIOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)XIOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)XIOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)XIOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)XIOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)XIOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)XIOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)XIOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)XIOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)XIOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)XIOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)XIOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)XIOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)XIOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)XIOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)XIOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)XIOMUXC_SW_PAD_CTL_PAD_COUNT (93U)XIOMUXC_SELECT_INPUT_DAISY_MASK (0x7U)XIOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)XIOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)XIOMUXC_SELECT_INPUT_COUNT (114U)XIOMUXC_BASE (0x401F8000u)XIOMUXC ((IOMUXC_Type *)IOMUXC_BASE)XIOMUXC_BASE_ADDRS { IOMUXC_BASE }XIOMUXC_BASE_PTRS { IOMUXC }YIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)YIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)YIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)YIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)YIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)YIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)YIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)YIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)YIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)YIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)YIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)YIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)YIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)YIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)YIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)YIOMUXC_GPR_GPR1_GINT_MASK (0x1000U)YIOMUXC_GPR_GPR1_GINT_SHIFT (12U)YIOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)YIOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)YIOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)YIOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)YIOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)YIOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)YIOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)YIOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)YIOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)YIOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)YIOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)YIOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)YIOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)YIOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)YIOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)YIOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)YIOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)YIOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)YIOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)YIOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)YIOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)YIOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)YIOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)YIOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)YIOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)YIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)YIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)YIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)YIOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)YIOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)YIOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)YIOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U)YIOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U)YIOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK)YIOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)YIOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)YIOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)YIOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)YIOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)YIOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)YIOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)YIOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)YIOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)YIOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)YIOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)YIOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)YIOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)YIOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)YIOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)YIOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)YIOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)YIOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)YIOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)YIOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)YIOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)YIOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)YIOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)YIOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)YIOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)YIOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)YIOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)YIOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)YIOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)YIOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)YIOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)YIOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)YIOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)YIOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)ZIOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)ZIOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)ZIOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)ZIOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)ZIOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)ZIOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)ZIOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)ZIOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)ZIOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)ZIOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)ZIOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)ZIOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)ZIOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)ZIOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)ZIOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)ZIOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)ZIOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)ZIOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)ZIOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)ZIOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)ZIOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)ZIOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)ZIOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)ZIOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)ZIOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)ZIOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)ZIOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)ZIOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)ZIOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)ZIOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)ZIOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)ZIOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)ZIOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)ZIOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)ZIOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)ZIOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)ZIOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)ZIOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)ZIOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)ZIOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)ZIOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)ZIOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)ZIOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)ZIOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)ZIOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)ZIOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)ZIOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)ZIOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)ZIOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)ZIOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)ZIOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)[IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)[IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)[IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)[IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)[IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)[IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)[IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)[IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)[IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)[IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)[IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)[IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)[IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)[IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)[IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)[IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)[IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)[IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)[IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)[IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)[IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)[IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)[IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)[IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)[IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)[IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)[IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)[IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)[IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)[IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)[IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)[IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)[IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)[IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)[IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)[IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)[IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)[IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)[IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)[IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)[IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)[IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)[IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)[IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)[IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)[IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)[IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)[IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)[IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)[IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)[IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)[IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)[IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)[IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)[IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)[IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)[IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)[IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)\IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)\IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)\IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)\IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)\IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)\IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)\IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)\IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)\IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)\IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)\IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)\IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)\IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)\IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)\IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)\IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)\IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)\IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)\IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)\IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)\IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)\IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)\IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)\IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)\IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)\IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)\IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)\IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)\IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)\IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)\IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)\IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)\IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)\IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)\IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)\IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)\IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)\IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)\IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)\IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)\IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)\IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)\IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)\IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)\IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)\IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)\IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)\IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)\IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)\IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)\IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)\IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)\IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)\IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)\IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)\IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)\IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)\IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)\IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)\IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)\IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)\IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)\IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)\IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)\IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)\IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)\IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)\IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)\IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)\IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)\IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)\IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)\IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)\IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)\IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)\IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)\IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)\IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)\IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)\IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)\IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)\IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)\IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)\IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)\IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)\IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)\IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)\IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)\IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)]IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)]IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x7E00U)]IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)]IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)]IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)]IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)]IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)]IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)]IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)]IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)]IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)]IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)]IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)]IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)]IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)]IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)]IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)]IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)]IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)]IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)]IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)]IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)]IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)]IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)]IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)]IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)]IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)]IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)]IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)]IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)]IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)]IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)]IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)]IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)]IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)]IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)]IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)]IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)]IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)]IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)]IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)]IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)]IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)]IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)]IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)]IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)]IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)]IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)]IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)]IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)]IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)]IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)]IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)]IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)]IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)]IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)]IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)]IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)]IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)]IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)]IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)]IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)]IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)]IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)^IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)^IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)^IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)^IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)^IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)^IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)^IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)^IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)^IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)^IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)^IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)^IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)^IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U)^IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U)^IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)^IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFU)^IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)^IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)^IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)^IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)^IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)^IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)^IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)^IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)^IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)^IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)^IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)^IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)^IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)^IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)^IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)^IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)^IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)^IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)^IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)^IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)^IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)^IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)^IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)^IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)^IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)^IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)^IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)^IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)^IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)^IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK)^IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)^IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)^IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)^IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)^IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)^IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U)^IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK)^IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)^IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)^IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)^IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)^IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)^IOMUXC_GPR_BASE (0x400AC000u)^IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)^IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }^IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)`IOMUXC_SNVS_BASE (0x400A8000u)`IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)`IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }`IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }aIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)aIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)aIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)aIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)aIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)aIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)aIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)aIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)aIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)aIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)aIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)aIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)aIOMUXC_SNVS_GPR_BASE (0x400A4000u)aIOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)aIOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }aIOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }aKPP_KPCR_KRE_MASK (0xFFU)aKPP_KPCR_KRE_SHIFT (0U)aKPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)aKPP_KPCR_KCO_MASK (0xFF00U)aKPP_KPCR_KCO_SHIFT (8U)aKPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)aKPP_KPSR_KPKD_MASK (0x1U)aKPP_KPSR_KPKD_SHIFT (0U)aKPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)aKPP_KPSR_KPKR_MASK (0x2U)aKPP_KPSR_KPKR_SHIFT (1U)aKPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)aKPP_KPSR_KDSC_MASK (0x4U)aKPP_KPSR_KDSC_SHIFT (2U)aKPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)aKPP_KPSR_KRSS_MASK (0x8U)aKPP_KPSR_KRSS_SHIFT (3U)aKPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)aKPP_KPSR_KDIE_MASK (0x100U)aKPP_KPSR_KDIE_SHIFT (8U)aKPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)aKPP_KPSR_KRIE_MASK (0x200U)aKPP_KPSR_KRIE_SHIFT (9U)aKPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)aKPP_KDDR_KRDD_MASK (0xFFU)bKPP_KDDR_KRDD_SHIFT (0U)bKPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)bKPP_KDDR_KCDD_MASK (0xFF00U)bKPP_KDDR_KCDD_SHIFT (8U)bKPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)bKPP_KPDR_KRD_MASK (0xFFU)bKPP_KPDR_KRD_SHIFT (0U)bKPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)bKPP_KPDR_KCD_MASK (0xFF00U)bKPP_KPDR_KCD_SHIFT (8U)bKPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)bKPP_BASE (0x401FC000u)bKPP ((KPP_Type *)KPP_BASE)bKPP_BASE_ADDRS { KPP_BASE }bKPP_BASE_PTRS { KPP }bKPP_IRQS { KPP_IRQn }bLPI2C_VERID_FEATURE_MASK (0xFFFFU)bLPI2C_VERID_FEATURE_SHIFT (0U)bLPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)bLPI2C_VERID_MINOR_MASK (0xFF0000U)bLPI2C_VERID_MINOR_SHIFT (16U)bLPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)bLPI2C_VERID_MAJOR_MASK (0xFF000000U)bLPI2C_VERID_MAJOR_SHIFT (24U)bLPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)bLPI2C_PARAM_MTXFIFO_MASK (0xFU)bLPI2C_PARAM_MTXFIFO_SHIFT (0U)bLPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)bLPI2C_PARAM_MRXFIFO_MASK (0xF00U)bLPI2C_PARAM_MRXFIFO_SHIFT (8U)bLPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)bLPI2C_MCR_MEN_MASK (0x1U)cLPI2C_MCR_MEN_SHIFT (0U)cLPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)cLPI2C_MCR_RST_MASK (0x2U)cLPI2C_MCR_RST_SHIFT (1U)cLPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)cLPI2C_MCR_DOZEN_MASK (0x4U)cLPI2C_MCR_DOZEN_SHIFT (2U)cLPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)cLPI2C_MCR_DBGEN_MASK (0x8U)cLPI2C_MCR_DBGEN_SHIFT (3U)cLPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)cLPI2C_MCR_RTF_MASK (0x100U)cLPI2C_MCR_RTF_SHIFT (8U)cLPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)cLPI2C_MCR_RRF_MASK (0x200U)cLPI2C_MCR_RRF_SHIFT (9U)cLPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)cLPI2C_MSR_TDF_MASK (0x1U)cLPI2C_MSR_TDF_SHIFT (0U)cLPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)cLPI2C_MSR_RDF_MASK (0x2U)cLPI2C_MSR_RDF_SHIFT (1U)cLPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)cLPI2C_MSR_EPF_MASK (0x100U)cLPI2C_MSR_EPF_SHIFT (8U)cLPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)cLPI2C_MSR_SDF_MASK (0x200U)cLPI2C_MSR_SDF_SHIFT (9U)cLPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)cLPI2C_MSR_NDF_MASK (0x400U)cLPI2C_MSR_NDF_SHIFT (10U)cLPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)cLPI2C_MSR_ALF_MASK (0x800U)cLPI2C_MSR_ALF_SHIFT (11U)cLPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)cLPI2C_MSR_FEF_MASK (0x1000U)cLPI2C_MSR_FEF_SHIFT (12U)cLPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)cLPI2C_MSR_PLTF_MASK (0x2000U)cLPI2C_MSR_PLTF_SHIFT (13U)cLPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)cLPI2C_MSR_DMF_MASK (0x4000U)cLPI2C_MSR_DMF_SHIFT (14U)cLPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)cLPI2C_MSR_MBF_MASK (0x1000000U)cLPI2C_MSR_MBF_SHIFT (24U)cLPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)cLPI2C_MSR_BBF_MASK (0x2000000U)cLPI2C_MSR_BBF_SHIFT (25U)cLPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)cLPI2C_MIER_TDIE_MASK (0x1U)cLPI2C_MIER_TDIE_SHIFT (0U)cLPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)cLPI2C_MIER_RDIE_MASK (0x2U)cLPI2C_MIER_RDIE_SHIFT (1U)cLPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)cLPI2C_MIER_EPIE_MASK (0x100U)cLPI2C_MIER_EPIE_SHIFT (8U)cLPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)cLPI2C_MIER_SDIE_MASK (0x200U)cLPI2C_MIER_SDIE_SHIFT (9U)cLPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)cLPI2C_MIER_NDIE_MASK (0x400U)cLPI2C_MIER_NDIE_SHIFT (10U)cLPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)cLPI2C_MIER_ALIE_MASK (0x800U)cLPI2C_MIER_ALIE_SHIFT (11U)cLPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)cLPI2C_MIER_FEIE_MASK (0x1000U)cLPI2C_MIER_FEIE_SHIFT (12U)cLPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)cLPI2C_MIER_PLTIE_MASK (0x2000U)cLPI2C_MIER_PLTIE_SHIFT (13U)cLPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)cLPI2C_MIER_DMIE_MASK (0x4000U)cLPI2C_MIER_DMIE_SHIFT (14U)cLPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)cLPI2C_MDER_TDDE_MASK (0x1U)cLPI2C_MDER_TDDE_SHIFT (0U)cLPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)cLPI2C_MDER_RDDE_MASK (0x2U)cLPI2C_MDER_RDDE_SHIFT (1U)cLPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)cLPI2C_MCFGR0_HREN_MASK (0x1U)cLPI2C_MCFGR0_HREN_SHIFT (0U)cLPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)cLPI2C_MCFGR0_HRPOL_MASK (0x2U)cLPI2C_MCFGR0_HRPOL_SHIFT (1U)cLPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)cLPI2C_MCFGR0_HRSEL_MASK (0x4U)cLPI2C_MCFGR0_HRSEL_SHIFT (2U)cLPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)cLPI2C_MCFGR0_CIRFIFO_MASK (0x100U)cLPI2C_MCFGR0_CIRFIFO_SHIFT (8U)cLPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)cLPI2C_MCFGR0_RDMO_MASK (0x200U)cLPI2C_MCFGR0_RDMO_SHIFT (9U)cLPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)cLPI2C_MCFGR1_PRESCALE_MASK (0x7U)cLPI2C_MCFGR1_PRESCALE_SHIFT (0U)cLPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)cLPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)cLPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)cLPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)cLPI2C_MCFGR1_IGNACK_MASK (0x200U)cLPI2C_MCFGR1_IGNACK_SHIFT (9U)cLPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)cLPI2C_MCFGR1_TIMECFG_MASK (0x400U)dLPI2C_MCFGR1_TIMECFG_SHIFT (10U)dLPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)dLPI2C_MCFGR1_MATCFG_MASK (0x70000U)dLPI2C_MCFGR1_MATCFG_SHIFT (16U)dLPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)dLPI2C_MCFGR1_PINCFG_MASK (0x7000000U)dLPI2C_MCFGR1_PINCFG_SHIFT (24U)dLPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)dLPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)dLPI2C_MCFGR2_BUSIDLE_SHIFT (0U)dLPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)dLPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)dLPI2C_MCFGR2_FILTSCL_SHIFT (16U)dLPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)dLPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)dLPI2C_MCFGR2_FILTSDA_SHIFT (24U)dLPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)dLPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)dLPI2C_MCFGR3_PINLOW_SHIFT (8U)dLPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)dLPI2C_MDMR_MATCH0_MASK (0xFFU)dLPI2C_MDMR_MATCH0_SHIFT (0U)dLPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)dLPI2C_MDMR_MATCH1_MASK (0xFF0000U)dLPI2C_MDMR_MATCH1_SHIFT (16U)dLPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)dLPI2C_MCCR0_CLKLO_MASK (0x3FU)dLPI2C_MCCR0_CLKLO_SHIFT (0U)dLPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)dLPI2C_MCCR0_CLKHI_MASK (0x3F00U)dLPI2C_MCCR0_CLKHI_SHIFT (8U)dLPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)dLPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)dLPI2C_MCCR0_SETHOLD_SHIFT (16U)dLPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)dLPI2C_MCCR0_DATAVD_MASK (0x3F000000U)dLPI2C_MCCR0_DATAVD_SHIFT (24U)dLPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)dLPI2C_MCCR1_CLKLO_MASK (0x3FU)dLPI2C_MCCR1_CLKLO_SHIFT (0U)dLPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)dLPI2C_MCCR1_CLKHI_MASK (0x3F00U)dLPI2C_MCCR1_CLKHI_SHIFT (8U)dLPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)dLPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)dLPI2C_MCCR1_SETHOLD_SHIFT (16U)dLPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)dLPI2C_MCCR1_DATAVD_MASK (0x3F000000U)dLPI2C_MCCR1_DATAVD_SHIFT (24U)dLPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)dLPI2C_MFCR_TXWATER_MASK (0x3U)dLPI2C_MFCR_TXWATER_SHIFT (0U)dLPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)dLPI2C_MFCR_RXWATER_MASK (0x30000U)dLPI2C_MFCR_RXWATER_SHIFT (16U)dLPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)dLPI2C_MFSR_TXCOUNT_MASK (0x7U)dLPI2C_MFSR_TXCOUNT_SHIFT (0U)dLPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)dLPI2C_MFSR_RXCOUNT_MASK (0x70000U)dLPI2C_MFSR_RXCOUNT_SHIFT (16U)dLPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)dLPI2C_MTDR_DATA_MASK (0xFFU)dLPI2C_MTDR_DATA_SHIFT (0U)dLPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)dLPI2C_MTDR_CMD_MASK (0x700U)dLPI2C_MTDR_CMD_SHIFT (8U)dLPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)dLPI2C_MRDR_DATA_MASK (0xFFU)dLPI2C_MRDR_DATA_SHIFT (0U)dLPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)dLPI2C_MRDR_RXEMPTY_MASK (0x4000U)dLPI2C_MRDR_RXEMPTY_SHIFT (14U)dLPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)dLPI2C_SCR_SEN_MASK (0x1U)dLPI2C_SCR_SEN_SHIFT (0U)dLPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)dLPI2C_SCR_RST_MASK (0x2U)dLPI2C_SCR_RST_SHIFT (1U)dLPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)dLPI2C_SCR_FILTEN_MASK (0x10U)dLPI2C_SCR_FILTEN_SHIFT (4U)dLPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)dLPI2C_SCR_FILTDZ_MASK (0x20U)dLPI2C_SCR_FILTDZ_SHIFT (5U)dLPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)dLPI2C_SCR_RTF_MASK (0x100U)dLPI2C_SCR_RTF_SHIFT (8U)eLPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)eLPI2C_SCR_RRF_MASK (0x200U)eLPI2C_SCR_RRF_SHIFT (9U)eLPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)eLPI2C_SSR_TDF_MASK (0x1U)eLPI2C_SSR_TDF_SHIFT (0U)eLPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)eLPI2C_SSR_RDF_MASK (0x2U)eLPI2C_SSR_RDF_SHIFT (1U)eLPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)eLPI2C_SSR_AVF_MASK (0x4U)eLPI2C_SSR_AVF_SHIFT (2U)eLPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)eLPI2C_SSR_TAF_MASK (0x8U)eLPI2C_SSR_TAF_SHIFT (3U)eLPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)eLPI2C_SSR_RSF_MASK (0x100U)eLPI2C_SSR_RSF_SHIFT (8U)eLPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)eLPI2C_SSR_SDF_MASK (0x200U)eLPI2C_SSR_SDF_SHIFT (9U)eLPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)eLPI2C_SSR_BEF_MASK (0x400U)eLPI2C_SSR_BEF_SHIFT (10U)eLPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)eLPI2C_SSR_FEF_MASK (0x800U)eLPI2C_SSR_FEF_SHIFT (11U)eLPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)eLPI2C_SSR_AM0F_MASK (0x1000U)eLPI2C_SSR_AM0F_SHIFT (12U)eLPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)eLPI2C_SSR_AM1F_MASK (0x2000U)eLPI2C_SSR_AM1F_SHIFT (13U)eLPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)eLPI2C_SSR_GCF_MASK (0x4000U)eLPI2C_SSR_GCF_SHIFT (14U)eLPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)eLPI2C_SSR_SARF_MASK (0x8000U)eLPI2C_SSR_SARF_SHIFT (15U)eLPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)eLPI2C_SSR_SBF_MASK (0x1000000U)eLPI2C_SSR_SBF_SHIFT (24U)eLPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)eLPI2C_SSR_BBF_MASK (0x2000000U)eLPI2C_SSR_BBF_SHIFT (25U)eLPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)eLPI2C_SIER_TDIE_MASK (0x1U)eLPI2C_SIER_TDIE_SHIFT (0U)eLPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)eLPI2C_SIER_RDIE_MASK (0x2U)eLPI2C_SIER_RDIE_SHIFT (1U)eLPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)eLPI2C_SIER_AVIE_MASK (0x4U)eLPI2C_SIER_AVIE_SHIFT (2U)eLPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)eLPI2C_SIER_TAIE_MASK (0x8U)eLPI2C_SIER_TAIE_SHIFT (3U)eLPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)eLPI2C_SIER_RSIE_MASK (0x100U)eLPI2C_SIER_RSIE_SHIFT (8U)eLPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)eLPI2C_SIER_SDIE_MASK (0x200U)eLPI2C_SIER_SDIE_SHIFT (9U)eLPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)eLPI2C_SIER_BEIE_MASK (0x400U)eLPI2C_SIER_BEIE_SHIFT (10U)eLPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)eLPI2C_SIER_FEIE_MASK (0x800U)eLPI2C_SIER_FEIE_SHIFT (11U)eLPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)eLPI2C_SIER_AM0IE_MASK (0x1000U)eLPI2C_SIER_AM0IE_SHIFT (12U)eLPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)eLPI2C_SIER_AM1F_MASK (0x2000U)eLPI2C_SIER_AM1F_SHIFT (13U)eLPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)eLPI2C_SIER_GCIE_MASK (0x4000U)eLPI2C_SIER_GCIE_SHIFT (14U)eLPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)eLPI2C_SIER_SARIE_MASK (0x8000U)eLPI2C_SIER_SARIE_SHIFT (15U)eLPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)eLPI2C_SDER_TDDE_MASK (0x1U)eLPI2C_SDER_TDDE_SHIFT (0U)eLPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)eLPI2C_SDER_RDDE_MASK (0x2U)eLPI2C_SDER_RDDE_SHIFT (1U)eLPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)eLPI2C_SDER_AVDE_MASK (0x4U)eLPI2C_SDER_AVDE_SHIFT (2U)eLPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)eLPI2C_SCFGR1_ADRSTALL_MASK (0x1U)eLPI2C_SCFGR1_ADRSTALL_SHIFT (0U)eLPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)eLPI2C_SCFGR1_RXSTALL_MASK (0x2U)eLPI2C_SCFGR1_RXSTALL_SHIFT (1U)eLPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)eLPI2C_SCFGR1_TXDSTALL_MASK (0x4U)eLPI2C_SCFGR1_TXDSTALL_SHIFT (2U)eLPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)eLPI2C_SCFGR1_ACKSTALL_MASK (0x8U)eLPI2C_SCFGR1_ACKSTALL_SHIFT (3U)eLPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)eLPI2C_SCFGR1_GCEN_MASK (0x100U)eLPI2C_SCFGR1_GCEN_SHIFT (8U)eLPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)eLPI2C_SCFGR1_SAEN_MASK (0x200U)eLPI2C_SCFGR1_SAEN_SHIFT (9U)eLPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)eLPI2C_SCFGR1_TXCFG_MASK (0x400U)eLPI2C_SCFGR1_TXCFG_SHIFT (10U)eLPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)fLPI2C_SCFGR1_RXCFG_MASK (0x800U)fLPI2C_SCFGR1_RXCFG_SHIFT (11U)fLPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)fLPI2C_SCFGR1_IGNACK_MASK (0x1000U)fLPI2C_SCFGR1_IGNACK_SHIFT (12U)fLPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)fLPI2C_SCFGR1_HSMEN_MASK (0x2000U)fLPI2C_SCFGR1_HSMEN_SHIFT (13U)fLPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)fLPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)fLPI2C_SCFGR1_ADDRCFG_SHIFT (16U)fLPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)fLPI2C_SCFGR2_CLKHOLD_MASK (0xFU)fLPI2C_SCFGR2_CLKHOLD_SHIFT (0U)fLPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)fLPI2C_SCFGR2_DATAVD_MASK (0x3F00U)fLPI2C_SCFGR2_DATAVD_SHIFT (8U)fLPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)fLPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)fLPI2C_SCFGR2_FILTSCL_SHIFT (16U)fLPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)fLPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)fLPI2C_SCFGR2_FILTSDA_SHIFT (24U)fLPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)fLPI2C_SAMR_ADDR0_MASK (0x7FEU)fLPI2C_SAMR_ADDR0_SHIFT (1U)fLPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)fLPI2C_SAMR_ADDR1_MASK (0x7FE0000U)fLPI2C_SAMR_ADDR1_SHIFT (17U)fLPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)fLPI2C_SASR_RADDR_MASK (0x7FFU)fLPI2C_SASR_RADDR_SHIFT (0U)fLPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)fLPI2C_SASR_ANV_MASK (0x4000U)fLPI2C_SASR_ANV_SHIFT (14U)fLPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)fLPI2C_STAR_TXNACK_MASK (0x1U)fLPI2C_STAR_TXNACK_SHIFT (0U)fLPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)fLPI2C_STDR_DATA_MASK (0xFFU)fLPI2C_STDR_DATA_SHIFT (0U)fLPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)fLPI2C_SRDR_DATA_MASK (0xFFU)fLPI2C_SRDR_DATA_SHIFT (0U)fLPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)fLPI2C_SRDR_RXEMPTY_MASK (0x4000U)fLPI2C_SRDR_RXEMPTY_SHIFT (14U)fLPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)fLPI2C_SRDR_SOF_MASK (0x8000U)fLPI2C_SRDR_SOF_SHIFT (15U)fLPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)fLPI2C1_BASE (0x403F0000u)fLPI2C1 ((LPI2C_Type *)LPI2C1_BASE)fLPI2C2_BASE (0x403F4000u)fLPI2C2 ((LPI2C_Type *)LPI2C2_BASE)fLPI2C3_BASE (0x403F8000u)fLPI2C3 ((LPI2C_Type *)LPI2C3_BASE)fLPI2C4_BASE (0x403FC000u)fLPI2C4 ((LPI2C_Type *)LPI2C4_BASE)fLPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }fLPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }fLPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }gLPSPI_VERID_FEATURE_MASK (0xFFFFU)gLPSPI_VERID_FEATURE_SHIFT (0U)gLPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)gLPSPI_VERID_MINOR_MASK (0xFF0000U)gLPSPI_VERID_MINOR_SHIFT (16U)gLPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)gLPSPI_VERID_MAJOR_MASK (0xFF000000U)gLPSPI_VERID_MAJOR_SHIFT (24U)gLPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)gLPSPI_PARAM_TXFIFO_MASK (0xFFU)gLPSPI_PARAM_TXFIFO_SHIFT (0U)gLPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)gLPSPI_PARAM_RXFIFO_MASK (0xFF00U)gLPSPI_PARAM_RXFIFO_SHIFT (8U)gLPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)gLPSPI_PARAM_PCSNUM_MASK (0xFF0000U)gLPSPI_PARAM_PCSNUM_SHIFT (16U)gLPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)gLPSPI_CR_MEN_MASK (0x1U)gLPSPI_CR_MEN_SHIFT (0U)gLPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)gLPSPI_CR_RST_MASK (0x2U)gLPSPI_CR_RST_SHIFT (1U)gLPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)gLPSPI_CR_DOZEN_MASK (0x4U)gLPSPI_CR_DOZEN_SHIFT (2U)gLPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)gLPSPI_CR_DBGEN_MASK (0x8U)gLPSPI_CR_DBGEN_SHIFT (3U)gLPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)gLPSPI_CR_RTF_MASK (0x100U)gLPSPI_CR_RTF_SHIFT (8U)gLPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)gLPSPI_CR_RRF_MASK (0x200U)gLPSPI_CR_RRF_SHIFT (9U)gLPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)gLPSPI_SR_TDF_MASK (0x1U)gLPSPI_SR_TDF_SHIFT (0U)gLPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)gLPSPI_SR_RDF_MASK (0x2U)gLPSPI_SR_RDF_SHIFT (1U)gLPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)gLPSPI_SR_WCF_MASK (0x100U)gLPSPI_SR_WCF_SHIFT (8U)gLPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)gLPSPI_SR_FCF_MASK (0x200U)gLPSPI_SR_FCF_SHIFT (9U)gLPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)gLPSPI_SR_TCF_MASK (0x400U)gLPSPI_SR_TCF_SHIFT (10U)gLPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)gLPSPI_SR_TEF_MASK (0x800U)gLPSPI_SR_TEF_SHIFT (11U)gLPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)gLPSPI_SR_REF_MASK (0x1000U)gLPSPI_SR_REF_SHIFT (12U)gLPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)gLPSPI_SR_DMF_MASK (0x2000U)gLPSPI_SR_DMF_SHIFT (13U)gLPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)gLPSPI_SR_MBF_MASK (0x1000000U)gLPSPI_SR_MBF_SHIFT (24U)gLPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)gLPSPI_IER_TDIE_MASK (0x1U)gLPSPI_IER_TDIE_SHIFT (0U)gLPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)gLPSPI_IER_RDIE_MASK (0x2U)gLPSPI_IER_RDIE_SHIFT (1U)gLPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)gLPSPI_IER_WCIE_MASK (0x100U)gLPSPI_IER_WCIE_SHIFT (8U)gLPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)gLPSPI_IER_FCIE_MASK (0x200U)gLPSPI_IER_FCIE_SHIFT (9U)gLPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)gLPSPI_IER_TCIE_MASK (0x400U)gLPSPI_IER_TCIE_SHIFT (10U)gLPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)gLPSPI_IER_TEIE_MASK (0x800U)gLPSPI_IER_TEIE_SHIFT (11U)gLPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)gLPSPI_IER_REIE_MASK (0x1000U)hLPSPI_IER_REIE_SHIFT (12U)hLPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)hLPSPI_IER_DMIE_MASK (0x2000U)hLPSPI_IER_DMIE_SHIFT (13U)hLPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)hLPSPI_DER_TDDE_MASK (0x1U)hLPSPI_DER_TDDE_SHIFT (0U)hLPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)hLPSPI_DER_RDDE_MASK (0x2U)hLPSPI_DER_RDDE_SHIFT (1U)hLPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)hLPSPI_CFGR0_HREN_MASK (0x1U)hLPSPI_CFGR0_HREN_SHIFT (0U)hLPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)hLPSPI_CFGR0_HRPOL_MASK (0x2U)hLPSPI_CFGR0_HRPOL_SHIFT (1U)hLPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)hLPSPI_CFGR0_HRSEL_MASK (0x4U)hLPSPI_CFGR0_HRSEL_SHIFT (2U)hLPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)hLPSPI_CFGR0_CIRFIFO_MASK (0x100U)hLPSPI_CFGR0_CIRFIFO_SHIFT (8U)hLPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)hLPSPI_CFGR0_RDMO_MASK (0x200U)hLPSPI_CFGR0_RDMO_SHIFT (9U)hLPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)hLPSPI_CFGR1_MASTER_MASK (0x1U)hLPSPI_CFGR1_MASTER_SHIFT (0U)hLPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)hLPSPI_CFGR1_SAMPLE_MASK (0x2U)hLPSPI_CFGR1_SAMPLE_SHIFT (1U)hLPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)hLPSPI_CFGR1_AUTOPCS_MASK (0x4U)hLPSPI_CFGR1_AUTOPCS_SHIFT (2U)hLPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)hLPSPI_CFGR1_NOSTALL_MASK (0x8U)hLPSPI_CFGR1_NOSTALL_SHIFT (3U)hLPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)hLPSPI_CFGR1_PCSPOL_MASK (0xF00U)hLPSPI_CFGR1_PCSPOL_SHIFT (8U)hLPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)hLPSPI_CFGR1_MATCFG_MASK (0x70000U)hLPSPI_CFGR1_MATCFG_SHIFT (16U)hLPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)hLPSPI_CFGR1_PINCFG_MASK (0x3000000U)hLPSPI_CFGR1_PINCFG_SHIFT (24U)hLPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)hLPSPI_CFGR1_OUTCFG_MASK (0x4000000U)hLPSPI_CFGR1_OUTCFG_SHIFT (26U)hLPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)hLPSPI_CFGR1_PCSCFG_MASK (0x8000000U)hLPSPI_CFGR1_PCSCFG_SHIFT (27U)hLPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)hLPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)hLPSPI_DMR0_MATCH0_SHIFT (0U)hLPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)hLPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)hLPSPI_DMR1_MATCH1_SHIFT (0U)hLPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)hLPSPI_CCR_SCKDIV_MASK (0xFFU)hLPSPI_CCR_SCKDIV_SHIFT (0U)hLPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)hLPSPI_CCR_DBT_MASK (0xFF00U)hLPSPI_CCR_DBT_SHIFT (8U)hLPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)hLPSPI_CCR_PCSSCK_MASK (0xFF0000U)hLPSPI_CCR_PCSSCK_SHIFT (16U)hLPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)hLPSPI_CCR_SCKPCS_MASK (0xFF000000U)hLPSPI_CCR_SCKPCS_SHIFT (24U)hLPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)hLPSPI_FCR_TXWATER_MASK (0xFU)hLPSPI_FCR_TXWATER_SHIFT (0U)hLPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)hLPSPI_FCR_RXWATER_MASK (0xF0000U)hLPSPI_FCR_RXWATER_SHIFT (16U)hLPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)hLPSPI_FSR_TXCOUNT_MASK (0x1FU)hLPSPI_FSR_TXCOUNT_SHIFT (0U)hLPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)hLPSPI_FSR_RXCOUNT_MASK (0x1F0000U)hLPSPI_FSR_RXCOUNT_SHIFT (16U)hLPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)hLPSPI_TCR_FRAMESZ_MASK (0xFFFU)hLPSPI_TCR_FRAMESZ_SHIFT (0U)hLPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)hLPSPI_TCR_WIDTH_MASK (0x30000U)hLPSPI_TCR_WIDTH_SHIFT (16U)hLPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)hLPSPI_TCR_TXMSK_MASK (0x40000U)hLPSPI_TCR_TXMSK_SHIFT (18U)hLPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)iLPSPI_TCR_RXMSK_MASK (0x80000U)iLPSPI_TCR_RXMSK_SHIFT (19U)iLPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)iLPSPI_TCR_CONTC_MASK (0x100000U)iLPSPI_TCR_CONTC_SHIFT (20U)iLPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)iLPSPI_TCR_CONT_MASK (0x200000U)iLPSPI_TCR_CONT_SHIFT (21U)iLPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)iLPSPI_TCR_BYSW_MASK (0x400000U)iLPSPI_TCR_BYSW_SHIFT (22U)iLPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)iLPSPI_TCR_LSBF_MASK (0x800000U)iLPSPI_TCR_LSBF_SHIFT (23U)iLPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)iLPSPI_TCR_PCS_MASK (0x3000000U)iLPSPI_TCR_PCS_SHIFT (24U)iLPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)iLPSPI_TCR_PRESCALE_MASK (0x38000000U)iLPSPI_TCR_PRESCALE_SHIFT (27U)iLPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)iLPSPI_TCR_CPHA_MASK (0x40000000U)iLPSPI_TCR_CPHA_SHIFT (30U)iLPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)iLPSPI_TCR_CPOL_MASK (0x80000000U)iLPSPI_TCR_CPOL_SHIFT (31U)iLPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)iLPSPI_TDR_DATA_MASK (0xFFFFFFFFU)iLPSPI_TDR_DATA_SHIFT (0U)iLPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)iLPSPI_RSR_SOF_MASK (0x1U)iLPSPI_RSR_SOF_SHIFT (0U)iLPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)iLPSPI_RSR_RXEMPTY_MASK (0x2U)iLPSPI_RSR_RXEMPTY_SHIFT (1U)iLPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)iLPSPI_RDR_DATA_MASK (0xFFFFFFFFU)iLPSPI_RDR_DATA_SHIFT (0U)iLPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)iLPSPI1_BASE (0x40394000u)iLPSPI1 ((LPSPI_Type *)LPSPI1_BASE)iLPSPI2_BASE (0x40398000u)iLPSPI2 ((LPSPI_Type *)LPSPI2_BASE)iLPSPI3_BASE (0x4039C000u)iLPSPI3 ((LPSPI_Type *)LPSPI3_BASE)iLPSPI4_BASE (0x403A0000u)iLPSPI4 ((LPSPI_Type *)LPSPI4_BASE)iLPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }iLPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }iLPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }iLPUART_VERID_FEATURE_MASK (0xFFFFU)iLPUART_VERID_FEATURE_SHIFT (0U)iLPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)iLPUART_VERID_MINOR_MASK (0xFF0000U)jLPUART_VERID_MINOR_SHIFT (16U)jLPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)jLPUART_VERID_MAJOR_MASK (0xFF000000U)jLPUART_VERID_MAJOR_SHIFT (24U)jLPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)jLPUART_PARAM_TXFIFO_MASK (0xFFU)jLPUART_PARAM_TXFIFO_SHIFT (0U)jLPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)jLPUART_PARAM_RXFIFO_MASK (0xFF00U)jLPUART_PARAM_RXFIFO_SHIFT (8U)jLPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)jLPUART_GLOBAL_RST_MASK (0x2U)jLPUART_GLOBAL_RST_SHIFT (1U)jLPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)jLPUART_PINCFG_TRGSEL_MASK (0x3U)jLPUART_PINCFG_TRGSEL_SHIFT (0U)jLPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)jLPUART_BAUD_SBR_MASK (0x1FFFU)jLPUART_BAUD_SBR_SHIFT (0U)jLPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)jLPUART_BAUD_SBNS_MASK (0x2000U)jLPUART_BAUD_SBNS_SHIFT (13U)jLPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)jLPUART_BAUD_RXEDGIE_MASK (0x4000U)jLPUART_BAUD_RXEDGIE_SHIFT (14U)jLPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)jLPUART_BAUD_LBKDIE_MASK (0x8000U)jLPUART_BAUD_LBKDIE_SHIFT (15U)jLPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)jLPUART_BAUD_RESYNCDIS_MASK (0x10000U)jLPUART_BAUD_RESYNCDIS_SHIFT (16U)jLPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)jLPUART_BAUD_BOTHEDGE_MASK (0x20000U)jLPUART_BAUD_BOTHEDGE_SHIFT (17U)jLPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)jLPUART_BAUD_MATCFG_MASK (0xC0000U)jLPUART_BAUD_MATCFG_SHIFT (18U)jLPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)jLPUART_BAUD_RIDMAE_MASK (0x100000U)jLPUART_BAUD_RIDMAE_SHIFT (20U)jLPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)jLPUART_BAUD_RDMAE_MASK (0x200000U)jLPUART_BAUD_RDMAE_SHIFT (21U)jLPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)jLPUART_BAUD_TDMAE_MASK (0x800000U)jLPUART_BAUD_TDMAE_SHIFT (23U)jLPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)jLPUART_BAUD_OSR_MASK (0x1F000000U)jLPUART_BAUD_OSR_SHIFT (24U)jLPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)jLPUART_BAUD_M10_MASK (0x20000000U)jLPUART_BAUD_M10_SHIFT (29U)jLPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)jLPUART_BAUD_MAEN2_MASK (0x40000000U)jLPUART_BAUD_MAEN2_SHIFT (30U)jLPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)jLPUART_BAUD_MAEN1_MASK (0x80000000U)jLPUART_BAUD_MAEN1_SHIFT (31U)jLPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)jLPUART_STAT_MA2F_MASK (0x4000U)jLPUART_STAT_MA2F_SHIFT (14U)jLPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)jLPUART_STAT_MA1F_MASK (0x8000U)jLPUART_STAT_MA1F_SHIFT (15U)jLPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)jLPUART_STAT_PF_MASK (0x10000U)jLPUART_STAT_PF_SHIFT (16U)jLPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)jLPUART_STAT_FE_MASK (0x20000U)jLPUART_STAT_FE_SHIFT (17U)jLPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)jLPUART_STAT_NF_MASK (0x40000U)jLPUART_STAT_NF_SHIFT (18U)jLPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)jLPUART_STAT_OR_MASK (0x80000U)jLPUART_STAT_OR_SHIFT (19U)jLPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)jLPUART_STAT_IDLE_MASK (0x100000U)jLPUART_STAT_IDLE_SHIFT (20U)jLPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)jLPUART_STAT_RDRF_MASK (0x200000U)jLPUART_STAT_RDRF_SHIFT (21U)jLPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)jLPUART_STAT_TC_MASK (0x400000U)jLPUART_STAT_TC_SHIFT (22U)jLPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)jLPUART_STAT_TDRE_MASK (0x800000U)jLPUART_STAT_TDRE_SHIFT (23U)jLPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)jLPUART_STAT_RAF_MASK (0x1000000U)jLPUART_STAT_RAF_SHIFT (24U)jLPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)jLPUART_STAT_LBKDE_MASK (0x2000000U)jLPUART_STAT_LBKDE_SHIFT (25U)jLPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)jLPUART_STAT_BRK13_MASK (0x4000000U)jLPUART_STAT_BRK13_SHIFT (26U)jLPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)jLPUART_STAT_RWUID_MASK (0x8000000U)jLPUART_STAT_RWUID_SHIFT (27U)jLPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)jLPUART_STAT_RXINV_MASK (0x10000000U)jLPUART_STAT_RXINV_SHIFT (28U)jLPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)jLPUART_STAT_MSBF_MASK (0x20000000U)jLPUART_STAT_MSBF_SHIFT (29U)jLPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)jLPUART_STAT_RXEDGIF_MASK (0x40000000U)kLPUART_STAT_RXEDGIF_SHIFT (30U)kLPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)kLPUART_STAT_LBKDIF_MASK (0x80000000U)kLPUART_STAT_LBKDIF_SHIFT (31U)kLPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)kLPUART_CTRL_PT_MASK (0x1U)kLPUART_CTRL_PT_SHIFT (0U)kLPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)kLPUART_CTRL_PE_MASK (0x2U)kLPUART_CTRL_PE_SHIFT (1U)kLPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)kLPUART_CTRL_ILT_MASK (0x4U)kLPUART_CTRL_ILT_SHIFT (2U)kLPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)kLPUART_CTRL_WAKE_MASK (0x8U)kLPUART_CTRL_WAKE_SHIFT (3U)kLPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)kLPUART_CTRL_M_MASK (0x10U)kLPUART_CTRL_M_SHIFT (4U)kLPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)kLPUART_CTRL_RSRC_MASK (0x20U)kLPUART_CTRL_RSRC_SHIFT (5U)kLPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)kLPUART_CTRL_DOZEEN_MASK (0x40U)kLPUART_CTRL_DOZEEN_SHIFT (6U)kLPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)kLPUART_CTRL_LOOPS_MASK (0x80U)kLPUART_CTRL_LOOPS_SHIFT (7U)kLPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)kLPUART_CTRL_IDLECFG_MASK (0x700U)kLPUART_CTRL_IDLECFG_SHIFT (8U)kLPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)kLPUART_CTRL_M7_MASK (0x800U)kLPUART_CTRL_M7_SHIFT (11U)kLPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)kLPUART_CTRL_MA2IE_MASK (0x4000U)kLPUART_CTRL_MA2IE_SHIFT (14U)kLPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)kLPUART_CTRL_MA1IE_MASK (0x8000U)kLPUART_CTRL_MA1IE_SHIFT (15U)kLPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)kLPUART_CTRL_SBK_MASK (0x10000U)kLPUART_CTRL_SBK_SHIFT (16U)kLPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)kLPUART_CTRL_RWU_MASK (0x20000U)kLPUART_CTRL_RWU_SHIFT (17U)kLPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)kLPUART_CTRL_RE_MASK (0x40000U)kLPUART_CTRL_RE_SHIFT (18U)kLPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)kLPUART_CTRL_TE_MASK (0x80000U)kLPUART_CTRL_TE_SHIFT (19U)kLPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)kLPUART_CTRL_ILIE_MASK (0x100000U)kLPUART_CTRL_ILIE_SHIFT (20U)kLPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)kLPUART_CTRL_RIE_MASK (0x200000U)kLPUART_CTRL_RIE_SHIFT (21U)kLPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)kLPUART_CTRL_TCIE_MASK (0x400000U)kLPUART_CTRL_TCIE_SHIFT (22U)kLPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)kLPUART_CTRL_TIE_MASK (0x800000U)kLPUART_CTRL_TIE_SHIFT (23U)kLPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)kLPUART_CTRL_PEIE_MASK (0x1000000U)kLPUART_CTRL_PEIE_SHIFT (24U)kLPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)kLPUART_CTRL_FEIE_MASK (0x2000000U)kLPUART_CTRL_FEIE_SHIFT (25U)kLPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)kLPUART_CTRL_NEIE_MASK (0x4000000U)kLPUART_CTRL_NEIE_SHIFT (26U)kLPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)kLPUART_CTRL_ORIE_MASK (0x8000000U)kLPUART_CTRL_ORIE_SHIFT (27U)kLPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)kLPUART_CTRL_TXINV_MASK (0x10000000U)kLPUART_CTRL_TXINV_SHIFT (28U)kLPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)kLPUART_CTRL_TXDIR_MASK (0x20000000U)kLPUART_CTRL_TXDIR_SHIFT (29U)kLPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)kLPUART_CTRL_R9T8_MASK (0x40000000U)kLPUART_CTRL_R9T8_SHIFT (30U)kLPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)kLPUART_CTRL_R8T9_MASK (0x80000000U)kLPUART_CTRL_R8T9_SHIFT (31U)kLPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)kLPUART_DATA_R0T0_MASK (0x1U)kLPUART_DATA_R0T0_SHIFT (0U)kLPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)kLPUART_DATA_R1T1_MASK (0x2U)kLPUART_DATA_R1T1_SHIFT (1U)kLPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)kLPUART_DATA_R2T2_MASK (0x4U)kLPUART_DATA_R2T2_SHIFT (2U)kLPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)kLPUART_DATA_R3T3_MASK (0x8U)kLPUART_DATA_R3T3_SHIFT (3U)kLPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)kLPUART_DATA_R4T4_MASK (0x10U)kLPUART_DATA_R4T4_SHIFT (4U)kLPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)kLPUART_DATA_R5T5_MASK (0x20U)kLPUART_DATA_R5T5_SHIFT (5U)kLPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)kLPUART_DATA_R6T6_MASK (0x40U)kLPUART_DATA_R6T6_SHIFT (6U)kLPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)kLPUART_DATA_R7T7_MASK (0x80U)kLPUART_DATA_R7T7_SHIFT (7U)kLPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)kLPUART_DATA_R8T8_MASK (0x100U)kLPUART_DATA_R8T8_SHIFT (8U)kLPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)kLPUART_DATA_R9T9_MASK (0x200U)kLPUART_DATA_R9T9_SHIFT (9U)kLPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)kLPUART_DATA_IDLINE_MASK (0x800U)lLPUART_DATA_IDLINE_SHIFT (11U)lLPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)lLPUART_DATA_RXEMPT_MASK (0x1000U)lLPUART_DATA_RXEMPT_SHIFT (12U)lLPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)lLPUART_DATA_FRETSC_MASK (0x2000U)lLPUART_DATA_FRETSC_SHIFT (13U)lLPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)lLPUART_DATA_PARITYE_MASK (0x4000U)lLPUART_DATA_PARITYE_SHIFT (14U)lLPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)lLPUART_DATA_NOISY_MASK (0x8000U)lLPUART_DATA_NOISY_SHIFT (15U)lLPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)lLPUART_MATCH_MA1_MASK (0x3FFU)lLPUART_MATCH_MA1_SHIFT (0U)lLPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)lLPUART_MATCH_MA2_MASK (0x3FF0000U)lLPUART_MATCH_MA2_SHIFT (16U)lLPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)lLPUART_MODIR_TXCTSE_MASK (0x1U)lLPUART_MODIR_TXCTSE_SHIFT (0U)lLPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)lLPUART_MODIR_TXRTSE_MASK (0x2U)lLPUART_MODIR_TXRTSE_SHIFT (1U)lLPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)lLPUART_MODIR_TXRTSPOL_MASK (0x4U)lLPUART_MODIR_TXRTSPOL_SHIFT (2U)lLPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)lLPUART_MODIR_RXRTSE_MASK (0x8U)lLPUART_MODIR_RXRTSE_SHIFT (3U)lLPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)lLPUART_MODIR_TXCTSC_MASK (0x10U)lLPUART_MODIR_TXCTSC_SHIFT (4U)lLPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)lLPUART_MODIR_TXCTSSRC_MASK (0x20U)lLPUART_MODIR_TXCTSSRC_SHIFT (5U)lLPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)lLPUART_MODIR_RTSWATER_MASK (0x300U)lLPUART_MODIR_RTSWATER_SHIFT (8U)lLPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)lLPUART_MODIR_TNP_MASK (0x30000U)lLPUART_MODIR_TNP_SHIFT (16U)lLPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)lLPUART_MODIR_IREN_MASK (0x40000U)lLPUART_MODIR_IREN_SHIFT (18U)lLPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)lLPUART_FIFO_RXFIFOSIZE_MASK (0x7U)lLPUART_FIFO_RXFIFOSIZE_SHIFT (0U)lLPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)lLPUART_FIFO_RXFE_MASK (0x8U)lLPUART_FIFO_RXFE_SHIFT (3U)lLPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)lLPUART_FIFO_TXFIFOSIZE_MASK (0x70U)lLPUART_FIFO_TXFIFOSIZE_SHIFT (4U)lLPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)lLPUART_FIFO_TXFE_MASK (0x80U)lLPUART_FIFO_TXFE_SHIFT (7U)lLPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)lLPUART_FIFO_RXUFE_MASK (0x100U)lLPUART_FIFO_RXUFE_SHIFT (8U)lLPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)lLPUART_FIFO_TXOFE_MASK (0x200U)lLPUART_FIFO_TXOFE_SHIFT (9U)lLPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)lLPUART_FIFO_RXIDEN_MASK (0x1C00U)lLPUART_FIFO_RXIDEN_SHIFT (10U)lLPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)lLPUART_FIFO_RXFLUSH_MASK (0x4000U)lLPUART_FIFO_RXFLUSH_SHIFT (14U)lLPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)lLPUART_FIFO_TXFLUSH_MASK (0x8000U)lLPUART_FIFO_TXFLUSH_SHIFT (15U)lLPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)lLPUART_FIFO_RXUF_MASK (0x10000U)lLPUART_FIFO_RXUF_SHIFT (16U)lLPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)lLPUART_FIFO_TXOF_MASK (0x20000U)lLPUART_FIFO_TXOF_SHIFT (17U)lLPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)lLPUART_FIFO_RXEMPT_MASK (0x400000U)lLPUART_FIFO_RXEMPT_SHIFT (22U)lLPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)lLPUART_FIFO_TXEMPT_MASK (0x800000U)lLPUART_FIFO_TXEMPT_SHIFT (23U)lLPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)lLPUART_WATER_TXWATER_MASK (0x3U)lLPUART_WATER_TXWATER_SHIFT (0U)lLPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)lLPUART_WATER_TXCOUNT_MASK (0x700U)lLPUART_WATER_TXCOUNT_SHIFT (8U)lLPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)lLPUART_WATER_RXWATER_MASK (0x30000U)lLPUART_WATER_RXWATER_SHIFT (16U)lLPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)lLPUART_WATER_RXCOUNT_MASK (0x7000000U)lLPUART_WATER_RXCOUNT_SHIFT (24U)lLPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)lLPUART1_BASE (0x40184000u)lLPUART1 ((LPUART_Type *)LPUART1_BASE)mLPUART2_BASE (0x40188000u)mLPUART2 ((LPUART_Type *)LPUART2_BASE)mLPUART3_BASE (0x4018C000u)mLPUART3 ((LPUART_Type *)LPUART3_BASE)mLPUART4_BASE (0x40190000u)mLPUART4 ((LPUART_Type *)LPUART4_BASE)mLPUART5_BASE (0x40194000u)mLPUART5 ((LPUART_Type *)LPUART5_BASE)mLPUART6_BASE (0x40198000u)mLPUART6 ((LPUART_Type *)LPUART6_BASE)mLPUART7_BASE (0x4019C000u)mLPUART7 ((LPUART_Type *)LPUART7_BASE)mLPUART8_BASE (0x401A0000u)mLPUART8 ((LPUART_Type *)LPUART8_BASE)mLPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }mLPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }mLPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }nOCOTP_CTRL_ADDR_MASK (0x3FU)nOCOTP_CTRL_ADDR_SHIFT (0U)nOCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)nOCOTP_CTRL_BUSY_MASK (0x100U)nOCOTP_CTRL_BUSY_SHIFT (8U)nOCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)nOCOTP_CTRL_ERROR_MASK (0x200U)nOCOTP_CTRL_ERROR_SHIFT (9U)nOCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)nOCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)nOCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)nOCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)nOCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)nOCOTP_CTRL_WR_UNLOCK_SHIFT (16U)nOCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)nOCOTP_CTRL_SET_ADDR_MASK (0x3FU)nOCOTP_CTRL_SET_ADDR_SHIFT (0U)nOCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)nOCOTP_CTRL_SET_BUSY_MASK (0x100U)nOCOTP_CTRL_SET_BUSY_SHIFT (8U)nOCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)nOCOTP_CTRL_SET_ERROR_MASK (0x200U)nOCOTP_CTRL_SET_ERROR_SHIFT (9U)nOCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)nOCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)nOCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)nOCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)nOCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)nOCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)nOCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)nOCOTP_CTRL_CLR_ADDR_MASK (0x3FU)nOCOTP_CTRL_CLR_ADDR_SHIFT (0U)nOCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)nOCOTP_CTRL_CLR_BUSY_MASK (0x100U)nOCOTP_CTRL_CLR_BUSY_SHIFT (8U)nOCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)nOCOTP_CTRL_CLR_ERROR_MASK (0x200U)nOCOTP_CTRL_CLR_ERROR_SHIFT (9U)nOCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)nOCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)nOCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)nOCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)nOCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)nOCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)nOCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)nOCOTP_CTRL_TOG_ADDR_MASK (0x3FU)nOCOTP_CTRL_TOG_ADDR_SHIFT (0U)nOCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)nOCOTP_CTRL_TOG_BUSY_MASK (0x100U)nOCOTP_CTRL_TOG_BUSY_SHIFT (8U)nOCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)nOCOTP_CTRL_TOG_ERROR_MASK (0x200U)nOCOTP_CTRL_TOG_ERROR_SHIFT (9U)nOCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)nOCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)nOCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)nOCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)nOCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)nOCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)nOCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)nOCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)nOCOTP_TIMING_STROBE_PROG_SHIFT (0U)nOCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)nOCOTP_TIMING_RELAX_MASK (0xF000U)nOCOTP_TIMING_RELAX_SHIFT (12U)nOCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)nOCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)nOCOTP_TIMING_STROBE_READ_SHIFT (16U)nOCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)nOCOTP_TIMING_WAIT_MASK (0xFC00000U)nOCOTP_TIMING_WAIT_SHIFT (22U)nOCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)nOCOTP_DATA_DATA_MASK (0xFFFFFFFFU)oOCOTP_DATA_DATA_SHIFT (0U)oOCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)oOCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)oOCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)oOCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)oOCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)oOCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)oOCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)oOCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)oOCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)oOCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)oOCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)oOCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)oOCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)oOCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)oOCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)oOCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)oOCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)oOCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)oOCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)oOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)oOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)oOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)oOCOTP_SCS_HAB_JDE_MASK (0x1U)oOCOTP_SCS_HAB_JDE_SHIFT (0U)oOCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)oOCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)oOCOTP_SCS_SPARE_SHIFT (1U)oOCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)oOCOTP_SCS_LOCK_MASK (0x80000000U)oOCOTP_SCS_LOCK_SHIFT (31U)oOCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)oOCOTP_SCS_SET_HAB_JDE_MASK (0x1U)oOCOTP_SCS_SET_HAB_JDE_SHIFT (0U)oOCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)oOCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)oOCOTP_SCS_SET_SPARE_SHIFT (1U)oOCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)oOCOTP_SCS_SET_LOCK_MASK (0x80000000U)oOCOTP_SCS_SET_LOCK_SHIFT (31U)oOCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)oOCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)oOCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)oOCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)oOCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)oOCOTP_SCS_CLR_SPARE_SHIFT (1U)oOCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)oOCOTP_SCS_CLR_LOCK_MASK (0x80000000U)oOCOTP_SCS_CLR_LOCK_SHIFT (31U)oOCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)oOCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)oOCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)oOCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)oOCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)oOCOTP_SCS_TOG_SPARE_SHIFT (1U)oOCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)oOCOTP_SCS_TOG_LOCK_MASK (0x80000000U)oOCOTP_SCS_TOG_LOCK_SHIFT (31U)oOCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)oOCOTP_VERSION_STEP_MASK (0xFFFFU)oOCOTP_VERSION_STEP_SHIFT (0U)oOCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)oOCOTP_VERSION_MINOR_MASK (0xFF0000U)oOCOTP_VERSION_MINOR_SHIFT (16U)oOCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)oOCOTP_VERSION_MAJOR_MASK (0xFF000000U)oOCOTP_VERSION_MAJOR_SHIFT (24U)oOCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)oOCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)oOCOTP_TIMING2_RELAX_PROG_SHIFT (0U)oOCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)oOCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)oOCOTP_TIMING2_RELAX_READ_SHIFT (16U)oOCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)oOCOTP_TIMING2_RELAX1_MASK (0x1FC00000U)oOCOTP_TIMING2_RELAX1_SHIFT (22U)oOCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK)oOCOTP_LOCK_TESTER_MASK (0x3U)oOCOTP_LOCK_TESTER_SHIFT (0U)oOCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)oOCOTP_LOCK_BOOT_CFG_MASK (0xCU)oOCOTP_LOCK_BOOT_CFG_SHIFT (2U)oOCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)oOCOTP_LOCK_MEM_TRIM_MASK (0x30U)oOCOTP_LOCK_MEM_TRIM_SHIFT (4U)oOCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)oOCOTP_LOCK_SJC_RESP_MASK (0x40U)oOCOTP_LOCK_SJC_RESP_SHIFT (6U)pOCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)pOCOTP_LOCK_MAC_ADDR_MASK (0x300U)pOCOTP_LOCK_MAC_ADDR_SHIFT (8U)pOCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)pOCOTP_LOCK_GP1_MASK (0xC00U)pOCOTP_LOCK_GP1_SHIFT (10U)pOCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)pOCOTP_LOCK_GP2_MASK (0x3000U)pOCOTP_LOCK_GP2_SHIFT (12U)pOCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)pOCOTP_LOCK_SRK_MASK (0x4000U)pOCOTP_LOCK_SRK_SHIFT (14U)pOCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK)pOCOTP_LOCK_OTPMK_MSB_MASK (0x8000U)pOCOTP_LOCK_OTPMK_MSB_SHIFT (15U)pOCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK)pOCOTP_LOCK_SW_GP1_MASK (0x10000U)pOCOTP_LOCK_SW_GP1_SHIFT (16U)pOCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)pOCOTP_LOCK_OTPMK_LSB_MASK (0x20000U)pOCOTP_LOCK_OTPMK_LSB_SHIFT (17U)pOCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK)pOCOTP_LOCK_ANALOG_MASK (0xC0000U)pOCOTP_LOCK_ANALOG_SHIFT (18U)pOCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)pOCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)pOCOTP_LOCK_OTPMK_CRC_SHIFT (20U)pOCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)pOCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)pOCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)pOCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)pOCOTP_LOCK_MISC_CONF_MASK (0x400000U)pOCOTP_LOCK_MISC_CONF_SHIFT (22U)pOCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)pOCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)pOCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)pOCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)pOCOTP_LOCK_GP3_MASK (0xC000000U)pOCOTP_LOCK_GP3_SHIFT (26U)pOCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)pOCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)pOCOTP_LOCK_FIELD_RETURN_SHIFT (28U)pOCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)pOCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG0_BITS_SHIFT (0U)pOCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)pOCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG1_BITS_SHIFT (0U)pOCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)pOCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG2_BITS_SHIFT (0U)pOCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)pOCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG3_BITS_SHIFT (0U)pOCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)pOCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG4_BITS_SHIFT (0U)pOCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)pOCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG5_BITS_SHIFT (0U)pOCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)pOCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG6_BITS_SHIFT (0U)pOCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)pOCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM0_BITS_SHIFT (0U)pOCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)pOCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM1_BITS_SHIFT (0U)pOCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)pOCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM2_BITS_SHIFT (0U)pOCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)pOCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM3_BITS_SHIFT (0U)pOCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)pOCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM4_BITS_SHIFT (0U)pOCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)qOCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)qOCOTP_ANA0_BITS_SHIFT (0U)qOCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)qOCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)qOCOTP_ANA1_BITS_SHIFT (0U)qOCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)qOCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)qOCOTP_ANA2_BITS_SHIFT (0U)qOCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)qOCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK0_BITS_SHIFT (0U)qOCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)qOCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK1_BITS_SHIFT (0U)qOCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)qOCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK2_BITS_SHIFT (0U)qOCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)qOCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK3_BITS_SHIFT (0U)qOCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)qOCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK4_BITS_SHIFT (0U)qOCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)qOCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK5_BITS_SHIFT (0U)qOCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)qOCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK6_BITS_SHIFT (0U)qOCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)qOCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK7_BITS_SHIFT (0U)qOCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)qOCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)qOCOTP_SJC_RESP0_BITS_SHIFT (0U)qOCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)qOCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)qOCOTP_SJC_RESP1_BITS_SHIFT (0U)qOCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)qOCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)qOCOTP_MAC0_BITS_SHIFT (0U)qOCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)qOCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)qOCOTP_MAC1_BITS_SHIFT (0U)qOCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)qOCOTP_GP3_BITS_MASK (0xFFFFFFFFU)qOCOTP_GP3_BITS_SHIFT (0U)qOCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)qOCOTP_GP1_BITS_MASK (0xFFFFFFFFU)qOCOTP_GP1_BITS_SHIFT (0U)qOCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)qOCOTP_GP2_BITS_MASK (0xFFFFFFFFU)qOCOTP_GP2_BITS_SHIFT (0U)qOCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)rOCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP1_BITS_SHIFT (0U)rOCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)rOCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP20_BITS_SHIFT (0U)rOCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)rOCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP21_BITS_SHIFT (0U)rOCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)rOCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP22_BITS_SHIFT (0U)rOCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)rOCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP23_BITS_SHIFT (0U)rOCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)rOCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)rOCOTP_MISC_CONF0_BITS_SHIFT (0U)rOCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)rOCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)rOCOTP_MISC_CONF1_BITS_SHIFT (0U)rOCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)rOCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)rOCOTP_SRK_REVOKE_BITS_SHIFT (0U)rOCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)rOCOTP_BASE (0x401F4000u)rOCOTP ((OCOTP_Type *)OCOTP_BASE)rOCOTP_BASE_ADDRS { OCOTP_BASE }rOCOTP_BASE_PTRS { OCOTP }rPGC_MEGA_CTRL_PCR_MASK (0x1U)rPGC_MEGA_CTRL_PCR_SHIFT (0U)rPGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)rPGC_MEGA_PUPSCR_SW_MASK (0x3FU)rPGC_MEGA_PUPSCR_SW_SHIFT (0U)rPGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)rPGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)rPGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)rPGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)rPGC_MEGA_PDNSCR_ISO_MASK (0x3FU)sPGC_MEGA_PDNSCR_ISO_SHIFT (0U)sPGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)sPGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)sPGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)sPGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)sPGC_MEGA_SR_PSR_MASK (0x1U)sPGC_MEGA_SR_PSR_SHIFT (0U)sPGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)sPGC_CPU_CTRL_PCR_MASK (0x1U)sPGC_CPU_CTRL_PCR_SHIFT (0U)sPGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)sPGC_CPU_PUPSCR_SW_MASK (0x3FU)sPGC_CPU_PUPSCR_SW_SHIFT (0U)sPGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)sPGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)sPGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)sPGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)sPGC_CPU_PDNSCR_ISO_MASK (0x3FU)sPGC_CPU_PDNSCR_ISO_SHIFT (0U)sPGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)sPGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)sPGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)sPGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)sPGC_CPU_SR_PSR_MASK (0x1U)sPGC_CPU_SR_PSR_SHIFT (0U)sPGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)sPGC_BASE (0x400F4000u)sPGC ((PGC_Type *)PGC_BASE)sPGC_BASE_ADDRS { PGC_BASE }sPGC_BASE_PTRS { PGC }sPIT_MCR_FRZ_MASK (0x1U)sPIT_MCR_FRZ_SHIFT (0U)sPIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)sPIT_MCR_MDIS_MASK (0x2U)sPIT_MCR_MDIS_SHIFT (1U)sPIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)sPIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)sPIT_LTMR64H_LTH_SHIFT (0U)sPIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)sPIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)sPIT_LTMR64L_LTL_SHIFT (0U)sPIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)tPIT_LDVAL_TSV_MASK (0xFFFFFFU)tPIT_LDVAL_TSV_SHIFT (0U)tPIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)tPIT_LDVAL_COUNT (4U)tPIT_CVAL_TVL_MASK (0xFFFFFFFFU)tPIT_CVAL_TVL_SHIFT (0U)tPIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)tPIT_CVAL_COUNT (4U)tPIT_TCTRL_TEN_MASK (0x1U)tPIT_TCTRL_TEN_SHIFT (0U)tPIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)tPIT_TCTRL_TIE_MASK (0x2U)tPIT_TCTRL_TIE_SHIFT (1U)tPIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)tPIT_TCTRL_CHN_MASK (0x4U)tPIT_TCTRL_CHN_SHIFT (2U)tPIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)tPIT_TCTRL_COUNT (4U)tPIT_TFLG_TIF_MASK (0x1U)tPIT_TFLG_TIF_SHIFT (0U)tPIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)tPIT_TFLG_COUNT (4U)tPIT_BASE (0x40084000u)tPIT ((PIT_Type *)PIT_BASE)tPIT_BASE_ADDRS { PIT_BASE }tPIT_BASE_PTRS { PIT }tPIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }tPMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)tPMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)tPMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)tPMU_REG_1P1_ENABLE_BO_MASK (0x2U)tPMU_REG_1P1_ENABLE_BO_SHIFT (1U)tPMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)tPMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)tPMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)uPMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)uPMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)uPMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)uPMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)uPMU_REG_1P1_BO_OFFSET_MASK (0x70U)uPMU_REG_1P1_BO_OFFSET_SHIFT (4U)uPMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)uPMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)uPMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)uPMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)uPMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)uPMU_REG_1P1_BO_VDD1P1_SHIFT (16U)uPMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)uPMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)uPMU_REG_1P1_OK_VDD1P1_SHIFT (17U)uPMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)uPMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)uPMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)uPMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)uPMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)uPMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)uPMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)uPMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)uPMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)uPMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)uPMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)uPMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)uPMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)uPMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)uPMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)uPMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)uPMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)uPMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)uPMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)uPMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)uPMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)uPMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)uPMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)uPMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)uPMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)uPMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)uPMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)uPMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)uPMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)uPMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)uPMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)uPMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)uPMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)uPMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)uPMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)uPMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)uPMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)uPMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)uPMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)uPMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)uPMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)uPMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)uPMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)uPMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)uPMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)uPMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)uPMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)uPMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)uPMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)uPMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)uPMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)uPMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)uPMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)uPMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)uPMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)uPMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)uPMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)uPMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)uPMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)uPMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)uPMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)uPMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)uPMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)uPMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)uPMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)uPMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)uPMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)uPMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)uPMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)uPMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)uPMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)uPMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)uPMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)uPMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)uPMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)uPMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)uPMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)uPMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)uPMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)uPMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)uPMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)uPMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)uPMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)uPMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)uPMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)uPMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)uPMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)uPMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)uPMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)uPMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)uPMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)uPMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)uPMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)uPMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)uPMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)uPMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)uPMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)vPMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)vPMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)vPMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)vPMU_REG_3P0_ENABLE_BO_MASK (0x2U)vPMU_REG_3P0_ENABLE_BO_SHIFT (1U)vPMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)vPMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)vPMU_REG_3P0_BO_OFFSET_MASK (0x70U)vPMU_REG_3P0_BO_OFFSET_SHIFT (4U)vPMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)vPMU_REG_3P0_VBUS_SEL_MASK (0x80U)vPMU_REG_3P0_VBUS_SEL_SHIFT (7U)vPMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)vPMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)vPMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)vPMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)vPMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)vPMU_REG_3P0_BO_VDD3P0_SHIFT (16U)vPMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)vPMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)vPMU_REG_3P0_OK_VDD3P0_SHIFT (17U)vPMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)vPMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)vPMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)vPMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)vPMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)vPMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)vPMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)vPMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)vPMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)vPMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)vPMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)vPMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)vPMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)vPMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)vPMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)vPMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)vPMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)vPMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)vPMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)vPMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)vPMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)vPMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)vPMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)vPMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)vPMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)vPMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)vPMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)vPMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)vPMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)vPMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)vPMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)vPMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)vPMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)vPMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)vPMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)vPMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)vPMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)vPMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)vPMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)vPMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)vPMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)vPMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)vPMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)vPMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)vPMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)vPMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)vPMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)vPMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)vPMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)vPMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)vPMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)vPMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)vPMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)vPMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)vPMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)vPMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)vPMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)vPMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)vPMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)vPMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)vPMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)vPMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)vPMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)vPMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)vPMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)vPMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)vPMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)vPMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)vPMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)vPMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)vPMU_REG_2P5_ENABLE_BO_MASK (0x2U)vPMU_REG_2P5_ENABLE_BO_SHIFT (1U)vPMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)vPMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)vPMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)vPMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)vPMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)vPMU_REG_2P5_BO_OFFSET_MASK (0x70U)vPMU_REG_2P5_BO_OFFSET_SHIFT (4U)vPMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)vPMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)wPMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)wPMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)wPMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)wPMU_REG_2P5_BO_VDD2P5_SHIFT (16U)wPMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)wPMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)wPMU_REG_2P5_OK_VDD2P5_SHIFT (17U)wPMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)wPMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)wPMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)wPMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)wPMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)wPMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)wPMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)wPMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)wPMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)wPMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)wPMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)wPMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)wPMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)wPMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)wPMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)wPMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)wPMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)wPMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)wPMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)wPMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)wPMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)wPMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)wPMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)wPMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)wPMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)wPMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)wPMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)wPMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)wPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)wPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)wPMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)wPMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)wPMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)wPMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)wPMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)wPMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)wPMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)wPMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)wPMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)wPMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)wPMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)wPMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)wPMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)wPMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)wPMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)wPMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)wPMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)wPMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)wPMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)wPMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)wPMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)wPMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)wPMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)wPMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)wPMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)wPMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)wPMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)wPMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)wPMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)wPMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)wPMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)wPMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)wPMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)wPMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)wPMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)wPMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)wPMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)wPMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)wPMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)wPMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)wPMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)wPMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)wPMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)wPMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)wPMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)wPMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)wPMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)wPMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)wPMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)wPMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)wPMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)wPMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)wPMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)wPMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)wPMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)wPMU_REG_CORE_REG0_TARG_MASK (0x1FU)wPMU_REG_CORE_REG0_TARG_SHIFT (0U)wPMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)wPMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)wPMU_REG_CORE_REG0_ADJ_SHIFT (5U)wPMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)wPMU_REG_CORE_REG1_TARG_MASK (0x3E00U)wPMU_REG_CORE_REG1_TARG_SHIFT (9U)wPMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)wPMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)wPMU_REG_CORE_REG1_ADJ_SHIFT (14U)wPMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)wPMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)wPMU_REG_CORE_REG2_TARG_SHIFT (18U)wPMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)wPMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)wPMU_REG_CORE_REG2_ADJ_SHIFT (23U)wPMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)wPMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)wPMU_REG_CORE_RAMP_RATE_SHIFT (27U)xPMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)xPMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)xPMU_REG_CORE_FET_ODRIVE_SHIFT (29U)xPMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)xPMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)xPMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)xPMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)xPMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)xPMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)xPMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)xPMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)xPMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)xPMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)xPMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)xPMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)xPMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)xPMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)xPMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)xPMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)xPMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)xPMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)xPMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)xPMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)xPMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)xPMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)xPMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)xPMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)xPMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)xPMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)xPMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)xPMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)xPMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)xPMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)xPMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)xPMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)xPMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)xPMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)xPMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)xPMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)xPMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)xPMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)xPMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)xPMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)xPMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)xPMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)xPMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)xPMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)xPMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)xPMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)xPMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)xPMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)xPMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)xPMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)xPMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)xPMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)xPMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)xPMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)xPMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)xPMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)xPMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)xPMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)xPMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)xPMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)xPMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)xPMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)xPMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)xPMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)xPMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)xPMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)xPMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)xPMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)xPMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)xPMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)xPMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)xPMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)xPMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)xPMU_MISC0_REFTOP_PWD_MASK (0x1U)xPMU_MISC0_REFTOP_PWD_SHIFT (0U)xPMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)xPMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)xPMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)xPMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)xPMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)xPMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)xPMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)xPMU_MISC0_REFTOP_VBGUP_MASK (0x80U)xPMU_MISC0_REFTOP_VBGUP_SHIFT (7U)xPMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)xPMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)xPMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)xPMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)xPMU_MISC0_RTC_RINGOSC_EN_MASK (0x1000U)xPMU_MISC0_RTC_RINGOSC_EN_SHIFT (12U)xPMU_MISC0_RTC_RINGOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_RINGOSC_EN_SHIFT)) & PMU_MISC0_RTC_RINGOSC_EN_MASK)xPMU_MISC0_OSC_I_MASK (0x6000U)xPMU_MISC0_OSC_I_SHIFT (13U)xPMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)xPMU_MISC0_OSC_XTALOK_MASK (0x8000U)xPMU_MISC0_OSC_XTALOK_SHIFT (15U)xPMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)xPMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)xPMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)xPMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)xPMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)xPMU_MISC0_CLKGATE_CTRL_SHIFT (25U)xPMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)xPMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)xPMU_MISC0_CLKGATE_DELAY_SHIFT (26U)xPMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)xPMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)xPMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)xPMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)yPMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)yPMU_MISC0_XTAL_24M_PWD_SHIFT (30U)yPMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)yPMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)yPMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)yPMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)yPMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)yPMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)yPMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)yPMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)yPMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)yPMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)yPMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)yPMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)yPMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)yPMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)yPMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)yPMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)yPMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)yPMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)yPMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)yPMU_MISC0_SET_RTC_RINGOSC_EN_MASK (0x1000U)yPMU_MISC0_SET_RTC_RINGOSC_EN_SHIFT (12U)yPMU_MISC0_SET_RTC_RINGOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_RINGOSC_EN_SHIFT)) & PMU_MISC0_SET_RTC_RINGOSC_EN_MASK)yPMU_MISC0_SET_OSC_I_MASK (0x6000U)yPMU_MISC0_SET_OSC_I_SHIFT (13U)yPMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)yPMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)yPMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)yPMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)yPMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)yPMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)yPMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)yPMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)yPMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)yPMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)yPMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)yPMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)yPMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)yPMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)yPMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)yPMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)yPMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)yPMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)yPMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)yPMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)yPMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)yPMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)yPMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)yPMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)yPMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)yPMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)yPMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)yPMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)yPMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)yPMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)yPMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)yPMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)yPMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)yPMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)yPMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)yPMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)yPMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)yPMU_MISC0_CLR_RTC_RINGOSC_EN_MASK (0x1000U)yPMU_MISC0_CLR_RTC_RINGOSC_EN_SHIFT (12U)yPMU_MISC0_CLR_RTC_RINGOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_RINGOSC_EN_SHIFT)) & PMU_MISC0_CLR_RTC_RINGOSC_EN_MASK)yPMU_MISC0_CLR_OSC_I_MASK (0x6000U)yPMU_MISC0_CLR_OSC_I_SHIFT (13U)yPMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)yPMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)yPMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)yPMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)yPMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)yPMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)yPMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)yPMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)yPMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)yPMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)yPMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)yPMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)yPMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)yPMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)yPMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)yPMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)yPMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)yPMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)yPMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)yPMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)yPMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)yPMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)yPMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)yPMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)yPMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)yPMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)yPMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)yPMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)yPMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)yPMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)yPMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)yPMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)yPMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)yPMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)yPMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)yPMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)yPMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)yPMU_MISC0_TOG_RTC_RINGOSC_EN_MASK (0x1000U)yPMU_MISC0_TOG_RTC_RINGOSC_EN_SHIFT (12U)yPMU_MISC0_TOG_RTC_RINGOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_RINGOSC_EN_SHIFT)) & PMU_MISC0_TOG_RTC_RINGOSC_EN_MASK)yPMU_MISC0_TOG_OSC_I_MASK (0x6000U)yPMU_MISC0_TOG_OSC_I_SHIFT (13U)yPMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)yPMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)yPMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)yPMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)yPMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)yPMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)zPMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)zPMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)zPMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)zPMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)zPMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)zPMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)zPMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)zPMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)zPMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)zPMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)zPMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)zPMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)zPMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)zPMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)zPMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)zPMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)zPMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)zPMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)zPMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)zPMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)zPMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)zPMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)zPMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)zPMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)zPMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)zPMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)zPMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)zPMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)zPMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)zPMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)zPMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)zPMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)zPMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)zPMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)zPMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)zPMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)zPMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)zPMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)zPMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)zPMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)zPMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)zPMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)zPMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)zPMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)zPMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)zPMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)zPMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)zPMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)zPMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)zPMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)zPMU_MISC1_IRQ_ANA_BO_SHIFT (30U)zPMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)zPMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)zPMU_MISC1_IRQ_DIG_BO_SHIFT (31U)zPMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)zPMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)zPMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)zPMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)zPMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)zPMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)zPMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)zPMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)zPMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)zPMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)zPMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)zPMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)zPMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)zPMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)zPMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)zPMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)zPMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)zPMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)zPMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)zPMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)zPMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)zPMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)zPMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)zPMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)zPMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)zPMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)zPMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)zPMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)zPMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)zPMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)zPMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)zPMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)zPMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)zPMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)zPMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)zPMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)zPMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)zPMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)zPMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)zPMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)zPMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)zPMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)zPMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)zPMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)zPMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)zPMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)zPMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)zPMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)zPMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)zPMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)zPMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)zPMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)zPMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)zPMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)zPMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)zPMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)zPMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)zPMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)zPMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)zPMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)zPMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)zPMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U){PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U){PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK){PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U){PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U){PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK){PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U){PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U){PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK){PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U){PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U){PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK){PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U){PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U){PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK){PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U){PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U){PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK){PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU){PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U){PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK){PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U){PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U){PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK){PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U){PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U){PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK){PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U){PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U){PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK){PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U){PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U){PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK){PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U){PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U){PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK){PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U){PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U){PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK){PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U){PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U){PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK){PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U){PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U){PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK){PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U){PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U){PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK){PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U){PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U){PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK){PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U){PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U){PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK){PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U){PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U){PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK){PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U){PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U){PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK){PMU_MISC2_REG0_BO_STATUS_MASK (0x8U){PMU_MISC2_REG0_BO_STATUS_SHIFT (3U){PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK){PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U){PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U){PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK){PMU_MISC2_PLL3_disable_MASK (0x80U){PMU_MISC2_PLL3_disable_SHIFT (7U){PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK){PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U){PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U){PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK){PMU_MISC2_REG1_BO_STATUS_MASK (0x800U){PMU_MISC2_REG1_BO_STATUS_SHIFT (11U){PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK){PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U){PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U){PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK){PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U){PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U){PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK){PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U){PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U){PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK){PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U){PMU_MISC2_REG2_BO_STATUS_SHIFT (19U){PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK){PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U){PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U){PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK){PMU_MISC2_REG2_OK_MASK (0x400000U){PMU_MISC2_REG2_OK_SHIFT (22U){PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK){PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U){PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U){PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK){PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U){PMU_MISC2_REG0_STEP_TIME_SHIFT (24U){PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK){PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U){PMU_MISC2_REG1_STEP_TIME_SHIFT (26U){PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK){PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U){PMU_MISC2_REG2_STEP_TIME_SHIFT (28U){PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK){PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U){PMU_MISC2_VIDEO_DIV_SHIFT (30U){PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK){PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U){PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U){PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK){PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U){PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U){PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK){PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U){PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U){PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)|PMU_MISC2_SET_PLL3_disable_MASK (0x80U)|PMU_MISC2_SET_PLL3_disable_SHIFT (7U)|PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)|PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)|PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)|PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)|PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)|PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)|PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)|PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)|PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)|PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)|PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)|PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)|PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)|PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)|PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)|PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)|PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)|PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)|PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)|PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)|PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)|PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)|PMU_MISC2_SET_REG2_OK_MASK (0x400000U)|PMU_MISC2_SET_REG2_OK_SHIFT (22U)|PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)|PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)|PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)|PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)|PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)|PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)|PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)|PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)|PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)|PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)|PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)|PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)|PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)|PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)|PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)|PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)|PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)|PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)|PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)|PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)|PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)|PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)|PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)|PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)|PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)|PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)|PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)|PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)|PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)|PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)|PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)|PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)|PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)|PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)|PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)|PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)|PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)|PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)|PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)|PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)|PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)|PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)|PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)|PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)|PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)|PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)|PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)|PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)|PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)|PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)|PMU_MISC2_CLR_REG2_OK_SHIFT (22U)|PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)|PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)|PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)|PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)|PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)|PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)|PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)|PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)|PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)|PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)|PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)|PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)|PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)|PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)|PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)|PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)|PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)|PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)|PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)|PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)|PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)|PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)|PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)|PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)|PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)|PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)|PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)|PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)|PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)|PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)|PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)|PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)|PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)|PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)|PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)|PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)|PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)|PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)|PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)|PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)|PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)|PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)|PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)}PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)}PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)}PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)}PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)}PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)}PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)}PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)}PMU_MISC2_TOG_REG2_OK_SHIFT (22U)}PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)}PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)}PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)}PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)}PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)}PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)}PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)}PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)}PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)}PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)}PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)}PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)}PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)}PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)}PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)}PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)}PMU_BASE (0x400D8000u)}PMU ((PMU_Type *)PMU_BASE)}PMU_BASE_ADDRS { PMU_BASE }}PMU_BASE_PTRS { PMU }~PWM_CNT_CNT_MASK (0xFFFFU)~PWM_CNT_CNT_SHIFT (0U)~PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)~PWM_CNT_COUNT (4U)~PWM_INIT_INIT_MASK (0xFFFFU)~PWM_INIT_INIT_SHIFT (0U)~PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)~PWM_INIT_COUNT (4U)~PWM_CTRL2_CLK_SEL_MASK (0x3U)~PWM_CTRL2_CLK_SEL_SHIFT (0U)~PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)~PWM_CTRL2_RELOAD_SEL_MASK (0x4U)~PWM_CTRL2_RELOAD_SEL_SHIFT (2U)~PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)~PWM_CTRL2_FORCE_SEL_MASK (0x38U)~PWM_CTRL2_FORCE_SEL_SHIFT (3U)~PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)~PWM_CTRL2_FORCE_MASK (0x40U)~PWM_CTRL2_FORCE_SHIFT (6U)~PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)~PWM_CTRL2_FRCEN_MASK (0x80U)~PWM_CTRL2_FRCEN_SHIFT (7U)~PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)~PWM_CTRL2_INIT_SEL_MASK (0x300U)~PWM_CTRL2_INIT_SEL_SHIFT (8U)~PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)~PWM_CTRL2_PWMX_INIT_MASK (0x400U)~PWM_CTRL2_PWMX_INIT_SHIFT (10U)~PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)~PWM_CTRL2_PWM45_INIT_MASK (0x800U)~PWM_CTRL2_PWM45_INIT_SHIFT (11U)~PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)~PWM_CTRL2_PWM23_INIT_MASK (0x1000U)~PWM_CTRL2_PWM23_INIT_SHIFT (12U)~PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)~PWM_CTRL2_INDEP_MASK (0x2000U)~PWM_CTRL2_INDEP_SHIFT (13U)~PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)~PWM_CTRL2_WAITEN_MASK (0x4000U)~PWM_CTRL2_WAITEN_SHIFT (14U)~PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)~PWM_CTRL2_DBGEN_MASK (0x8000U)~PWM_CTRL2_DBGEN_SHIFT (15U)~PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)~PWM_CTRL2_COUNT (4U)~PWM_CTRL_DBLEN_MASK (0x1U)~PWM_CTRL_DBLEN_SHIFT (0U)~PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)~PWM_CTRL_DBLX_MASK (0x2U)~PWM_CTRL_DBLX_SHIFT (1U)~PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)~PWM_CTRL_LDMOD_MASK (0x4U)~PWM_CTRL_LDMOD_SHIFT (2U)~PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)~PWM_CTRL_SPLIT_MASK (0x8U)~PWM_CTRL_SPLIT_SHIFT (3U)~PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)~PWM_CTRL_PRSC_MASK (0x70U)~PWM_CTRL_PRSC_SHIFT (4U)~PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)~PWM_CTRL_COMPMODE_MASK (0x80U)~PWM_CTRL_COMPMODE_SHIFT (7U)~PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)~PWM_CTRL_DT_MASK (0x300U)~PWM_CTRL_DT_SHIFT (8U)~PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)~PWM_CTRL_FULL_MASK (0x400U)~PWM_CTRL_FULL_SHIFT (10U)~PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)~PWM_CTRL_HALF_MASK (0x800U)~PWM_CTRL_HALF_SHIFT (11U)~PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)~PWM_CTRL_LDFQ_MASK (0xF000U)~PWM_CTRL_LDFQ_SHIFT (12U)~PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)~PWM_CTRL_COUNT (4U)~PWM_VAL0_VAL0_MASK (0xFFFFU)~PWM_VAL0_VAL0_SHIFT (0U)~PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)~PWM_VAL0_COUNT (4U)~PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)~PWM_FRACVAL1_FRACVAL1_SHIFT (11U)~PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)~PWM_FRACVAL1_COUNT (4U)~PWM_VAL1_VAL1_MASK (0xFFFFU)~PWM_VAL1_VAL1_SHIFT (0U)~PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)~PWM_VAL1_COUNT (4U)PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)PWM_FRACVAL2_FRACVAL2_SHIFT (11U)PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)PWM_FRACVAL2_COUNT (4U)PWM_VAL2_VAL2_MASK (0xFFFFU)PWM_VAL2_VAL2_SHIFT (0U)PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)PWM_VAL2_COUNT (4U)PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)PWM_FRACVAL3_FRACVAL3_SHIFT (11U)PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)PWM_FRACVAL3_COUNT (4U)PWM_VAL3_VAL3_MASK (0xFFFFU)PWM_VAL3_VAL3_SHIFT (0U)PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)PWM_VAL3_COUNT (4U)PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)PWM_FRACVAL4_FRACVAL4_SHIFT (11U)PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)PWM_FRACVAL4_COUNT (4U)PWM_VAL4_VAL4_MASK (0xFFFFU)PWM_VAL4_VAL4_SHIFT (0U)PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)PWM_VAL4_COUNT (4U)PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)PWM_FRACVAL5_FRACVAL5_SHIFT (11U)PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)PWM_FRACVAL5_COUNT (4U)PWM_VAL5_VAL5_MASK (0xFFFFU)PWM_VAL5_VAL5_SHIFT (0U)PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)PWM_VAL5_COUNT (4U)PWM_FRCTRL_FRAC1_EN_MASK (0x2U)PWM_FRCTRL_FRAC1_EN_SHIFT (1U)PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)PWM_FRCTRL_FRAC23_EN_MASK (0x4U)PWM_FRCTRL_FRAC23_EN_SHIFT (2U)PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)PWM_FRCTRL_FRAC45_EN_MASK (0x10U)PWM_FRCTRL_FRAC45_EN_SHIFT (4U)PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)PWM_FRCTRL_FRAC_PU_MASK (0x100U)PWM_FRCTRL_FRAC_PU_SHIFT (8U)PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)PWM_FRCTRL_TEST_MASK (0x8000U)PWM_FRCTRL_TEST_SHIFT (15U)PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)PWM_FRCTRL_COUNT (4U)PWM_OCTRL_PWMXFS_MASK (0x3U)PWM_OCTRL_PWMXFS_SHIFT (0U)PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)PWM_OCTRL_PWMBFS_MASK (0xCU)PWM_OCTRL_PWMBFS_SHIFT (2U)PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)PWM_OCTRL_PWMAFS_MASK (0x30U)PWM_OCTRL_PWMAFS_SHIFT (4U)PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)PWM_OCTRL_POLX_MASK (0x100U)PWM_OCTRL_POLX_SHIFT (8U)PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)PWM_OCTRL_POLB_MASK (0x200U)PWM_OCTRL_POLB_SHIFT (9U)PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)PWM_OCTRL_POLA_MASK (0x400U)PWM_OCTRL_POLA_SHIFT (10U)PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)PWM_OCTRL_PWMX_IN_MASK (0x2000U)PWM_OCTRL_PWMX_IN_SHIFT (13U)PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)PWM_OCTRL_PWMB_IN_MASK (0x4000U)PWM_OCTRL_PWMB_IN_SHIFT (14U)PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)PWM_OCTRL_PWMA_IN_MASK (0x8000U)PWM_OCTRL_PWMA_IN_SHIFT (15U)PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)PWM_OCTRL_COUNT (4U)PWM_STS_CMPF_MASK (0x3FU)PWM_STS_CMPF_SHIFT (0U)PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)PWM_STS_CFX0_MASK (0x40U)PWM_STS_CFX0_SHIFT (6U)PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)PWM_STS_CFX1_MASK (0x80U)PWM_STS_CFX1_SHIFT (7U)PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)PWM_STS_CFB0_MASK (0x100U)PWM_STS_CFB0_SHIFT (8U)PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)PWM_STS_CFB1_MASK (0x200U)PWM_STS_CFB1_SHIFT (9U)PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)PWM_STS_CFA0_MASK (0x400U)PWM_STS_CFA0_SHIFT (10U)PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)PWM_STS_CFA1_MASK (0x800U)PWM_STS_CFA1_SHIFT (11U)PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)PWM_STS_RF_MASK (0x1000U)PWM_STS_RF_SHIFT (12U)PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)PWM_STS_REF_MASK (0x2000U)PWM_STS_REF_SHIFT (13U)PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)PWM_STS_RUF_MASK (0x4000U)PWM_STS_RUF_SHIFT (14U)PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)PWM_STS_COUNT (4U)PWM_INTEN_CMPIE_MASK (0x3FU)PWM_INTEN_CMPIE_SHIFT (0U)PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)PWM_INTEN_CX0IE_MASK (0x40U)PWM_INTEN_CX0IE_SHIFT (6U)PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)PWM_INTEN_CX1IE_MASK (0x80U)PWM_INTEN_CX1IE_SHIFT (7U)PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)PWM_INTEN_CB0IE_MASK (0x100U)PWM_INTEN_CB0IE_SHIFT (8U)PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)PWM_INTEN_CB1IE_MASK (0x200U)PWM_INTEN_CB1IE_SHIFT (9U)PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)PWM_INTEN_CA0IE_MASK (0x400U)PWM_INTEN_CA0IE_SHIFT (10U)PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)PWM_INTEN_CA1IE_MASK (0x800U)€PWM_INTEN_CA1IE_SHIFT (11U)ÀPWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)ĀPWM_INTEN_RIE_MASK (0x1000U)ŀPWM_INTEN_RIE_SHIFT (12U)ƀPWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)ǀPWM_INTEN_REIE_MASK (0x2000U)ȀPWM_INTEN_REIE_SHIFT (13U)ɀPWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)̀PWM_INTEN_COUNT (4U)рPWM_DMAEN_CX0DE_MASK (0x1U)ҀPWM_DMAEN_CX0DE_SHIFT (0U)ӀPWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)ԀPWM_DMAEN_CX1DE_MASK (0x2U)ՀPWM_DMAEN_CX1DE_SHIFT (1U)րPWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)׀PWM_DMAEN_CB0DE_MASK (0x4U)؀PWM_DMAEN_CB0DE_SHIFT (2U)ـPWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)ڀPWM_DMAEN_CB1DE_MASK (0x8U)ۀPWM_DMAEN_CB1DE_SHIFT (3U)܀PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)݀PWM_DMAEN_CA0DE_MASK (0x10U)ހPWM_DMAEN_CA0DE_SHIFT (4U)߀PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)PWM_DMAEN_CA1DE_MASK (0x20U)PWM_DMAEN_CA1DE_SHIFT (5U)PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)PWM_DMAEN_CAPTDE_MASK (0xC0U)PWM_DMAEN_CAPTDE_SHIFT (6U)PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)PWM_DMAEN_FAND_MASK (0x100U)PWM_DMAEN_FAND_SHIFT (8U)PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)PWM_DMAEN_VALDE_MASK (0x200U)PWM_DMAEN_VALDE_SHIFT (9U)PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)PWM_DMAEN_COUNT (4U)PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)PWM_TCTRL_TRGFRQ_MASK (0x1000U)PWM_TCTRL_TRGFRQ_SHIFT (12U)PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)PWM_TCTRL_PWBOT1_MASK (0x4000U)PWM_TCTRL_PWBOT1_SHIFT (14U)PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)PWM_TCTRL_PWAOT0_MASK (0x8000U)PWM_TCTRL_PWAOT0_SHIFT (15U)PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)PWM_TCTRL_COUNT (4U)PWM_DISMAP_DIS0A_MASK (0xFU)PWM_DISMAP_DIS0A_SHIFT (0U)PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)PWM_DISMAP_DIS1A_MASK (0xFU)PWM_DISMAP_DIS1A_SHIFT (0U)PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)PWM_DISMAP_DIS0B_MASK (0xF0U)PWM_DISMAP_DIS0B_SHIFT (4U)PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)PWM_DISMAP_DIS1B_MASK (0xF0U)PWM_DISMAP_DIS1B_SHIFT (4U)PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)PWM_DISMAP_DIS1X_MASK (0xF00U)PWM_DISMAP_DIS1X_SHIFT (8U)PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)PWM_DISMAP_DIS0X_MASK (0xF00U)PWM_DISMAP_DIS0X_SHIFT (8U)PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)PWM_DISMAP_COUNT (4U)PWM_DISMAP_COUNT2 (2U)PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)PWM_DTCNT0_DTCNT0_SHIFT (0U)PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)PWM_DTCNT0_COUNT (4U)PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)PWM_DTCNT1_DTCNT1_SHIFT (0U)PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)PWM_DTCNT1_COUNT (4U)PWM_CAPTCTRLA_ARMA_MASK (0x1U)PWM_CAPTCTRLA_ARMA_SHIFT (0U)PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)PWM_CAPTCTRLA_EDGA0_MASK (0xCU)PWM_CAPTCTRLA_EDGA0_SHIFT (2U)PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)PWM_CAPTCTRLA_EDGA1_MASK (0x30U)PWM_CAPTCTRLA_EDGA1_SHIFT (4U)PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)ÁPWM_CAPTCTRLA_INP_SELA_SHIFT (6U)āPWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)ŁPWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)ƁPWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)ǁPWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)ȁPWM_CAPTCTRLA_CFAWM_MASK (0x300U)ɁPWM_CAPTCTRLA_CFAWM_SHIFT (8U)ʁPWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)ˁPWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)́PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)́PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)΁PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)ρPWM_CAPTCTRLA_CA1CNT_SHIFT (13U)ЁPWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)ԁPWM_CAPTCTRLA_COUNT (4U)؁PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)فPWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)ځPWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)ہPWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)܁PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)݁PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)PWM_CAPTCOMPA_COUNT (4U)PWM_CAPTCTRLB_ARMB_MASK (0x1U)PWM_CAPTCTRLB_ARMB_SHIFT (0U)PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)PWM_CAPTCTRLB_EDGB0_MASK (0xCU)PWM_CAPTCTRLB_EDGB0_SHIFT (2U)PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)PWM_CAPTCTRLB_EDGB1_MASK (0x30U)PWM_CAPTCTRLB_EDGB1_SHIFT (4U)PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)PWM_CAPTCTRLB_CFBWM_MASK (0x300U)PWM_CAPTCTRLB_CFBWM_SHIFT (8U)PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)PWM_CAPTCTRLB_COUNT (4U)PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)PWM_CAPTCOMPB_COUNT (4U)PWM_CAPTCTRLX_ARMX_MASK (0x1U)PWM_CAPTCTRLX_ARMX_SHIFT (0U)PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)PWM_CAPTCTRLX_EDGX0_MASK (0xCU)PWM_CAPTCTRLX_EDGX0_SHIFT (2U)PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)PWM_CAPTCTRLX_EDGX1_MASK (0x30U)PWM_CAPTCTRLX_EDGX1_SHIFT (4U)PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)PWM_CAPTCTRLX_CFXWM_MASK (0x300U)PWM_CAPTCTRLX_CFXWM_SHIFT (8U)PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)PWM_CAPTCTRLX_COUNT (4U)PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)PWM_CAPTCOMPX_COUNT (4U)ÂPWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)ĂPWM_CVAL0_CAPTVAL0_SHIFT (0U)łPWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)ɂPWM_CVAL0_COUNT (4U)͂PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)΂PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)ςPWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)ӂPWM_CVAL0CYC_COUNT (4U)ׂPWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)؂PWM_CVAL1_CAPTVAL1_SHIFT (0U)قPWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)݂PWM_CVAL1_COUNT (4U)PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)PWM_CVAL1CYC_COUNT (4U)PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)PWM_CVAL2_CAPTVAL2_SHIFT (0U)PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)PWM_CVAL2_COUNT (4U)PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)PWM_CVAL2CYC_COUNT (4U)PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)PWM_CVAL3_CAPTVAL3_SHIFT (0U)PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)PWM_CVAL3_COUNT (4U)PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)PWM_CVAL3CYC_COUNT (4U)PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)PWM_CVAL4_CAPTVAL4_SHIFT (0U)PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)PWM_CVAL4_COUNT (4U)PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)PWM_CVAL4CYC_COUNT (4U)PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)PWM_CVAL5_CAPTVAL5_SHIFT (0U)PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)PWM_CVAL5_COUNT (4U)PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)PWM_CVAL5CYC_COUNT (4U)PWM_OUTEN_PWMX_EN_MASK (0xFU)PWM_OUTEN_PWMX_EN_SHIFT (0U)PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)PWM_OUTEN_PWMB_EN_MASK (0xF0U)PWM_OUTEN_PWMB_EN_SHIFT (4U)PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)PWM_OUTEN_PWMA_EN_MASK (0xF00U)ƒPWM_OUTEN_PWMA_EN_SHIFT (8U)ÃPWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)ȃPWM_MASK_MASKX_MASK (0xFU)ɃPWM_MASK_MASKX_SHIFT (0U)ʃPWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)˃PWM_MASK_MASKB_MASK (0xF0U)̃PWM_MASK_MASKB_SHIFT (4U)̓PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)΃PWM_MASK_MASKA_MASK (0xF00U)σPWM_MASK_MASKA_SHIFT (8U)ЃPWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)уPWM_MASK_UPDATE_MASK_MASK (0xF000U)҃PWM_MASK_UPDATE_MASK_SHIFT (12U)ӃPWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)؃PWM_SWCOUT_SM0OUT45_MASK (0x1U)كPWM_SWCOUT_SM0OUT45_SHIFT (0U)ڃPWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)ۃPWM_SWCOUT_SM0OUT23_MASK (0x2U)܃PWM_SWCOUT_SM0OUT23_SHIFT (1U)݃PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)ރPWM_SWCOUT_SM1OUT45_MASK (0x4U)߃PWM_SWCOUT_SM1OUT45_SHIFT (2U)PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)PWM_SWCOUT_SM1OUT23_MASK (0x8U)PWM_SWCOUT_SM1OUT23_SHIFT (3U)PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)PWM_SWCOUT_SM2OUT45_MASK (0x10U)PWM_SWCOUT_SM2OUT45_SHIFT (4U)PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)PWM_SWCOUT_SM2OUT23_MASK (0x20U)PWM_SWCOUT_SM2OUT23_SHIFT (5U)PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)PWM_SWCOUT_SM3OUT45_MASK (0x40U)PWM_SWCOUT_SM3OUT45_SHIFT (6U)PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)PWM_SWCOUT_SM3OUT23_MASK (0x80U)PWM_SWCOUT_SM3OUT23_SHIFT (7U)PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)PWM_MCTRL_LDOK_MASK (0xFU)PWM_MCTRL_LDOK_SHIFT (0U)PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)PWM_MCTRL_CLDOK_MASK (0xF0U)PWM_MCTRL_CLDOK_SHIFT (4U)PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)PWM_MCTRL_RUN_MASK (0xF00U)PWM_MCTRL_RUN_SHIFT (8U)PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)PWM_MCTRL_IPOL_MASK (0xF000U)PWM_MCTRL_IPOL_SHIFT (12U)PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)PWM_MCTRL2_MONPLL_MASK (0x3U)PWM_MCTRL2_MONPLL_SHIFT (0U)PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)PWM_FCTRL_FIE_MASK (0xFU)PWM_FCTRL_FIE_SHIFT (0U)PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)PWM_FCTRL_FSAFE_MASK (0xF0U)PWM_FCTRL_FSAFE_SHIFT (4U)PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)PWM_FCTRL_FAUTO_MASK (0xF00U)PWM_FCTRL_FAUTO_SHIFT (8U)PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)PWM_FCTRL_FLVL_MASK (0xF000U)PWM_FCTRL_FLVL_SHIFT (12U)PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)PWM_FSTS_FFLAG_MASK (0xFU)PWM_FSTS_FFLAG_SHIFT (0U)PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)PWM_FSTS_FFULL_MASK (0xF0U)PWM_FSTS_FFULL_SHIFT (4U)PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)PWM_FSTS_FFPIN_MASK (0xF00U)PWM_FSTS_FFPIN_SHIFT (8U)PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)PWM_FSTS_FHALF_MASK (0xF000U)PWM_FSTS_FHALF_SHIFT (12U)„PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)DŽPWM_FFILT_FILT_PER_MASK (0xFFU)ȄPWM_FFILT_FILT_PER_SHIFT (0U)ɄPWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)ʄPWM_FFILT_FILT_CNT_MASK (0x700U)˄PWM_FFILT_FILT_CNT_SHIFT (8U)̄PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)̈́PWM_FFILT_GSTR_MASK (0x8000U)΄PWM_FFILT_GSTR_SHIFT (15U)τPWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)ԄPWM_FTST_FTEST_MASK (0x1U)ՄPWM_FTST_FTEST_SHIFT (0U)քPWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)ۄPWM_FCTRL2_NOCOMB_MASK (0xFU)܄PWM_FCTRL2_NOCOMB_SHIFT (0U)݄PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)PWM1_BASE (0x403DC000u)PWM1 ((PWM_Type *)PWM1_BASE)PWM2_BASE (0x403E0000u)PWM2 ((PWM_Type *)PWM2_BASE)PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE }PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2 }PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn }PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn }ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)ROMC_ROMPATCHD_DATAX_SHIFT (0U)ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)ROMC_ROMPATCHD_COUNT (8U)ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)ROMC_ROMPATCHA_THUMBX_MASK (0x1U)ROMC_ROMPATCHA_THUMBX_SHIFT (0U)ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)ROMC_ROMPATCHA_ADDRX_SHIFT (1U)ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)ÅROMC_ROMPATCHA_COUNT (16U)DžROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)ȅROMC_ROMPATCHSR_SOURCE_SHIFT (0U)ɅROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)ʅROMC_ROMPATCHSR_SW_MASK (0x20000U)˅ROMC_ROMPATCHSR_SW_SHIFT (17U)̅ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)ׅROMC_BASE (0x40180000u)مROMC ((ROMC_Type *)ROMC_BASE)ۅROMC_BASE_ADDRS { ROMC_BASE }݅ROMC_BASE_PTRS { ROMC }RTWDOG_CS_STOP_MASK (0x1U)RTWDOG_CS_STOP_SHIFT (0U)RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)RTWDOG_CS_WAIT_MASK (0x2U)RTWDOG_CS_WAIT_SHIFT (1U)RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)RTWDOG_CS_DBG_MASK (0x4U)RTWDOG_CS_DBG_SHIFT (2U)RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)RTWDOG_CS_TST_MASK (0x18U)RTWDOG_CS_TST_SHIFT (3U)RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)RTWDOG_CS_UPDATE_MASK (0x20U)RTWDOG_CS_UPDATE_SHIFT (5U)RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)RTWDOG_CS_INT_MASK (0x40U)RTWDOG_CS_INT_SHIFT (6U)RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)RTWDOG_CS_EN_MASK (0x80U)RTWDOG_CS_EN_SHIFT (7U)RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)RTWDOG_CS_CLK_MASK (0x300U)RTWDOG_CS_CLK_SHIFT (8U)RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)RTWDOG_CS_RCS_MASK (0x400U)RTWDOG_CS_RCS_SHIFT (10U)RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)RTWDOG_CS_ULK_MASK (0x800U)RTWDOG_CS_ULK_SHIFT (11U)RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)RTWDOG_CS_PRES_MASK (0x1000U)RTWDOG_CS_PRES_SHIFT (12U)RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)RTWDOG_CS_CMD32EN_MASK (0x2000U)RTWDOG_CS_CMD32EN_SHIFT (13U)RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)RTWDOG_CS_FLG_MASK (0x4000U)RTWDOG_CS_FLG_SHIFT (14U)RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)RTWDOG_CS_WIN_MASK (0x8000U)RTWDOG_CS_WIN_SHIFT (15U)RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)RTWDOG_CNT_CNTLOW_MASK (0xFFU)RTWDOG_CNT_CNTLOW_SHIFT (0U)RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)RTWDOG_CNT_CNTHIGH_SHIFT (8U)RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)†RTWDOG_WIN_WINLOW_MASK (0xFFU)ÆRTWDOG_WIN_WINLOW_SHIFT (0U)ĆRTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)ņRTWDOG_WIN_WINHIGH_MASK (0xFF00U)ƆRTWDOG_WIN_WINHIGH_SHIFT (8U)džRTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)҆RTWDOG_BASE (0x400BC000u)ԆRTWDOG ((RTWDOG_Type *)RTWDOG_BASE)ֆRTWDOG_BASE_ADDRS { RTWDOG_BASE }؆RTWDOG_BASE_PTRS { RTWDOG }چRTWDOG_IRQS { RTWDOG_IRQn }܆RTWDOG_UPDATE_KEY (0xD928C520U)݆RTWDOG_REFRESH_KEY (0xB480A602U)SEMC_MCR_SWRST_MASK (0x1U)SEMC_MCR_SWRST_SHIFT (0U)SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)SEMC_MCR_MDIS_MASK (0x2U)SEMC_MCR_MDIS_SHIFT (1U)SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)SEMC_MCR_DQSMD_MASK (0x4U)SEMC_MCR_DQSMD_SHIFT (2U)SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)SEMC_MCR_WPOL0_MASK (0x40U)SEMC_MCR_WPOL0_SHIFT (6U)SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)SEMC_MCR_WPOL1_MASK (0x80U)SEMC_MCR_WPOL1_SHIFT (7U)SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)SEMC_MCR_CTO_MASK (0xFF0000U)SEMC_MCR_CTO_SHIFT (16U)SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)‡SEMC_MCR_BTO_MASK (0x1F000000U)ÇSEMC_MCR_BTO_SHIFT (24U)ćSEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)ɇSEMC_IOCR_MUX_A8_MASK (0x7U)ʇSEMC_IOCR_MUX_A8_SHIFT (0U)ˇSEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)̇SEMC_IOCR_MUX_CSX0_MASK (0x38U)͇SEMC_IOCR_MUX_CSX0_SHIFT (3U)·SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)χSEMC_IOCR_MUX_CSX1_MASK (0x1C0U)ЇSEMC_IOCR_MUX_CSX1_SHIFT (6U)чSEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)҇SEMC_IOCR_MUX_CSX2_MASK (0xE00U)ӇSEMC_IOCR_MUX_CSX2_SHIFT (9U)ԇSEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)ՇSEMC_IOCR_MUX_CSX3_MASK (0x7000U)ևSEMC_IOCR_MUX_CSX3_SHIFT (12U)ׇSEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)؇SEMC_IOCR_MUX_RDY_MASK (0x38000U)هSEMC_IOCR_MUX_RDY_SHIFT (15U)ڇSEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)߇SEMC_BMCR0_WQOS_MASK (0xFU)SEMC_BMCR0_WQOS_SHIFT (0U)SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)SEMC_BMCR0_WAGE_MASK (0xF0U)SEMC_BMCR0_WAGE_SHIFT (4U)SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)SEMC_BMCR0_WSH_MASK (0xFF00U)SEMC_BMCR0_WSH_SHIFT (8U)SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)SEMC_BMCR0_WRWS_MASK (0xFF0000U)SEMC_BMCR0_WRWS_SHIFT (16U)SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)SEMC_BMCR1_WQOS_MASK (0xFU)SEMC_BMCR1_WQOS_SHIFT (0U)SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)SEMC_BMCR1_WAGE_MASK (0xF0U)SEMC_BMCR1_WAGE_SHIFT (4U)SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)SEMC_BMCR1_WPH_MASK (0xFF00U)SEMC_BMCR1_WPH_SHIFT (8U)SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)SEMC_BMCR1_WRWS_MASK (0xFF0000U)SEMC_BMCR1_WRWS_SHIFT (16U)SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)SEMC_BMCR1_WBR_MASK (0xFF000000U)SEMC_BMCR1_WBR_SHIFT (24U)SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)SEMC_BR_VLD_MASK (0x1U)SEMC_BR_VLD_SHIFT (0U)SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)SEMC_BR_MS_MASK (0x3EU)SEMC_BR_MS_SHIFT (1U)SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)SEMC_BR_BA_MASK (0xFFFFF000U)SEMC_BR_BA_SHIFT (12U)SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)SEMC_BR_COUNT (9U)SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)SEMC_INTEN_IPCMDERREN_MASK (0x2U)SEMC_INTEN_IPCMDERREN_SHIFT (1U)SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)SEMC_INTEN_AXICMDERREN_MASK (0x4U)SEMC_INTEN_AXICMDERREN_SHIFT (2U)SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)SEMC_INTEN_AXIBUSERREN_MASK (0x8U)SEMC_INTEN_AXIBUSERREN_SHIFT (3U)SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)SEMC_INTEN_NDNOPENDEN_MASK (0x20U)SEMC_INTEN_NDNOPENDEN_SHIFT (5U)SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)SEMC_INTR_IPCMDDONE_MASK (0x1U)SEMC_INTR_IPCMDDONE_SHIFT (0U)SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)SEMC_INTR_IPCMDERR_MASK (0x2U)SEMC_INTR_IPCMDERR_SHIFT (1U)SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)SEMC_INTR_AXICMDERR_MASK (0x4U)SEMC_INTR_AXICMDERR_SHIFT (2U)SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)SEMC_INTR_AXIBUSERR_MASK (0x8U)SEMC_INTR_AXIBUSERR_SHIFT (3U)SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)SEMC_INTR_NDPAGEEND_MASK (0x10U)SEMC_INTR_NDPAGEEND_SHIFT (4U)SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)SEMC_INTR_NDNOPEND_MASK (0x20U)SEMC_INTR_NDNOPEND_SHIFT (5U)SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)SEMC_SDRAMCR0_PS_MASK (0x1U)SEMC_SDRAMCR0_PS_SHIFT (0U)SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)SEMC_SDRAMCR0_BL_MASK (0x70U)ˆSEMC_SDRAMCR0_BL_SHIFT (4U)ÈSEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)ĈSEMC_SDRAMCR0_COL_MASK (0x300U)ňSEMC_SDRAMCR0_COL_SHIFT (8U)ƈSEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)LjSEMC_SDRAMCR0_CL_MASK (0xC00U)ȈSEMC_SDRAMCR0_CL_SHIFT (10U)ɈSEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)ΈSEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)ψSEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)ЈSEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)шSEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)҈SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)ӈSEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)ԈSEMC_SDRAMCR1_RFRC_MASK (0x1F00U)ՈSEMC_SDRAMCR1_RFRC_SHIFT (8U)ֈSEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)׈SEMC_SDRAMCR1_WRC_MASK (0xE000U)؈SEMC_SDRAMCR1_WRC_SHIFT (13U)وSEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)ڈSEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)ۈSEMC_SDRAMCR1_CKEOFF_SHIFT (16U)܈SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)݈SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)ވSEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)߈SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)SEMC_SDRAMCR2_SRRC_MASK (0xFFU)SEMC_SDRAMCR2_SRRC_SHIFT (0U)SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)SEMC_SDRAMCR2_REF2REF_SHIFT (8U)SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)SEMC_SDRAMCR2_ITO_SHIFT (24U)SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)SEMC_SDRAMCR3_REN_MASK (0x1U)SEMC_SDRAMCR3_REN_SHIFT (0U)SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)SEMC_SDRAMCR3_REBL_MASK (0xEU)SEMC_SDRAMCR3_REBL_SHIFT (1U)SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)SEMC_SDRAMCR3_RT_MASK (0xFF0000U)SEMC_SDRAMCR3_RT_SHIFT (16U)SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)SEMC_SDRAMCR3_UT_MASK (0xFF000000U)SEMC_SDRAMCR3_UT_SHIFT (24U)SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)SEMC_NANDCR0_PS_MASK (0x1U)SEMC_NANDCR0_PS_SHIFT (0U)SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)SEMC_NANDCR0_BL_MASK (0x70U)SEMC_NANDCR0_BL_SHIFT (4U)SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)SEMC_NANDCR0_EDO_MASK (0x80U)SEMC_NANDCR0_EDO_SHIFT (7U)SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)SEMC_NANDCR0_COL_MASK (0x700U)SEMC_NANDCR0_COL_SHIFT (8U)SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)SEMC_NANDCR1_CES_MASK (0xFU)SEMC_NANDCR1_CES_SHIFT (0U)SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)SEMC_NANDCR1_CEH_MASK (0xF0U)SEMC_NANDCR1_CEH_SHIFT (4U)SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)SEMC_NANDCR1_WEL_MASK (0xF00U)SEMC_NANDCR1_WEL_SHIFT (8U)SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)SEMC_NANDCR1_WEH_MASK (0xF000U)SEMC_NANDCR1_WEH_SHIFT (12U)SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)SEMC_NANDCR1_REL_MASK (0xF0000U)SEMC_NANDCR1_REL_SHIFT (16U)SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)SEMC_NANDCR1_REH_MASK (0xF00000U)SEMC_NANDCR1_REH_SHIFT (20U)SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)SEMC_NANDCR1_TA_MASK (0xF000000U)SEMC_NANDCR1_TA_SHIFT (24U)SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)SEMC_NANDCR1_CEITV_MASK (0xF0000000U)SEMC_NANDCR1_CEITV_SHIFT (28U)SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)SEMC_NANDCR2_TWHR_MASK (0x3FU)SEMC_NANDCR2_TWHR_SHIFT (0U)SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)SEMC_NANDCR2_TRHW_MASK (0xFC0U)SEMC_NANDCR2_TRHW_SHIFT (6U)SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)SEMC_NANDCR2_TADL_MASK (0x3F000U)SEMC_NANDCR2_TADL_SHIFT (12U)SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)SEMC_NANDCR2_TRR_MASK (0xFC0000U)SEMC_NANDCR2_TRR_SHIFT (18U)SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)SEMC_NANDCR2_TWB_MASK (0x3F000000U)SEMC_NANDCR2_TWB_SHIFT (24U)SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)ƉSEMC_NANDCR3_NDOPT1_MASK (0x1U)ljSEMC_NANDCR3_NDOPT1_SHIFT (0U)ȉSEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)ɉSEMC_NANDCR3_NDOPT2_MASK (0x2U)ʉSEMC_NANDCR3_NDOPT2_SHIFT (1U)ˉSEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)̉SEMC_NANDCR3_NDOPT3_MASK (0x4U)͉SEMC_NANDCR3_NDOPT3_SHIFT (2U)ΉSEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)ӉSEMC_NORCR0_PS_MASK (0x1U)ԉSEMC_NORCR0_PS_SHIFT (0U)ՉSEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)։SEMC_NORCR0_BL_MASK (0x70U)׉SEMC_NORCR0_BL_SHIFT (4U)؉SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)ىSEMC_NORCR0_AM_MASK (0x300U)ډSEMC_NORCR0_AM_SHIFT (8U)ۉSEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)܉SEMC_NORCR0_ADVP_MASK (0x400U)݉SEMC_NORCR0_ADVP_SHIFT (10U)މSEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)߉SEMC_NORCR0_COL_MASK (0xF000U)SEMC_NORCR0_COL_SHIFT (12U)SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)SEMC_NORCR1_CES_MASK (0xFU)SEMC_NORCR1_CES_SHIFT (0U)SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)SEMC_NORCR1_CEH_MASK (0xF0U)SEMC_NORCR1_CEH_SHIFT (4U)SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)SEMC_NORCR1_AS_MASK (0xF00U)SEMC_NORCR1_AS_SHIFT (8U)SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)SEMC_NORCR1_AH_MASK (0xF000U)SEMC_NORCR1_AH_SHIFT (12U)SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)SEMC_NORCR1_WEL_MASK (0xF0000U)SEMC_NORCR1_WEL_SHIFT (16U)SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)SEMC_NORCR1_WEH_MASK (0xF00000U)SEMC_NORCR1_WEH_SHIFT (20U)SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)SEMC_NORCR1_REL_MASK (0xF000000U)SEMC_NORCR1_REL_SHIFT (24U)SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)SEMC_NORCR1_REH_MASK (0xF0000000U)SEMC_NORCR1_REH_SHIFT (28U)SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)SEMC_NORCR2_WDS_MASK (0xFU)SEMC_NORCR2_WDS_SHIFT (0U)SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)SEMC_NORCR2_WDH_MASK (0xF0U)SEMC_NORCR2_WDH_SHIFT (4U)SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)SEMC_NORCR2_TA_MASK (0xF00U)SEMC_NORCR2_TA_SHIFT (8U)SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)SEMC_NORCR2_AWDH_MASK (0xF000U)SEMC_NORCR2_AWDH_SHIFT (12U)SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)SEMC_NORCR2_LC_MASK (0xF0000U)SEMC_NORCR2_LC_SHIFT (16U)SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)SEMC_NORCR2_RD_MASK (0xF00000U)SEMC_NORCR2_RD_SHIFT (20U)SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)SEMC_NORCR2_CEITV_MASK (0xF000000U)SEMC_NORCR2_CEITV_SHIFT (24U)SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)SEMC_SRAMCR0_PS_MASK (0x1U)SEMC_SRAMCR0_PS_SHIFT (0U)SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)SEMC_SRAMCR0_BL_MASK (0x70U)SEMC_SRAMCR0_BL_SHIFT (4U)SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)SEMC_SRAMCR0_AM_MASK (0x300U)SEMC_SRAMCR0_AM_SHIFT (8U)SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)SEMC_SRAMCR0_ADVP_MASK (0x400U)SEMC_SRAMCR0_ADVP_SHIFT (10U)SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)SEMC_SRAMCR0_COL_MASK (0xF000U)SEMC_SRAMCR0_COL_SHIFT (12U)SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)SEMC_SRAMCR1_CES_MASK (0xFU)SEMC_SRAMCR1_CES_SHIFT (0U)SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)SEMC_SRAMCR1_CEH_MASK (0xF0U)SEMC_SRAMCR1_CEH_SHIFT (4U)SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)SEMC_SRAMCR1_AS_MASK (0xF00U)SEMC_SRAMCR1_AS_SHIFT (8U)SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)SEMC_SRAMCR1_AH_MASK (0xF000U)SEMC_SRAMCR1_AH_SHIFT (12U)SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)SEMC_SRAMCR1_WEL_MASK (0xF0000U)SEMC_SRAMCR1_WEL_SHIFT (16U)SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)SEMC_SRAMCR1_WEH_MASK (0xF00000U)SEMC_SRAMCR1_WEH_SHIFT (20U)SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)SEMC_SRAMCR1_REL_MASK (0xF000000U)SEMC_SRAMCR1_REL_SHIFT (24U)ŠSEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)ÊSEMC_SRAMCR1_REH_MASK (0xF0000000U)ĊSEMC_SRAMCR1_REH_SHIFT (28U)ŊSEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)ʊSEMC_SRAMCR2_WDS_MASK (0xFU)ˊSEMC_SRAMCR2_WDS_SHIFT (0U)̊SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)͊SEMC_SRAMCR2_WDH_MASK (0xF0U)ΊSEMC_SRAMCR2_WDH_SHIFT (4U)ϊSEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)ЊSEMC_SRAMCR2_TA_MASK (0xF00U)ъSEMC_SRAMCR2_TA_SHIFT (8U)ҊSEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)ӊSEMC_SRAMCR2_AWDH_MASK (0xF000U)ԊSEMC_SRAMCR2_AWDH_SHIFT (12U)ՊSEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)֊SEMC_SRAMCR2_LC_MASK (0xF0000U)׊SEMC_SRAMCR2_LC_SHIFT (16U)؊SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)يSEMC_SRAMCR2_RD_MASK (0xF00000U)ڊSEMC_SRAMCR2_RD_SHIFT (20U)ۊSEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)܊SEMC_SRAMCR2_CEITV_MASK (0xF000000U)݊SEMC_SRAMCR2_CEITV_SHIFT (24U)ފSEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)SEMC_DBICR0_PS_MASK (0x1U)SEMC_DBICR0_PS_SHIFT (0U)SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)SEMC_DBICR0_BL_MASK (0x70U)SEMC_DBICR0_BL_SHIFT (4U)SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)SEMC_DBICR0_COL_MASK (0xF000U)SEMC_DBICR0_COL_SHIFT (12U)SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)SEMC_DBICR1_CES_MASK (0xFU)SEMC_DBICR1_CES_SHIFT (0U)SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)SEMC_DBICR1_CEH_MASK (0xF0U)SEMC_DBICR1_CEH_SHIFT (4U)SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)SEMC_DBICR1_WEL_MASK (0xF00U)SEMC_DBICR1_WEL_SHIFT (8U)SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)SEMC_DBICR1_WEH_MASK (0xF000U)SEMC_DBICR1_WEH_SHIFT (12U)SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)SEMC_DBICR1_REL_MASK (0xF0000U)SEMC_DBICR1_REL_SHIFT (16U)SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)SEMC_DBICR1_REH_MASK (0xF00000U)SEMC_DBICR1_REH_SHIFT (20U)SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)SEMC_DBICR1_CEITV_MASK (0xF000000U)SEMC_DBICR1_CEITV_SHIFT (24U)SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)SEMC_IPCR0_SA_SHIFT (0U)SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)SEMC_IPCR1_DATSZ_MASK (0x7U)SEMC_IPCR1_DATSZ_SHIFT (0U)SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)SEMC_IPCR2_BM0_MASK (0x1U)SEMC_IPCR2_BM0_SHIFT (0U)SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)SEMC_IPCR2_BM1_MASK (0x2U)SEMC_IPCR2_BM1_SHIFT (1U)SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)SEMC_IPCR2_BM2_MASK (0x4U)SEMC_IPCR2_BM2_SHIFT (2U)SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)SEMC_IPCR2_BM3_MASK (0x8U)SEMC_IPCR2_BM3_SHIFT (3U)SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)SEMC_IPCMD_CMD_MASK (0xFFFFU)SEMC_IPCMD_CMD_SHIFT (0U)SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)SEMC_IPCMD_KEY_MASK (0xFFFF0000U)SEMC_IPCMD_KEY_SHIFT (16U)SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)SEMC_IPTXDAT_DAT_SHIFT (0U)SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)SEMC_IPRXDAT_DAT_SHIFT (0U)SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)SEMC_STS0_IDLE_MASK (0x1U)SEMC_STS0_IDLE_SHIFT (0U)SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)‹SEMC_STS0_NARDY_MASK (0x2U)ËSEMC_STS0_NARDY_SHIFT (1U)ċSEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)ɋSEMC_STS2_NDWRPEND_MASK (0x8U)ʋSEMC_STS2_NDWRPEND_SHIFT (3U)ˋSEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)ЋSEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)ыSEMC_STS12_NDADDR_SHIFT (0U)ҋSEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)݋SEMC_BASE (0x402F0000u)ߋSEMC ((SEMC_Type *)SEMC_BASE)SEMC_BASE_ADDRS { SEMC_BASE }SEMC_BASE_PTRS { SEMC }SEMC_IRQS { SEMC_IRQn }SNVS_HPLR_ZMK_WSL_MASK (0x1U)SNVS_HPLR_ZMK_WSL_SHIFT (0U)SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)SNVS_HPLR_ZMK_RSL_MASK (0x2U)SNVS_HPLR_ZMK_RSL_SHIFT (1U)SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)SNVS_HPLR_SRTC_SL_MASK (0x4U)SNVS_HPLR_SRTC_SL_SHIFT (2U)SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)SNVS_HPLR_LPCALB_SL_MASK (0x8U)SNVS_HPLR_LPCALB_SL_SHIFT (3U)SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)SNVS_HPLR_MC_SL_MASK (0x10U)SNVS_HPLR_MC_SL_SHIFT (4U)SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)SNVS_HPLR_GPR_SL_MASK (0x20U)SNVS_HPLR_GPR_SL_SHIFT (5U)SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)SNVS_HPLR_LPSVCR_SL_MASK (0x40U)SNVS_HPLR_LPSVCR_SL_SHIFT (6U)SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)SNVS_HPLR_LPTDCR_SL_MASK (0x100U)SNVS_HPLR_LPTDCR_SL_SHIFT (8U)SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)SNVS_HPLR_MKS_SL_MASK (0x200U)SNVS_HPLR_MKS_SL_SHIFT (9U)SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)ŒSNVS_HPLR_HPSVCR_L_MASK (0x10000U)ÌSNVS_HPLR_HPSVCR_L_SHIFT (16U)ČSNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)ŌSNVS_HPLR_HPSICR_L_MASK (0x20000U)ƌSNVS_HPLR_HPSICR_L_SHIFT (17U)njSNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)ȌSNVS_HPLR_HAC_L_MASK (0x40000U)ɌSNVS_HPLR_HAC_L_SHIFT (18U)ʌSNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)όSNVS_HPCOMR_SSM_ST_MASK (0x1U)ЌSNVS_HPCOMR_SSM_ST_SHIFT (0U)ьSNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)ҌSNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)ӌSNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)ԌSNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)ՌSNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)֌SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)׌SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)،SNVS_HPCOMR_LP_SWR_MASK (0x10U)ٌSNVS_HPCOMR_LP_SWR_SHIFT (4U)ڌSNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)یSNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)܌SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)݌SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)ތSNVS_HPCOMR_SW_SV_MASK (0x100U)ߌSNVS_HPCOMR_SW_SV_SHIFT (8U)SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)SNVS_HPCOMR_SW_FSV_MASK (0x200U)SNVS_HPCOMR_SW_FSV_SHIFT (9U)SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)SNVS_HPCOMR_SW_LPSV_MASK (0x400U)SNVS_HPCOMR_SW_LPSV_SHIFT (10U)SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)SNVS_HPCOMR_MKS_EN_MASK (0x2000U)SNVS_HPCOMR_MKS_EN_SHIFT (13U)SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)SNVS_HPCOMR_HAC_EN_MASK (0x10000U)SNVS_HPCOMR_HAC_EN_SHIFT (16U)SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)SNVS_HPCOMR_HAC_STOP_SHIFT (19U)SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)SNVS_HPCR_RTC_EN_MASK (0x1U)SNVS_HPCR_RTC_EN_SHIFT (0U)SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)SNVS_HPCR_HPTA_EN_MASK (0x2U)SNVS_HPCR_HPTA_EN_SHIFT (1U)SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)SNVS_HPCR_DIS_PI_MASK (0x4U)SNVS_HPCR_DIS_PI_SHIFT (2U)SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)SNVS_HPCR_PI_EN_MASK (0x8U)SNVS_HPCR_PI_EN_SHIFT (3U)SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)SNVS_HPCR_PI_FREQ_MASK (0xF0U)SNVS_HPCR_PI_FREQ_SHIFT (4U)SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)SNVS_HPCR_HPCALB_EN_MASK (0x100U)SNVS_HPCR_HPCALB_EN_SHIFT (8U)SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)SNVS_HPCR_HPCALB_VAL_SHIFT (10U)SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)SNVS_HPCR_HP_TS_MASK (0x10000U)SNVS_HPCR_HP_TS_SHIFT (16U)SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)SNVS_HPCR_BTN_CONFIG_SHIFT (24U)SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)SNVS_HPCR_BTN_MASK_MASK (0x8000000U)SNVS_HPCR_BTN_MASK_SHIFT (27U)SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)SNVS_HPSICR_SV0_EN_MASK (0x1U)SNVS_HPSICR_SV0_EN_SHIFT (0U)SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)SNVS_HPSICR_SV1_EN_MASK (0x2U)SNVS_HPSICR_SV1_EN_SHIFT (1U)SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)SNVS_HPSICR_SV2_EN_MASK (0x4U)SNVS_HPSICR_SV2_EN_SHIFT (2U)SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)SNVS_HPSICR_SV3_EN_MASK (0x8U)SNVS_HPSICR_SV3_EN_SHIFT (3U)SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)SNVS_HPSICR_SV4_EN_MASK (0x10U)SNVS_HPSICR_SV4_EN_SHIFT (4U)SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)SNVS_HPSICR_SV5_EN_MASK (0x20U)SNVS_HPSICR_SV5_EN_SHIFT (5U)SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)SNVS_HPSICR_LPSVI_EN_SHIFT (31U)SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)SNVS_HPSVCR_SV0_CFG_MASK (0x1U)SNVS_HPSVCR_SV0_CFG_SHIFT (0U)SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)SNVS_HPSVCR_SV1_CFG_MASK (0x2U)SNVS_HPSVCR_SV1_CFG_SHIFT (1U)SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)SNVS_HPSVCR_SV2_CFG_MASK (0x4U)SNVS_HPSVCR_SV2_CFG_SHIFT (2U)ÍSNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)čSNVS_HPSVCR_SV3_CFG_MASK (0x8U)ōSNVS_HPSVCR_SV3_CFG_SHIFT (3U)ƍSNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)ǍSNVS_HPSVCR_SV4_CFG_MASK (0x10U)ȍSNVS_HPSVCR_SV4_CFG_SHIFT (4U)ɍSNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)ʍSNVS_HPSVCR_SV5_CFG_MASK (0x60U)ˍSNVS_HPSVCR_SV5_CFG_SHIFT (5U)̍SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)͍SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)΍SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)ύSNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)ԍSNVS_HPSR_HPTA_MASK (0x1U)ՍSNVS_HPSR_HPTA_SHIFT (0U)֍SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)׍SNVS_HPSR_PI_MASK (0x2U)؍SNVS_HPSR_PI_SHIFT (1U)ٍSNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)ڍSNVS_HPSR_LPDIS_MASK (0x10U)ۍSNVS_HPSR_LPDIS_SHIFT (4U)܍SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)ݍSNVS_HPSR_BTN_MASK (0x40U)ލSNVS_HPSR_BTN_SHIFT (6U)ߍSNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)SNVS_HPSR_BI_MASK (0x80U)SNVS_HPSR_BI_SHIFT (7U)SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)SNVS_HPSR_SSM_STATE_MASK (0xF00U)SNVS_HPSR_SSM_STATE_SHIFT (8U)SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)SNVS_HPSR_ZMK_ZERO_SHIFT (31U)SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)SNVS_HPSVSR_SV0_MASK (0x1U)SNVS_HPSVSR_SV0_SHIFT (0U)SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)SNVS_HPSVSR_SV1_MASK (0x2U)SNVS_HPSVSR_SV1_SHIFT (1U)SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)SNVS_HPSVSR_SV2_MASK (0x4U)SNVS_HPSVSR_SV2_SHIFT (2U)SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)SNVS_HPSVSR_SV3_MASK (0x8U)SNVS_HPSVSR_SV3_SHIFT (3U)SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)SNVS_HPSVSR_SV4_MASK (0x10U)SNVS_HPSVSR_SV4_SHIFT (4U)SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)SNVS_HPSVSR_SV5_MASK (0x20U)SNVS_HPSVSR_SV5_SHIFT (5U)SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)SNVS_HPSVSR_SW_SV_MASK (0x2000U)SNVS_HPSVSR_SW_SV_SHIFT (13U)SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)SNVS_HPSVSR_SW_FSV_MASK (0x4000U)SNVS_HPSVSR_SW_FSV_SHIFT (14U)SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)SNVS_HPSVSR_SW_LPSV_SHIFT (15U)SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)SNVS_HPRTCMR_RTC_MASK (0x7FFFU)SNVS_HPRTCMR_RTC_SHIFT (0U)SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)SNVS_HPRTCLR_RTC_SHIFT (0U)SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)SNVS_HPTAMR_HPTA_MS_SHIFT (0U)SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)ŽSNVS_HPTALR_HPTA_LS_SHIFT (0U)ÎSNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)ȎSNVS_LPLR_ZMK_WHL_MASK (0x1U)ɎSNVS_LPLR_ZMK_WHL_SHIFT (0U)ʎSNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)ˎSNVS_LPLR_ZMK_RHL_MASK (0x2U)̎SNVS_LPLR_ZMK_RHL_SHIFT (1U)͎SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)ΎSNVS_LPLR_SRTC_HL_MASK (0x4U)ώSNVS_LPLR_SRTC_HL_SHIFT (2U)ЎSNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)юSNVS_LPLR_LPCALB_HL_MASK (0x8U)ҎSNVS_LPLR_LPCALB_HL_SHIFT (3U)ӎSNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)ԎSNVS_LPLR_MC_HL_MASK (0x10U)ՎSNVS_LPLR_MC_HL_SHIFT (4U)֎SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)׎SNVS_LPLR_GPR_HL_MASK (0x20U)؎SNVS_LPLR_GPR_HL_SHIFT (5U)َSNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)ڎSNVS_LPLR_LPSVCR_HL_MASK (0x40U)ێSNVS_LPLR_LPSVCR_HL_SHIFT (6U)܎SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)ݎSNVS_LPLR_LPTDCR_HL_MASK (0x100U)ގSNVS_LPLR_LPTDCR_HL_SHIFT (8U)ߎSNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)SNVS_LPLR_MKS_HL_MASK (0x200U)SNVS_LPLR_MKS_HL_SHIFT (9U)SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)SNVS_LPCR_SRTC_ENV_MASK (0x1U)SNVS_LPCR_SRTC_ENV_SHIFT (0U)SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)SNVS_LPCR_LPTA_EN_MASK (0x2U)SNVS_LPCR_LPTA_EN_SHIFT (1U)SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)SNVS_LPCR_MC_ENV_MASK (0x4U)SNVS_LPCR_MC_ENV_SHIFT (2U)SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)SNVS_LPCR_LPWUI_EN_MASK (0x8U)SNVS_LPCR_LPWUI_EN_SHIFT (3U)SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)SNVS_LPCR_DP_EN_MASK (0x20U)SNVS_LPCR_DP_EN_SHIFT (5U)SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)SNVS_LPCR_TOP_MASK (0x40U)SNVS_LPCR_TOP_SHIFT (6U)SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)SNVS_LPCR_LPCALB_EN_MASK (0x100U)SNVS_LPCR_LPCALB_EN_SHIFT (8U)SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)SNVS_LPCR_LPCALB_VAL_SHIFT (10U)SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)SNVS_LPCR_DEBOUNCE_SHIFT (18U)SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)SNVS_LPCR_ON_TIME_MASK (0x300000U)SNVS_LPCR_ON_TIME_SHIFT (20U)SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)SNVS_LPCR_PK_EN_MASK (0x400000U)SNVS_LPCR_PK_EN_SHIFT (22U)SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)SNVS_LPSVCR_SV0_EN_MASK (0x1U)SNVS_LPSVCR_SV0_EN_SHIFT (0U)SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)SNVS_LPSVCR_SV1_EN_MASK (0x2U)SNVS_LPSVCR_SV1_EN_SHIFT (1U)SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)SNVS_LPSVCR_SV2_EN_MASK (0x4U)SNVS_LPSVCR_SV2_EN_SHIFT (2U)SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)SNVS_LPSVCR_SV3_EN_MASK (0x8U)SNVS_LPSVCR_SV3_EN_SHIFT (3U)SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)SNVS_LPSVCR_SV4_EN_MASK (0x10U)SNVS_LPSVCR_SV4_EN_SHIFT (4U)SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)SNVS_LPSVCR_SV5_EN_MASK (0x20U)SNVS_LPSVCR_SV5_EN_SHIFT (5U)SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)ďSNVS_LPTDCR_SRTCR_EN_MASK (0x2U)ŏSNVS_LPTDCR_SRTCR_EN_SHIFT (1U)ƏSNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)ǏSNVS_LPTDCR_MCR_EN_MASK (0x4U)ȏSNVS_LPTDCR_MCR_EN_SHIFT (2U)ɏSNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)ʏSNVS_LPTDCR_ET1_EN_MASK (0x200U)ˏSNVS_LPTDCR_ET1_EN_SHIFT (9U)̏SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)͏SNVS_LPTDCR_ET1P_MASK (0x800U)ΏSNVS_LPTDCR_ET1P_SHIFT (11U)ϏSNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)ЏSNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)яSNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)ҏSNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)ӏSNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)ԏSNVS_LPTDCR_POR_OBSERV_SHIFT (15U)ՏSNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)֏SNVS_LPTDCR_OSCB_MASK (0x10000000U)׏SNVS_LPTDCR_OSCB_SHIFT (28U)؏SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)ݏSNVS_LPSR_LPTA_MASK (0x1U)ޏSNVS_LPSR_LPTA_SHIFT (0U)ߏSNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)SNVS_LPSR_SRTCR_MASK (0x2U)SNVS_LPSR_SRTCR_SHIFT (1U)SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)SNVS_LPSR_MCR_MASK (0x4U)SNVS_LPSR_MCR_SHIFT (2U)SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)SNVS_LPSR_PGD_MASK (0x8U)SNVS_LPSR_PGD_SHIFT (3U)SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)SNVS_LPSR_ET1D_MASK (0x200U)SNVS_LPSR_ET1D_SHIFT (9U)SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)SNVS_LPSR_ESVD_MASK (0x10000U)SNVS_LPSR_ESVD_SHIFT (16U)SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)SNVS_LPSR_EO_MASK (0x20000U)SNVS_LPSR_EO_SHIFT (17U)SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)SNVS_LPSR_SPO_MASK (0x40000U)SNVS_LPSR_SPO_SHIFT (18U)SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)SNVS_LPSR_SED_MASK (0x100000U)SNVS_LPSR_SED_SHIFT (20U)SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)SNVS_LPSR_LPNS_MASK (0x40000000U)SNVS_LPSR_LPNS_SHIFT (30U)SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)SNVS_LPSR_LPS_MASK (0x80000000U)SNVS_LPSR_LPS_SHIFT (31U)SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)SNVS_LPSRTCMR_SRTC_SHIFT (0U)SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)SNVS_LPSRTCLR_SRTC_SHIFT (0U)SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)SNVS_LPTAR_LPTA_SHIFT (0U)SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)SNVS_LPPGDR_PGD_SHIFT (0U)SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)SNVS_LPZMKR_ZMK_SHIFT (0U)SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)SNVS_LPZMKR_COUNT (8U)SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)ƐSNVS_LPGPR_ALIAS_COUNT (4U)ʐSNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)ːSNVS_LPGPR_GPR_SHIFT (0U)̐SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)АSNVS_LPGPR_COUNT (4U)ԐSNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)ՐSNVS_HPVIDR1_MINOR_REV_SHIFT (0U)֐SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)אSNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)ؐSNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)ِSNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)ڐSNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)ېSNVS_HPVIDR1_IP_ID_SHIFT (16U)ܐSNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)SNVS_HPVIDR2_ECO_REV_SHIFT (8U)SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)SNVS_HPVIDR2_IP_ERA_SHIFT (24U)SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)SNVS_BASE (0x400D4000u)SNVS ((SNVS_Type *)SNVS_BASE)SNVS_BASE_ADDRS { SNVS_BASE }SNVS_BASE_PTRS { SNVS }SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }SPDIF_SCR_USRC_SEL_MASK (0x3U)SPDIF_SCR_USRC_SEL_SHIFT (0U)SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)SPDIF_SCR_TXSEL_MASK (0x1CU)SPDIF_SCR_TXSEL_SHIFT (2U)SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)SPDIF_SCR_VALCTRL_MASK (0x20U)SPDIF_SCR_VALCTRL_SHIFT (5U)SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)SPDIF_SCR_DMA_TX_EN_MASK (0x100U)SPDIF_SCR_DMA_TX_EN_SHIFT (8U)SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)‘SPDIF_SCR_DMA_RX_EN_MASK (0x200U)ÑSPDIF_SCR_DMA_RX_EN_SHIFT (9U)đSPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)őSPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)ƑSPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)ǑSPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)ȑSPDIF_SCR_SOFT_RESET_MASK (0x1000U)ɑSPDIF_SCR_SOFT_RESET_SHIFT (12U)ʑSPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)ˑSPDIF_SCR_LOW_POWER_MASK (0x2000U)̑SPDIF_SCR_LOW_POWER_SHIFT (13U)͑SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)ΑSPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)ϑSPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)БSPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)ёSPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)ґSPDIF_SCR_TXAUTOSYNC_SHIFT (17U)ӑSPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)ԑSPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)ՑSPDIF_SCR_RXAUTOSYNC_SHIFT (18U)֑SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)בSPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)ؑSPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)ّSPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)ڑSPDIF_SCR_RXFIFO_RST_MASK (0x200000U)ۑSPDIF_SCR_RXFIFO_RST_SHIFT (21U)ܑSPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)ݑSPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)ޑSPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)ߑSPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)SPDIF_SRCD_USYNCMODE_MASK (0x2U)SPDIF_SRCD_USYNCMODE_SHIFT (1U)SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)SPDIF_SRPC_GAINSEL_MASK (0x38U)SPDIF_SRPC_GAINSEL_SHIFT (3U)SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)SPDIF_SRPC_LOCK_MASK (0x40U)SPDIF_SRPC_LOCK_SHIFT (6U)SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)SPDIF_SIE_RXFIFOFUL_MASK (0x1U)SPDIF_SIE_RXFIFOFUL_SHIFT (0U)SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)SPDIF_SIE_TXEM_MASK (0x2U)SPDIF_SIE_TXEM_SHIFT (1U)SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)SPDIF_SIE_LOCKLOSS_MASK (0x4U)SPDIF_SIE_LOCKLOSS_SHIFT (2U)SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)SPDIF_SIE_RXFIFORESYN_MASK (0x8U)SPDIF_SIE_RXFIFORESYN_SHIFT (3U)SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)SPDIF_SIE_UQERR_MASK (0x20U)SPDIF_SIE_UQERR_SHIFT (5U)SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)SPDIF_SIE_UQSYNC_MASK (0x40U)SPDIF_SIE_UQSYNC_SHIFT (6U)SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)SPDIF_SIE_QRXOV_MASK (0x80U)SPDIF_SIE_QRXOV_SHIFT (7U)SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)SPDIF_SIE_QRXFUL_MASK (0x100U)SPDIF_SIE_QRXFUL_SHIFT (8U)SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)SPDIF_SIE_URXOV_MASK (0x200U)SPDIF_SIE_URXOV_SHIFT (9U)SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)SPDIF_SIE_URXFUL_MASK (0x400U)SPDIF_SIE_URXFUL_SHIFT (10U)SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)SPDIF_SIE_BITERR_MASK (0x4000U)SPDIF_SIE_BITERR_SHIFT (14U)SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)SPDIF_SIE_SYMERR_MASK (0x8000U)SPDIF_SIE_SYMERR_SHIFT (15U)SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)SPDIF_SIE_VALNOGOOD_MASK (0x10000U)SPDIF_SIE_VALNOGOOD_SHIFT (16U)SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)SPDIF_SIE_CNEW_MASK (0x20000U)SPDIF_SIE_CNEW_SHIFT (17U)SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)SPDIF_SIE_TXRESYN_MASK (0x40000U)SPDIF_SIE_TXRESYN_SHIFT (18U)SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)SPDIF_SIE_TXUNOV_MASK (0x80000U)SPDIF_SIE_TXUNOV_SHIFT (19U)SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)SPDIF_SIE_LOCK_MASK (0x100000U)SPDIF_SIE_LOCK_SHIFT (20U)SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)SPDIF_SIC_LOCKLOSS_MASK (0x4U)SPDIF_SIC_LOCKLOSS_SHIFT (2U)SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)SPDIF_SIC_RXFIFORESYN_MASK (0x8U)SPDIF_SIC_RXFIFORESYN_SHIFT (3U)SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)SPDIF_SIC_UQERR_MASK (0x20U)SPDIF_SIC_UQERR_SHIFT (5U)SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)SPDIF_SIC_UQSYNC_MASK (0x40U)’SPDIF_SIC_UQSYNC_SHIFT (6U)ÒSPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)ĒSPDIF_SIC_QRXOV_MASK (0x80U)ŒSPDIF_SIC_QRXOV_SHIFT (7U)ƒSPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)ǒSPDIF_SIC_URXOV_MASK (0x200U)ȒSPDIF_SIC_URXOV_SHIFT (9U)ɒSPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)ʒSPDIF_SIC_BITERR_MASK (0x4000U)˒SPDIF_SIC_BITERR_SHIFT (14U)̒SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)͒SPDIF_SIC_SYMERR_MASK (0x8000U)ΒSPDIF_SIC_SYMERR_SHIFT (15U)ϒSPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)ВSPDIF_SIC_VALNOGOOD_MASK (0x10000U)ђSPDIF_SIC_VALNOGOOD_SHIFT (16U)ҒSPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)ӒSPDIF_SIC_CNEW_MASK (0x20000U)ԒSPDIF_SIC_CNEW_SHIFT (17U)ՒSPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)֒SPDIF_SIC_TXRESYN_MASK (0x40000U)גSPDIF_SIC_TXRESYN_SHIFT (18U)ؒSPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)ْSPDIF_SIC_TXUNOV_MASK (0x80000U)ڒSPDIF_SIC_TXUNOV_SHIFT (19U)ےSPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)ܒSPDIF_SIC_LOCK_MASK (0x100000U)ݒSPDIF_SIC_LOCK_SHIFT (20U)ޒSPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)SPDIF_SIS_RXFIFOFUL_MASK (0x1U)SPDIF_SIS_RXFIFOFUL_SHIFT (0U)SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)SPDIF_SIS_TXEM_MASK (0x2U)SPDIF_SIS_TXEM_SHIFT (1U)SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)SPDIF_SIS_LOCKLOSS_MASK (0x4U)SPDIF_SIS_LOCKLOSS_SHIFT (2U)SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)SPDIF_SIS_RXFIFORESYN_MASK (0x8U)SPDIF_SIS_RXFIFORESYN_SHIFT (3U)SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)SPDIF_SIS_UQERR_MASK (0x20U)SPDIF_SIS_UQERR_SHIFT (5U)SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)SPDIF_SIS_UQSYNC_MASK (0x40U)SPDIF_SIS_UQSYNC_SHIFT (6U)SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)SPDIF_SIS_QRXOV_MASK (0x80U)SPDIF_SIS_QRXOV_SHIFT (7U)SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)SPDIF_SIS_QRXFUL_MASK (0x100U)SPDIF_SIS_QRXFUL_SHIFT (8U)SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)SPDIF_SIS_URXOV_MASK (0x200U)SPDIF_SIS_URXOV_SHIFT (9U)SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)SPDIF_SIS_URXFUL_MASK (0x400U)SPDIF_SIS_URXFUL_SHIFT (10U)SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)SPDIF_SIS_BITERR_MASK (0x4000U)SPDIF_SIS_BITERR_SHIFT (14U)SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)SPDIF_SIS_SYMERR_MASK (0x8000U)SPDIF_SIS_SYMERR_SHIFT (15U)SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)SPDIF_SIS_VALNOGOOD_MASK (0x10000U)SPDIF_SIS_VALNOGOOD_SHIFT (16U)SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)SPDIF_SIS_CNEW_MASK (0x20000U)SPDIF_SIS_CNEW_SHIFT (17U)SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)SPDIF_SIS_TXRESYN_MASK (0x40000U)SPDIF_SIS_TXRESYN_SHIFT (18U)SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)SPDIF_SIS_TXUNOV_MASK (0x80000U)SPDIF_SIS_TXUNOV_SHIFT (19U)SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)SPDIF_SIS_LOCK_MASK (0x100000U)SPDIF_SIS_LOCK_SHIFT (20U)SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)SPDIF_SRL_RXDATALEFT_SHIFT (0U)SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)SPDIF_SRR_RXDATARIGHT_SHIFT (0U)SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)SPDIF_SRU_RXUCHANNEL_SHIFT (0U)SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)“SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)ǓSPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)ȓSPDIF_STL_TXDATALEFT_SHIFT (0U)ɓSPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)ΓSPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)ϓSPDIF_STR_TXDATARIGHT_SHIFT (0U)ГSPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)ՓSPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)֓SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)דSPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)ܓSPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)ݓSPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)ޓSPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)SPDIF_SRFM_FREQMEAS_SHIFT (0U)SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)SPDIF_STC_TXCLK_DF_MASK (0x7FU)SPDIF_STC_TXCLK_DF_SHIFT (0U)SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)SPDIF_STC_SYSCLK_DF_SHIFT (11U)SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)SPDIF_BASE (0x40380000u)SPDIF ((SPDIF_Type *)SPDIF_BASE)SPDIF_BASE_ADDRS { SPDIF_BASE }SPDIF_BASE_PTRS { SPDIF }SPDIF_IRQS { SPDIF_IRQn }SRC_SCR_LOCKUP_RST_MASK (0x10U)SRC_SCR_LOCKUP_RST_SHIFT (4U)SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK)SRC_SCR_MASK_WDOG_RST_MASK (0x780U)SRC_SCR_MASK_WDOG_RST_SHIFT (7U)SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)SRC_SCR_CORE0_RST_MASK (0x2000U)SRC_SCR_CORE0_RST_SHIFT (13U)SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)SRC_SCR_CORE0_DBG_RST_SHIFT (17U)SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)ÔSRC_SBMR1_BOOT_CFG1_MASK (0xFFU)ĔSRC_SBMR1_BOOT_CFG1_SHIFT (0U)ŔSRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)ƔSRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)ǔSRC_SBMR1_BOOT_CFG2_SHIFT (8U)ȔSRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)ɔSRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)ʔSRC_SBMR1_BOOT_CFG3_SHIFT (16U)˔SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)̔SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)͔SRC_SBMR1_BOOT_CFG4_SHIFT (24U)ΔSRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)ӔSRC_SRSR_IPP_RESET_B_MASK (0x1U)ԔSRC_SRSR_IPP_RESET_B_SHIFT (0U)ՔSRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)֔SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)הSRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)ؔSRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)ٔSRC_SRSR_CSU_RESET_B_MASK (0x4U)ڔSRC_SRSR_CSU_RESET_B_SHIFT (2U)۔SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)ܔSRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)ݔSRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)ޔSRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)ߔSRC_SRSR_WDOG_RST_B_MASK (0x10U)SRC_SRSR_WDOG_RST_B_SHIFT (4U)SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)SRC_SRSR_JTAG_RST_B_MASK (0x20U)SRC_SRSR_JTAG_RST_B_SHIFT (5U)SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)SRC_SRSR_JTAG_SW_RST_MASK (0x40U)SRC_SRSR_JTAG_SW_RST_SHIFT (6U)SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)SRC_SRSR_WDOG3_RST_B_MASK (0x80U)SRC_SRSR_WDOG3_RST_B_SHIFT (7U)SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)SRC_SBMR2_SEC_CONFIG_MASK (0x3U)SRC_SBMR2_SEC_CONFIG_SHIFT (0U)SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)SRC_SBMR2_BMOD_MASK (0x3000000U)SRC_SBMR2_BMOD_SHIFT (24U)SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)SRC_GPR_COUNT (10U)SRC_BASE (0x400F8000u)SRC ((SRC_Type *)SRC_BASE)SRC_BASE_ADDRS { SRC_BASE }SRC_BASE_PTRS { SRC }SRC_IRQS { SRC_IRQn }SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASKSRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFTSRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASKSRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFTSRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASKSRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFTSRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASKSRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFTSRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASKSRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFTSRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)SRC_SRSR_W1C_BITS_MASK (SRC_SRSR_WDOG3_RST_B_MASK | SRC_SRSR_JTAG_SW_RST_MASK | SRC_SRSR_JTAG_RST_B_MASK | SRC_SRSR_WDOG_RST_B_MASK | SRC_SRSR_IPP_USER_RESET_B_MASK | SRC_SRSR_CSU_RESET_B_MASK | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK | SRC_SRSR_IPP_RESET_B_MASK)TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)ŖTEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)ƖTEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)ǖTEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)̖TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)͖TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)ΖTEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)ϖTEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)ЖTEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)іTEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)֖TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)זTEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)ؖTEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)ٖTEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)ږTEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)ۖTEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)TEMPMON_BASE (0x400D8000u)TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)TEMPMON_BASE_ADDRS { TEMPMON_BASE }TEMPMON_BASE_PTRS { TEMPMON }TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)TMR_COMP1_COMPARISON_1_SHIFT (0U)TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)TMR_COMP1_COUNT (4U)TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)TMR_COMP2_COMPARISON_2_SHIFT (0U)TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)TMR_COMP2_COUNT (4U)ėTMR_CAPT_CAPTURE_MASK (0xFFFFU)ŗTMR_CAPT_CAPTURE_SHIFT (0U)ƗTMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)ʗTMR_CAPT_COUNT (4U)ΗTMR_LOAD_LOAD_MASK (0xFFFFU)ϗTMR_LOAD_LOAD_SHIFT (0U)ЗTMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)ԗTMR_LOAD_COUNT (4U)ؗTMR_HOLD_HOLD_MASK (0xFFFFU)ٗTMR_HOLD_HOLD_SHIFT (0U)ڗTMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)ޗTMR_HOLD_COUNT (4U)TMR_CNTR_COUNTER_MASK (0xFFFFU)TMR_CNTR_COUNTER_SHIFT (0U)TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)TMR_CNTR_COUNT (4U)TMR_CTRL_OUTMODE_MASK (0x7U)TMR_CTRL_OUTMODE_SHIFT (0U)TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)TMR_CTRL_COINIT_MASK (0x8U)TMR_CTRL_COINIT_SHIFT (3U)TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)TMR_CTRL_DIR_MASK (0x10U)TMR_CTRL_DIR_SHIFT (4U)TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)TMR_CTRL_LENGTH_MASK (0x20U)TMR_CTRL_LENGTH_SHIFT (5U)TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)TMR_CTRL_ONCE_MASK (0x40U)TMR_CTRL_ONCE_SHIFT (6U)TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)TMR_CTRL_SCS_MASK (0x180U)TMR_CTRL_SCS_SHIFT (7U)TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)TMR_CTRL_PCS_MASK (0x1E00U)TMR_CTRL_PCS_SHIFT (9U)TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)TMR_CTRL_CM_MASK (0xE000U)TMR_CTRL_CM_SHIFT (13U)TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)TMR_CTRL_COUNT (4U)TMR_SCTRL_OEN_MASK (0x1U)TMR_SCTRL_OEN_SHIFT (0U)TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)TMR_SCTRL_OPS_MASK (0x2U)TMR_SCTRL_OPS_SHIFT (1U)TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)TMR_SCTRL_FORCE_MASK (0x4U)TMR_SCTRL_FORCE_SHIFT (2U)TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)TMR_SCTRL_VAL_MASK (0x8U)TMR_SCTRL_VAL_SHIFT (3U)TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)TMR_SCTRL_EEOF_MASK (0x10U)TMR_SCTRL_EEOF_SHIFT (4U)TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)TMR_SCTRL_MSTR_MASK (0x20U)TMR_SCTRL_MSTR_SHIFT (5U)TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)TMR_SCTRL_INPUT_MASK (0x100U)TMR_SCTRL_INPUT_SHIFT (8U)TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)TMR_SCTRL_IPS_MASK (0x200U)TMR_SCTRL_IPS_SHIFT (9U)TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)TMR_SCTRL_IEFIE_MASK (0x400U)TMR_SCTRL_IEFIE_SHIFT (10U)TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)TMR_SCTRL_IEF_MASK (0x800U)TMR_SCTRL_IEF_SHIFT (11U)TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)TMR_SCTRL_TOFIE_MASK (0x1000U)TMR_SCTRL_TOFIE_SHIFT (12U)TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)TMR_SCTRL_TOF_MASK (0x2000U)TMR_SCTRL_TOF_SHIFT (13U)TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)TMR_SCTRL_TCFIE_MASK (0x4000U)TMR_SCTRL_TCFIE_SHIFT (14U)TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)TMR_SCTRL_TCF_MASK (0x8000U)TMR_SCTRL_TCF_SHIFT (15U)TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)TMR_SCTRL_COUNT (4U)TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)ŘTMR_CMPLD1_COUNT (4U)ɘTMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)ʘTMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)˘TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)ϘTMR_CMPLD2_COUNT (4U)ӘTMR_CSCTRL_CL1_MASK (0x3U)ԘTMR_CSCTRL_CL1_SHIFT (0U)՘TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)֘TMR_CSCTRL_CL2_MASK (0xCU)טTMR_CSCTRL_CL2_SHIFT (2U)ؘTMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)٘TMR_CSCTRL_TCF1_MASK (0x10U)ژTMR_CSCTRL_TCF1_SHIFT (4U)ۘTMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)ܘTMR_CSCTRL_TCF2_MASK (0x20U)ݘTMR_CSCTRL_TCF2_SHIFT (5U)ޘTMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)ߘTMR_CSCTRL_TCF1EN_MASK (0x40U)TMR_CSCTRL_TCF1EN_SHIFT (6U)TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)TMR_CSCTRL_TCF2EN_MASK (0x80U)TMR_CSCTRL_TCF2EN_SHIFT (7U)TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)TMR_CSCTRL_UP_MASK (0x200U)TMR_CSCTRL_UP_SHIFT (9U)TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)TMR_CSCTRL_TCI_MASK (0x400U)TMR_CSCTRL_TCI_SHIFT (10U)TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)TMR_CSCTRL_ROC_MASK (0x800U)TMR_CSCTRL_ROC_SHIFT (11U)TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)TMR_CSCTRL_ALT_LOAD_SHIFT (12U)TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)TMR_CSCTRL_FAULT_MASK (0x2000U)TMR_CSCTRL_FAULT_SHIFT (13U)TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)TMR_CSCTRL_DBG_EN_MASK (0xC000U)TMR_CSCTRL_DBG_EN_SHIFT (14U)TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)TMR_CSCTRL_COUNT (4U)TMR_FILT_FILT_PER_MASK (0xFFU)TMR_FILT_FILT_PER_SHIFT (0U)TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)TMR_FILT_FILT_CNT_MASK (0x700U)TMR_FILT_FILT_CNT_SHIFT (8U)TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)TMR_FILT_COUNT (4U)TMR_DMA_IEFDE_MASK (0x1U)TMR_DMA_IEFDE_SHIFT (0U)TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)TMR_DMA_CMPLD1DE_MASK (0x2U)TMR_DMA_CMPLD1DE_SHIFT (1U)TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)TMR_DMA_CMPLD2DE_MASK (0x4U)TMR_DMA_CMPLD2DE_SHIFT (2U)TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)TMR_DMA_COUNT (4U)TMR_ENBL_ENBL_MASK (0xFU)TMR_ENBL_ENBL_SHIFT (0U)TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)TMR_ENBL_COUNT (4U)TMR1_BASE (0x401DC000u)TMR1 ((TMR_Type *)TMR1_BASE)TMR2_BASE (0x401E0000u)TMR2 ((TMR_Type *)TMR2_BASE)TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE }TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2 }TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn }TRNG_MCTL_SAMP_MODE_MASK (0x3U)TRNG_MCTL_SAMP_MODE_SHIFT (0U)TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)TRNG_MCTL_OSC_DIV_MASK (0xCU)TRNG_MCTL_OSC_DIV_SHIFT (2U)TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)TRNG_MCTL_UNUSED4_MASK (0x10U)TRNG_MCTL_UNUSED4_SHIFT (4U)TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)TRNG_MCTL_TRNG_ACC_MASK (0x20U)TRNG_MCTL_TRNG_ACC_SHIFT (5U)TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)TRNG_MCTL_RST_DEF_MASK (0x40U)TRNG_MCTL_RST_DEF_SHIFT (6U)TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)TRNG_MCTL_FOR_SCLK_MASK (0x80U)TRNG_MCTL_FOR_SCLK_SHIFT (7U)TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)TRNG_MCTL_FCT_FAIL_MASK (0x100U)TRNG_MCTL_FCT_FAIL_SHIFT (8U)TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)TRNG_MCTL_FCT_VAL_MASK (0x200U)TRNG_MCTL_FCT_VAL_SHIFT (9U)TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)TRNG_MCTL_ENT_VAL_MASK (0x400U)TRNG_MCTL_ENT_VAL_SHIFT (10U)TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)TRNG_MCTL_TST_OUT_MASK (0x800U)TRNG_MCTL_TST_OUT_SHIFT (11U)TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)TRNG_MCTL_ERR_MASK (0x1000U)TRNG_MCTL_ERR_SHIFT (12U)TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)TRNG_MCTL_TSTOP_OK_MASK (0x2000U)TRNG_MCTL_TSTOP_OK_SHIFT (13U)TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)TRNG_MCTL_LRUN_CONT_MASK (0x4000U)TRNG_MCTL_LRUN_CONT_SHIFT (14U)TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)TRNG_MCTL_PRGM_MASK (0x10000U)TRNG_MCTL_PRGM_SHIFT (16U)TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)šTRNG_SCMISC_LRUN_MAX_MASK (0xFFU)ÚTRNG_SCMISC_LRUN_MAX_SHIFT (0U)ĚTRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)ŚTRNG_SCMISC_RTY_CT_MASK (0xF0000U)ƚTRNG_SCMISC_RTY_CT_SHIFT (16U)ǚTRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)̚TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)͚TRNG_PKRRNG_PKR_RNG_SHIFT (0U)ΚTRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)ӚTRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)ԚTRNG_PKRMAX_PKR_MAX_SHIFT (0U)՚TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)ښTRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)ۚTRNG_PKRSQ_PKR_SQ_SHIFT (0U)ܚTRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)TRNG_SDCTL_ENT_DLY_SHIFT (16U)TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)TRNG_SBLIM_SB_LIM_MASK (0x3FFU)TRNG_SBLIM_SB_LIM_SHIFT (0U)TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)TRNG_TOTSAM_TOT_SAM_SHIFT (0U)TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)TRNG_FRQCNT_FRQ_CT_SHIFT (0U)TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)TRNG_SCMC_MONO_CT_MASK (0xFFFFU)TRNG_SCMC_MONO_CT_SHIFT (0U)TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)TRNG_SCML_MONO_MAX_MASK (0xFFFFU)TRNG_SCML_MONO_MAX_SHIFT (0U)TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)TRNG_SCML_MONO_RNG_SHIFT (16U)TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)TRNG_SCR1C_R1_0_CT_SHIFT (0U)TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)TRNG_SCR1C_R1_1_CT_SHIFT (16U)TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)TRNG_SCR1L_RUN1_MAX_SHIFT (0U)TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)TRNG_SCR1L_RUN1_RNG_SHIFT (16U)TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)TRNG_SCR2C_R2_0_CT_SHIFT (0U)TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)TRNG_SCR2C_R2_1_CT_SHIFT (16U)TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)TRNG_SCR2L_RUN2_MAX_SHIFT (0U)TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)TRNG_SCR2L_RUN2_RNG_SHIFT (16U)›TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)ǛTRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)țTRNG_SCR3C_R3_0_CT_SHIFT (0U)ɛTRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)ʛTRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)˛TRNG_SCR3C_R3_1_CT_SHIFT (16U)̛TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)ћTRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)қTRNG_SCR3L_RUN3_MAX_SHIFT (0U)ӛTRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)ԛTRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)՛TRNG_SCR3L_RUN3_RNG_SHIFT (16U)֛TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)ۛTRNG_SCR4C_R4_0_CT_MASK (0xFFFU)ܛTRNG_SCR4C_R4_0_CT_SHIFT (0U)ݛTRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)ޛTRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)ߛTRNG_SCR4C_R4_1_CT_SHIFT (16U)TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)TRNG_SCR4L_RUN4_MAX_SHIFT (0U)TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)TRNG_SCR4L_RUN4_RNG_SHIFT (16U)TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)TRNG_SCR5C_R5_0_CT_SHIFT (0U)TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)TRNG_SCR5C_R5_1_CT_SHIFT (16U)TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)TRNG_SCR5L_RUN5_MAX_SHIFT (0U)TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)TRNG_SCR5L_RUN5_RNG_SHIFT (16U)TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)TRNG_STATUS_TF1BR0_MASK (0x1U)TRNG_STATUS_TF1BR0_SHIFT (0U)TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)TRNG_STATUS_TF1BR1_MASK (0x2U)TRNG_STATUS_TF1BR1_SHIFT (1U)TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)TRNG_STATUS_TF2BR0_MASK (0x4U)TRNG_STATUS_TF2BR0_SHIFT (2U)TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)TRNG_STATUS_TF2BR1_MASK (0x8U)TRNG_STATUS_TF2BR1_SHIFT (3U)TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)TRNG_STATUS_TF3BR0_MASK (0x10U)TRNG_STATUS_TF3BR0_SHIFT (4U)TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)TRNG_STATUS_TF3BR1_MASK (0x20U)TRNG_STATUS_TF3BR1_SHIFT (5U)TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)TRNG_STATUS_TF4BR0_MASK (0x40U)TRNG_STATUS_TF4BR0_SHIFT (6U)TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)TRNG_STATUS_TF4BR1_MASK (0x80U)TRNG_STATUS_TF4BR1_SHIFT (7U)TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)TRNG_STATUS_TF5BR0_MASK (0x100U)TRNG_STATUS_TF5BR0_SHIFT (8U)TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)TRNG_STATUS_TF5BR1_MASK (0x200U)TRNG_STATUS_TF5BR1_SHIFT (9U)TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)TRNG_STATUS_TF6PBR0_MASK (0x400U)TRNG_STATUS_TF6PBR0_SHIFT (10U)TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)TRNG_STATUS_TF6PBR1_MASK (0x800U)TRNG_STATUS_TF6PBR1_SHIFT (11U)TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)TRNG_STATUS_TFSB_MASK (0x1000U)TRNG_STATUS_TFSB_SHIFT (12U)TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)TRNG_STATUS_TFLR_MASK (0x2000U)TRNG_STATUS_TFLR_SHIFT (13U)TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)TRNG_STATUS_TFP_MASK (0x4000U)œTRNG_STATUS_TFP_SHIFT (14U)ÜTRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)ĜTRNG_STATUS_TFMB_MASK (0x8000U)ŜTRNG_STATUS_TFMB_SHIFT (15U)ƜTRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)ǜTRNG_STATUS_RETRY_CT_MASK (0xF0000U)ȜTRNG_STATUS_RETRY_CT_SHIFT (16U)ɜTRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)ΜTRNG_ENT_ENT_MASK (0xFFFFFFFFU)ϜTRNG_ENT_ENT_SHIFT (0U)МTRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)ԜTRNG_ENT_COUNT (16U)؜TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)ٜTRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)ڜTRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)ۜTRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)ܜTRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)ݜTRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)TRNG_SEC_CFG_UNUSED0_MASK (0x1U)TRNG_SEC_CFG_UNUSED0_SHIFT (0U)TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)TRNG_SEC_CFG_UNUSED2_MASK (0x4U)TRNG_SEC_CFG_UNUSED2_SHIFT (2U)TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)TRNG_INT_CTRL_HW_ERR_MASK (0x1U)TRNG_INT_CTRL_HW_ERR_SHIFT (0U)TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)TRNG_INT_CTRL_UNUSED_SHIFT (3U)TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)ŝTRNG_INT_MASK_HW_ERR_MASK (0x1U)ƝTRNG_INT_MASK_HW_ERR_SHIFT (0U)ǝTRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)ȝTRNG_INT_MASK_ENT_VAL_MASK (0x2U)ɝTRNG_INT_MASK_ENT_VAL_SHIFT (1U)ʝTRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)˝TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)̝TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)͝TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)ҝTRNG_INT_STATUS_HW_ERR_MASK (0x1U)ӝTRNG_INT_STATUS_HW_ERR_SHIFT (0U)ԝTRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)՝TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)֝TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)םTRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)؝TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)ٝTRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)ڝTRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)ߝTRNG_VID1_MIN_REV_MASK (0xFFU)TRNG_VID1_MIN_REV_SHIFT (0U)TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)TRNG_VID1_MAJ_REV_MASK (0xFF00U)TRNG_VID1_MAJ_REV_SHIFT (8U)TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)TRNG_VID1_IP_ID_MASK (0xFFFF0000U)TRNG_VID1_IP_ID_SHIFT (16U)TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)TRNG_VID2_CONFIG_OPT_MASK (0xFFU)TRNG_VID2_CONFIG_OPT_SHIFT (0U)TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)TRNG_VID2_ECO_REV_MASK (0xFF00U)TRNG_VID2_ECO_REV_SHIFT (8U)TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)TRNG_VID2_INTG_OPT_MASK (0xFF0000U)TRNG_VID2_INTG_OPT_SHIFT (16U)TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)TRNG_VID2_ERA_MASK (0xFF000000U)TRNG_VID2_ERA_SHIFT (24U)TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)TRNG_BASE (0x400CC000u)TRNG ((TRNG_Type *)TRNG_BASE)TRNG_BASE_ADDRS { TRNG_BASE }TRNG_BASE_PTRS { TRNG }TRNG_IRQS { TRNG_IRQn }ߞUSB_ID_ID_MASK (0x3FU)USB_ID_ID_SHIFT (0U)USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)USB_ID_NID_MASK (0x3F00U)USB_ID_NID_SHIFT (8U)USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)USB_ID_REVISION_MASK (0xFF0000U)USB_ID_REVISION_SHIFT (16U)USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)USB_HWGENERAL_PHYW_MASK (0x30U)USB_HWGENERAL_PHYW_SHIFT (4U)USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)USB_HWGENERAL_PHYM_MASK (0x1C0U)USB_HWGENERAL_PHYM_SHIFT (6U)USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)USB_HWGENERAL_SM_MASK (0x600U)USB_HWGENERAL_SM_SHIFT (9U)USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)USB_HWHOST_HC_MASK (0x1U)USB_HWHOST_HC_SHIFT (0U)USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)USB_HWHOST_NPORT_MASK (0xEU)USB_HWHOST_NPORT_SHIFT (1U)USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)USB_HWDEVICE_DC_MASK (0x1U)USB_HWDEVICE_DC_SHIFT (0U)USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)USB_HWDEVICE_DEVEP_MASK (0x3EU)USB_HWDEVICE_DEVEP_SHIFT (1U)USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)USB_HWTXBUF_TXBURST_MASK (0xFFU)USB_HWTXBUF_TXBURST_SHIFT (0U)USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)USB_HWTXBUF_TXCHANADD_SHIFT (16U)USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)USB_HWRXBUF_RXBURST_MASK (0xFFU)USB_HWRXBUF_RXBURST_SHIFT (0U)USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)USB_HWRXBUF_RXADD_MASK (0xFF00U)USB_HWRXBUF_RXADD_SHIFT (8U)USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER0LD_GPTLD_SHIFT (0U)USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER1LD_GPTLD_SHIFT (0U)USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)ŸUSB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)ßUSB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)ğUSB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)şUSB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)ƟUSB_GPTIMER1CTRL_GPTRST_SHIFT (30U)ǟUSB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)ȟUSB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)ɟUSB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)ʟUSB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)ϟUSB_SBUSCFG_AHBBRST_MASK (0x7U)ПUSB_SBUSCFG_AHBBRST_SHIFT (0U)џUSB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)֟USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)ןUSB_CAPLENGTH_CAPLENGTH_SHIFT (0U)؟USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)ݟUSB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)ޟUSB_HCIVERSION_HCIVERSION_SHIFT (0U)ߟUSB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)USB_HCSPARAMS_N_PORTS_MASK (0xFU)USB_HCSPARAMS_N_PORTS_SHIFT (0U)USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)USB_HCSPARAMS_PPC_MASK (0x10U)USB_HCSPARAMS_PPC_SHIFT (4U)USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)USB_HCSPARAMS_N_PCC_MASK (0xF00U)USB_HCSPARAMS_N_PCC_SHIFT (8U)USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)USB_HCSPARAMS_N_CC_MASK (0xF000U)USB_HCSPARAMS_N_CC_SHIFT (12U)USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)USB_HCSPARAMS_PI_MASK (0x10000U)USB_HCSPARAMS_PI_SHIFT (16U)USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)USB_HCSPARAMS_N_PTT_MASK (0xF00000U)USB_HCSPARAMS_N_PTT_SHIFT (20U)USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)USB_HCSPARAMS_N_TT_MASK (0xF000000U)USB_HCSPARAMS_N_TT_SHIFT (24U)USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)USB_HCCPARAMS_ADC_MASK (0x1U)USB_HCCPARAMS_ADC_SHIFT (0U)USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)USB_HCCPARAMS_PFL_MASK (0x2U)USB_HCCPARAMS_PFL_SHIFT (1U)USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)USB_HCCPARAMS_ASP_MASK (0x4U)USB_HCCPARAMS_ASP_SHIFT (2U)USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)USB_HCCPARAMS_IST_MASK (0xF0U)USB_HCCPARAMS_IST_SHIFT (4U)USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)USB_HCCPARAMS_EECP_MASK (0xFF00U)USB_HCCPARAMS_EECP_SHIFT (8U)USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)USB_DCIVERSION_DCIVERSION_SHIFT (0U)USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)USB_DCCPARAMS_DEN_MASK (0x1FU)USB_DCCPARAMS_DEN_SHIFT (0U)USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)USB_DCCPARAMS_DC_MASK (0x80U)USB_DCCPARAMS_DC_SHIFT (7U)USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)USB_DCCPARAMS_HC_MASK (0x100U)USB_DCCPARAMS_HC_SHIFT (8U)USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)USB_USBCMD_RS_MASK (0x1U)USB_USBCMD_RS_SHIFT (0U)USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)USB_USBCMD_RST_MASK (0x2U)USB_USBCMD_RST_SHIFT (1U)USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)USB_USBCMD_FS_1_MASK (0xCU)USB_USBCMD_FS_1_SHIFT (2U)USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)USB_USBCMD_PSE_MASK (0x10U)USB_USBCMD_PSE_SHIFT (4U)USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)USB_USBCMD_ASE_MASK (0x20U)USB_USBCMD_ASE_SHIFT (5U)USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)USB_USBCMD_IAA_MASK (0x40U)USB_USBCMD_IAA_SHIFT (6U)USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)USB_USBCMD_ASP_MASK (0x300U)USB_USBCMD_ASP_SHIFT (8U)USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)USB_USBCMD_ASPE_MASK (0x800U)USB_USBCMD_ASPE_SHIFT (11U)USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)USB_USBCMD_ATDTW_MASK (0x1000U)USB_USBCMD_ATDTW_SHIFT (12U)USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)USB_USBCMD_SUTW_MASK (0x2000U)USB_USBCMD_SUTW_SHIFT (13U)USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) USB_USBCMD_FS_2_MASK (0x8000U)àUSB_USBCMD_FS_2_SHIFT (15U)ĠUSB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)ŠUSB_USBCMD_ITC_MASK (0xFF0000U)ƠUSB_USBCMD_ITC_SHIFT (16U)ǠUSB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)̠USB_USBSTS_UI_MASK (0x1U)͠USB_USBSTS_UI_SHIFT (0U)ΠUSB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)ϠUSB_USBSTS_UEI_MASK (0x2U)РUSB_USBSTS_UEI_SHIFT (1U)ѠUSB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)ҠUSB_USBSTS_PCI_MASK (0x4U)ӠUSB_USBSTS_PCI_SHIFT (2U)ԠUSB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)ՠUSB_USBSTS_FRI_MASK (0x8U)֠USB_USBSTS_FRI_SHIFT (3U)נUSB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)ؠUSB_USBSTS_SEI_MASK (0x10U)٠USB_USBSTS_SEI_SHIFT (4U)ڠUSB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)۠USB_USBSTS_AAI_MASK (0x20U)ܠUSB_USBSTS_AAI_SHIFT (5U)ݠUSB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)ޠUSB_USBSTS_URI_MASK (0x40U)ߠUSB_USBSTS_URI_SHIFT (6U)USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)USB_USBSTS_SRI_MASK (0x80U)USB_USBSTS_SRI_SHIFT (7U)USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)USB_USBSTS_SLI_MASK (0x100U)USB_USBSTS_SLI_SHIFT (8U)USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)USB_USBSTS_ULPII_MASK (0x400U)USB_USBSTS_ULPII_SHIFT (10U)USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)USB_USBSTS_HCH_MASK (0x1000U)USB_USBSTS_HCH_SHIFT (12U)USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)USB_USBSTS_RCL_MASK (0x2000U)USB_USBSTS_RCL_SHIFT (13U)USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)USB_USBSTS_PS_MASK (0x4000U)USB_USBSTS_PS_SHIFT (14U)USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)USB_USBSTS_AS_MASK (0x8000U)USB_USBSTS_AS_SHIFT (15U)USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)USB_USBSTS_NAKI_MASK (0x10000U)USB_USBSTS_NAKI_SHIFT (16U)USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)USB_USBSTS_TI0_MASK (0x1000000U)USB_USBSTS_TI0_SHIFT (24U)USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)USB_USBSTS_TI1_MASK (0x2000000U)USB_USBSTS_TI1_SHIFT (25U)USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)USB_USBINTR_UE_MASK (0x1U)USB_USBINTR_UE_SHIFT (0U)USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)USB_USBINTR_UEE_MASK (0x2U)USB_USBINTR_UEE_SHIFT (1U)USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)USB_USBINTR_PCE_MASK (0x4U)USB_USBINTR_PCE_SHIFT (2U)USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)USB_USBINTR_FRE_MASK (0x8U)USB_USBINTR_FRE_SHIFT (3U)USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)USB_USBINTR_SEE_MASK (0x10U)USB_USBINTR_SEE_SHIFT (4U)USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)USB_USBINTR_AAE_MASK (0x20U)USB_USBINTR_AAE_SHIFT (5U)USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)USB_USBINTR_URE_MASK (0x40U)USB_USBINTR_URE_SHIFT (6U)USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)USB_USBINTR_SRE_MASK (0x80U)USB_USBINTR_SRE_SHIFT (7U)USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)USB_USBINTR_SLE_MASK (0x100U)USB_USBINTR_SLE_SHIFT (8U)USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)USB_USBINTR_ULPIE_MASK (0x400U)USB_USBINTR_ULPIE_SHIFT (10U)USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)USB_USBINTR_NAKE_MASK (0x10000U)USB_USBINTR_NAKE_SHIFT (16U)USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)USB_USBINTR_UAIE_MASK (0x40000U)USB_USBINTR_UAIE_SHIFT (18U)USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)USB_USBINTR_UPIE_MASK (0x80000U)USB_USBINTR_UPIE_SHIFT (19U)USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)USB_USBINTR_TIE0_MASK (0x1000000U)USB_USBINTR_TIE0_SHIFT (24U)USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)USB_USBINTR_TIE1_MASK (0x2000000U)USB_USBINTR_TIE1_SHIFT (25U)USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)USB_FRINDEX_FRINDEX_MASK (0x3FFFU)USB_FRINDEX_FRINDEX_SHIFT (0U)USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)USB_DEVICEADDR_USBADRA_MASK (0x1000000U)USB_DEVICEADDR_USBADRA_SHIFT (24U)USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)USB_DEVICEADDR_USBADR_MASK (0xFE000000U)USB_DEVICEADDR_USBADR_SHIFT (25U)USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)šUSB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)ơUSB_PERIODICLISTBASE_BASEADR_SHIFT (12U)ǡUSB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)̡USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)͡USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)ΡUSB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)ӡUSB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)ԡUSB_ENDPTLISTADDR_EPBASE_SHIFT (11U)աUSB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)ڡUSB_BURSTSIZE_RXPBURST_MASK (0xFFU)ۡUSB_BURSTSIZE_RXPBURST_SHIFT (0U)ܡUSB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)ݡUSB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)ޡUSB_BURSTSIZE_TXPBURST_SHIFT (8U)ߡUSB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)USB_ENDPTNAK_EPRN_MASK (0xFFU)USB_ENDPTNAK_EPRN_SHIFT (0U)USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)USB_ENDPTNAK_EPTN_MASK (0xFF0000U)USB_ENDPTNAK_EPTN_SHIFT (16U)USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)USB_ENDPTNAKEN_EPRNE_SHIFT (0U)USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)USB_ENDPTNAKEN_EPTNE_SHIFT (16U)USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)USB_CONFIGFLAG_CF_MASK (0x1U)USB_CONFIGFLAG_CF_SHIFT (0U)USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)USB_PORTSC1_CCS_MASK (0x1U)USB_PORTSC1_CCS_SHIFT (0U)USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)USB_PORTSC1_CSC_MASK (0x2U)USB_PORTSC1_CSC_SHIFT (1U)USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)USB_PORTSC1_PE_MASK (0x4U)USB_PORTSC1_PE_SHIFT (2U)USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)USB_PORTSC1_PEC_MASK (0x8U)USB_PORTSC1_PEC_SHIFT (3U)USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)USB_PORTSC1_OCA_MASK (0x10U)USB_PORTSC1_OCA_SHIFT (4U)USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)USB_PORTSC1_OCC_MASK (0x20U)USB_PORTSC1_OCC_SHIFT (5U)USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)USB_PORTSC1_FPR_MASK (0x40U)USB_PORTSC1_FPR_SHIFT (6U)USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)USB_PORTSC1_SUSP_MASK (0x80U)USB_PORTSC1_SUSP_SHIFT (7U)USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)USB_PORTSC1_PR_MASK (0x100U)USB_PORTSC1_PR_SHIFT (8U)USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)USB_PORTSC1_HSP_MASK (0x200U)USB_PORTSC1_HSP_SHIFT (9U)USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)USB_PORTSC1_LS_MASK (0xC00U)USB_PORTSC1_LS_SHIFT (10U)USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)USB_PORTSC1_PP_MASK (0x1000U)USB_PORTSC1_PP_SHIFT (12U)USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)USB_PORTSC1_PO_MASK (0x2000U)USB_PORTSC1_PO_SHIFT (13U)USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)USB_PORTSC1_PIC_MASK (0xC000U)USB_PORTSC1_PIC_SHIFT (14U)USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)USB_PORTSC1_PTC_MASK (0xF0000U)USB_PORTSC1_PTC_SHIFT (16U)USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)USB_PORTSC1_WKCN_MASK (0x100000U)USB_PORTSC1_WKCN_SHIFT (20U)USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)USB_PORTSC1_WKDC_MASK (0x200000U)USB_PORTSC1_WKDC_SHIFT (21U)USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)USB_PORTSC1_WKOC_MASK (0x400000U)USB_PORTSC1_WKOC_SHIFT (22U)USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)¢USB_PORTSC1_PHCD_MASK (0x800000U)âUSB_PORTSC1_PHCD_SHIFT (23U)ĢUSB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)ŢUSB_PORTSC1_PFSC_MASK (0x1000000U)ƢUSB_PORTSC1_PFSC_SHIFT (24U)ǢUSB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)ȢUSB_PORTSC1_PTS_2_MASK (0x2000000U)ɢUSB_PORTSC1_PTS_2_SHIFT (25U)ʢUSB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)ˢUSB_PORTSC1_PSPD_MASK (0xC000000U)̢USB_PORTSC1_PSPD_SHIFT (26U)͢USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)΢USB_PORTSC1_PTW_MASK (0x10000000U)ϢUSB_PORTSC1_PTW_SHIFT (28U)ТUSB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)ѢUSB_PORTSC1_STS_MASK (0x20000000U)ҢUSB_PORTSC1_STS_SHIFT (29U)ӢUSB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)ԢUSB_PORTSC1_PTS_1_MASK (0xC0000000U)բUSB_PORTSC1_PTS_1_SHIFT (30U)֢USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)ۢUSB_OTGSC_VD_MASK (0x1U)ܢUSB_OTGSC_VD_SHIFT (0U)ݢUSB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)ޢUSB_OTGSC_VC_MASK (0x2U)ߢUSB_OTGSC_VC_SHIFT (1U)USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)USB_OTGSC_OT_MASK (0x8U)USB_OTGSC_OT_SHIFT (3U)USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)USB_OTGSC_DP_MASK (0x10U)USB_OTGSC_DP_SHIFT (4U)USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)USB_OTGSC_IDPU_MASK (0x20U)USB_OTGSC_IDPU_SHIFT (5U)USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)USB_OTGSC_ID_MASK (0x100U)USB_OTGSC_ID_SHIFT (8U)USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)USB_OTGSC_AVV_MASK (0x200U)USB_OTGSC_AVV_SHIFT (9U)USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)USB_OTGSC_ASV_MASK (0x400U)USB_OTGSC_ASV_SHIFT (10U)USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)USB_OTGSC_BSV_MASK (0x800U)USB_OTGSC_BSV_SHIFT (11U)USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)USB_OTGSC_BSE_MASK (0x1000U)USB_OTGSC_BSE_SHIFT (12U)USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)USB_OTGSC_TOG_1MS_MASK (0x2000U)USB_OTGSC_TOG_1MS_SHIFT (13U)USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)USB_OTGSC_DPS_MASK (0x4000U)USB_OTGSC_DPS_SHIFT (14U)USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)USB_OTGSC_IDIS_MASK (0x10000U)USB_OTGSC_IDIS_SHIFT (16U)USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)USB_OTGSC_AVVIS_MASK (0x20000U)USB_OTGSC_AVVIS_SHIFT (17U)USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)USB_OTGSC_ASVIS_MASK (0x40000U)USB_OTGSC_ASVIS_SHIFT (18U)USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)USB_OTGSC_BSVIS_MASK (0x80000U)USB_OTGSC_BSVIS_SHIFT (19U)USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)USB_OTGSC_BSEIS_MASK (0x100000U)USB_OTGSC_BSEIS_SHIFT (20U)USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)USB_OTGSC_STATUS_1MS_MASK (0x200000U)USB_OTGSC_STATUS_1MS_SHIFT (21U)USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)USB_OTGSC_DPIS_MASK (0x400000U)USB_OTGSC_DPIS_SHIFT (22U)USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)USB_OTGSC_IDIE_MASK (0x1000000U)USB_OTGSC_IDIE_SHIFT (24U)USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)USB_OTGSC_AVVIE_MASK (0x2000000U)USB_OTGSC_AVVIE_SHIFT (25U)USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)USB_OTGSC_ASVIE_MASK (0x4000000U)USB_OTGSC_ASVIE_SHIFT (26U)USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)USB_OTGSC_BSVIE_MASK (0x8000000U)USB_OTGSC_BSVIE_SHIFT (27U)USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)USB_OTGSC_BSEIE_MASK (0x10000000U)USB_OTGSC_BSEIE_SHIFT (28U)USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)USB_OTGSC_EN_1MS_MASK (0x20000000U)USB_OTGSC_EN_1MS_SHIFT (29U)USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)USB_OTGSC_DPIE_MASK (0x40000000U)USB_OTGSC_DPIE_SHIFT (30U)USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)USB_USBMODE_CM_MASK (0x3U)USB_USBMODE_CM_SHIFT (0U)USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)USB_USBMODE_ES_MASK (0x4U)USB_USBMODE_ES_SHIFT (2U)USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)USB_USBMODE_SLOM_MASK (0x8U)USB_USBMODE_SLOM_SHIFT (3U)USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)USB_USBMODE_SDIS_MASK (0x10U)USB_USBMODE_SDIS_SHIFT (4U)USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)ģUSB_ENDPTPRIME_PERB_MASK (0xFFU)ţUSB_ENDPTPRIME_PERB_SHIFT (0U)ƣUSB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)ǣUSB_ENDPTPRIME_PETB_MASK (0xFF0000U)ȣUSB_ENDPTPRIME_PETB_SHIFT (16U)ɣUSB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)ΣUSB_ENDPTFLUSH_FERB_MASK (0xFFU)ϣUSB_ENDPTFLUSH_FERB_SHIFT (0U)УUSB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)ѣUSB_ENDPTFLUSH_FETB_MASK (0xFF0000U)ңUSB_ENDPTFLUSH_FETB_SHIFT (16U)ӣUSB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)أUSB_ENDPTSTAT_ERBR_MASK (0xFFU)٣USB_ENDPTSTAT_ERBR_SHIFT (0U)ڣUSB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)ۣUSB_ENDPTSTAT_ETBR_MASK (0xFF0000U)ܣUSB_ENDPTSTAT_ETBR_SHIFT (16U)ݣUSB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)USB_ENDPTCTRL0_RXS_MASK (0x1U)USB_ENDPTCTRL0_RXS_SHIFT (0U)USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)USB_ENDPTCTRL0_RXT_MASK (0xCU)USB_ENDPTCTRL0_RXT_SHIFT (2U)USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)USB_ENDPTCTRL0_RXE_MASK (0x80U)USB_ENDPTCTRL0_RXE_SHIFT (7U)USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)USB_ENDPTCTRL0_TXS_MASK (0x10000U)USB_ENDPTCTRL0_TXS_SHIFT (16U)USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)USB_ENDPTCTRL0_TXT_MASK (0xC0000U)USB_ENDPTCTRL0_TXT_SHIFT (18U)USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)USB_ENDPTCTRL0_TXE_MASK (0x800000U)USB_ENDPTCTRL0_TXE_SHIFT (23U)USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)USB_ENDPTCTRL_RXS_MASK (0x1U)USB_ENDPTCTRL_RXS_SHIFT (0U)USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)USB_ENDPTCTRL_RXD_MASK (0x2U)USB_ENDPTCTRL_RXD_SHIFT (1U)USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)USB_ENDPTCTRL_RXT_MASK (0xCU)USB_ENDPTCTRL_RXT_SHIFT (2U)USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)USB_ENDPTCTRL_RXI_MASK (0x20U)USB_ENDPTCTRL_RXI_SHIFT (5U)USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)USB_ENDPTCTRL_RXR_MASK (0x40U)USB_ENDPTCTRL_RXR_SHIFT (6U)USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)USB_ENDPTCTRL_RXE_MASK (0x80U)USB_ENDPTCTRL_RXE_SHIFT (7U)USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)USB_ENDPTCTRL_TXS_MASK (0x10000U)USB_ENDPTCTRL_TXS_SHIFT (16U)USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)USB_ENDPTCTRL_TXD_MASK (0x20000U)USB_ENDPTCTRL_TXD_SHIFT (17U)USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)USB_ENDPTCTRL_TXT_MASK (0xC0000U)USB_ENDPTCTRL_TXT_SHIFT (18U)USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)USB_ENDPTCTRL_TXI_MASK (0x200000U)USB_ENDPTCTRL_TXI_SHIFT (21U)USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)USB_ENDPTCTRL_TXR_MASK (0x400000U)USB_ENDPTCTRL_TXR_SHIFT (22U)USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)USB_ENDPTCTRL_TXE_MASK (0x800000U)USB_ENDPTCTRL_TXE_SHIFT (23U)USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)USB_ENDPTCTRL_COUNT (7U)USB_BASE (0x402E0000u)USB ((USB_Type *)USB_BASE)USB_BASE_ADDRS { 0u, USB_BASE }USB_BASE_PTRS { (USB_Type *)0u, USB }USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn }GPTIMER0CTL GPTIMER0CTRLGPTIMER1CTL GPTIMER1CTRLUSB_SBUSCFG SBUSCFGEPLISTADDR ENDPTLISTADDREPSETUPSR ENDPTSETUPSTAT¤EPPRIME ENDPTPRIMEäEPFLUSH ENDPTFLUSHĤEPSR ENDPTSTATŤEPCOMPLETE ENDPTCOMPLETEƤEPCR ENDPTCTRLǤEPCR0 ENDPTCTRL0ȤUSBHS_ID_ID_MASK USB_ID_ID_MASKɤUSBHS_ID_ID_SHIFT USB_ID_ID_SHIFTʤUSBHS_ID_ID(x) USB_ID_ID(x)ˤUSBHS_ID_NID_MASK USB_ID_NID_MASK̤USBHS_ID_NID_SHIFT USB_ID_NID_SHIFTͤUSBHS_ID_NID(x) USB_ID_NID(x)ΤUSBHS_ID_REVISION_MASK USB_ID_REVISION_MASKϤUSBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFTФUSBHS_ID_REVISION(x) USB_ID_REVISION(x)ѤUSBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASKҤUSBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFTӤUSBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)ԤUSBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASKդUSBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT֤USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)פUSBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASKؤUSBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT٤USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)ڤUSBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASKۤUSBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFTܤUSBHS_HWHOST_HC(x) USB_HWHOST_HC(x)ݤUSBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASKޤUSBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFTߤUSBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASKUSBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFTUSBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASKUSBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFTUSBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASKUSBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFTUSBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASKUSBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFTUSBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASKUSBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFTUSBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASKUSBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFTUSBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASKUSBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFTUSBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASKUSBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFTUSBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASKUSBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFTUSBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASKUSBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFTUSBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASKUSBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFTUSBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASKUSBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFTUSBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASKUSBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFTUSBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASKUSBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFTUSBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASKUSBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFTUSBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASKUSBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFTUSBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASKUSBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFTUSBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASKUSBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFTUSBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASKUSBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFTUSBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASKUSBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFTUSBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASKUSBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFTUSBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASKUSBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFTUSBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASKUSBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFTUSBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASKUSBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFTUSBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASKUSBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFTUSBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASKUSBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFTUSBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASKUSBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFTUSBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASKUSBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFTUSBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASKUSBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFTUSBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASKUSBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFTUSBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASKUSBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFTUSBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASKUSBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFTUSBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK¥USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFTåUSBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)ĥUSBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASKťUSBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFTƥUSBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)ǥUSBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASKȥUSBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFTɥUSBHS_USBCMD_RS(x) USB_USBCMD_RS(x)ʥUSBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK˥USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT̥USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)ͥUSBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASKΥUSBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFTϥUSBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)ХUSBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASKѥUSBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFTҥUSBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)ӥUSBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASKԥUSBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFTեUSBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)֥USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASKץUSBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFTإUSBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)٥USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASKڥUSBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFTۥUSBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)ܥUSBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASKݥUSBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFTޥUSBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)ߥUSBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASKUSBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFTUSBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASKUSBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFTUSBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASKUSBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFTUSBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASKUSBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFTUSBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASKUSBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFTUSBHS_USBSTS_UI(x) USB_USBSTS_UI(x)USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASKUSBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFTUSBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASKUSBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFTUSBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASKUSBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFTUSBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASKUSBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFTUSBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASKUSBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFTUSBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASKUSBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFTUSBHS_USBSTS_URI(x) USB_USBSTS_URI(x)USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASKUSBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFTUSBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASKUSBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFTUSBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASKUSBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFTUSBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASKUSBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFTUSBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASKUSBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFTUSBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASKUSBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFTUSBHS_USBSTS_PS(x) USB_USBSTS_PS(x)USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASKUSBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFTUSBHS_USBSTS_AS(x) USB_USBSTS_AS(x)USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASKUSBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFTUSBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASKUSBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFTUSBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASKUSBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFTUSBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASKUSBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFTUSBHS_USBINTR_UE(x) USB_USBINTR_UE(x)USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASKUSBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFTUSBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASKUSBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFTUSBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASKUSBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFTUSBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASKUSBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFTUSBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASKUSBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFTUSBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASKUSBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFTUSBHS_USBINTR_URE(x) USB_USBINTR_URE(x)USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASKUSBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFTUSBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASKUSBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFTUSBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASKUSBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFTUSBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASKUSBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFTUSBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASKUSBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFTUSBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)¦USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASKæUSBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFTĦUSBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)ŦUSBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASKƦUSBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFTǦUSBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)ȦUSBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASKɦUSBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFTʦUSBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)˦USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK̦USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFTͦUSBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)ΦUSBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASKϦUSBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFTЦUSBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)ѦUSBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASKҦUSBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFTӦUSBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)ԦUSBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASKզUSBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT֦USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)צUSBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASKئUSBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT٦USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)ڦUSBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASKۦUSBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFTܦUSBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)ݦUSBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASKަUSBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFTߦUSBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASKUSBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFTUSBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASKUSBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFTUSBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASKUSBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFTUSBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASKUSBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFTUSBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASKUSBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFTUSBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASKUSBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFTUSBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASKUSBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFTUSBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASKUSBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFTUSBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASKUSBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFTUSBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASKUSBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFTUSBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASKUSBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFTUSBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASKUSBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFTUSBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASKUSBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFTUSBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASKUSBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFTUSBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASKUSBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFTUSBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASKUSBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFTUSBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASKUSBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFTUSBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASKUSBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFTUSBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASKUSBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFTUSBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASKUSBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFTUSBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASKUSBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFTUSBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASKUSBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFTUSBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASKUSBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFTUSBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASKUSBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFTUSBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASKUSBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFTUSBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASKUSBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFTUSBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASKUSBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFTUSBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASKUSBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFTUSBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASKUSBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFTUSBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASKUSBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFTUSBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASKUSBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFTUSBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASKUSBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFTUSBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASKUSBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT§USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)çUSBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASKħUSBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFTŧUSBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)ƧUSBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASKǧUSBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFTȧUSBHS_OTGSC_VD(x) USB_OTGSC_VD(x)ɧUSBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASKʧUSBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT˧USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)̧USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASKͧUSBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFTΧUSBHS_OTGSC_OT(x) USB_OTGSC_OT(x)ϧUSBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASKЧUSBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFTѧUSBHS_OTGSC_DP(x) USB_OTGSC_DP(x)ҧUSBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASKӧUSBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFTԧUSBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)էUSBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK֧USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFTקUSBHS_OTGSC_ID(x) USB_OTGSC_ID(x)اUSBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK٧USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFTڧUSBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)ۧUSBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASKܧUSBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFTݧUSBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)ާUSBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASKߧUSBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFTUSBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASKUSBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFTUSBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASKUSBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFTUSBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASKUSBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFTUSBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASKUSBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFTUSBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASKUSBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFTUSBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASKUSBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFTUSBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASKUSBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFTUSBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASKUSBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFTUSBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASKUSBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFTUSBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASKUSBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFTUSBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASKUSBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFTUSBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASKUSBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFTUSBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASKUSBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFTUSBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASKUSBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFTUSBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASKUSBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFTUSBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASKUSBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFTUSBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASKUSBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFTUSBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASKUSBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFTUSBHS_USBMODE_CM(x) USB_USBMODE_CM(x)USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASKUSBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFTUSBHS_USBMODE_ES(x) USB_USBMODE_ES(x)USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASKUSBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFTUSBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASKUSBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFTUSBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASKUSBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFTUSBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASKUSBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFTUSBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASKUSBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFTUSBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASKUSBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFTUSBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASKUSBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFTUSBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASKUSBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFTUSBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASKUSBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFTUSBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASKUSBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFTUSBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASKUSBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFTUSBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASKUSBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFTUSBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASKUSBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFTUSBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK¨USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFTèUSBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)ĨUSBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASKŨUSBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFTƨUSBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)ǨUSBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASKȨUSBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFTɨUSBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)ʨUSBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK˨USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT̨USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)ͨUSBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASKΨUSBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFTϨUSBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)ШUSBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASKѨUSBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFTҨUSBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)ӨUSBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASKԨUSBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFTըUSBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)֨USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASKרUSBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFTبUSBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)٨USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASKڨUSBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFTۨUSBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)ܨUSBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASKݨUSBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFTިUSBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)ߨUSBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASKUSBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFTUSBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASKUSBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFTUSBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASKUSBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFTUSBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASKUSBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFTUSBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASKUSBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFTUSBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASKUSBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFTUSBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNTUSBHS_Type USB_TypeUSBHS_BASE_ADDRS USB_BASEUSBHS_IRQS USB_OTG1_IRQnUSBHS_IRQHandler USB_OTG1_IRQHandlerUSBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)ȩUSBNC_BASE (0x402E0000u)ʩUSBNC ((USBNC_Type *)USBNC_BASE)̩USBNC_BASE_ADDRS { 0u, USBNC_BASE }ΩUSBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC }USBPHY_PWD_RSVD0_MASK (0x3FFU)USBPHY_PWD_RSVD0_SHIFT (0U)USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)USBPHY_PWD_TXPWDFS_MASK (0x400U)USBPHY_PWD_TXPWDFS_SHIFT (10U)USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)USBPHY_PWD_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)USBPHY_PWD_RSVD1_MASK (0x1E000U)USBPHY_PWD_RSVD1_SHIFT (13U)USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)USBPHY_PWD_RXPWDENV_MASK (0x20000U)USBPHY_PWD_RXPWDENV_SHIFT (17U)USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)USBPHY_PWD_RXPWDRX_MASK (0x100000U)USBPHY_PWD_RXPWDRX_SHIFT (20U)USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)USBPHY_PWD_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_RSVD2_SHIFT (21U)USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)USBPHY_PWD_SET_RSVD0_SHIFT (0U)USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)USBPHY_PWD_SET_RSVD1_SHIFT (13U)USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)ªUSBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)êUSBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)ĪUSBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)ŪUSBPHY_PWD_SET_RXPWDRX_SHIFT (20U)ƪUSBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)ǪUSBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)ȪUSBPHY_PWD_SET_RSVD2_SHIFT (21U)ɪUSBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)ΪUSBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)ϪUSBPHY_PWD_CLR_RSVD0_SHIFT (0U)ЪUSBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)ѪUSBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)ҪUSBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)ӪUSBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)ԪUSBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)ժUSBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)֪USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)תUSBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)تUSBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)٪USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)ڪUSBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)۪USBPHY_PWD_CLR_RSVD1_SHIFT (13U)ܪUSBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)ݪUSBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)ުUSBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)ߪUSBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_CLR_RSVD2_SHIFT (21U)USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)USBPHY_PWD_TOG_RSVD0_SHIFT (0U)USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)USBPHY_PWD_TOG_RSVD1_SHIFT (13U)USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_TOG_RSVD2_SHIFT (21U)USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)USBPHY_TX_D_CAL_MASK (0xFU)USBPHY_TX_D_CAL_SHIFT (0U)USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)USBPHY_TX_RSVD0_MASK (0xF0U)USBPHY_TX_RSVD0_SHIFT (4U)USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)USBPHY_TX_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TXCAL45DN_SHIFT (8U)USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)USBPHY_TX_RSVD1_MASK (0xF000U)USBPHY_TX_RSVD1_SHIFT (12U)USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)USBPHY_TX_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TXCAL45DP_SHIFT (16U)USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)USBPHY_TX_RSVD2_MASK (0x3F00000U)USBPHY_TX_RSVD2_SHIFT (20U)USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_RSVD5_MASK (0xE0000000U)USBPHY_TX_RSVD5_SHIFT (29U)USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)USBPHY_TX_SET_D_CAL_MASK (0xFU)USBPHY_TX_SET_D_CAL_SHIFT (0U)USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)USBPHY_TX_SET_RSVD0_MASK (0xF0U)USBPHY_TX_SET_RSVD0_SHIFT (4U)USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)USBPHY_TX_SET_RSVD1_MASK (0xF000U)USBPHY_TX_SET_RSVD1_SHIFT (12U)USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)USBPHY_TX_SET_RSVD2_SHIFT (20U)USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)«USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)ëUSBPHY_TX_SET_RSVD5_MASK (0xE0000000U)īUSBPHY_TX_SET_RSVD5_SHIFT (29U)ūUSBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)ʫUSBPHY_TX_CLR_D_CAL_MASK (0xFU)˫USBPHY_TX_CLR_D_CAL_SHIFT (0U)̫USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)ͫUSBPHY_TX_CLR_RSVD0_MASK (0xF0U)ΫUSBPHY_TX_CLR_RSVD0_SHIFT (4U)ϫUSBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)ЫUSBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)ѫUSBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)ҫUSBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)ӫUSBPHY_TX_CLR_RSVD1_MASK (0xF000U)ԫUSBPHY_TX_CLR_RSVD1_SHIFT (12U)իUSBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)֫USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)׫USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)ثUSBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)٫USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)ګUSBPHY_TX_CLR_RSVD2_SHIFT (20U)۫USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)ܫUSBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)ݫUSBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)ޫUSBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)߫USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)USBPHY_TX_CLR_RSVD5_SHIFT (29U)USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)USBPHY_TX_TOG_D_CAL_MASK (0xFU)USBPHY_TX_TOG_D_CAL_SHIFT (0U)USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)USBPHY_TX_TOG_RSVD0_MASK (0xF0U)USBPHY_TX_TOG_RSVD0_SHIFT (4U)USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)USBPHY_TX_TOG_RSVD1_MASK (0xF000U)USBPHY_TX_TOG_RSVD1_SHIFT (12U)USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)USBPHY_TX_TOG_RSVD2_SHIFT (20U)USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)USBPHY_TX_TOG_RSVD5_SHIFT (29U)USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)USBPHY_RX_ENVADJ_MASK (0x7U)USBPHY_RX_ENVADJ_SHIFT (0U)USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)USBPHY_RX_RSVD0_MASK (0x8U)USBPHY_RX_RSVD0_SHIFT (3U)USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)USBPHY_RX_DISCONADJ_MASK (0x70U)USBPHY_RX_DISCONADJ_SHIFT (4U)USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)USBPHY_RX_RSVD1_MASK (0x3FFF80U)USBPHY_RX_RSVD1_SHIFT (7U)USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)USBPHY_RX_RXDBYPASS_MASK (0x400000U)USBPHY_RX_RXDBYPASS_SHIFT (22U)USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)USBPHY_RX_RSVD2_MASK (0xFF800000U)USBPHY_RX_RSVD2_SHIFT (23U)USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)USBPHY_RX_SET_ENVADJ_MASK (0x7U)USBPHY_RX_SET_ENVADJ_SHIFT (0U)USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)USBPHY_RX_SET_RSVD0_MASK (0x8U)USBPHY_RX_SET_RSVD0_SHIFT (3U)USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)USBPHY_RX_SET_DISCONADJ_MASK (0x70U)USBPHY_RX_SET_DISCONADJ_SHIFT (4U)USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)USBPHY_RX_SET_RSVD1_SHIFT (7U)USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)USBPHY_RX_SET_RSVD2_SHIFT (23U)USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)USBPHY_RX_CLR_ENVADJ_MASK (0x7U)USBPHY_RX_CLR_ENVADJ_SHIFT (0U)USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)USBPHY_RX_CLR_RSVD0_MASK (0x8U)USBPHY_RX_CLR_RSVD0_SHIFT (3U)USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)USBPHY_RX_CLR_RSVD1_SHIFT (7U)USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)USBPHY_RX_CLR_RSVD2_SHIFT (23U)USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)ĬUSBPHY_RX_TOG_ENVADJ_MASK (0x7U)ŬUSBPHY_RX_TOG_ENVADJ_SHIFT (0U)ƬUSBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)ǬUSBPHY_RX_TOG_RSVD0_MASK (0x8U)ȬUSBPHY_RX_TOG_RSVD0_SHIFT (3U)ɬUSBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)ʬUSBPHY_RX_TOG_DISCONADJ_MASK (0x70U)ˬUSBPHY_RX_TOG_DISCONADJ_SHIFT (4U)̬USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)ͬUSBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)άUSBPHY_RX_TOG_RSVD1_SHIFT (7U)ϬUSBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)ЬUSBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)ѬUSBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)ҬUSBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)ӬUSBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)ԬUSBPHY_RX_TOG_RSVD2_SHIFT (23U)լUSBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)ڬUSBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)۬USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)ܬUSBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)ݬUSBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)ެUSBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)߬USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)USBPHY_CTRL_RSVD1_MASK (0x6000000U)USBPHY_CTRL_RSVD1_SHIFT (25U)USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)USBPHY_CTRL_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SFTRST_SHIFT (31U)USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)­USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)íUSBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)ĭUSBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)ŭUSBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)ƭUSBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)ǭUSBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)ȭUSBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)ɭUSBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)ʭUSBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)˭USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)̭USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)ͭUSBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)έUSBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)ϭUSBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)ЭUSBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)ѭUSBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)ҭUSBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)ӭUSBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)ԭUSBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)խUSBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)֭USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)׭USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)حUSBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)٭USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)ڭUSBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)ۭUSBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)ܭUSBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)ݭUSBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)ޭUSBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)߭USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)USBPHY_CTRL_SET_RSVD1_SHIFT (25U)USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SET_SFTRST_SHIFT (31U)USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)®USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)îUSBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)ĮUSBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)ŮUSBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)ƮUSBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)ǮUSBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)ȮUSBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)ɮUSBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)ʮUSBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)ˮUSBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)̮USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)ͮUSBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)ήUSBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)ϮUSBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)ЮUSBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)ѮUSBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)ҮUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)ӮUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)ԮUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)ծUSBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)֮USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)׮USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)خUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)ٮUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)ڮUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)ۮUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)ܮUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)ݮUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)ޮUSBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)߮USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)¯USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)ïUSBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)įUSBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)ůUSBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)ƯUSBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)ǯUSBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)ȯUSBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)ɯUSBPHY_CTRL_TOG_RSVD1_SHIFT (25U)ʯUSBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)˯USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)̯USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)ͯUSBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)ίUSBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)ϯUSBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)ЯUSBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)ѯUSBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)үUSBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)ӯUSBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)ԯUSBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)կUSBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)֯USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)ׯUSBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)دUSBPHY_CTRL_TOG_SFTRST_SHIFT (31U)ٯUSBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)ޯUSBPHY_STATUS_RSVD0_MASK (0x7U)߯USBPHY_STATUS_RSVD0_SHIFT (0U)USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)USBPHY_STATUS_RSVD1_MASK (0x30U)USBPHY_STATUS_RSVD1_SHIFT (4U)USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)USBPHY_STATUS_RSVD2_MASK (0x80U)USBPHY_STATUS_RSVD2_SHIFT (7U)USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)USBPHY_STATUS_RSVD3_MASK (0x200U)USBPHY_STATUS_RSVD3_SHIFT (9U)USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)USBPHY_STATUS_RSVD4_SHIFT (11U)USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_RSVD0_SHIFT (6U)USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_RSVD1_SHIFT (13U)USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_RSVD2_SHIFT (21U)USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)USBPHY_DEBUG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_RSVD3_SHIFT (31U)USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)°USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)ðUSBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)İUSBPHY_DEBUG_SET_RSVD1_SHIFT (13U)ŰUSBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)ưUSBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)ǰUSBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)ȰUSBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)ɰUSBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)ʰUSBPHY_DEBUG_SET_RSVD2_SHIFT (21U)˰USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)̰USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)ͰUSBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)ΰUSBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)ϰUSBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)аUSBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)ѰUSBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)ҰUSBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)ӰUSBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)԰USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)հUSBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)ְUSBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)װUSBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)ذUSBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)ٰUSBPHY_DEBUG_SET_RSVD3_SHIFT (31U)ڰUSBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)߰USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)±USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)ñUSBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)ıUSBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)űUSBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)ƱUSBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)DZUSBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)ȱUSBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)ɱUSBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)αUSBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)ϱUSBPHY_DEBUG1_RSVD0_SHIFT (0U)бUSBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)ѱUSBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)ұUSBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)ӱUSBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)ԱUSBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)ձUSBPHY_DEBUG1_RSVD1_SHIFT (15U)ֱUSBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)۱USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)ܱUSBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)ݱUSBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)ޱUSBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)߱USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)USBPHY_VERSION_STEP_MASK (0xFFFFU)USBPHY_VERSION_STEP_SHIFT (0U)USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)USBPHY_VERSION_MINOR_MASK (0xFF0000U)USBPHY_VERSION_MINOR_SHIFT (16U)USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)USBPHY_VERSION_MAJOR_MASK (0xFF000000U)USBPHY_VERSION_MAJOR_SHIFT (24U)USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)USBPHY_BASE (0x400D9000u)USBPHY ((USBPHY_Type *)USBPHY_BASE)USBPHY_BASE_ADDRS { 0u, USBPHY_BASE }USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY }USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn }USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASKUSBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFTUSBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASKUSBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFTUSBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)زUSB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)ٲUSB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)ڲUSB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)۲USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)ܲUSB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)ݲUSB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)޲USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)߲USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_COUNT (2U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)USB_ANALOG_CHRG_DETECT_COUNT (2U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)ijUSB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)ųUSB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)ƳUSB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)dzUSB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)ȳUSB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)ɳUSB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)ʳUSB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)˳USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)̳USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)гUSB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)ԳUSB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)ճUSB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)ֳUSB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)׳USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)سUSB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)ٳUSB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)ڳUSB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)۳USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)ܳUSB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_COUNT (2U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_SET_COUNT (2U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_CLR_COUNT (2U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)´USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)ƴUSB_ANALOG_MISC_TOG_COUNT (2U)ʴUSB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)˴USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)̴USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)״USB_ANALOG_BASE (0x400D8000u)ٴUSB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)۴USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }ݴUSB_ANALOG_BASE_PTRS { USB_ANALOG }USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)USDHC_BLK_ATT_BLKCNT_SHIFT (16U)USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)USDHC_CMD_ARG_CMDARG_SHIFT (0U)USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)µUSDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)õUSDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)ĵUSDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)ŵUSDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)ʵUSDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)˵USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)̵USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)ѵUSDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)ҵUSDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)ӵUSDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)صUSDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)ٵUSDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)ڵUSDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)ߵUSDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)USDHC_PRES_STATE_CIHB_MASK (0x1U)USDHC_PRES_STATE_CIHB_SHIFT (0U)USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)USDHC_PRES_STATE_CDIHB_MASK (0x2U)USDHC_PRES_STATE_CDIHB_SHIFT (1U)USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)USDHC_PRES_STATE_DLA_MASK (0x4U)USDHC_PRES_STATE_DLA_SHIFT (2U)USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)USDHC_PRES_STATE_SDSTB_MASK (0x8U)USDHC_PRES_STATE_SDSTB_SHIFT (3U)USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)USDHC_PRES_STATE_IPGOFF_MASK (0x10U)USDHC_PRES_STATE_IPGOFF_SHIFT (4U)USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)USDHC_PRES_STATE_HCKOFF_MASK (0x20U)USDHC_PRES_STATE_HCKOFF_SHIFT (5U)USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)USDHC_PRES_STATE_PEROFF_MASK (0x40U)USDHC_PRES_STATE_PEROFF_SHIFT (6U)USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)USDHC_PRES_STATE_SDOFF_MASK (0x80U)USDHC_PRES_STATE_SDOFF_SHIFT (7U)USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)USDHC_PRES_STATE_WTA_MASK (0x100U)USDHC_PRES_STATE_WTA_SHIFT (8U)USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)USDHC_PRES_STATE_RTA_MASK (0x200U)USDHC_PRES_STATE_RTA_SHIFT (9U)USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)USDHC_PRES_STATE_BWEN_MASK (0x400U)USDHC_PRES_STATE_BWEN_SHIFT (10U)USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)USDHC_PRES_STATE_BREN_MASK (0x800U)USDHC_PRES_STATE_BREN_SHIFT (11U)USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)USDHC_PRES_STATE_RTR_MASK (0x1000U)USDHC_PRES_STATE_RTR_SHIFT (12U)USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)USDHC_PRES_STATE_TSCD_MASK (0x8000U)USDHC_PRES_STATE_TSCD_SHIFT (15U)USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)USDHC_PRES_STATE_CINST_MASK (0x10000U)USDHC_PRES_STATE_CINST_SHIFT (16U)USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)USDHC_PRES_STATE_CDPL_MASK (0x40000U)USDHC_PRES_STATE_CDPL_SHIFT (18U)USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)USDHC_PRES_STATE_WPSPL_MASK (0x80000U)USDHC_PRES_STATE_WPSPL_SHIFT (19U)USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)USDHC_PRES_STATE_CLSL_MASK (0x800000U)USDHC_PRES_STATE_CLSL_SHIFT (23U)USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)USDHC_PRES_STATE_DLSL_SHIFT (24U)USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)USDHC_PROT_CTRL_LCTL_MASK (0x1U)USDHC_PROT_CTRL_LCTL_SHIFT (0U)USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)USDHC_PROT_CTRL_DTW_MASK (0x6U)USDHC_PROT_CTRL_DTW_SHIFT (1U)USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)USDHC_PROT_CTRL_D3CD_MASK (0x8U)USDHC_PROT_CTRL_D3CD_SHIFT (3U)USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)USDHC_PROT_CTRL_EMODE_MASK (0x30U)USDHC_PROT_CTRL_EMODE_SHIFT (4U)USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)USDHC_PROT_CTRL_CDTL_MASK (0x40U)USDHC_PROT_CTRL_CDTL_SHIFT (6U)USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)USDHC_PROT_CTRL_CDSS_MASK (0x80U)USDHC_PROT_CTRL_CDSS_SHIFT (7U)USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)USDHC_PROT_CTRL_DMASEL_MASK (0x300U)USDHC_PROT_CTRL_DMASEL_SHIFT (8U)USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)¶USDHC_PROT_CTRL_CREQ_MASK (0x20000U)öUSDHC_PROT_CTRL_CREQ_SHIFT (17U)ĶUSDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)ŶUSDHC_PROT_CTRL_RWCTL_MASK (0x40000U)ƶUSDHC_PROT_CTRL_RWCTL_SHIFT (18U)ǶUSDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)ȶUSDHC_PROT_CTRL_IABG_MASK (0x80000U)ɶUSDHC_PROT_CTRL_IABG_SHIFT (19U)ʶUSDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)˶USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)̶USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)ͶUSDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)ζUSDHC_PROT_CTRL_WECINT_MASK (0x1000000U)϶USDHC_PROT_CTRL_WECINT_SHIFT (24U)жUSDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)ѶUSDHC_PROT_CTRL_WECINS_MASK (0x2000000U)ҶUSDHC_PROT_CTRL_WECINS_SHIFT (25U)ӶUSDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)ԶUSDHC_PROT_CTRL_WECRM_MASK (0x4000000U)նUSDHC_PROT_CTRL_WECRM_SHIFT (26U)ֶUSDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)׶USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)ضUSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)ٶUSDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)ڶUSDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)۶USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)ܶUSDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)USDHC_SYS_CTRL_DVS_MASK (0xF0U)USDHC_SYS_CTRL_DVS_SHIFT (4U)USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)USDHC_SYS_CTRL_DTOCV_SHIFT (16U)USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)USDHC_SYS_CTRL_RSTA_SHIFT (24U)USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)USDHC_SYS_CTRL_RSTC_SHIFT (25U)USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)USDHC_SYS_CTRL_RSTD_SHIFT (26U)USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)USDHC_SYS_CTRL_INITA_MASK (0x8000000U)USDHC_SYS_CTRL_INITA_SHIFT (27U)USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)USDHC_SYS_CTRL_RSTT_SHIFT (28U)USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)USDHC_INT_STATUS_CC_MASK (0x1U)USDHC_INT_STATUS_CC_SHIFT (0U)USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)USDHC_INT_STATUS_TC_MASK (0x2U)USDHC_INT_STATUS_TC_SHIFT (1U)USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)USDHC_INT_STATUS_BGE_MASK (0x4U)USDHC_INT_STATUS_BGE_SHIFT (2U)USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)USDHC_INT_STATUS_DINT_MASK (0x8U)USDHC_INT_STATUS_DINT_SHIFT (3U)USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)USDHC_INT_STATUS_BWR_MASK (0x10U)USDHC_INT_STATUS_BWR_SHIFT (4U)USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)USDHC_INT_STATUS_BRR_MASK (0x20U)USDHC_INT_STATUS_BRR_SHIFT (5U)USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)USDHC_INT_STATUS_CINS_MASK (0x40U)USDHC_INT_STATUS_CINS_SHIFT (6U)USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)USDHC_INT_STATUS_CRM_MASK (0x80U)USDHC_INT_STATUS_CRM_SHIFT (7U)USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)USDHC_INT_STATUS_CINT_MASK (0x100U)USDHC_INT_STATUS_CINT_SHIFT (8U)USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)USDHC_INT_STATUS_RTE_MASK (0x1000U)USDHC_INT_STATUS_RTE_SHIFT (12U)USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)USDHC_INT_STATUS_TP_MASK (0x4000U)USDHC_INT_STATUS_TP_SHIFT (14U)USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)USDHC_INT_STATUS_CTOE_MASK (0x10000U)USDHC_INT_STATUS_CTOE_SHIFT (16U)USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)USDHC_INT_STATUS_CCE_MASK (0x20000U)USDHC_INT_STATUS_CCE_SHIFT (17U)USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)USDHC_INT_STATUS_CEBE_MASK (0x40000U)USDHC_INT_STATUS_CEBE_SHIFT (18U)USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)USDHC_INT_STATUS_CIE_MASK (0x80000U)USDHC_INT_STATUS_CIE_SHIFT (19U)USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)USDHC_INT_STATUS_DTOE_MASK (0x100000U)USDHC_INT_STATUS_DTOE_SHIFT (20U)USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)USDHC_INT_STATUS_DCE_MASK (0x200000U)USDHC_INT_STATUS_DCE_SHIFT (21U)USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)USDHC_INT_STATUS_DEBE_MASK (0x400000U)USDHC_INT_STATUS_DEBE_SHIFT (22U)USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)USDHC_INT_STATUS_AC12E_MASK (0x1000000U)USDHC_INT_STATUS_AC12E_SHIFT (24U)USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)USDHC_INT_STATUS_TNE_MASK (0x4000000U)USDHC_INT_STATUS_TNE_SHIFT (26U)USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)USDHC_INT_STATUS_DMAE_MASK (0x10000000U)USDHC_INT_STATUS_DMAE_SHIFT (28U)USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)÷USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)ķUSDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)ŷUSDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)ƷUSDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)ǷUSDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)ȷUSDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)ɷUSDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)ʷUSDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)˷USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)̷USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)ͷUSDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)ηUSDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)ϷUSDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)зUSDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)ѷUSDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)ҷUSDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)ӷUSDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)ԷUSDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)շUSDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)ַUSDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)׷USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)طUSDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)ٷUSDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)ڷUSDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)۷USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)ܷUSDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)ݷUSDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)޷USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)߷USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)¸USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)øUSDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)ĸUSDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)ɸUSDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)ʸUSDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)˸USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)̸USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)͸USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)θUSDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)ϸUSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)иUSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)ѸUSDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)ҸUSDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)ӸUSDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)ԸUSDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)ոUSDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)ָUSDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)׸USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)ظUSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)ٸUSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)ڸUSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)۸USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)ܸUSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)ݸUSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)޸USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)߸USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)USDHC_WTMK_LVL_RD_WML_SHIFT (0U)USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)USDHC_WTMK_LVL_WR_WML_SHIFT (16U)USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)USDHC_MIX_CTRL_DMAEN_MASK (0x1U)USDHC_MIX_CTRL_DMAEN_SHIFT (0U)USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)USDHC_MIX_CTRL_BCEN_MASK (0x2U)USDHC_MIX_CTRL_BCEN_SHIFT (1U)USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)USDHC_MIX_CTRL_AC12EN_MASK (0x4U)USDHC_MIX_CTRL_AC12EN_SHIFT (2U)USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)USDHC_MIX_CTRL_AC23EN_MASK (0x80U)USDHC_MIX_CTRL_AC23EN_SHIFT (7U)USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)¹USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)ùUSDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)ĹUSDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)ŹUSDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)ƹUSDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)˹USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)̹USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)͹USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)ιUSDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)ϹUSDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)йUSDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)ѹUSDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)ҹUSDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)ӹUSDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)ԹUSDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)չUSDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)ֹUSDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)׹USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)عUSDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)ٹUSDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)ڹUSDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)۹USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)ܹUSDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)ݹUSDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)޹USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)߹USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)ºUSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)úUSDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)ȺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)ɺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)ʺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)˺USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)̺USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)ͺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)κUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)ϺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)кUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)ѺUSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)ҺUSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)ӺUSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)ԺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)պUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)ֺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)׺USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)غUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)ٺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)ںUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)ۺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)ܺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)ݺUSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)޺USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)ߺUSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)USDHC_VEND_SPEC_VSELECT_MASK (0x2U)USDHC_VEND_SPEC_VSELECT_SHIFT (1U)USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U)USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U)USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK)USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)»USDHC1_BASE (0x402C0000u)ĻUSDHC1 ((USDHC_Type *)USDHC1_BASE)ƻUSDHC2_BASE (0x402C4000u)ȻUSDHC2 ((USDHC_Type *)USDHC2_BASE)ʻUSDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }̻USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }λUSDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }WDOG_WCR_WDZST_MASK (0x1U)WDOG_WCR_WDZST_SHIFT (0U)WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)WDOG_WCR_WDBG_MASK (0x2U)WDOG_WCR_WDBG_SHIFT (1U)WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)WDOG_WCR_WDE_MASK (0x4U)WDOG_WCR_WDE_SHIFT (2U)WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)WDOG_WCR_WDT_MASK (0x8U)WDOG_WCR_WDT_SHIFT (3U)WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)WDOG_WCR_SRS_MASK (0x10U)WDOG_WCR_SRS_SHIFT (4U)WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)WDOG_WCR_WDA_MASK (0x20U)WDOG_WCR_WDA_SHIFT (5U)WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)WDOG_WCR_SRE_MASK (0x40U)WDOG_WCR_SRE_SHIFT (6U)WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)WDOG_WCR_WDW_MASK (0x80U)WDOG_WCR_WDW_SHIFT (7U)WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)WDOG_WCR_WT_MASK (0xFF00U)WDOG_WCR_WT_SHIFT (8U)WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)WDOG_WSR_WSR_MASK (0xFFFFU)WDOG_WSR_WSR_SHIFT (0U)WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)WDOG_WRSR_SFTW_MASK (0x1U)WDOG_WRSR_SFTW_SHIFT (0U)WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)WDOG_WRSR_TOUT_MASK (0x2U)WDOG_WRSR_TOUT_SHIFT (1U)WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)WDOG_WRSR_POR_MASK (0x10U)WDOG_WRSR_POR_SHIFT (4U)WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)WDOG_WICR_WICT_MASK (0xFFU)WDOG_WICR_WICT_SHIFT (0U)WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)WDOG_WICR_WTIS_MASK (0x4000U)WDOG_WICR_WTIS_SHIFT (14U)WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)WDOG_WICR_WIE_MASK (0x8000U)WDOG_WICR_WIE_SHIFT (15U)WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)WDOG_WMCR_PDE_MASK (0x1U)WDOG_WMCR_PDE_SHIFT (0U)WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)WDOG1_BASE (0x400B8000u)WDOG1 ((WDOG_Type *)WDOG1_BASE)üWDOG2_BASE (0x400D0000u)żWDOG2 ((WDOG_Type *)WDOG2_BASE)ǼWDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }ɼWDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }˼WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }XBARA_SEL0_SEL0_MASK (0x7FU)XBARA_SEL0_SEL0_SHIFT (0U)XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)XBARA_SEL0_SEL1_MASK (0x7F00U)XBARA_SEL0_SEL1_SHIFT (8U)XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)XBARA_SEL1_SEL2_MASK (0x7FU)XBARA_SEL1_SEL2_SHIFT (0U)XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)XBARA_SEL1_SEL3_MASK (0x7F00U)XBARA_SEL1_SEL3_SHIFT (8U)XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)½XBARA_SEL2_SEL4_MASK (0x7FU)ýXBARA_SEL2_SEL4_SHIFT (0U)ĽXBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)ŽXBARA_SEL2_SEL5_MASK (0x7F00U)ƽXBARA_SEL2_SEL5_SHIFT (8U)ǽXBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)̽XBARA_SEL3_SEL6_MASK (0x7FU)ͽXBARA_SEL3_SEL6_SHIFT (0U)νXBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)ϽXBARA_SEL3_SEL7_MASK (0x7F00U)нXBARA_SEL3_SEL7_SHIFT (8U)ѽXBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)ֽXBARA_SEL4_SEL8_MASK (0x7FU)׽XBARA_SEL4_SEL8_SHIFT (0U)ؽXBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)ٽXBARA_SEL4_SEL9_MASK (0x7F00U)ڽXBARA_SEL4_SEL9_SHIFT (8U)۽XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)XBARA_SEL5_SEL10_MASK (0x7FU)XBARA_SEL5_SEL10_SHIFT (0U)XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)XBARA_SEL5_SEL11_MASK (0x7F00U)XBARA_SEL5_SEL11_SHIFT (8U)XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)XBARA_SEL6_SEL12_MASK (0x7FU)XBARA_SEL6_SEL12_SHIFT (0U)XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)XBARA_SEL6_SEL13_MASK (0x7F00U)XBARA_SEL6_SEL13_SHIFT (8U)XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)XBARA_SEL7_SEL14_MASK (0x7FU)XBARA_SEL7_SEL14_SHIFT (0U)XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)XBARA_SEL7_SEL15_MASK (0x7F00U)XBARA_SEL7_SEL15_SHIFT (8U)XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)XBARA_SEL8_SEL16_MASK (0x7FU)XBARA_SEL8_SEL16_SHIFT (0U)XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)XBARA_SEL8_SEL17_MASK (0x7F00U)XBARA_SEL8_SEL17_SHIFT (8U)XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)XBARA_SEL9_SEL18_MASK (0x7FU)XBARA_SEL9_SEL18_SHIFT (0U)XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)XBARA_SEL9_SEL19_MASK (0x7F00U)XBARA_SEL9_SEL19_SHIFT (8U)XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)XBARA_SEL10_SEL20_MASK (0x7FU)XBARA_SEL10_SEL20_SHIFT (0U)XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)XBARA_SEL10_SEL21_MASK (0x7F00U)XBARA_SEL10_SEL21_SHIFT (8U)XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)XBARA_SEL11_SEL22_MASK (0x7FU)XBARA_SEL11_SEL22_SHIFT (0U)XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)XBARA_SEL11_SEL23_MASK (0x7F00U)XBARA_SEL11_SEL23_SHIFT (8U)XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)XBARA_SEL12_SEL24_MASK (0x7FU)XBARA_SEL12_SEL24_SHIFT (0U)XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)XBARA_SEL12_SEL25_MASK (0x7F00U)XBARA_SEL12_SEL25_SHIFT (8U)XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)XBARA_SEL13_SEL26_MASK (0x7FU)XBARA_SEL13_SEL26_SHIFT (0U)XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)XBARA_SEL13_SEL27_MASK (0x7F00U)XBARA_SEL13_SEL27_SHIFT (8U)XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)XBARA_SEL14_SEL28_MASK (0x7FU)XBARA_SEL14_SEL28_SHIFT (0U)XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)XBARA_SEL14_SEL29_MASK (0x7F00U)XBARA_SEL14_SEL29_SHIFT (8U)XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)ľXBARA_SEL15_SEL30_MASK (0x7FU)žXBARA_SEL15_SEL30_SHIFT (0U)ƾXBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)ǾXBARA_SEL15_SEL31_MASK (0x7F00U)ȾXBARA_SEL15_SEL31_SHIFT (8U)ɾXBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)ξXBARA_SEL16_SEL32_MASK (0x7FU)ϾXBARA_SEL16_SEL32_SHIFT (0U)оXBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)ѾXBARA_SEL16_SEL33_MASK (0x7F00U)ҾXBARA_SEL16_SEL33_SHIFT (8U)ӾXBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)ؾXBARA_SEL17_SEL34_MASK (0x7FU)پXBARA_SEL17_SEL34_SHIFT (0U)ھXBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)۾XBARA_SEL17_SEL35_MASK (0x7F00U)ܾXBARA_SEL17_SEL35_SHIFT (8U)ݾXBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)XBARA_SEL18_SEL36_MASK (0x7FU)XBARA_SEL18_SEL36_SHIFT (0U)XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)XBARA_SEL18_SEL37_MASK (0x7F00U)XBARA_SEL18_SEL37_SHIFT (8U)XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)XBARA_SEL19_SEL38_MASK (0x7FU)XBARA_SEL19_SEL38_SHIFT (0U)XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)XBARA_SEL19_SEL39_MASK (0x7F00U)XBARA_SEL19_SEL39_SHIFT (8U)XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)XBARA_SEL20_SEL40_MASK (0x7FU)XBARA_SEL20_SEL40_SHIFT (0U)XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)XBARA_SEL20_SEL41_MASK (0x7F00U)XBARA_SEL20_SEL41_SHIFT (8U)XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)XBARA_SEL21_SEL42_MASK (0x7FU)XBARA_SEL21_SEL42_SHIFT (0U)XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)XBARA_SEL21_SEL43_MASK (0x7F00U)XBARA_SEL21_SEL43_SHIFT (8U)XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)XBARA_SEL22_SEL44_MASK (0x7FU)XBARA_SEL22_SEL44_SHIFT (0U)XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)XBARA_SEL22_SEL45_MASK (0x7F00U)XBARA_SEL22_SEL45_SHIFT (8U)XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)XBARA_SEL23_SEL46_MASK (0x7FU)XBARA_SEL23_SEL46_SHIFT (0U)XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)XBARA_SEL23_SEL47_MASK (0x7F00U)XBARA_SEL23_SEL47_SHIFT (8U)XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)XBARA_SEL24_SEL48_MASK (0x7FU)XBARA_SEL24_SEL48_SHIFT (0U)XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)XBARA_SEL24_SEL49_MASK (0x7F00U)XBARA_SEL24_SEL49_SHIFT (8U)XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)XBARA_SEL25_SEL50_MASK (0x7FU)XBARA_SEL25_SEL50_SHIFT (0U)XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)XBARA_SEL25_SEL51_MASK (0x7F00U)XBARA_SEL25_SEL51_SHIFT (8U)XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)XBARA_SEL26_SEL52_MASK (0x7FU)XBARA_SEL26_SEL52_SHIFT (0U)XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)XBARA_SEL26_SEL53_MASK (0x7F00U)XBARA_SEL26_SEL53_SHIFT (8U)XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)XBARA_SEL27_SEL54_MASK (0x7FU)XBARA_SEL27_SEL54_SHIFT (0U)XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)XBARA_SEL27_SEL55_MASK (0x7F00U)XBARA_SEL27_SEL55_SHIFT (8U)XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)ƿXBARA_SEL28_SEL56_MASK (0x7FU)ǿXBARA_SEL28_SEL56_SHIFT (0U)ȿXBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)ɿXBARA_SEL28_SEL57_MASK (0x7F00U)ʿXBARA_SEL28_SEL57_SHIFT (8U)˿XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)пXBARA_SEL29_SEL58_MASK (0x7FU)ѿXBARA_SEL29_SEL58_SHIFT (0U)ҿXBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)ӿXBARA_SEL29_SEL59_MASK (0x7F00U)ԿXBARA_SEL29_SEL59_SHIFT (8U)տXBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)ڿXBARA_SEL30_SEL60_MASK (0x7FU)ۿXBARA_SEL30_SEL60_SHIFT (0U)ܿXBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)ݿXBARA_SEL30_SEL61_MASK (0x7F00U)޿XBARA_SEL30_SEL61_SHIFT (8U)߿XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)XBARA_SEL31_SEL62_MASK (0x7FU)XBARA_SEL31_SEL62_SHIFT (0U)XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)XBARA_SEL31_SEL63_MASK (0x7F00U)XBARA_SEL31_SEL63_SHIFT (8U)XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)XBARA_SEL32_SEL64_MASK (0x7FU)XBARA_SEL32_SEL64_SHIFT (0U)XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)XBARA_SEL32_SEL65_MASK (0x7F00U)XBARA_SEL32_SEL65_SHIFT (8U)XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)XBARA_SEL33_SEL66_MASK (0x7FU)XBARA_SEL33_SEL66_SHIFT (0U)XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)XBARA_SEL33_SEL67_MASK (0x7F00U)XBARA_SEL33_SEL67_SHIFT (8U)XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)XBARA_SEL34_SEL68_MASK (0x7FU)XBARA_SEL34_SEL68_SHIFT (0U)XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)XBARA_SEL34_SEL69_MASK (0x7F00U)XBARA_SEL34_SEL69_SHIFT (8U)XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)XBARA_SEL35_SEL70_MASK (0x7FU)XBARA_SEL35_SEL70_SHIFT (0U)XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)XBARA_SEL35_SEL71_MASK (0x7F00U)XBARA_SEL35_SEL71_SHIFT (8U)XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)XBARA_SEL36_SEL72_MASK (0x7FU)XBARA_SEL36_SEL72_SHIFT (0U)XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)XBARA_SEL36_SEL73_MASK (0x7F00U)XBARA_SEL36_SEL73_SHIFT (8U)XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)XBARA_SEL37_SEL74_MASK (0x7FU)XBARA_SEL37_SEL74_SHIFT (0U)XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)XBARA_SEL37_SEL75_MASK (0x7F00U)XBARA_SEL37_SEL75_SHIFT (8U)XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)XBARA_SEL38_SEL76_MASK (0x7FU)XBARA_SEL38_SEL76_SHIFT (0U)XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)XBARA_SEL38_SEL77_MASK (0x7F00U)XBARA_SEL38_SEL77_SHIFT (8U)XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)XBARA_SEL39_SEL78_MASK (0x7FU)XBARA_SEL39_SEL78_SHIFT (0U)XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)XBARA_SEL39_SEL79_MASK (0x7F00U)XBARA_SEL39_SEL79_SHIFT (8U)XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)XBARA_SEL40_SEL80_MASK (0x7FU)XBARA_SEL40_SEL80_SHIFT (0U)XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)XBARA_SEL40_SEL81_MASK (0x7F00U)XBARA_SEL40_SEL81_SHIFT (8U)XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)XBARA_SEL41_SEL82_MASK (0x7FU)XBARA_SEL41_SEL82_SHIFT (0U)XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)XBARA_SEL41_SEL83_MASK (0x7F00U)XBARA_SEL41_SEL83_SHIFT (8U)XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)XBARA_SEL42_SEL84_MASK (0x7FU)XBARA_SEL42_SEL84_SHIFT (0U)XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)XBARA_SEL42_SEL85_MASK (0x7F00U)XBARA_SEL42_SEL85_SHIFT (8U)XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)XBARA_SEL43_SEL86_MASK (0x7FU)XBARA_SEL43_SEL86_SHIFT (0U)XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)XBARA_SEL43_SEL87_MASK (0x7F00U)XBARA_SEL43_SEL87_SHIFT (8U)XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)XBARA_SEL44_SEL88_MASK (0x7FU)XBARA_SEL44_SEL88_SHIFT (0U)XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)XBARA_SEL44_SEL89_MASK (0x7F00U)XBARA_SEL44_SEL89_SHIFT (8U)XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)XBARA_SEL45_SEL90_MASK (0x7FU)XBARA_SEL45_SEL90_SHIFT (0U)XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)XBARA_SEL45_SEL91_MASK (0x7F00U)XBARA_SEL45_SEL91_SHIFT (8U)XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)XBARA_SEL46_SEL92_MASK (0x7FU)XBARA_SEL46_SEL92_SHIFT (0U)XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)XBARA_SEL46_SEL93_MASK (0x7F00U)XBARA_SEL46_SEL93_SHIFT (8U)XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)XBARA_SEL47_SEL94_MASK (0x7FU)XBARA_SEL47_SEL94_SHIFT (0U)XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)XBARA_SEL47_SEL95_MASK (0x7F00U)XBARA_SEL47_SEL95_SHIFT (8U)XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)XBARA_SEL48_SEL96_MASK (0x7FU)XBARA_SEL48_SEL96_SHIFT (0U)XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)XBARA_SEL48_SEL97_MASK (0x7F00U)XBARA_SEL48_SEL97_SHIFT (8U)XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)XBARA_SEL49_SEL98_MASK (0x7FU)XBARA_SEL49_SEL98_SHIFT (0U)XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)XBARA_SEL49_SEL99_MASK (0x7F00U)XBARA_SEL49_SEL99_SHIFT (8U)XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)XBARA_SEL50_SEL100_MASK (0x7FU)XBARA_SEL50_SEL100_SHIFT (0U)XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)XBARA_SEL50_SEL101_MASK (0x7F00U)XBARA_SEL50_SEL101_SHIFT (8U)XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)XBARA_SEL51_SEL102_MASK (0x7FU)XBARA_SEL51_SEL102_SHIFT (0U)XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)XBARA_SEL51_SEL103_MASK (0x7F00U)XBARA_SEL51_SEL103_SHIFT (8U)XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)XBARA_SEL52_SEL104_MASK (0x7FU)XBARA_SEL52_SEL104_SHIFT (0U)XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)XBARA_SEL52_SEL105_MASK (0x7F00U)XBARA_SEL52_SEL105_SHIFT (8U)XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)XBARA_SEL53_SEL106_MASK (0x7FU)XBARA_SEL53_SEL106_SHIFT (0U)XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)XBARA_SEL53_SEL107_MASK (0x7F00U)XBARA_SEL53_SEL107_SHIFT (8U)XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)XBARA_SEL54_SEL108_MASK (0x7FU)XBARA_SEL54_SEL108_SHIFT (0U)XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)XBARA_SEL54_SEL109_MASK (0x7F00U)XBARA_SEL54_SEL109_SHIFT (8U)XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)XBARA_SEL55_SEL110_MASK (0x7FU)XBARA_SEL55_SEL110_SHIFT (0U)XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)XBARA_SEL55_SEL111_MASK (0x7F00U)XBARA_SEL55_SEL111_SHIFT (8U)XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)XBARA_SEL56_SEL112_MASK (0x7FU)XBARA_SEL56_SEL112_SHIFT (0U)XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)XBARA_SEL56_SEL113_MASK (0x7F00U)XBARA_SEL56_SEL113_SHIFT (8U)XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)XBARA_SEL57_SEL114_MASK (0x7FU)XBARA_SEL57_SEL114_SHIFT (0U)XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)XBARA_SEL57_SEL115_MASK (0x7F00U)XBARA_SEL57_SEL115_SHIFT (8U)XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)XBARA_SEL58_SEL116_MASK (0x7FU)XBARA_SEL58_SEL116_SHIFT (0U)XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)XBARA_SEL58_SEL117_MASK (0x7F00U)XBARA_SEL58_SEL117_SHIFT (8U)XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)XBARA_SEL59_SEL118_MASK (0x7FU)XBARA_SEL59_SEL118_SHIFT (0U)XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)XBARA_SEL59_SEL119_MASK (0x7F00U)XBARA_SEL59_SEL119_SHIFT (8U)XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)XBARA_SEL60_SEL120_MASK (0x7FU)XBARA_SEL60_SEL120_SHIFT (0U)XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)XBARA_SEL60_SEL121_MASK (0x7F00U)XBARA_SEL60_SEL121_SHIFT (8U)XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)XBARA_SEL61_SEL122_MASK (0x7FU)XBARA_SEL61_SEL122_SHIFT (0U)XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)XBARA_SEL61_SEL123_MASK (0x7F00U)XBARA_SEL61_SEL123_SHIFT (8U)XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)XBARA_SEL62_SEL124_MASK (0x7FU)XBARA_SEL62_SEL124_SHIFT (0U)XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)XBARA_SEL62_SEL125_MASK (0x7F00U)XBARA_SEL62_SEL125_SHIFT (8U)XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)XBARA_SEL63_SEL126_MASK (0x7FU)XBARA_SEL63_SEL126_SHIFT (0U)XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)XBARA_SEL63_SEL127_MASK (0x7F00U)XBARA_SEL63_SEL127_SHIFT (8U)XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)XBARA_SEL64_SEL128_MASK (0x7FU)XBARA_SEL64_SEL128_SHIFT (0U)XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)XBARA_SEL64_SEL129_MASK (0x7F00U)XBARA_SEL64_SEL129_SHIFT (8U)XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)XBARA_SEL65_SEL130_MASK (0x7FU)XBARA_SEL65_SEL130_SHIFT (0U)XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)XBARA_SEL65_SEL131_MASK (0x7F00U)XBARA_SEL65_SEL131_SHIFT (8U)XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)XBARA_CTRL0_DEN0_MASK (0x1U)XBARA_CTRL0_DEN0_SHIFT (0U)XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)XBARA_CTRL0_IEN0_MASK (0x2U)XBARA_CTRL0_IEN0_SHIFT (1U)XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)XBARA_CTRL0_EDGE0_MASK (0xCU)XBARA_CTRL0_EDGE0_SHIFT (2U)XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)XBARA_CTRL0_STS0_MASK (0x10U)XBARA_CTRL0_STS0_SHIFT (4U)XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)XBARA_CTRL0_DEN1_MASK (0x100U)XBARA_CTRL0_DEN1_SHIFT (8U)XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)XBARA_CTRL0_IEN1_MASK (0x200U)XBARA_CTRL0_IEN1_SHIFT (9U)XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)XBARA_CTRL0_EDGE1_MASK (0xC00U)XBARA_CTRL0_EDGE1_SHIFT (10U)XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)XBARA_CTRL0_STS1_MASK (0x1000U)XBARA_CTRL0_STS1_SHIFT (12U)XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)XBARA_CTRL1_DEN2_MASK (0x1U)XBARA_CTRL1_DEN2_SHIFT (0U)XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)XBARA_CTRL1_IEN2_MASK (0x2U)XBARA_CTRL1_IEN2_SHIFT (1U)XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)XBARA_CTRL1_EDGE2_MASK (0xCU)XBARA_CTRL1_EDGE2_SHIFT (2U)XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)XBARA_CTRL1_STS2_MASK (0x10U)XBARA_CTRL1_STS2_SHIFT (4U)XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)XBARA_CTRL1_DEN3_MASK (0x100U)XBARA_CTRL1_DEN3_SHIFT (8U)XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)XBARA_CTRL1_IEN3_MASK (0x200U)XBARA_CTRL1_IEN3_SHIFT (9U)XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)XBARA_CTRL1_EDGE3_MASK (0xC00U)XBARA_CTRL1_EDGE3_SHIFT (10U)XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)XBARA_CTRL1_STS3_MASK (0x1000U)XBARA_CTRL1_STS3_SHIFT (12U)XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)XBARA_BASE (0x403BC000u)XBARA ((XBARA_Type *)XBARA_BASE)XBARA_BASE_ADDRS { XBARA_BASE }XBARA_BASE_PTRS { XBARA }XBARB_SEL0_SEL0_MASK (0x3FU)XBARB_SEL0_SEL0_SHIFT (0U)XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)XBARB_SEL0_SEL1_MASK (0x3F00U)XBARB_SEL0_SEL1_SHIFT (8U)XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)XBARB_SEL1_SEL2_MASK (0x3FU)XBARB_SEL1_SEL2_SHIFT (0U)XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)XBARB_SEL1_SEL3_MASK (0x3F00U)XBARB_SEL1_SEL3_SHIFT (8U)XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)XBARB_SEL2_SEL4_MASK (0x3FU)XBARB_SEL2_SEL4_SHIFT (0U)XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)XBARB_SEL2_SEL5_MASK (0x3F00U)XBARB_SEL2_SEL5_SHIFT (8U)XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)XBARB_SEL3_SEL6_MASK (0x3FU)XBARB_SEL3_SEL6_SHIFT (0U)XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)XBARB_SEL3_SEL7_MASK (0x3F00U)XBARB_SEL3_SEL7_SHIFT (8U)XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)XBARB_SEL4_SEL8_MASK (0x3FU)XBARB_SEL4_SEL8_SHIFT (0U)XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)XBARB_SEL4_SEL9_MASK (0x3F00U)XBARB_SEL4_SEL9_SHIFT (8U)XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)XBARB_SEL5_SEL10_MASK (0x3FU)XBARB_SEL5_SEL10_SHIFT (0U)XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)XBARB_SEL5_SEL11_MASK (0x3F00U)XBARB_SEL5_SEL11_SHIFT (8U)XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)XBARB_SEL6_SEL12_MASK (0x3FU)XBARB_SEL6_SEL12_SHIFT (0U)XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)XBARB_SEL6_SEL13_MASK (0x3F00U)XBARB_SEL6_SEL13_SHIFT (8U)XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)XBARB_SEL7_SEL14_MASK (0x3FU)XBARB_SEL7_SEL14_SHIFT (0U)XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)XBARB_SEL7_SEL15_MASK (0x3F00U)XBARB_SEL7_SEL15_SHIFT (8U)XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)XBARB_BASE (0x403C0000u)XBARB ((XBARB_Type *)XBARB_BASE)XBARB_BASE_ADDRS { XBARB_BASE }XBARB_BASE_PTRS { XBARB }XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)XTALOSC24M_BASE (0x400D8000u)XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }XTALOSC24M_BASE_PTRS { XTALOSC24M }NXP_VAL2FLD(field,value) (((value) << (field ## _SHIFT)) & (field ## _MASK))NXP_FLD2VAL(field,value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) __CORE_CM7_H_GENERIC "?B__CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)C__CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB)D__CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB )G__CORTEX_M (7U)U__FPU_USED 0U__CORE_CM7_H_DEPENDANT __I volatile const__O volatile__IO volatile__IM volatile const__OM volatile__IOM volatileAPSR_N_Pos 31UAPSR_N_Msk (1UL << APSR_N_Pos)APSR_Z_Pos 30UAPSR_Z_Msk (1UL << APSR_Z_Pos)APSR_C_Pos 29UAPSR_C_Msk (1UL << APSR_C_Pos)APSR_V_Pos 28UAPSR_V_Msk (1UL << APSR_V_Pos)APSR_Q_Pos 27UAPSR_Q_Msk (1UL << APSR_Q_Pos)APSR_GE_Pos 16UAPSR_GE_Msk (0xFUL << APSR_GE_Pos)IPSR_ISR_Pos 0UIPSR_ISR_Msk (0x1FFUL )xPSR_N_Pos 31UxPSR_N_Msk (1UL << xPSR_N_Pos)xPSR_Z_Pos 30UxPSR_Z_Msk (1UL << xPSR_Z_Pos)xPSR_C_Pos 29UxPSR_C_Msk (1UL << xPSR_C_Pos)xPSR_V_Pos 28UxPSR_V_Msk (1UL << xPSR_V_Pos)xPSR_Q_Pos 27UxPSR_Q_Msk (1UL << xPSR_Q_Pos)xPSR_ICI_IT_2_Pos 25UxPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)xPSR_T_Pos 24UxPSR_T_Msk (1UL << xPSR_T_Pos)xPSR_GE_Pos 16UxPSR_GE_Msk (0xFUL << xPSR_GE_Pos)xPSR_ICI_IT_1_Pos 10UxPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)xPSR_ISR_Pos 0UxPSR_ISR_Msk (0x1FFUL )CONTROL_FPCA_Pos 2UCONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)CONTROL_SPSEL_Pos 1UCONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)CONTROL_nPRIV_Pos 0UCONTROL_nPRIV_Msk (1UL )NVIC_STIR_INTID_Pos 0UNVIC_STIR_INTID_Msk (0x1FFUL )SCB_CPUID_IMPLEMENTER_Pos 24USCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)SCB_CPUID_VARIANT_Pos 20USCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)SCB_CPUID_ARCHITECTURE_Pos 16USCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)SCB_CPUID_PARTNO_Pos 4USCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)SCB_CPUID_REVISION_Pos 0USCB_CPUID_REVISION_Msk (0xFUL )SCB_ICSR_NMIPENDSET_Pos 31USCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)SCB_ICSR_PENDSVSET_Pos 28USCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)SCB_ICSR_PENDSVCLR_Pos 27USCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)SCB_ICSR_PENDSTSET_Pos 26USCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)SCB_ICSR_PENDSTCLR_Pos 25USCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)SCB_ICSR_ISRPREEMPT_Pos 23USCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)SCB_ICSR_ISRPENDING_Pos 22USCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)SCB_ICSR_VECTPENDING_Pos 12USCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)SCB_ICSR_RETTOBASE_Pos 11USCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)SCB_ICSR_VECTACTIVE_Pos 0USCB_ICSR_VECTACTIVE_Msk (0x1FFUL )SCB_VTOR_TBLOFF_Pos 7USCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)SCB_AIRCR_VECTKEY_Pos 16USCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)SCB_AIRCR_VECTKEYSTAT_Pos 16USCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)SCB_AIRCR_ENDIANESS_Pos 15USCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)SCB_AIRCR_PRIGROUP_Pos 8USCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)SCB_AIRCR_SYSRESETREQ_Pos 2USCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)SCB_AIRCR_VECTCLRACTIVE_Pos 1USCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)SCB_AIRCR_VECTRESET_Pos 0USCB_AIRCR_VECTRESET_Msk (1UL )SCB_SCR_SEVONPEND_Pos 4USCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)SCB_SCR_SLEEPDEEP_Pos 2USCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)SCB_SCR_SLEEPONEXIT_Pos 1USCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)SCB_CCR_BP_Pos 18USCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)SCB_CCR_IC_Pos 17USCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)SCB_CCR_DC_Pos 16USCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)SCB_CCR_STKALIGN_Pos 9USCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)SCB_CCR_BFHFNMIGN_Pos 8USCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)SCB_CCR_DIV_0_TRP_Pos 4USCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)SCB_CCR_UNALIGN_TRP_Pos 3USCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)SCB_CCR_USERSETMPEND_Pos 1USCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)SCB_CCR_NONBASETHRDENA_Pos 0USCB_CCR_NONBASETHRDENA_Msk (1UL )SCB_SHCSR_USGFAULTENA_Pos 18USCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)SCB_SHCSR_BUSFAULTENA_Pos 17USCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)SCB_SHCSR_MEMFAULTENA_Pos 16USCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)SCB_SHCSR_SVCALLPENDED_Pos 15USCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)SCB_SHCSR_BUSFAULTPENDED_Pos 14USCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)SCB_SHCSR_MEMFAULTPENDED_Pos 13USCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)SCB_SHCSR_USGFAULTPENDED_Pos 12USCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)SCB_SHCSR_SYSTICKACT_Pos 11USCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)SCB_SHCSR_PENDSVACT_Pos 10USCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)SCB_SHCSR_MONITORACT_Pos 8USCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)SCB_SHCSR_SVCALLACT_Pos 7USCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)SCB_SHCSR_USGFAULTACT_Pos 3USCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)SCB_SHCSR_BUSFAULTACT_Pos 1USCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)SCB_SHCSR_MEMFAULTACT_Pos 0USCB_SHCSR_MEMFAULTACT_Msk (1UL )SCB_CFSR_USGFAULTSR_Pos 16USCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)SCB_CFSR_BUSFAULTSR_Pos 8USCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)SCB_CFSR_MEMFAULTSR_Pos 0USCB_CFSR_MEMFAULTSR_Msk (0xFFUL )SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)SCB_CFSR_IACCVIOL_Msk (1UL )SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)SCB_HFSR_DEBUGEVT_Pos 31USCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)SCB_HFSR_FORCED_Pos 30USCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)SCB_HFSR_VECTTBL_Pos 1USCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)SCB_DFSR_EXTERNAL_Pos 4USCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)SCB_DFSR_VCATCH_Pos 3USCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)SCB_DFSR_DWTTRAP_Pos 2USCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)SCB_DFSR_BKPT_Pos 1USCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)SCB_DFSR_HALTED_Pos 0USCB_DFSR_HALTED_Msk (1UL )SCB_CLIDR_LOUU_Pos 27USCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)SCB_CLIDR_LOC_Pos 24USCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)SCB_CTR_FORMAT_Pos 29USCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)SCB_CTR_CWG_Pos 24USCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)SCB_CTR_ERG_Pos 20USCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)SCB_CTR_DMINLINE_Pos 16USCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)SCB_CTR_IMINLINE_Pos 0USCB_CTR_IMINLINE_Msk (0xFUL )SCB_CCSIDR_WT_Pos 31USCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)SCB_CCSIDR_WB_Pos 30USCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)SCB_CCSIDR_RA_Pos 29USCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)SCB_CCSIDR_WA_Pos 28USCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)SCB_CCSIDR_NUMSETS_Pos 13USCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)SCB_CCSIDR_ASSOCIATIVITY_Pos 3USCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)SCB_CCSIDR_LINESIZE_Pos 0USCB_CCSIDR_LINESIZE_Msk (7UL )SCB_CSSELR_LEVEL_Pos 1USCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)SCB_CSSELR_IND_Pos 0USCB_CSSELR_IND_Msk (1UL )SCB_STIR_INTID_Pos 0USCB_STIR_INTID_Msk (0x1FFUL )SCB_DCISW_WAY_Pos 30USCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)SCB_DCISW_SET_Pos 5USCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)SCB_DCCSW_WAY_Pos 30USCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)SCB_DCCSW_SET_Pos 5USCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)SCB_DCCISW_WAY_Pos 30USCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)SCB_DCCISW_SET_Pos 5USCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)SCB_ITCMCR_SZ_Pos 3USCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)SCB_ITCMCR_RETEN_Pos 2USCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)SCB_ITCMCR_RMW_Pos 1USCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)SCB_ITCMCR_EN_Pos 0USCB_ITCMCR_EN_Msk (1UL )SCB_DTCMCR_SZ_Pos 3USCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)SCB_DTCMCR_RETEN_Pos 2USCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)SCB_DTCMCR_RMW_Pos 1USCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)SCB_DTCMCR_EN_Pos 0USCB_DTCMCR_EN_Msk (1UL )SCB_AHBPCR_SZ_Pos 1USCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)SCB_AHBPCR_EN_Pos 0USCB_AHBPCR_EN_Msk (1UL )SCB_CACR_FORCEWT_Pos 2USCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)SCB_CACR_ECCEN_Pos 1USCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)SCB_CACR_SIWT_Pos 0USCB_CACR_SIWT_Msk (1UL )SCB_AHBSCR_INITCOUNT_Pos 11USCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)SCB_AHBSCR_TPRI_Pos 2USCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)SCB_AHBSCR_CTL_Pos 0USCB_AHBSCR_CTL_Msk (3UL )SCB_ABFSR_AXIMTYPE_Pos 8USCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)SCB_ABFSR_EPPB_Pos 4USCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)SCB_ABFSR_AXIM_Pos 3USCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)SCB_ABFSR_AHBP_Pos 2USCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)SCB_ABFSR_DTCM_Pos 1USCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)SCB_ABFSR_ITCM_Pos 0USCB_ABFSR_ITCM_Msk (1UL )SCnSCB_ICTR_INTLINESNUM_Pos 0USCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12USCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)SCnSCB_ACTLR_DISRAMODE_Pos 11USCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)SCnSCB_ACTLR_FPEXCODIS_Pos 10USCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)SCnSCB_ACTLR_DISFOLD_Pos 2USCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)SCnSCB_ACTLR_DISMCYCINT_Pos 0USCnSCB_ACTLR_DISMCYCINT_Msk (1UL )SysTick_CTRL_COUNTFLAG_Pos 16USysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)SysTick_CTRL_CLKSOURCE_Pos 2USysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)SysTick_CTRL_TICKINT_Pos 1USysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)SysTick_CTRL_ENABLE_Pos 0USysTick_CTRL_ENABLE_Msk (1UL )SysTick_LOAD_RELOAD_Pos 0USysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )SysTick_VAL_CURRENT_Pos 0USysTick_VAL_CURRENT_Msk (0xFFFFFFUL )SysTick_CALIB_NOREF_Pos 31USysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)SysTick_CALIB_SKEW_Pos 30USysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)SysTick_CALIB_TENMS_Pos 0USysTick_CALIB_TENMS_Msk (0xFFFFFFUL )ITM_TPR_PRIVMASK_Pos 0UITM_TPR_PRIVMASK_Msk (0xFUL )ITM_TCR_BUSY_Pos 23UITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)ITM_TCR_TraceBusID_Pos 16UITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)ITM_TCR_GTSFREQ_Pos 10UITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)ITM_TCR_TSPrescale_Pos 8UITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)ITM_TCR_SWOENA_Pos 4UITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)ITM_TCR_DWTENA_Pos 3UITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)ITM_TCR_SYNCENA_Pos 2UITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)ITM_TCR_TSENA_Pos 1UITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)ITM_TCR_ITMENA_Pos 0UITM_TCR_ITMENA_Msk (1UL )ITM_IWR_ATVALIDM_Pos 0UITM_IWR_ATVALIDM_Msk (1UL )ITM_IRR_ATREADYM_Pos 0UITM_IRR_ATREADYM_Msk (1UL )ITM_IMCR_INTEGRATION_Pos 0UITM_IMCR_INTEGRATION_Msk (1UL )ITM_LSR_ByteAcc_Pos 2UITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)ITM_LSR_Access_Pos 1UITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)ITM_LSR_Present_Pos 0UITM_LSR_Present_Msk (1UL )DWT_CTRL_NUMCOMP_Pos 28UDWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)DWT_CTRL_NOTRCPKT_Pos 27UDWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) DWT_CTRL_NOEXTTRIG_Pos 26U DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) DWT_CTRL_NOCYCCNT_Pos 25U DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) DWT_CTRL_NOPRFCNT_Pos 24U DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) DWT_CTRL_CYCEVTENA_Pos 22U DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) DWT_CTRL_FOLDEVTENA_Pos 21U DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) DWT_CTRL_LSUEVTENA_Pos 20U DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) DWT_CTRL_SLEEPEVTENA_Pos 19U DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) DWT_CTRL_EXCEVTENA_Pos 18U DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) DWT_CTRL_CPIEVTENA_Pos 17U DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) DWT_CTRL_EXCTRCENA_Pos 16U DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) DWT_CTRL_PCSAMPLENA_Pos 12U DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) DWT_CTRL_SYNCTAP_Pos 10U DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) DWT_CTRL_CYCTAP_Pos 9U DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) DWT_CTRL_POSTINIT_Pos 5U DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) DWT_CTRL_POSTPRESET_Pos 1U DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) DWT_CTRL_CYCCNTENA_Pos 0U DWT_CTRL_CYCCNTENA_Msk (0x1UL ) DWT_CPICNT_CPICNT_Pos 0U DWT_CPICNT_CPICNT_Msk (0xFFUL ) DWT_EXCCNT_EXCCNT_Pos 0U DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) DWT_SLEEPCNT_SLEEPCNT_Pos 0U DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) DWT_LSUCNT_LSUCNT_Pos 0U DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) DWT_FOLDCNT_FOLDCNT_Pos 0U DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) DWT_MASK_MASK_Pos 0U DWT_MASK_MASK_Msk (0x1FUL ) DWT_FUNCTION_MATCHED_Pos 24U DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) DWT_FUNCTION_DATAVADDR1_Pos 16U DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) DWT_FUNCTION_DATAVADDR0_Pos 12U DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) DWT_FUNCTION_DATAVSIZE_Pos 10U DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) DWT_FUNCTION_LNK1ENA_Pos 9U DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) DWT_FUNCTION_DATAVMATCH_Pos 8U DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) DWT_FUNCTION_CYCMATCH_Pos 7U DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) DWT_FUNCTION_EMITRANGE_Pos 5U DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) DWT_FUNCTION_FUNCTION_Pos 0U DWT_FUNCTION_FUNCTION_Msk (0xFUL ) TPI_ACPR_PRESCALER_Pos 0U TPI_ACPR_PRESCALER_Msk (0x1FFFUL ) TPI_SPPR_TXMODE_Pos 0U TPI_SPPR_TXMODE_Msk (0x3UL ) TPI_FFSR_FtNonStop_Pos 3U TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) TPI_FFSR_TCPresent_Pos 2U TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) TPI_FFSR_FtStopped_Pos 1U TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) TPI_FFSR_FlInProg_Pos 0U TPI_FFSR_FlInProg_Msk (0x1UL ) TPI_FFCR_TrigIn_Pos 8U TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) TPI_FFCR_EnFCont_Pos 1U TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) TPI_TRIGGER_TRIGGER_Pos 0U TPI_TRIGGER_TRIGGER_Msk (0x1UL ) TPI_FIFO0_ITM_ATVALID_Pos 29U TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) TPI_FIFO0_ITM_bytecount_Pos 27U TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) TPI_FIFO0_ETM_ATVALID_Pos 26U TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) TPI_FIFO0_ETM_bytecount_Pos 24U TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) TPI_FIFO0_ETM2_Pos 16U TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) TPI_FIFO0_ETM1_Pos 8U TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) TPI_FIFO0_ETM0_Pos 0U TPI_FIFO0_ETM0_Msk (0xFFUL ) TPI_ITATBCTR2_ATREADY_Pos 0U TPI_ITATBCTR2_ATREADY_Msk (0x1UL ) TPI_FIFO1_ITM_ATVALID_Pos 29U TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) TPI_FIFO1_ITM_bytecount_Pos 27U TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) TPI_FIFO1_ETM_ATVALID_Pos 26U TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) TPI_FIFO1_ETM_bytecount_Pos 24U TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) TPI_FIFO1_ITM2_Pos 16U TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) TPI_FIFO1_ITM1_Pos 8U TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) TPI_FIFO1_ITM0_Pos 0U TPI_FIFO1_ITM0_Msk (0xFFUL ) TPI_ITATBCTR0_ATREADY_Pos 0U TPI_ITATBCTR0_ATREADY_Msk (0x1UL ) TPI_ITCTRL_Mode_Pos 0U TPI_ITCTRL_Mode_Msk (0x1UL ) TPI_DEVID_NRZVALID_Pos 11U TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) TPI_DEVID_MANCVALID_Pos 10U TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) TPI_DEVID_PTINVALID_Pos 9U TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) TPI_DEVID_MinBufSz_Pos 6U TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) TPI_DEVID_AsynClkIn_Pos 5U TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) TPI_DEVID_NrTraceInput_Pos 0U TPI_DEVID_NrTraceInput_Msk (0x1FUL ) TPI_DEVTYPE_MajorType_Pos 4U TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) TPI_DEVTYPE_SubType_Pos 0U TPI_DEVTYPE_SubType_Msk (0xFUL ) MPU_TYPE_IREGION_Pos 16U MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) MPU_TYPE_DREGION_Pos 8U MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) MPU_TYPE_SEPARATE_Pos 0U MPU_TYPE_SEPARATE_Msk (1UL ) MPU_CTRL_PRIVDEFENA_Pos 2U MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) MPU_CTRL_HFNMIENA_Pos 1U MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) MPU_CTRL_ENABLE_Pos 0U MPU_CTRL_ENABLE_Msk (1UL ) MPU_RNR_REGION_Pos 0U MPU_RNR_REGION_Msk (0xFFUL ) MPU_RBAR_ADDR_Pos 5U MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) MPU_RBAR_VALID_Pos 4U MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) MPU_RBAR_REGION_Pos 0U MPU_RBAR_REGION_Msk (0xFUL ) MPU_RASR_ATTRS_Pos 16U MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) MPU_RASR_XN_Pos 28U MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) MPU_RASR_AP_Pos 24U MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) MPU_RASR_TEX_Pos 19U MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) MPU_RASR_S_Pos 18U MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) MPU_RASR_C_Pos 17U MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) MPU_RASR_B_Pos 16U MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) MPU_RASR_SRD_Pos 8U MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) MPU_RASR_SIZE_Pos 1U MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) MPU_RASR_ENABLE_Pos 0U MPU_RASR_ENABLE_Msk (1UL ) FPU_FPCCR_ASPEN_Pos 31U FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) FPU_FPCCR_LSPEN_Pos 30U FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) FPU_FPCCR_MONRDY_Pos 8U FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) FPU_FPCCR_BFRDY_Pos 6U FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) FPU_FPCCR_MMRDY_Pos 5U FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) FPU_FPCCR_HFRDY_Pos 4U FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) FPU_FPCCR_THREAD_Pos 3U FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) FPU_FPCCR_USER_Pos 1U FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) FPU_FPCCR_LSPACT_Pos 0U FPU_FPCCR_LSPACT_Msk (1UL ) FPU_FPCAR_ADDRESS_Pos 3U FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) FPU_FPDSCR_AHP_Pos 26U FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) FPU_FPDSCR_DN_Pos 25U FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) FPU_FPDSCR_FZ_Pos 24U FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) FPU_FPDSCR_RMode_Pos 22U FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) FPU_MVFR0_FP_rounding_modes_Pos 28U FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) FPU_MVFR0_Short_vectors_Pos 24U FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) FPU_MVFR0_Square_root_Pos 20U FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) FPU_MVFR0_Divide_Pos 16U FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) FPU_MVFR0_FP_excep_trapping_Pos 12U FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) FPU_MVFR0_Double_precision_Pos 8U FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) FPU_MVFR0_Single_precision_Pos 4U FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) FPU_MVFR0_A_SIMD_registers_Pos 0U FPU_MVFR0_A_SIMD_registers_Msk (0xFUL ) FPU_MVFR1_FP_fused_MAC_Pos 28U FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) FPU_MVFR1_FP_HPFP_Pos 24U FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) FPU_MVFR1_D_NaN_mode_Pos 4U FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) FPU_MVFR1_FtZ_mode_Pos 0U FPU_MVFR1_FtZ_mode_Msk (0xFUL ) CoreDebug_DHCSR_DBGKEY_Pos 16U CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) CoreDebug_DHCSR_S_RESET_ST_Pos 25U CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) CoreDebug_DHCSR_S_LOCKUP_Pos 19U CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) CoreDebug_DHCSR_S_SLEEP_Pos 18U CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) CoreDebug_DHCSR_S_HALT_Pos 17U CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) CoreDebug_DHCSR_S_REGRDY_Pos 16U CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) CoreDebug_DHCSR_C_MASKINTS_Pos 3U CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) CoreDebug_DHCSR_C_STEP_Pos 2U CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) CoreDebug_DHCSR_C_HALT_Pos 1U CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) CoreDebug_DHCSR_C_DEBUGEN_Pos 0U CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) CoreDebug_DCRSR_REGWnR_Pos 16U CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) CoreDebug_DCRSR_REGSEL_Pos 0U CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) CoreDebug_DEMCR_TRCENA_Pos 24U CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) CoreDebug_DEMCR_MON_REQ_Pos 19U CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) CoreDebug_DEMCR_MON_STEP_Pos 18U CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) CoreDebug_DEMCR_MON_PEND_Pos 17U CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) CoreDebug_DEMCR_MON_EN_Pos 16U CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) CoreDebug_DEMCR_VC_HARDERR_Pos 10U CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) CoreDebug_DEMCR_VC_INTERR_Pos 9U CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) CoreDebug_DEMCR_VC_BUSERR_Pos 8U CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) CoreDebug_DEMCR_VC_STATERR_Pos 7U CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) CoreDebug_DEMCR_VC_CHKERR_Pos 6U CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) CoreDebug_DEMCR_VC_NOCPERR_Pos 5U CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) CoreDebug_DEMCR_VC_MMERR_Pos 4U CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) CoreDebug_DEMCR_VC_CORERESET_Pos 0U CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) _VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) _FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) SCS_BASE (0xE000E000UL) ITM_BASE (0xE0000000UL) DWT_BASE (0xE0001000UL) TPI_BASE (0xE0040000UL) CoreDebug_BASE (0xE000EDF0UL) SysTick_BASE (SCS_BASE + 0x0010UL) NVIC_BASE (SCS_BASE + 0x0100UL) SCB_BASE (SCS_BASE + 0x0D00UL) SCnSCB ((SCnSCB_Type *) SCS_BASE ) SCB ((SCB_Type *) SCB_BASE ) SysTick ((SysTick_Type *) SysTick_BASE ) NVIC ((NVIC_Type *) NVIC_BASE ) ITM ((ITM_Type *) ITM_BASE ) DWT ((DWT_Type *) DWT_BASE ) TPI ((TPI_Type *) TPI_BASE ) CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) MPU_BASE (SCS_BASE + 0x0D90UL) MPU ((MPU_Type *) MPU_BASE ) FPU_BASE (SCS_BASE + 0x0F30UL) FPU ((FPU_Type *) FPU_BASE )NVIC_SetPriorityGrouping __NVIC_SetPriorityGroupingNVIC_GetPriorityGrouping __NVIC_GetPriorityGroupingNVIC_EnableIRQ __NVIC_EnableIRQNVIC_GetEnableIRQ __NVIC_GetEnableIRQNVIC_DisableIRQ __NVIC_DisableIRQNVIC_GetPendingIRQ __NVIC_GetPendingIRQNVIC_SetPendingIRQ __NVIC_SetPendingIRQNVIC_ClearPendingIRQ __NVIC_ClearPendingIRQNVIC_GetActive __NVIC_GetActiveNVIC_SetPriority __NVIC_SetPriorityNVIC_GetPriority __NVIC_GetPriorityNVIC_SystemReset __NVIC_SystemResetNVIC_SetVector __NVIC_SetVectorNVIC_GetVector __NVIC_GetVectorNVIC_USER_IRQ_OFFSET 16CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)#$%&+FLEXSPI_LUT_KEY_VAL (0x5AF05AF0ul),FLEXSPI_WAIT_TIMEOUT_NS (500000000UL)-FLEXSPI_FREQ_1GHz (1000000000UL)/FREQ_1MHz (1000000UL)0FLEXSPI_DLLCR_DEFAULT (0x100UL)2FLEXSPI0_CLK_GATE_OFFSET 13U3FLEXSPI1_CLK_GATE_OFFSET 15U5CMD_LUT_FOR_IP_CMD 1=FLEXSPI_PINMUX_VAL 0x08'__FSL_FLEXSPI_H__ )/FlexSPI_LUT_COUNT (64)1FlexSPI_AHB_RX_BUF_COUNT (4U)3FlexSPI_ASFM_BASE (0x00000000U)5FlexSPI_AHB_RX_BUF_DEPTH (512U)7FlexSPI_AHB_TX_BUF_DEPTH (32U)9FlexSPI_IP_RX_BUF_DEPTH (256U);FlexSPI_IP_TX_BUF_DEPTH (256U)>FLEXSPI_CFG_BLK_TAG (0x42464346UL)?FLEXSPI_CFG_BLK_VERSION (0x56010400UL)@FLEXSPI_CFG_BLK_SIZE (512)CFLEXSPI_FEATURE_HAS_PARALLEL_MODE 1FCMD_INDEX_READ 0GCMD_INDEX_READSTATUS 1HCMD_INDEX_WRITEENABLE 2ICMD_INDEX_WRITE 4KCMD_LUT_SEQ_IDX_READ 0LCMD_LUT_SEQ_IDX_READSTATUS 1MCMD_LUT_SEQ_IDX_WRITEENABLE 3NCMD_LUT_SEQ_IDX_WRITE 9PCMD_SDR 0x01QCMD_DDR 0x21RRADDR_SDR 0x02SRADDR_DDR 0x22TCADDR_SDR 0x03UCADDR_DDR 0x23VMODE1_SDR 0x04WMODE1_DDR 0x24XMODE2_SDR 0x05YMODE2_DDR 0x25ZMODE4_SDR 0x06[MODE4_DDR 0x26\MODE8_SDR 0x07]MODE8_DDR 0x27^WRITE_SDR 0x08_WRITE_DDR 0x28`READ_SDR 0x09aREAD_DDR 0x29bLEARN_SDR 0x0AcLEARN_DDR 0x2AdDATSZ_SDR 0x0BeDATSZ_DDR 0x2BfDUMMY_SDR 0x0CgDUMMY_DDR 0x2ChDUMMY_RWDS_SDR 0x0DiDUMMY_RWDS_DDR 0x2DjJMP_ON_CS 0x1FkSTOP 0mFLEXSPI_1PAD 0nFLEXSPI_2PAD 1oFLEXSPI_4PAD 2pFLEXSPI_8PAD 3rFLEXSPI_LUT_SEQ(cmd0,pad0,op0,cmd1,pad1,op1) (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset))&'()*0MAX_24BIT_ADDRESSING_SIZE (16UL * 1024 * 1024)2NOR_CMD_LUT_FOR_IP_CMD 1~SFDP_SIGNATURE 0x50444653'__FLEXSPI_NOR_FLASH_H__ )*-NOR_CMD_INDEX_READ CMD_INDEX_READ.NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS/NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE0NOR_CMD_INDEX_ERASESECTOR 31NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE2NOR_CMD_INDEX_CHIPERASE 53NOR_CMD_INDEX_DUMMY 64NOR_CMD_INDEX_ERASEBLOCK 76NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ7NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS9NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2;NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE=NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4?NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5@NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8ANOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITECNOR_CMD_LUT_SEQ_IDX_CHIPERASE 11DNOR_CMD_LUT_SEQ_IDX_READ_SFDP 13ENOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14GNOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 %FREQ_396MHz (396000000U)&FREQ_480MHz (480000000U)'FREQ_528MHz (528000000U)(FREQ_24MHz (24000000U)+SW_MUX_CTL_PAD_FLEXSPIB_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05,SW_MUX_CTL_PAD_FLEXSPIB_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00-SW_MUX_CTL_PAD_FLEXSPIB_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01.SW_MUX_CTL_PAD_FLEXSPIB_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02/SW_MUX_CTL_PAD_FLEXSPIB_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_030SW_MUX_CTL_PAD_FLEXSPIB_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_041SW_MUX_CTL_PAD_FLEXSPIB_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_012SW_MUX_CTL_PAD_FLEXSPIB_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_044SW_MUX_CTL_PAD_FLEXSPIA_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_055SW_MUX_CTL_PAD_FLEXSPIA_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_066SW_MUX_CTL_PAD_FLEXSPIA_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_007SW_MUX_CTL_PAD_FLEXSPIA_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_078SW_MUX_CTL_PAD_FLEXSPIA_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_089SW_MUX_CTL_PAD_FLEXSPIA_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09:SW_MUX_CTL_PAD_FLEXSPIA_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10;SW_MUX_CTL_PAD_FLEXSPIA_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11SW_PAD_CTL_PAD_FLEXSPIB_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05?SW_PAD_CTL_PAD_FLEXSPIB_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00@SW_PAD_CTL_PAD_FLEXSPIB_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01ASW_PAD_CTL_PAD_FLEXSPIB_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02BSW_PAD_CTL_PAD_FLEXSPIB_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03CSW_PAD_CTL_PAD_FLEXSPIB_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04DSW_PAD_CTL_PAD_FLEXSPIB_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01ESW_PAD_CTL_PAD_FLEXSPIB_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04GSW_PAD_CTL_PAD_FLEXSPIA_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05HSW_PAD_CTL_PAD_FLEXSPIA_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06ISW_PAD_CTL_PAD_FLEXSPIA_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00JSW_PAD_CTL_PAD_FLEXSPIA_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07KSW_PAD_CTL_PAD_FLEXSPIA_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08LSW_PAD_CTL_PAD_FLEXSPIA_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09MSW_PAD_CTL_PAD_FLEXSPIA_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10NSW_PAD_CTL_PAD_FLEXSPIA_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11OSW_PAD_CTL_PAD_FLEXSPIA_SCLK_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04QFLEXSPIA_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1)RFLEXSPIB_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1)SFLEXSPIA_SS1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(6)TFLEXSPIB_SS1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(6)UFLEXSPIB_SS0_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4)VFLEXSPIB_DQS_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4)]FLEXSPI_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(0) | IOMUXC_SW_PAD_CTL_PAD_PUS(0))gFLEXSPI_DQS_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | IOMUXC_SW_PAD_CTL_PAD_HYS(1)) %FREQ_396MHz (396UL * 1000 * 1000)&FREQ_528MHz (528UL * 1000 * 1000)'FREQ_24MHz (24UL * 1000 * 1000)(FREQ_480MHz (480UL * 1000 * 1000) _FSL_COMMON_H_ "#$%&,8MAKE_STATUS(group,code) ((((group)*100) + (code)));MAKE_VERSION(major,minor,bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))@FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))DDEBUG_CONSOLE_DEVICE_TYPE_NONE 0UEDEBUG_CONSOLE_DEVICE_TYPE_UART 1UFDEBUG_CONSOLE_DEVICE_TYPE_LPUART 2UGDEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3UHDEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4UIDEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5UJDEBUG_CONSOLE_DEVICE_TYPE_IUART 6UKDEBUG_CONSOLE_DEVICE_TYPE_VUSART 7UMIN(a,b) ((a) < (b) ? (a) : (b))MAX(a,b) ((a) > (b) ? (a) : (b))ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))USEC_TO_COUNT(us,clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)COUNT_TO_USEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)MSEC_TO_COUNT(ms,clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)COUNT_TO_MSEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)SDK_ALIGN(var,alignbytes) __align(alignbytes) varSDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) varSDK_SIZEALIGN(var,alignbytes) ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) varAT_NONCACHEABLE_SECTION_ALIGN(var,alignbytes) __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) varAT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) varAT_NONCACHEABLE_SECTION_ALIGN_INIT(var,alignbytes) __attribute__((section("NonCacheable.init"))) __align(alignbytes) varALIGN_DOWN(x,a) ((x) & -(a))ALIGN_UP(x,a) (-(-(x) & -(a)))#_FSL_CLOCK_H_ %&'(6FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))9CCM_TUPLE(reg,shift,mask,busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)):CCM_TUPLE_REG(base,tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU))));CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))=CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)?CCM_NO_BUSY_WAIT (0x20U)DCCM_ANALOG_TUPLE(reg,shift) ((((uint32_t)(&((CCM_ANALOG_Type *)0U) -> reg) & 0xFFFU) << 16U) | (shift))ECCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)FCCM_ANALOG_TUPLE_REG_OFF(base,tuple,off) (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))GCCM_ANALOG_TUPLE_REG(base,tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)ICCM_ANALOG_PLL_BYPASS_SHIFT (16U)JCCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)KCCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)XFSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0^CLKPN_FREQ 0UtCLOCK_SetXtal0Freq CLOCK_SetXtalFrequCLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreqxADC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 }~AOI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Aoi1 }BEE_CLOCKS { kCLOCK_Bee }CMP_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 }DCDC_CLOCKS { kCLOCK_Dcdc }DCP_CLOCKS { kCLOCK_Dcp }DMAMUX_CLOCKS { kCLOCK_Dma }EDMA_CLOCKS { kCLOCK_Dma }ENC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2 }ENET_CLOCKS { kCLOCK_Enet }EWM_CLOCKS { kCLOCK_Ewm0 }FLEXCAN_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 }FLEXCAN_PERIPH_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S }FLEXIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Flexio1 }FLEXRAM_CLOCKS { kCLOCK_FlexRam }FLEXSPI_CLOCKS { kCLOCK_FlexSpi }GPIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 }GPT_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 }KPP_CLOCKS { kCLOCK_Kpp }LPI2C_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 }LPSPI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 }LPUART_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 }PIT_CLOCKS { kCLOCK_Pit }PWM_CLOCKS { { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid } , { kCLOCK_Pwm1, kCLOCK_Pwm1,kCLOCK_Pwm1, kCLOCK_Pwm1 } , { kCLOCK_Pwm2, kCLOCK_Pwm2,kCLOCK_Pwm2, kCLOCK_Pwm2 } }RTWDOG_CLOCKS { kCLOCK_Wdog3 }SAI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 }SEMC_CLOCKS { kCLOCK_Semc }TMR_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2 }TRNG_CLOCKS { kCLOCK_Trng }WDOG_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 }USDHC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 }SPDIF_CLOCKS { kCLOCK_Spdif }XBARA_CLOCKS { kCLOCK_Xbar1 }XBARB_CLOCKS { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2 }kCLOCK_CoreSysClk kCLOCK_CpuClkCLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq"##_FSL_CLOCK_H_ %&'(6FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))9CCM_TUPLE(reg,shift,mask,busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)):CCM_TUPLE_REG(base,tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU))));CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))=CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)?CCM_NO_BUSY_WAIT (0x20U)DCCM_ANALOG_TUPLE(reg,shift) ((((uint32_t)(&((CCM_ANALOG_Type *)0U) -> reg) & 0xFFFU) << 16U) | (shift))ECCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)FCCM_ANALOG_TUPLE_REG_OFF(base,tuple,off) (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))GCCM_ANALOG_TUPLE_REG(base,tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)ICCM_ANALOG_PLL_BYPASS_SHIFT (16U)JCCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)KCCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)XFSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0^CLKPN_FREQ 0UtCLOCK_SetXtal0Freq CLOCK_SetXtalFrequCLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreqxADC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 }~AOI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Aoi1 }BEE_CLOCKS { kCLOCK_Bee }CMP_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 }DCDC_CLOCKS { kCLOCK_Dcdc }DCP_CLOCKS { kCLOCK_Dcp }DMAMUX_CLOCKS { kCLOCK_Dma }EDMA_CLOCKS { kCLOCK_Dma }ENC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2 }ENET_CLOCKS { kCLOCK_Enet }EWM_CLOCKS { kCLOCK_Ewm0 }FLEXCAN_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 }FLEXCAN_PERIPH_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S }FLEXIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Flexio1 }FLEXRAM_CLOCKS { kCLOCK_FlexRam }FLEXSPI_CLOCKS { kCLOCK_FlexSpi }GPIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 }GPT_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 }KPP_CLOCKS { kCLOCK_Kpp }LPI2C_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 }LPSPI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 }LPUART_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 }PIT_CLOCKS { kCLOCK_Pit }PWM_CLOCKS { { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid } , { kCLOCK_Pwm1, kCLOCK_Pwm1,kCLOCK_Pwm1, kCLOCK_Pwm1 } , { kCLOCK_Pwm2, kCLOCK_Pwm2,kCLOCK_Pwm2, kCLOCK_Pwm2 } }RTWDOG_CLOCKS { kCLOCK_Wdog3 }SAI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 }SEMC_CLOCKS { kCLOCK_Semc }TMR_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2 }TRNG_CLOCKS { kCLOCK_Trng }WDOG_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 }USDHC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 }SPDIF_CLOCKS { kCLOCK_Spdif }XBARA_CLOCKS { kCLOCK_Xbar1 }XBARB_CLOCKS { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2 }kCLOCK_CoreSysClk kCLOCK_CpuClkCLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq '__FLEXSPI_NOR_FLASH_H__ )*-NOR_CMD_INDEX_READ CMD_INDEX_READ.NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS/NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE0NOR_CMD_INDEX_ERASESECTOR 31NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE2NOR_CMD_INDEX_CHIPERASE 53NOR_CMD_INDEX_DUMMY 64NOR_CMD_INDEX_ERASEBLOCK 76NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ7NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS9NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2;NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE=NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4?NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5@NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8ANOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITECNOR_CMD_LUT_SEQ_IDX_CHIPERASE 11DNOR_CMD_LUT_SEQ_IDX_READ_SFDP 13ENOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14GNOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15'__FSL_FLEXSPI_H__ )/FlexSPI_LUT_COUNT (64)1FlexSPI_AHB_RX_BUF_COUNT (4U)3FlexSPI_ASFM_BASE (0x00000000U)5FlexSPI_AHB_RX_BUF_DEPTH (512U)7FlexSPI_AHB_TX_BUF_DEPTH (32U)9FlexSPI_IP_RX_BUF_DEPTH (256U);FlexSPI_IP_TX_BUF_DEPTH (256U)>FLEXSPI_CFG_BLK_TAG (0x42464346UL)?FLEXSPI_CFG_BLK_VERSION (0x56010400UL)@FLEXSPI_CFG_BLK_SIZE (512)CFLEXSPI_FEATURE_HAS_PARALLEL_MODE 1FCMD_INDEX_READ 0GCMD_INDEX_READSTATUS 1HCMD_INDEX_WRITEENABLE 2ICMD_INDEX_WRITE 4KCMD_LUT_SEQ_IDX_READ 0LCMD_LUT_SEQ_IDX_READSTATUS 1MCMD_LUT_SEQ_IDX_WRITEENABLE 3NCMD_LUT_SEQ_IDX_WRITE 9PCMD_SDR 0x01QCMD_DDR 0x21RRADDR_SDR 0x02SRADDR_DDR 0x22TCADDR_SDR 0x03UCADDR_DDR 0x23VMODE1_SDR 0x04WMODE1_DDR 0x24XMODE2_SDR 0x05YMODE2_DDR 0x25ZMODE4_SDR 0x06[MODE4_DDR 0x26\MODE8_SDR 0x07]MODE8_DDR 0x27^WRITE_SDR 0x08_WRITE_DDR 0x28`READ_SDR 0x09aREAD_DDR 0x29bLEARN_SDR 0x0AcLEARN_DDR 0x2AdDATSZ_SDR 0x0BeDATSZ_DDR 0x2BfDUMMY_SDR 0x0CgDUMMY_DDR 0x2ChDUMMY_RWDS_SDR 0x0DiDUMMY_RWDS_DDR 0x2DjJMP_ON_CS 0x1FkSTOP 0mFLEXSPI_1PAD 0nFLEXSPI_2PAD 1oFLEXSPI_4PAD 2pFLEXSPI_8PAD 3rFLEXSPI_LUT_SEQ(cmd0,pad0,op0,cmd1,pad1,op1) (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset)) _FSL_COMMON_H_ "#$%&,8MAKE_STATUS(group,code) ((((group)*100) + (code)));MAKE_VERSION(major,minor,bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))@FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))DDEBUG_CONSOLE_DEVICE_TYPE_NONE 0UEDEBUG_CONSOLE_DEVICE_TYPE_UART 1UFDEBUG_CONSOLE_DEVICE_TYPE_LPUART 2UGDEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3UHDEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4UIDEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5UJDEBUG_CONSOLE_DEVICE_TYPE_IUART 6UKDEBUG_CONSOLE_DEVICE_TYPE_VUSART 7UMIN(a,b) ((a) < (b) ? (a) : (b))MAX(a,b) ((a) > (b) ? (a) : (b))ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))USEC_TO_COUNT(us,clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)COUNT_TO_USEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)MSEC_TO_COUNT(ms,clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)COUNT_TO_MSEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)SDK_ALIGN(var,alignbytes) __align(alignbytes) varSDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) varSDK_SIZEALIGN(var,alignbytes) ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) varAT_NONCACHEABLE_SECTION_ALIGN(var,alignbytes) __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) varAT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) varAT_NONCACHEABLE_SECTION_ALIGN_INIT(var,alignbytes) __attribute__((section("NonCacheable.init"))) __align(alignbytes) varALIGN_DOWN(x,a) ((x) & -(a))ALIGN_UP(x,a) (-(-(x) & -(a)))K_MIMXRT1021_H_ OMCU_MEM_MAP_VERSION 0x0000UQMCU_MEM_MAP_VERSION_MINOR 0x0001U^NUMBER_OF_INT_VECTORS 158__MPU_PRESENT 1__ICACHE_PRESENT 1__DCACHE_PRESENT 1__DTCM_PRESENT 1__NVIC_PRIO_BITS 4__Vendor_SysTickConfig 0__FPU_PRESENT 1ADC_HC_ADCH_MASK (0x1FU)ADC_HC_ADCH_SHIFT (0U)ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)ADC_HC_AIEN_MASK (0x80U)ADC_HC_AIEN_SHIFT (7U)ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)ADC_HC_COUNT (8U)ADC_HS_COCO0_MASK (0x1U)ADC_HS_COCO0_SHIFT (0U)ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)ADC_R_CDATA_MASK (0xFFFU)ADC_R_CDATA_SHIFT (0U)ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)ADC_R_COUNT (8U) ADC_CFG_ADICLK_MASK (0x3U) ADC_CFG_ADICLK_SHIFT (0U) ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) ADC_CFG_MODE_MASK (0xCU) ADC_CFG_MODE_SHIFT (2U) ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) ADC_CFG_ADLSMP_MASK (0x10U) ADC_CFG_ADLSMP_SHIFT (4U) ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) ADC_CFG_ADIV_MASK (0x60U) ADC_CFG_ADIV_SHIFT (5U) ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) ADC_CFG_ADLPC_MASK (0x80U) ADC_CFG_ADLPC_SHIFT (7U) ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) ADC_CFG_ADSTS_MASK (0x300U) ADC_CFG_ADSTS_SHIFT (8U) ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) ADC_CFG_ADHSC_MASK (0x400U) ADC_CFG_ADHSC_SHIFT (10U) ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) ADC_CFG_REFSEL_MASK (0x1800U) ADC_CFG_REFSEL_SHIFT (11U) ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) ADC_CFG_ADTRG_MASK (0x2000U) ADC_CFG_ADTRG_SHIFT (13U) ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) ADC_CFG_AVGS_MASK (0xC000U) ADC_CFG_AVGS_SHIFT (14U) ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) ADC_CFG_OVWREN_MASK (0x10000U) ADC_CFG_OVWREN_SHIFT (16U) ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) ADC_GC_ADACKEN_MASK (0x1U) ADC_GC_ADACKEN_SHIFT (0U) ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) ADC_GC_DMAEN_MASK (0x2U) ADC_GC_DMAEN_SHIFT (1U) ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) ADC_GC_ACREN_MASK (0x4U) ADC_GC_ACREN_SHIFT (2U) ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) ADC_GC_ACFGT_MASK (0x8U) ADC_GC_ACFGT_SHIFT (3U) ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) ADC_GC_ACFE_MASK (0x10U) ADC_GC_ACFE_SHIFT (4U) ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) ADC_GC_AVGE_MASK (0x20U) ADC_GC_AVGE_SHIFT (5U) ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) ADC_GC_ADCO_MASK (0x40U) ADC_GC_ADCO_SHIFT (6U) ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) ADC_GC_CAL_MASK (0x80U) ADC_GC_CAL_SHIFT (7U) ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) ADC_GS_ADACT_MASK (0x1U) ADC_GS_ADACT_SHIFT (0U) ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) ADC_GS_CALF_MASK (0x2U) ADC_GS_CALF_SHIFT (1U) ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) ADC_GS_AWKST_MASK (0x4U) ADC_GS_AWKST_SHIFT (2U) ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) ADC_CV_CV1_MASK (0xFFFU) ADC_CV_CV1_SHIFT (0U) ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) ADC_CV_CV2_MASK (0xFFF0000U) ADC_CV_CV2_SHIFT (16U) ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) ADC_OFS_OFS_MASK (0xFFFU) ADC_OFS_OFS_SHIFT (0U) ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) ADC_OFS_SIGN_MASK (0x1000U) ADC_OFS_SIGN_SHIFT (12U) ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) ADC_CAL_CAL_CODE_MASK (0xFU) ADC_CAL_CAL_CODE_SHIFT (0U) ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) ADC1_BASE (0x400C4000u) ADC1 ((ADC_Type *)ADC1_BASE) ADC2_BASE (0x400C8000u) ADC2 ((ADC_Type *)ADC2_BASE) ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) ADC_ETC_CTRL_SOFTRST_SHIFT (31U) ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) ADC_ETC_TRIGn_CTRL_COUNT (8U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) ADC_ETC_TRIGn_COUNTER_COUNT (8U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) ADC_ETC_BASE (0x403B0000u) ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } ADC_ETC_BASE_PTRS { ADC_ETC } ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } AIPSTZ_MPR_MPROT5_MASK (0xF00U) AIPSTZ_MPR_MPROT5_SHIFT (8U) AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) AIPSTZ_MPR_MPROT3_MASK (0xF0000U) AIPSTZ_MPR_MPROT3_SHIFT (16U) AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) AIPSTZ_MPR_MPROT2_MASK (0xF00000U) AIPSTZ_MPR_MPROT2_SHIFT (20U) AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) AIPSTZ_MPR_MPROT1_MASK (0xF000000U) AIPSTZ_MPR_MPROT1_SHIFT (24U) AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) AIPSTZ_MPR_MPROT0_SHIFT (28U) AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) AIPSTZ_OPACR_OPAC7_MASK (0xFU)AIPSTZ_OPACR_OPAC7_SHIFT (0U)AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)AIPSTZ_OPACR_OPAC6_MASK (0xF0U)AIPSTZ_OPACR_OPAC6_SHIFT (4U)AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)AIPSTZ_OPACR_OPAC5_MASK (0xF00U)AIPSTZ_OPACR_OPAC5_SHIFT (8U)AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)AIPSTZ_OPACR_OPAC4_MASK (0xF000U)AIPSTZ_OPACR_OPAC4_SHIFT (12U)AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)AIPSTZ_OPACR_OPAC3_SHIFT (16U)AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)AIPSTZ_OPACR_OPAC2_SHIFT (20U)AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)AIPSTZ_OPACR_OPAC1_SHIFT (24U)AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)AIPSTZ_OPACR_OPAC0_SHIFT (28U)AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)AIPSTZ_OPACR1_OPAC15_MASK (0xFU)AIPSTZ_OPACR1_OPAC15_SHIFT (0U)AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)AIPSTZ_OPACR1_OPAC14_SHIFT (4U)AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)AIPSTZ_OPACR1_OPAC13_SHIFT (8U)AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)AIPSTZ_OPACR1_OPAC12_SHIFT (12U)AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)AIPSTZ_OPACR1_OPAC11_SHIFT (16U)AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)AIPSTZ_OPACR1_OPAC10_SHIFT (20U)AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)AIPSTZ_OPACR1_OPAC9_SHIFT (24U)AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)AIPSTZ_OPACR1_OPAC8_SHIFT (28U)AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)AIPSTZ_OPACR2_OPAC23_MASK (0xFU)AIPSTZ_OPACR2_OPAC23_SHIFT (0U)AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)AIPSTZ_OPACR2_OPAC22_SHIFT (4U)AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)AIPSTZ_OPACR2_OPAC21_SHIFT (8U)AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)AIPSTZ_OPACR2_OPAC20_SHIFT (12U)AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)AIPSTZ_OPACR2_OPAC19_SHIFT (16U)AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)AIPSTZ_OPACR2_OPAC18_SHIFT (20U)AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)AIPSTZ_OPACR2_OPAC17_SHIFT (24U)AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)AIPSTZ_OPACR2_OPAC16_SHIFT (28U)AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)AIPSTZ_OPACR3_OPAC31_MASK (0xFU)AIPSTZ_OPACR3_OPAC31_SHIFT (0U)AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)AIPSTZ_OPACR3_OPAC30_SHIFT (4U)AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)AIPSTZ_OPACR3_OPAC29_SHIFT (8U)AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)AIPSTZ_OPACR3_OPAC28_SHIFT (12U)AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)AIPSTZ_OPACR3_OPAC27_SHIFT (16U)AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)AIPSTZ_OPACR3_OPAC26_SHIFT (20U)AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)AIPSTZ_OPACR3_OPAC25_SHIFT (24U)AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)AIPSTZ_OPACR3_OPAC24_SHIFT (28U)AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)AIPSTZ_OPACR4_OPAC33_SHIFT (24U)AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)AIPSTZ_OPACR4_OPAC32_SHIFT (28U)AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)AIPSTZ1_BASE (0x4007C000u)AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)AIPSTZ2_BASE (0x4017C000u)AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)AIPSTZ3_BASE (0x4027C000u)AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)AIPSTZ4_BASE (0x4037C000u)AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }AOI_BFCRT01_PT1_DC_MASK (0x3U)AOI_BFCRT01_PT1_DC_SHIFT (0U)AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)AOI_BFCRT01_PT1_CC_MASK (0xCU)AOI_BFCRT01_PT1_CC_SHIFT (2U)AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)AOI_BFCRT01_PT1_BC_MASK (0x30U)AOI_BFCRT01_PT1_BC_SHIFT (4U)AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)AOI_BFCRT01_PT1_AC_MASK (0xC0U)AOI_BFCRT01_PT1_AC_SHIFT (6U)AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)AOI_BFCRT01_PT0_DC_MASK (0x300U)AOI_BFCRT01_PT0_DC_SHIFT (8U)AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)AOI_BFCRT01_PT0_CC_MASK (0xC00U)AOI_BFCRT01_PT0_CC_SHIFT (10U)AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)AOI_BFCRT01_PT0_BC_MASK (0x3000U)AOI_BFCRT01_PT0_BC_SHIFT (12U)AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)AOI_BFCRT01_PT0_AC_MASK (0xC000U)AOI_BFCRT01_PT0_AC_SHIFT (14U)AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)AOI_BFCRT01_COUNT (4U)AOI_BFCRT23_PT3_DC_MASK (0x3U)AOI_BFCRT23_PT3_DC_SHIFT (0U)AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)AOI_BFCRT23_PT3_CC_MASK (0xCU)AOI_BFCRT23_PT3_CC_SHIFT (2U)AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)AOI_BFCRT23_PT3_BC_MASK (0x30U)AOI_BFCRT23_PT3_BC_SHIFT (4U)AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)AOI_BFCRT23_PT3_AC_MASK (0xC0U)AOI_BFCRT23_PT3_AC_SHIFT (6U)AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)AOI_BFCRT23_PT2_DC_MASK (0x300U)AOI_BFCRT23_PT2_DC_SHIFT (8U)AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)AOI_BFCRT23_PT2_CC_MASK (0xC00U)AOI_BFCRT23_PT2_CC_SHIFT (10U)AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)AOI_BFCRT23_PT2_BC_MASK (0x3000U)AOI_BFCRT23_PT2_BC_SHIFT (12U)AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)AOI_BFCRT23_PT2_AC_MASK (0xC000U)AOI_BFCRT23_PT2_AC_SHIFT (14U)AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)AOI_BFCRT23_COUNT (4U)AOI_BASE (0x403B4000u)AOI ((AOI_Type *)AOI_BASE)AOI_BASE_ADDRS { AOI_BASE }AOI_BASE_PTRS { AOI }CAN_MCR_MAXMB_MASK (0x7FU)CAN_MCR_MAXMB_SHIFT (0U)CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)CAN_MCR_IDAM_MASK (0x300U)CAN_MCR_IDAM_SHIFT (8U)CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)CAN_MCR_AEN_MASK (0x1000U)CAN_MCR_AEN_SHIFT (12U)CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)CAN_MCR_LPRIOEN_MASK (0x2000U)CAN_MCR_LPRIOEN_SHIFT (13U)CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)CAN_MCR_IRMQ_MASK (0x10000U)CAN_MCR_IRMQ_SHIFT (16U)CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)CAN_MCR_SRXDIS_MASK (0x20000U)CAN_MCR_SRXDIS_SHIFT (17U)CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)CAN_MCR_WAKSRC_MASK (0x80000U)CAN_MCR_WAKSRC_SHIFT (19U)CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)CAN_MCR_LPMACK_MASK (0x100000U)CAN_MCR_LPMACK_SHIFT (20U)CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)CAN_MCR_WRNEN_MASK (0x200000U)CAN_MCR_WRNEN_SHIFT (21U)CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)CAN_MCR_SLFWAK_MASK (0x400000U)CAN_MCR_SLFWAK_SHIFT (22U)CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)CAN_MCR_SUPV_MASK (0x800000U)CAN_MCR_SUPV_SHIFT (23U)CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)CAN_MCR_FRZACK_MASK (0x1000000U)CAN_MCR_FRZACK_SHIFT (24U)CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)CAN_MCR_SOFTRST_MASK (0x2000000U)CAN_MCR_SOFTRST_SHIFT (25U)CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)CAN_MCR_WAKMSK_MASK (0x4000000U)CAN_MCR_WAKMSK_SHIFT (26U)CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)CAN_MCR_NOTRDY_MASK (0x8000000U)CAN_MCR_NOTRDY_SHIFT (27U)CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)CAN_MCR_HALT_MASK (0x10000000U)CAN_MCR_HALT_SHIFT (28U)CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)CAN_MCR_RFEN_MASK (0x20000000U)CAN_MCR_RFEN_SHIFT (29U)CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)CAN_MCR_FRZ_MASK (0x40000000U)CAN_MCR_FRZ_SHIFT (30U)CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)CAN_MCR_MDIS_MASK (0x80000000U)CAN_MCR_MDIS_SHIFT (31U)CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)CAN_CTRL1_PROPSEG_MASK (0x7U)CAN_CTRL1_PROPSEG_SHIFT (0U)CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)CAN_CTRL1_LOM_MASK (0x8U)CAN_CTRL1_LOM_SHIFT (3U)CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)CAN_CTRL1_LBUF_MASK (0x10U)CAN_CTRL1_LBUF_SHIFT (4U)CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)CAN_CTRL1_TSYN_MASK (0x20U)CAN_CTRL1_TSYN_SHIFT (5U)CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)CAN_CTRL1_BOFFREC_MASK (0x40U)CAN_CTRL1_BOFFREC_SHIFT (6U)CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)CAN_CTRL1_SMP_MASK (0x80U)CAN_CTRL1_SMP_SHIFT (7U)CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)CAN_CTRL1_RWRNMSK_MASK (0x400U)CAN_CTRL1_RWRNMSK_SHIFT (10U)CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)CAN_CTRL1_TWRNMSK_MASK (0x800U)CAN_CTRL1_TWRNMSK_SHIFT (11U)CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)CAN_CTRL1_LPB_MASK (0x1000U)CAN_CTRL1_LPB_SHIFT (12U)CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)CAN_CTRL1_ERRMSK_MASK (0x4000U)CAN_CTRL1_ERRMSK_SHIFT (14U)CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)CAN_CTRL1_BOFFMSK_MASK (0x8000U)CAN_CTRL1_BOFFMSK_SHIFT (15U)CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)CAN_CTRL1_PSEG2_MASK (0x70000U)CAN_CTRL1_PSEG2_SHIFT (16U)CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)CAN_CTRL1_PSEG1_MASK (0x380000U)CAN_CTRL1_PSEG1_SHIFT (19U)CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)CAN_CTRL1_RJW_MASK (0xC00000U)CAN_CTRL1_RJW_SHIFT (22U)CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)CAN_CTRL1_PRESDIV_MASK (0xFF000000U)CAN_CTRL1_PRESDIV_SHIFT (24U)CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)CAN_TIMER_TIMER_MASK (0xFFFFU)CAN_TIMER_TIMER_SHIFT (0U)CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)CAN_RXMGMASK_MG_SHIFT (0U)CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)CAN_RX14MASK_RX14M_SHIFT (0U)CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)CAN_RX15MASK_RX15M_SHIFT (0U)CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)CAN_ESR1_WAKINT_MASK (0x1U)CAN_ESR1_WAKINT_SHIFT (0U)CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)CAN_ESR1_ERRINT_MASK (0x2U)CAN_ESR1_ERRINT_SHIFT (1U)CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)CAN_ESR1_BOFFINT_MASK (0x4U)CAN_ESR1_BOFFINT_SHIFT (2U)CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)CAN_ESR1_RX_MASK (0x8U)CAN_ESR1_RX_SHIFT (3U)CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)CAN_ESR1_FLTCONF_MASK (0x30U)CAN_ESR1_FLTCONF_SHIFT (4U)CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)CAN_ESR1_TX_MASK (0x40U)CAN_ESR1_TX_SHIFT (6U)CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)CAN_ESR1_IDLE_MASK (0x80U)CAN_ESR1_IDLE_SHIFT (7U)CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)CAN_ESR1_RXWRN_MASK (0x100U)CAN_ESR1_RXWRN_SHIFT (8U)CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)CAN_ESR1_TXWRN_MASK (0x200U)CAN_ESR1_TXWRN_SHIFT (9U)CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)CAN_ESR1_STFERR_MASK (0x400U)CAN_ESR1_STFERR_SHIFT (10U)CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)CAN_ESR1_FRMERR_MASK (0x800U)CAN_ESR1_FRMERR_SHIFT (11U)CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)CAN_ESR1_CRCERR_MASK (0x1000U)CAN_ESR1_CRCERR_SHIFT (12U)CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)CAN_ESR1_ACKERR_MASK (0x2000U)CAN_ESR1_ACKERR_SHIFT (13U)CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)CAN_ESR1_BIT0ERR_MASK (0x4000U)CAN_ESR1_BIT0ERR_SHIFT (14U)CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)CAN_ESR1_BIT1ERR_MASK (0x8000U)CAN_ESR1_BIT1ERR_SHIFT (15U)CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)CAN_ESR1_RWRNINT_MASK (0x10000U)CAN_ESR1_RWRNINT_SHIFT (16U)CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)CAN_ESR1_TWRNINT_MASK (0x20000U)CAN_ESR1_TWRNINT_SHIFT (17U)CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)CAN_ESR1_SYNCH_MASK (0x40000U)CAN_ESR1_SYNCH_SHIFT (18U)CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)CAN_IMASK2_BUFHM_SHIFT (0U)CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)CAN_IMASK1_BUFLM_SHIFT (0U)CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)CAN_IFLAG2_BUFHI_SHIFT (0U)CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)CAN_IFLAG1_BUF4TO0I_SHIFT (0U)CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)CAN_IFLAG1_BUF5I_MASK (0x20U)CAN_IFLAG1_BUF5I_SHIFT (5U)CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)CAN_IFLAG1_BUF6I_MASK (0x40U)CAN_IFLAG1_BUF6I_SHIFT (6U)CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)CAN_IFLAG1_BUF7I_MASK (0x80U)CAN_IFLAG1_BUF7I_SHIFT (7U)CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)CAN_IFLAG1_BUF31TO8I_SHIFT (8U)CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)CAN_CTRL2_EACEN_MASK (0x10000U)CAN_CTRL2_EACEN_SHIFT (16U)CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)CAN_CTRL2_RRS_MASK (0x20000U)CAN_CTRL2_RRS_SHIFT (17U)CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)CAN_CTRL2_MRP_MASK (0x40000U)CAN_CTRL2_MRP_SHIFT (18U)CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)CAN_CTRL2_TASD_MASK (0xF80000U)CAN_CTRL2_TASD_SHIFT (19U)CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)CAN_CTRL2_RFFN_MASK (0xF000000U)CAN_CTRL2_RFFN_SHIFT (24U)CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)CAN_CTRL2_WRMFRZ_MASK (0x10000000U)CAN_CTRL2_WRMFRZ_SHIFT (28U)CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)CAN_ESR2_IMB_MASK (0x2000U)CAN_ESR2_IMB_SHIFT (13U)CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)CAN_ESR2_VPS_MASK (0x4000U)CAN_ESR2_VPS_SHIFT (14U)CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)CAN_ESR2_LPTM_MASK (0x7F0000U)CAN_ESR2_LPTM_SHIFT (16U)CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)CAN_CRCR_TXCRC_MASK (0x7FFFU)CAN_CRCR_TXCRC_SHIFT (0U)CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)CAN_CRCR_MBCRC_MASK (0x7F0000U)CAN_CRCR_MBCRC_SHIFT (16U)CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)CAN_RXFGMASK_FGM_SHIFT (0U)CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)CAN_RXFIR_IDHIT_MASK (0x1FFU)CAN_RXFIR_IDHIT_SHIFT (0U)CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)CAN_CS_TIME_STAMP_MASK (0xFFFFU)CAN_CS_TIME_STAMP_SHIFT (0U)CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)CAN_CS_DLC_MASK (0xF0000U)CAN_CS_DLC_SHIFT (16U)CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)CAN_CS_RTR_MASK (0x100000U)CAN_CS_RTR_SHIFT (20U)CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)CAN_CS_IDE_MASK (0x200000U)CAN_CS_IDE_SHIFT (21U)CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)CAN_CS_SRR_MASK (0x400000U)CAN_CS_SRR_SHIFT (22U)CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)CAN_CS_CODE_MASK (0xF000000U)CAN_CS_CODE_SHIFT (24U)CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)CAN_CS_COUNT (64U)CAN_ID_EXT_MASK (0x3FFFFU)CAN_ID_EXT_SHIFT (0U)CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)CAN_ID_STD_MASK (0x1FFC0000U)CAN_ID_STD_SHIFT (18U)CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)CAN_ID_PRIO_MASK (0xE0000000U)CAN_ID_PRIO_SHIFT (29U)CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)CAN_ID_COUNT (64U)CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)CAN_WORD0_DATA_BYTE_3_SHIFT (0U)CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)CAN_WORD0_DATA_BYTE_2_SHIFT (8U)CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)CAN_WORD0_DATA_BYTE_1_SHIFT (16U)CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)CAN_WORD0_DATA_BYTE_0_SHIFT (24U)CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)CAN_WORD0_COUNT (64U)CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)CAN_WORD1_DATA_BYTE_7_SHIFT (0U)CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)CAN_WORD1_DATA_BYTE_6_SHIFT (8U)CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)CAN_WORD1_DATA_BYTE_5_SHIFT (16U)CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)CAN_WORD1_DATA_BYTE_4_SHIFT (24U)CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)CAN_WORD1_COUNT (64U)CAN_RXIMR_MI_MASK (0xFFFFFFFFU)CAN_RXIMR_MI_SHIFT (0U)CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)CAN_RXIMR_COUNT (64U)CAN_GFWR_GFWR_MASK (0xFFU)CAN_GFWR_GFWR_SHIFT (0U)CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)CAN1_BASE (0x401D0000u)CAN1 ((CAN_Type *)CAN1_BASE)CAN2_BASE (0x401D4000u)CAN2 ((CAN_Type *)CAN2_BASE)CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASKCAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFTCAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASKCAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFTCAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)CCM_CCR_OSCNT_MASK (0xFFU)CCM_CCR_OSCNT_SHIFT (0U)CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)CCM_CCR_COSC_EN_MASK (0x1000U)CCM_CCR_COSC_EN_SHIFT (12U)CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)CCM_CCR_RBC_EN_MASK (0x8000000U)CCM_CCR_RBC_EN_SHIFT (27U)CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)CCM_CSR_REF_EN_B_MASK (0x1U)CCM_CSR_REF_EN_B_SHIFT (0U)CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)CCM_CSR_CAMP2_READY_MASK (0x8U)CCM_CSR_CAMP2_READY_SHIFT (3U)CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)CCM_CSR_COSC_READY_MASK (0x20U)CCM_CSR_COSC_READY_SHIFT (5U)CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)CCM_CACRR_ARM_PODF_MASK (0x7U)CCM_CACRR_ARM_PODF_SHIFT (0U)CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)CCM_CBCDR_IPG_PODF_MASK (0x300U)CCM_CBCDR_IPG_PODF_SHIFT (8U)CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)CCM_CBCDR_AHB_PODF_MASK (0x1C00U)CCM_CBCDR_AHB_PODF_SHIFT (10U)CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)CCM_CBCDR_SEMC_PODF_MASK (0x70000U)CCM_CBCDR_SEMC_PODF_SHIFT (16U)CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)CCM_CBCMR_LPSPI_PODF_SHIFT (26U)CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U)CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U)CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK)CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)CCM_CSCDR1_TRACE_PODF_SHIFT (25U)CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U)CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U)CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK)CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0xE000000U)CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U)CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)CCM_CLPCR_LPM_MASK (0x3U)CCM_CLPCR_LPM_SHIFT (0U)CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)CCM_CLPCR_SBYOS_MASK (0x40U)CCM_CLPCR_SBYOS_SHIFT (6U)CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)CCM_CLPCR_VSTBY_MASK (0x100U)CCM_CLPCR_VSTBY_SHIFT (8U)CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)CCM_CLPCR_STBY_COUNT_MASK (0x600U)CCM_CLPCR_STBY_COUNT_SHIFT (9U)CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)CCM_CISR_LRF_PLL_MASK (0x1U)CCM_CISR_LRF_PLL_SHIFT (0U)CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)CCM_CISR_COSC_READY_MASK (0x40U)CCM_CISR_COSC_READY_SHIFT (6U)CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)CCM_CIMR_MASK_COSC_READY_MASK (0x40U)CCM_CIMR_MASK_COSC_READY_SHIFT (6U)CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)CCM_CCOSR_CLKO1_SEL_MASK (0xFU)CCM_CCOSR_CLKO1_SEL_SHIFT (0U)CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)CCM_CCOSR_CLKO1_DIV_MASK (0x70U)CCM_CCOSR_CLKO1_DIV_SHIFT (4U)CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)CCM_CCOSR_CLKO1_EN_MASK (0x80U)CCM_CCOSR_CLKO1_EN_SHIFT (7U)CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)CCM_CCOSR_CLKO2_SEL_SHIFT (16U)CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)CCM_CCOSR_CLKO2_DIV_SHIFT (21U)CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)CCM_CCOSR_CLKO2_EN_SHIFT (24U)CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)CCM_CGPR_FPL_MASK (0x10000U)CCM_CGPR_FPL_SHIFT (16U)CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)CCM_CCGR0_CG0_MASK (0x3U)CCM_CCGR0_CG0_SHIFT (0U)CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)CCM_CCGR0_CG1_MASK (0xCU)CCM_CCGR0_CG1_SHIFT (2U)CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)CCM_CCGR0_CG2_MASK (0x30U)CCM_CCGR0_CG2_SHIFT (4U)CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)CCM_CCGR0_CG3_MASK (0xC0U)CCM_CCGR0_CG3_SHIFT (6U)CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)CCM_CCGR0_CG4_MASK (0x300U)CCM_CCGR0_CG4_SHIFT (8U)CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)CCM_CCGR0_CG5_MASK (0xC00U)CCM_CCGR0_CG5_SHIFT (10U)CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)CCM_CCGR0_CG6_MASK (0x3000U)CCM_CCGR0_CG6_SHIFT (12U)CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)CCM_CCGR0_CG7_MASK (0xC000U)CCM_CCGR0_CG7_SHIFT (14U)CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)CCM_CCGR0_CG8_MASK (0x30000U)CCM_CCGR0_CG8_SHIFT (16U)CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)CCM_CCGR0_CG9_MASK (0xC0000U)CCM_CCGR0_CG9_SHIFT (18U)CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)CCM_CCGR0_CG10_MASK (0x300000U)CCM_CCGR0_CG10_SHIFT (20U)CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)CCM_CCGR0_CG11_MASK (0xC00000U)CCM_CCGR0_CG11_SHIFT (22U)CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)CCM_CCGR0_CG12_MASK (0x3000000U)CCM_CCGR0_CG12_SHIFT (24U)CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)CCM_CCGR0_CG13_MASK (0xC000000U)CCM_CCGR0_CG13_SHIFT (26U)CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)CCM_CCGR0_CG14_MASK (0x30000000U)CCM_CCGR0_CG14_SHIFT (28U)CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)CCM_CCGR0_CG15_MASK (0xC0000000U)CCM_CCGR0_CG15_SHIFT (30U)CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)CCM_CCGR1_CG0_MASK (0x3U)CCM_CCGR1_CG0_SHIFT (0U)CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)CCM_CCGR1_CG1_MASK (0xCU)CCM_CCGR1_CG1_SHIFT (2U)CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)CCM_CCGR1_CG2_MASK (0x30U)CCM_CCGR1_CG2_SHIFT (4U)CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)CCM_CCGR1_CG3_MASK (0xC0U)CCM_CCGR1_CG3_SHIFT (6U)CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)CCM_CCGR1_CG4_MASK (0x300U)CCM_CCGR1_CG4_SHIFT (8U)CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)CCM_CCGR1_CG5_MASK (0xC00U)CCM_CCGR1_CG5_SHIFT (10U)CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)CCM_CCGR1_CG6_MASK (0x3000U)CCM_CCGR1_CG6_SHIFT (12U)CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)CCM_CCGR1_CG7_MASK (0xC000U)CCM_CCGR1_CG7_SHIFT (14U)CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)CCM_CCGR1_CG8_MASK (0x30000U)CCM_CCGR1_CG8_SHIFT (16U)CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)CCM_CCGR1_CG9_MASK (0xC0000U)CCM_CCGR1_CG9_SHIFT (18U)CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)CCM_CCGR1_CG10_MASK (0x300000U)CCM_CCGR1_CG10_SHIFT (20U)CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)CCM_CCGR1_CG11_MASK (0xC00000U)CCM_CCGR1_CG11_SHIFT (22U)CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)CCM_CCGR1_CG12_MASK (0x3000000U)CCM_CCGR1_CG12_SHIFT (24U)CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)CCM_CCGR1_CG13_MASK (0xC000000U)CCM_CCGR1_CG13_SHIFT (26U)CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)CCM_CCGR1_CG14_MASK (0x30000000U)CCM_CCGR1_CG14_SHIFT (28U)CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)CCM_CCGR1_CG15_MASK (0xC0000000U)CCM_CCGR1_CG15_SHIFT (30U)CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)CCM_CCGR2_CG0_MASK (0x3U)CCM_CCGR2_CG0_SHIFT (0U)CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)CCM_CCGR2_CG1_MASK (0xCU)CCM_CCGR2_CG1_SHIFT (2U)CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)CCM_CCGR2_CG2_MASK (0x30U)CCM_CCGR2_CG2_SHIFT (4U)CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)CCM_CCGR2_CG3_MASK (0xC0U)CCM_CCGR2_CG3_SHIFT (6U)CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)CCM_CCGR2_CG4_MASK (0x300U)CCM_CCGR2_CG4_SHIFT (8U)CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)CCM_CCGR2_CG5_MASK (0xC00U)CCM_CCGR2_CG5_SHIFT (10U)CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)CCM_CCGR2_CG6_MASK (0x3000U)CCM_CCGR2_CG6_SHIFT (12U)CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)CCM_CCGR2_CG7_MASK (0xC000U)CCM_CCGR2_CG7_SHIFT (14U)CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)CCM_CCGR2_CG8_MASK (0x30000U)CCM_CCGR2_CG8_SHIFT (16U)CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)CCM_CCGR2_CG9_MASK (0xC0000U)CCM_CCGR2_CG9_SHIFT (18U)CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)CCM_CCGR2_CG10_MASK (0x300000U)CCM_CCGR2_CG10_SHIFT (20U)CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)CCM_CCGR2_CG11_MASK (0xC00000U)CCM_CCGR2_CG11_SHIFT (22U)CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)CCM_CCGR2_CG12_MASK (0x3000000U)CCM_CCGR2_CG12_SHIFT (24U)CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)CCM_CCGR2_CG13_MASK (0xC000000U)CCM_CCGR2_CG13_SHIFT (26U)CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)CCM_CCGR2_CG14_MASK (0x30000000U)CCM_CCGR2_CG14_SHIFT (28U)CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)CCM_CCGR2_CG15_MASK (0xC0000000U)CCM_CCGR2_CG15_SHIFT (30U)CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)CCM_CCGR3_CG0_MASK (0x3U)CCM_CCGR3_CG0_SHIFT (0U)CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)CCM_CCGR3_CG1_MASK (0xCU)CCM_CCGR3_CG1_SHIFT (2U)CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)CCM_CCGR3_CG2_MASK (0x30U)CCM_CCGR3_CG2_SHIFT (4U)CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)CCM_CCGR3_CG3_MASK (0xC0U)CCM_CCGR3_CG3_SHIFT (6U)CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)CCM_CCGR3_CG4_MASK (0x300U)CCM_CCGR3_CG4_SHIFT (8U)CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)CCM_CCGR3_CG5_MASK (0xC00U)CCM_CCGR3_CG5_SHIFT (10U)CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)CCM_CCGR3_CG6_MASK (0x3000U)CCM_CCGR3_CG6_SHIFT (12U)CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)CCM_CCGR3_CG7_MASK (0xC000U)CCM_CCGR3_CG7_SHIFT (14U)CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)CCM_CCGR3_CG8_MASK (0x30000U)CCM_CCGR3_CG8_SHIFT (16U)CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)CCM_CCGR3_CG9_MASK (0xC0000U)CCM_CCGR3_CG9_SHIFT (18U)CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)CCM_CCGR3_CG10_MASK (0x300000U)CCM_CCGR3_CG10_SHIFT (20U)CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)CCM_CCGR3_CG11_MASK (0xC00000U)CCM_CCGR3_CG11_SHIFT (22U)CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)CCM_CCGR3_CG12_MASK (0x3000000U)CCM_CCGR3_CG12_SHIFT (24U)CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)CCM_CCGR3_CG13_MASK (0xC000000U)CCM_CCGR3_CG13_SHIFT (26U)CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)CCM_CCGR3_CG14_MASK (0x30000000U)CCM_CCGR3_CG14_SHIFT (28U)CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)CCM_CCGR3_CG15_MASK (0xC0000000U)CCM_CCGR3_CG15_SHIFT (30U)CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)CCM_CCGR4_CG0_MASK (0x3U)CCM_CCGR4_CG0_SHIFT (0U)CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)CCM_CCGR4_CG1_MASK (0xCU)CCM_CCGR4_CG1_SHIFT (2U)CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)CCM_CCGR4_CG2_MASK (0x30U)CCM_CCGR4_CG2_SHIFT (4U)CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)CCM_CCGR4_CG3_MASK (0xC0U)CCM_CCGR4_CG3_SHIFT (6U)CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)CCM_CCGR4_CG4_MASK (0x300U)CCM_CCGR4_CG4_SHIFT (8U)CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)CCM_CCGR4_CG5_MASK (0xC00U)CCM_CCGR4_CG5_SHIFT (10U)CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)CCM_CCGR4_CG6_MASK (0x3000U)CCM_CCGR4_CG6_SHIFT (12U)CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)CCM_CCGR4_CG7_MASK (0xC000U)CCM_CCGR4_CG7_SHIFT (14U)CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)CCM_CCGR4_CG8_MASK (0x30000U)CCM_CCGR4_CG8_SHIFT (16U)CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)CCM_CCGR4_CG9_MASK (0xC0000U)CCM_CCGR4_CG9_SHIFT (18U)CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)CCM_CCGR4_CG10_MASK (0x300000U)CCM_CCGR4_CG10_SHIFT (20U)CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)CCM_CCGR4_CG11_MASK (0xC00000U)CCM_CCGR4_CG11_SHIFT (22U)CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)CCM_CCGR4_CG12_MASK (0x3000000U)CCM_CCGR4_CG12_SHIFT (24U)CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)CCM_CCGR4_CG13_MASK (0xC000000U)CCM_CCGR4_CG13_SHIFT (26U)CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)CCM_CCGR4_CG14_MASK (0x30000000U)CCM_CCGR4_CG14_SHIFT (28U)CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)CCM_CCGR4_CG15_MASK (0xC0000000U)CCM_CCGR4_CG15_SHIFT (30U)CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)CCM_CCGR5_CG0_MASK (0x3U)CCM_CCGR5_CG0_SHIFT (0U)CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)CCM_CCGR5_CG1_MASK (0xCU)CCM_CCGR5_CG1_SHIFT (2U)CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)CCM_CCGR5_CG2_MASK (0x30U)CCM_CCGR5_CG2_SHIFT (4U)CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)CCM_CCGR5_CG3_MASK (0xC0U)CCM_CCGR5_CG3_SHIFT (6U)CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)CCM_CCGR5_CG4_MASK (0x300U)CCM_CCGR5_CG4_SHIFT (8U)CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)CCM_CCGR5_CG5_MASK (0xC00U)CCM_CCGR5_CG5_SHIFT (10U)CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)CCM_CCGR5_CG6_MASK (0x3000U)CCM_CCGR5_CG6_SHIFT (12U)CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)CCM_CCGR5_CG7_MASK (0xC000U)CCM_CCGR5_CG7_SHIFT (14U)CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)CCM_CCGR5_CG8_MASK (0x30000U)CCM_CCGR5_CG8_SHIFT (16U)CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)CCM_CCGR5_CG9_MASK (0xC0000U)CCM_CCGR5_CG9_SHIFT (18U)CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)CCM_CCGR5_CG10_MASK (0x300000U)CCM_CCGR5_CG10_SHIFT (20U)CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)CCM_CCGR5_CG11_MASK (0xC00000U)CCM_CCGR5_CG11_SHIFT (22U)CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)CCM_CCGR5_CG12_MASK (0x3000000U)CCM_CCGR5_CG12_SHIFT (24U)CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)CCM_CCGR5_CG13_MASK (0xC000000U)CCM_CCGR5_CG13_SHIFT (26U)CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)CCM_CCGR5_CG14_MASK (0x30000000U)CCM_CCGR5_CG14_SHIFT (28U)CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)CCM_CCGR5_CG15_MASK (0xC0000000U)CCM_CCGR5_CG15_SHIFT (30U)CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)CCM_CCGR6_CG0_MASK (0x3U)CCM_CCGR6_CG0_SHIFT (0U)CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)CCM_CCGR6_CG1_MASK (0xCU)CCM_CCGR6_CG1_SHIFT (2U)CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)CCM_CCGR6_CG2_MASK (0x30U)CCM_CCGR6_CG2_SHIFT (4U)CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)CCM_CCGR6_CG3_MASK (0xC0U)CCM_CCGR6_CG3_SHIFT (6U)CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)CCM_CCGR6_CG4_MASK (0x300U)CCM_CCGR6_CG4_SHIFT (8U)CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)CCM_CCGR6_CG5_MASK (0xC00U)CCM_CCGR6_CG5_SHIFT (10U)CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)CCM_CCGR6_CG6_MASK (0x3000U)CCM_CCGR6_CG6_SHIFT (12U)CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)CCM_CCGR6_CG7_MASK (0xC000U)CCM_CCGR6_CG7_SHIFT (14U)CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)CCM_CCGR6_CG8_MASK (0x30000U)CCM_CCGR6_CG8_SHIFT (16U)CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)CCM_CCGR6_CG9_MASK (0xC0000U)CCM_CCGR6_CG9_SHIFT (18U)CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)CCM_CCGR6_CG10_MASK (0x300000U)CCM_CCGR6_CG10_SHIFT (20U)CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)CCM_CCGR6_CG11_MASK (0xC00000U)CCM_CCGR6_CG11_SHIFT (22U)CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)CCM_CCGR6_CG12_MASK (0x3000000U)CCM_CCGR6_CG12_SHIFT (24U)CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)CCM_CCGR6_CG13_MASK (0xC000000U)CCM_CCGR6_CG13_SHIFT (26U)CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)CCM_CCGR6_CG14_MASK (0x30000000U)CCM_CCGR6_CG14_SHIFT (28U)CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)CCM_CCGR6_CG15_MASK (0xC0000000U)CCM_CCGR6_CG15_SHIFT (30U)CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)CCM_BASE (0x400FC000u)CCM ((CCM_Type *)CCM_BASE)CCM_BASE_ADDRS { CCM_BASE }CCM_BASE_PTRS { CCM }CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU)CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U)CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U)CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U)CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK)CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U)CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U)CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK)CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U)CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U)CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK)CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK (0x400000U)CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT (22U)CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU)CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U)CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U)CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U)CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK)CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U)CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U)CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK)CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U)CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U)CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK)CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK (0x400000U)CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT (22U)CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU)CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U)CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U)CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U)CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U)CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U)CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U)CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U)CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK (0x400000U)CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT (22U)CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU)CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U)CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK)CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U)CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U)CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U)CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U)CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U)CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U)CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK (0x400000U)CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT (22U)CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK)CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)!CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)!CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)!CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)!CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)!CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)!CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)!CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)!CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)!CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)!CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)!CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)!CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)!CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)!CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)!CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)!CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)!CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)!CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)!CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)!CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)!CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)!CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)!CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)!CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)!CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)!CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)!CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)!CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)!CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)!CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)!CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)!CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)!CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)!CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)!CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)!CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)!CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)!CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)!CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)!CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)!CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)!CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)!CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)!CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)!CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)!CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)!CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)!CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)!CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)!CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)!CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)!CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)!CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)!CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)!CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)!CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)!CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)!CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)!CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)!CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)!CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)!CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)!CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)!CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)!CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)!CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)!CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)!CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)!CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)!CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)!CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)!CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)!CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)!CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)!CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)!CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)!CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)!CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)!CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)!CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)!CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)!CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)!CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)!CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)!CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)!CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)!CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)!CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)!CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)!CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)!CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)!CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)!CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)!CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)!CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)!CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)!CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)!CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)!CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)!CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)!CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)!CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)!CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)!CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)!CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)"CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)"CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)"CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)"CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)"CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)"CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)"CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)"CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)"CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)"CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)"CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)"CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)"CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)"CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)"CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)"CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)"CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)"CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)"CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)"CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)"CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)"CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)"CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)"CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)"CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)"CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)"CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)"CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)"CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)"CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)"CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)"CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)"CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)"CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)"CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)"CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)"CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)"CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)"CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)"CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)"CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)"CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)"CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)"CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)"CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)"CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)"CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)"CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)"CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)"CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)"CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)"CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)"CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)"CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)"CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)"CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)"CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)"CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)"CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)"CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)"CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)"CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)"CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)"CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)"CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)"CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)"CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)"CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)"CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)"CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)"CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)"CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)"CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)"CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)"CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)"CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)"CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)"CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)"CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)"CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)"CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)"CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)"CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)"CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)"CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)"CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)"CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)"CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)"CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)"CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)"CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)"CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)#CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)#CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)#CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)#CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)#CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)#CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)#CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)#CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)#CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)#CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)#CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)#CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)#CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)#CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)#CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)#CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)#CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)#CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)#CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)#CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)#CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)#CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)#CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)#CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)#CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)#CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)#CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)#CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)#CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)#CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)#CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)#CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)#CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)#CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)#CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)#CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)#CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)#CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)#CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)#CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)#CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)#CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)#CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)#CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)#CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)#CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)#CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)#CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)#CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)#CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)#CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)#CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)#CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)#CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)#CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)#CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)#CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)#CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)#CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)#CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)#CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)#CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)#CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)#CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)#CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)#CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U)#CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U)#CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)#CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)#CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)#CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)#CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)#CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)#CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)#CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)#CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)#CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)#CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)#CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)$CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)$CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)$CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)$CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)$CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)$CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)$CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)$CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)$CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)$CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)$CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)$CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)$CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)$CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)$CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)$CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)$CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)$CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)$CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)$CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)$CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)$CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)$CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)$CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)$CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)$CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)$CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)$CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)$CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)$CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)$CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)$CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)$CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)$CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)$CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)$CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)$CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)$CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)$CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)$CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U)$CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U)$CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)$CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)$CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)$CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)$CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)$CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)$CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)$CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)$CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)$CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)$CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)$CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)$CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)$CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)$CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)$CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)$CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)$CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)$CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)$CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)$CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)$CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)$CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)$CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)$CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)$CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)$CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)$CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)$CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)$CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)$CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)$CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)$CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)$CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)$CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)$CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)$CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)$CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)$CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)$CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)$CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)$CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)$CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)$CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)$CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U)$CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U)$CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK)$CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)$CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)$CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)$CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)$CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)$CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)$CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)$CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)$CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)$CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)$CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)$CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)$CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)$CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)$CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)$CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)$CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)%CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)%CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)%CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)%CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)%CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)%CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)%CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)%CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)%CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)%CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)%CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)%CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)%CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)%CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)%CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)%CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)%CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)%CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)%CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)%CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)%CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)%CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)%CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)%CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)%CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)%CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)%CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)%CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)%CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)%CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)%CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)%CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)%CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)%CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)%CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)%CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)%CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)%CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U)%CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U)%CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK)%CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)%CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)%CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)%CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)%CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)%CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)%CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)%CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)%CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)%CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)%CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)%CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)%CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)%CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)%CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)%CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)%CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)%CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)%CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)%CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)%CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)%CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)%CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)%CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)%CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)%CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)%CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)%CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)%CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)%CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)%CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)%CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)%CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)%CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)%CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)%CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)%CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)%CCM_ANALOG_BASE (0x400D8000u)%CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)%CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }%CCM_ANALOG_BASE_PTRS { CCM_ANALOG }&CMP_CR0_HYSTCTR_MASK (0x3U)&CMP_CR0_HYSTCTR_SHIFT (0U)&CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)&CMP_CR0_FILTER_CNT_MASK (0x70U)&CMP_CR0_FILTER_CNT_SHIFT (4U)&CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)&CMP_CR1_EN_MASK (0x1U)&CMP_CR1_EN_SHIFT (0U)&CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)&CMP_CR1_OPE_MASK (0x2U)&CMP_CR1_OPE_SHIFT (1U)&CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)&CMP_CR1_COS_MASK (0x4U)&CMP_CR1_COS_SHIFT (2U)&CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)&CMP_CR1_INV_MASK (0x8U)&CMP_CR1_INV_SHIFT (3U)&CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)&CMP_CR1_PMODE_MASK (0x10U)&CMP_CR1_PMODE_SHIFT (4U)&CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)&CMP_CR1_WE_MASK (0x40U)&CMP_CR1_WE_SHIFT (6U)&CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)&CMP_CR1_SE_MASK (0x80U)&CMP_CR1_SE_SHIFT (7U)&CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)&CMP_FPR_FILT_PER_MASK (0xFFU)&CMP_FPR_FILT_PER_SHIFT (0U)&CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)&CMP_SCR_COUT_MASK (0x1U)&CMP_SCR_COUT_SHIFT (0U)&CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)&CMP_SCR_CFF_MASK (0x2U)&CMP_SCR_CFF_SHIFT (1U)&CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)&CMP_SCR_CFR_MASK (0x4U)&CMP_SCR_CFR_SHIFT (2U)&CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)&CMP_SCR_IEF_MASK (0x8U)&CMP_SCR_IEF_SHIFT (3U)&CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)&CMP_SCR_IER_MASK (0x10U)&CMP_SCR_IER_SHIFT (4U)&CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)&CMP_SCR_DMAEN_MASK (0x40U)&CMP_SCR_DMAEN_SHIFT (6U)&CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)&CMP_DACCR_VOSEL_MASK (0x3FU)&CMP_DACCR_VOSEL_SHIFT (0U)&CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)&CMP_DACCR_VRSEL_MASK (0x40U)&CMP_DACCR_VRSEL_SHIFT (6U)&CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)&CMP_DACCR_DACEN_MASK (0x80U)&CMP_DACCR_DACEN_SHIFT (7U)&CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)&CMP_MUXCR_MSEL_MASK (0x7U)&CMP_MUXCR_MSEL_SHIFT (0U)&CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)&CMP_MUXCR_PSEL_MASK (0x38U)&CMP_MUXCR_PSEL_SHIFT (3U)&CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)&CMP1_BASE (0x40094000u)&CMP1 ((CMP_Type *)CMP1_BASE)&CMP2_BASE (0x40094008u)&CMP2 ((CMP_Type *)CMP2_BASE)&CMP3_BASE (0x40094010u)&CMP3 ((CMP_Type *)CMP3_BASE)&CMP4_BASE (0x40094018u)&CMP4 ((CMP_Type *)CMP4_BASE)&CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }&CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }&CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }'DCDC_REG0_PWD_ZCD_MASK (0x1U)'DCDC_REG0_PWD_ZCD_SHIFT (0U)'DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)'DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)'DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)'DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)'DCDC_REG0_SEL_CLK_MASK (0x4U)'DCDC_REG0_SEL_CLK_SHIFT (2U)'DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)'DCDC_REG0_PWD_OSC_INT_MASK (0x8U)'DCDC_REG0_PWD_OSC_INT_SHIFT (3U)'DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)'DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)'DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)'DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)'DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)'DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)'DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)'DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)'DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)'DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)'DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)'DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)'DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)'DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)'DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)'DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)'DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)'DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)'DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)'DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)'DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)'DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)'DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)'DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)'DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)'DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)'DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)'DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)'DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)'DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)'DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)'DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)'DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)'DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)'DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)'DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)'DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)'DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)'DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)'DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)'DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)'DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)'DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)'DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)'DCDC_REG0_XTAL_24M_OK_SHIFT (29U)'DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)'DCDC_REG0_STS_DC_OK_MASK (0x80000000U)'DCDC_REG0_STS_DC_OK_SHIFT (31U)'DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)'DCDC_REG1_REG_FBK_SEL_MASK (0x180U)'DCDC_REG1_REG_FBK_SEL_SHIFT (7U)'DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)'DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)'DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)'DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)'DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)'DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)'DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)'DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)'DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)'DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)'DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)'DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)'DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)'DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)'DCDC_REG1_VBG_TRIM_SHIFT (24U)'DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)'DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)'DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)'DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)'DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)'DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)'DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)'DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)'DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)'DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)'DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)'DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)(DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)(DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)(DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)(DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)(DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)(DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)(DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)(DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)(DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)(DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)(DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)(DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)(DCDC_REG3_TRG_MASK (0x1FU)(DCDC_REG3_TRG_SHIFT (0U)(DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)(DCDC_REG3_TARGET_LP_MASK (0x700U)(DCDC_REG3_TARGET_LP_SHIFT (8U)(DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)(DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)(DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)(DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)(DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)(DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)(DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)(DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)(DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)(DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)(DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)(DCDC_REG3_DISABLE_STEP_SHIFT (30U)(DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)(DCDC_BASE (0x40080000u)(DCDC ((DCDC_Type *)DCDC_BASE)(DCDC_BASE_ADDRS { DCDC_BASE }(DCDC_BASE_PTRS { DCDC }(DCDC_IRQS { DCDC_IRQn })DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU))DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U))DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK))DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U))DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U))DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK))DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U))DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U))DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK))DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U))DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U))DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK))DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U))DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U))DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK))DCP_CTRL_PRESENT_SHA_MASK (0x10000000U))DCP_CTRL_PRESENT_SHA_SHIFT (28U))DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK))DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U))DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U))DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK))DCP_CTRL_CLKGATE_MASK (0x40000000U))DCP_CTRL_CLKGATE_SHIFT (30U))DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK))DCP_CTRL_SFTRST_MASK (0x80000000U))DCP_CTRL_SFTRST_SHIFT (31U))DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK))DCP_STAT_IRQ_MASK (0xFU))DCP_STAT_IRQ_SHIFT (0U))DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK))DCP_STAT_RSVD_IRQ_MASK (0x100U))DCP_STAT_RSVD_IRQ_SHIFT (8U))DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK))DCP_STAT_READY_CHANNELS_MASK (0xFF0000U))DCP_STAT_READY_CHANNELS_SHIFT (16U))DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK))DCP_STAT_CUR_CHANNEL_MASK (0xF000000U))DCP_STAT_CUR_CHANNEL_SHIFT (24U))DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK))DCP_STAT_OTP_KEY_READY_MASK (0x10000000U))DCP_STAT_OTP_KEY_READY_SHIFT (28U))DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK))DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU))DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U))DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK))DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U))DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U))DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK))DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U))DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U))DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK))DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U))DCP_CHANNELCTRL_RSVD_SHIFT (17U))DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK))DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU))DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U))DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK))DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U))DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U))DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK))DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U))DCP_CAPABILITY0_RSVD_SHIFT (12U))DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK))DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U))DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U))DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK))DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U))DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U))DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK))DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU))DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U))DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK))DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U))DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U))DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK))DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU))DCP_CONTEXT_ADDR_SHIFT (0U))DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK))DCP_KEY_SUBWORD_MASK (0x3U)*DCP_KEY_SUBWORD_SHIFT (0U)*DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)*DCP_KEY_RSVD_SUBWORD_MASK (0xCU)*DCP_KEY_RSVD_SUBWORD_SHIFT (2U)*DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)*DCP_KEY_INDEX_MASK (0x30U)*DCP_KEY_INDEX_SHIFT (4U)*DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)*DCP_KEY_RSVD_INDEX_MASK (0xC0U)*DCP_KEY_RSVD_INDEX_SHIFT (6U)*DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)*DCP_KEY_RSVD_MASK (0xFFFFFF00U)*DCP_KEY_RSVD_SHIFT (8U)*DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)*DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)*DCP_KEYDATA_DATA_SHIFT (0U)*DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)*DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)*DCP_PACKET0_ADDR_SHIFT (0U)*DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)*DCP_PACKET1_INTERRUPT_MASK (0x1U)*DCP_PACKET1_INTERRUPT_SHIFT (0U)*DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)*DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)*DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)*DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)*DCP_PACKET1_CHAIN_MASK (0x4U)*DCP_PACKET1_CHAIN_SHIFT (2U)*DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)*DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)*DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)*DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)*DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)*DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)*DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)*DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)*DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)*DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)*DCP_PACKET1_ENABLE_HASH_MASK (0x40U)*DCP_PACKET1_ENABLE_HASH_SHIFT (6U)*DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)*DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)*DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)*DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)*DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)*DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)*DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)*DCP_PACKET1_CIPHER_INIT_MASK (0x200U)*DCP_PACKET1_CIPHER_INIT_SHIFT (9U)*DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)*DCP_PACKET1_OTP_KEY_MASK (0x400U)*DCP_PACKET1_OTP_KEY_SHIFT (10U)*DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)*DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)*DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)*DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)*DCP_PACKET1_HASH_INIT_MASK (0x1000U)*DCP_PACKET1_HASH_INIT_SHIFT (12U)*DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)*DCP_PACKET1_HASH_TERM_MASK (0x2000U)*DCP_PACKET1_HASH_TERM_SHIFT (13U)*DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)*DCP_PACKET1_CHECK_HASH_MASK (0x4000U)*DCP_PACKET1_CHECK_HASH_SHIFT (14U)*DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)*DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)*DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)*DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)*DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)*DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)*DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)*DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)*DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)*DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)*DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)*DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)*DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)*DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)*DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)*DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)*DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)*DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)*DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)*DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)*DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)*DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)*DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)*DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)*DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)*DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)*DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)*DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)*DCP_PACKET1_TAG_MASK (0xFF000000U)*DCP_PACKET1_TAG_SHIFT (24U)*DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)*DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)*DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)*DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)*DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)*DCP_PACKET2_CIPHER_MODE_SHIFT (4U)*DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)*DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)*DCP_PACKET2_KEY_SELECT_SHIFT (8U)*DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)*DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)*DCP_PACKET2_HASH_SELECT_SHIFT (16U)*DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)*DCP_PACKET2_RSVD_MASK (0xF00000U)*DCP_PACKET2_RSVD_SHIFT (20U)*DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)*DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)*DCP_PACKET2_CIPHER_CFG_SHIFT (24U)+DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)+DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)+DCP_PACKET3_ADDR_SHIFT (0U)+DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)+DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)+DCP_PACKET4_ADDR_SHIFT (0U)+DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)+DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)+DCP_PACKET5_COUNT_SHIFT (0U)+DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)+DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)+DCP_PACKET6_ADDR_SHIFT (0U)+DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)+DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)+DCP_CH0CMDPTR_ADDR_SHIFT (0U)+DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)+DCP_CH0SEMA_INCREMENT_MASK (0xFFU)+DCP_CH0SEMA_INCREMENT_SHIFT (0U)+DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)+DCP_CH0SEMA_VALUE_MASK (0xFF0000U)+DCP_CH0SEMA_VALUE_SHIFT (16U)+DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)+DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)+DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)+DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)+DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)+DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)+DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)+DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)+DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)+DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)+DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)+DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)+DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)+DCP_CH0STAT_ERROR_SRC_MASK (0x10U)+DCP_CH0STAT_ERROR_SRC_SHIFT (4U)+DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)+DCP_CH0STAT_ERROR_DST_MASK (0x20U)+DCP_CH0STAT_ERROR_DST_SHIFT (5U)+DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)+DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)+DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)+DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)+DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)+DCP_CH0STAT_ERROR_CODE_SHIFT (16U)+DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)+DCP_CH0STAT_TAG_MASK (0xFF000000U)+DCP_CH0STAT_TAG_SHIFT (24U)+DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)+DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)+DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)+DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)+DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)+DCP_CH0OPTS_RSVD_SHIFT (16U)+DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)+DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)+DCP_CH1CMDPTR_ADDR_SHIFT (0U)+DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)+DCP_CH1SEMA_INCREMENT_MASK (0xFFU)+DCP_CH1SEMA_INCREMENT_SHIFT (0U)+DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)+DCP_CH1SEMA_VALUE_MASK (0xFF0000U)+DCP_CH1SEMA_VALUE_SHIFT (16U)+DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)+DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)+DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)+DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)+DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)+DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)+DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)+DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)+DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)+DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)+DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)+DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)+DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)+DCP_CH1STAT_ERROR_SRC_MASK (0x10U)+DCP_CH1STAT_ERROR_SRC_SHIFT (4U)+DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)+DCP_CH1STAT_ERROR_DST_MASK (0x20U)+DCP_CH1STAT_ERROR_DST_SHIFT (5U)+DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)+DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)+DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U),DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK),DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U),DCP_CH1STAT_ERROR_CODE_SHIFT (16U),DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK),DCP_CH1STAT_TAG_MASK (0xFF000000U),DCP_CH1STAT_TAG_SHIFT (24U),DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK),DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU),DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U),DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK),DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U),DCP_CH1OPTS_RSVD_SHIFT (16U),DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK),DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU),DCP_CH2CMDPTR_ADDR_SHIFT (0U),DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK),DCP_CH2SEMA_INCREMENT_MASK (0xFFU),DCP_CH2SEMA_INCREMENT_SHIFT (0U),DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK),DCP_CH2SEMA_VALUE_MASK (0xFF0000U),DCP_CH2SEMA_VALUE_SHIFT (16U),DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK),DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U),DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U),DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK),DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U),DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U),DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK),DCP_CH2STAT_ERROR_SETUP_MASK (0x4U),DCP_CH2STAT_ERROR_SETUP_SHIFT (2U),DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK),DCP_CH2STAT_ERROR_PACKET_MASK (0x8U),DCP_CH2STAT_ERROR_PACKET_SHIFT (3U),DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK),DCP_CH2STAT_ERROR_SRC_MASK (0x10U),DCP_CH2STAT_ERROR_SRC_SHIFT (4U),DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK),DCP_CH2STAT_ERROR_DST_MASK (0x20U),DCP_CH2STAT_ERROR_DST_SHIFT (5U),DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK),DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U),DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U),DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK),DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U),DCP_CH2STAT_ERROR_CODE_SHIFT (16U),DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK),DCP_CH2STAT_TAG_MASK (0xFF000000U),DCP_CH2STAT_TAG_SHIFT (24U),DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK),DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU),DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U),DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK),DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U),DCP_CH2OPTS_RSVD_SHIFT (16U),DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK),DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU),DCP_CH3CMDPTR_ADDR_SHIFT (0U),DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK),DCP_CH3SEMA_INCREMENT_MASK (0xFFU),DCP_CH3SEMA_INCREMENT_SHIFT (0U),DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK),DCP_CH3SEMA_VALUE_MASK (0xFF0000U),DCP_CH3SEMA_VALUE_SHIFT (16U),DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK),DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U),DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U),DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK),DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U),DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U),DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK),DCP_CH3STAT_ERROR_SETUP_MASK (0x4U),DCP_CH3STAT_ERROR_SETUP_SHIFT (2U),DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK),DCP_CH3STAT_ERROR_PACKET_MASK (0x8U),DCP_CH3STAT_ERROR_PACKET_SHIFT (3U),DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK),DCP_CH3STAT_ERROR_SRC_MASK (0x10U),DCP_CH3STAT_ERROR_SRC_SHIFT (4U),DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK),DCP_CH3STAT_ERROR_DST_MASK (0x20U),DCP_CH3STAT_ERROR_DST_SHIFT (5U),DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK),DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U),DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U),DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK),DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U),DCP_CH3STAT_ERROR_CODE_SHIFT (16U),DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK),DCP_CH3STAT_TAG_MASK (0xFF000000U),DCP_CH3STAT_TAG_SHIFT (24U),DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK),DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)-DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)-DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)-DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)-DCP_CH3OPTS_RSVD_SHIFT (16U)-DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)-DCP_DBGSELECT_INDEX_MASK (0xFFU)-DCP_DBGSELECT_INDEX_SHIFT (0U)-DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)-DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)-DCP_DBGSELECT_RSVD_SHIFT (8U)-DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)-DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)-DCP_DBGDATA_DATA_SHIFT (0U)-DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)-DCP_PAGETABLE_ENABLE_MASK (0x1U)-DCP_PAGETABLE_ENABLE_SHIFT (0U)-DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)-DCP_PAGETABLE_FLUSH_MASK (0x2U)-DCP_PAGETABLE_FLUSH_SHIFT (1U)-DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)-DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)-DCP_PAGETABLE_BASE_SHIFT (2U)-DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)-DCP_VERSION_STEP_MASK (0xFFFFU)-DCP_VERSION_STEP_SHIFT (0U)-DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)-DCP_VERSION_MINOR_MASK (0xFF0000U)-DCP_VERSION_MINOR_SHIFT (16U)-DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)-DCP_VERSION_MAJOR_MASK (0xFF000000U)-DCP_VERSION_MAJOR_SHIFT (24U)-DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)-DCP_BASE (0x402FC000u)-DCP ((DCP_Type *)DCP_BASE)-DCP_BASE_ADDRS { DCP_BASE }-DCP_BASE_PTRS { DCP }-DCP_IRQS { DCP_IRQn }-DCP_VMI_IRQS { DCP_VMI_IRQn }.DMA_CR_EDBG_MASK (0x2U).DMA_CR_EDBG_SHIFT (1U).DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK).DMA_CR_ERCA_MASK (0x4U).DMA_CR_ERCA_SHIFT (2U).DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK).DMA_CR_ERGA_MASK (0x8U).DMA_CR_ERGA_SHIFT (3U).DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK).DMA_CR_HOE_MASK (0x10U).DMA_CR_HOE_SHIFT (4U).DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK).DMA_CR_HALT_MASK (0x20U).DMA_CR_HALT_SHIFT (5U).DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK).DMA_CR_CLM_MASK (0x40U).DMA_CR_CLM_SHIFT (6U).DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK).DMA_CR_EMLM_MASK (0x80U).DMA_CR_EMLM_SHIFT (7U).DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK).DMA_CR_GRP0PRI_MASK (0x100U).DMA_CR_GRP0PRI_SHIFT (8U).DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK).DMA_CR_GRP1PRI_MASK (0x400U).DMA_CR_GRP1PRI_SHIFT (10U).DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK).DMA_CR_ECX_MASK (0x10000U).DMA_CR_ECX_SHIFT (16U).DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK).DMA_CR_CX_MASK (0x20000U).DMA_CR_CX_SHIFT (17U).DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK).DMA_CR_ACTIVE_MASK (0x80000000U).DMA_CR_ACTIVE_SHIFT (31U).DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK).DMA_ES_DBE_MASK (0x1U).DMA_ES_DBE_SHIFT (0U).DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK).DMA_ES_SBE_MASK (0x2U).DMA_ES_SBE_SHIFT (1U).DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK).DMA_ES_SGE_MASK (0x4U).DMA_ES_SGE_SHIFT (2U).DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK).DMA_ES_NCE_MASK (0x8U).DMA_ES_NCE_SHIFT (3U).DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK).DMA_ES_DOE_MASK (0x10U).DMA_ES_DOE_SHIFT (4U).DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK).DMA_ES_DAE_MASK (0x20U).DMA_ES_DAE_SHIFT (5U).DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK).DMA_ES_SOE_MASK (0x40U).DMA_ES_SOE_SHIFT (6U).DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK).DMA_ES_SAE_MASK (0x80U).DMA_ES_SAE_SHIFT (7U).DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK).DMA_ES_ERRCHN_MASK (0x1F00U).DMA_ES_ERRCHN_SHIFT (8U).DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK).DMA_ES_CPE_MASK (0x4000U).DMA_ES_CPE_SHIFT (14U).DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK).DMA_ES_GPE_MASK (0x8000U).DMA_ES_GPE_SHIFT (15U).DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK).DMA_ES_ECX_MASK (0x10000U).DMA_ES_ECX_SHIFT (16U).DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK).DMA_ES_VLD_MASK (0x80000000U)/DMA_ES_VLD_SHIFT (31U)/DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)/DMA_ERQ_ERQ0_MASK (0x1U)/DMA_ERQ_ERQ0_SHIFT (0U)/DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)/DMA_ERQ_ERQ1_MASK (0x2U)/DMA_ERQ_ERQ1_SHIFT (1U)/DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)/DMA_ERQ_ERQ2_MASK (0x4U)/DMA_ERQ_ERQ2_SHIFT (2U)/DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)/DMA_ERQ_ERQ3_MASK (0x8U)/DMA_ERQ_ERQ3_SHIFT (3U)/DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)/DMA_ERQ_ERQ4_MASK (0x10U)/DMA_ERQ_ERQ4_SHIFT (4U)/DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)/DMA_ERQ_ERQ5_MASK (0x20U)/DMA_ERQ_ERQ5_SHIFT (5U)/DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)/DMA_ERQ_ERQ6_MASK (0x40U)/DMA_ERQ_ERQ6_SHIFT (6U)/DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)/DMA_ERQ_ERQ7_MASK (0x80U)/DMA_ERQ_ERQ7_SHIFT (7U)/DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)/DMA_ERQ_ERQ8_MASK (0x100U)/DMA_ERQ_ERQ8_SHIFT (8U)/DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)/DMA_ERQ_ERQ9_MASK (0x200U)/DMA_ERQ_ERQ9_SHIFT (9U)/DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)/DMA_ERQ_ERQ10_MASK (0x400U)/DMA_ERQ_ERQ10_SHIFT (10U)/DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)/DMA_ERQ_ERQ11_MASK (0x800U)/DMA_ERQ_ERQ11_SHIFT (11U)/DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)/DMA_ERQ_ERQ12_MASK (0x1000U)/DMA_ERQ_ERQ12_SHIFT (12U)/DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)/DMA_ERQ_ERQ13_MASK (0x2000U)/DMA_ERQ_ERQ13_SHIFT (13U)/DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)/DMA_ERQ_ERQ14_MASK (0x4000U)/DMA_ERQ_ERQ14_SHIFT (14U)/DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)/DMA_ERQ_ERQ15_MASK (0x8000U)/DMA_ERQ_ERQ15_SHIFT (15U)/DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)/DMA_ERQ_ERQ16_MASK (0x10000U)/DMA_ERQ_ERQ16_SHIFT (16U)/DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)/DMA_ERQ_ERQ17_MASK (0x20000U)/DMA_ERQ_ERQ17_SHIFT (17U)/DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)/DMA_ERQ_ERQ18_MASK (0x40000U)/DMA_ERQ_ERQ18_SHIFT (18U)/DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)/DMA_ERQ_ERQ19_MASK (0x80000U)/DMA_ERQ_ERQ19_SHIFT (19U)/DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)/DMA_ERQ_ERQ20_MASK (0x100000U)/DMA_ERQ_ERQ20_SHIFT (20U)/DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)/DMA_ERQ_ERQ21_MASK (0x200000U)/DMA_ERQ_ERQ21_SHIFT (21U)/DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)/DMA_ERQ_ERQ22_MASK (0x400000U)/DMA_ERQ_ERQ22_SHIFT (22U)/DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)/DMA_ERQ_ERQ23_MASK (0x800000U)/DMA_ERQ_ERQ23_SHIFT (23U)/DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)/DMA_ERQ_ERQ24_MASK (0x1000000U)/DMA_ERQ_ERQ24_SHIFT (24U)/DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)/DMA_ERQ_ERQ25_MASK (0x2000000U)/DMA_ERQ_ERQ25_SHIFT (25U)/DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)/DMA_ERQ_ERQ26_MASK (0x4000000U)/DMA_ERQ_ERQ26_SHIFT (26U)/DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)/DMA_ERQ_ERQ27_MASK (0x8000000U)/DMA_ERQ_ERQ27_SHIFT (27U)/DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)/DMA_ERQ_ERQ28_MASK (0x10000000U)/DMA_ERQ_ERQ28_SHIFT (28U)/DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)/DMA_ERQ_ERQ29_MASK (0x20000000U)/DMA_ERQ_ERQ29_SHIFT (29U)/DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)/DMA_ERQ_ERQ30_MASK (0x40000000U)/DMA_ERQ_ERQ30_SHIFT (30U)/DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)/DMA_ERQ_ERQ31_MASK (0x80000000U)/DMA_ERQ_ERQ31_SHIFT (31U)/DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)/DMA_EEI_EEI0_MASK (0x1U)/DMA_EEI_EEI0_SHIFT (0U)/DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)/DMA_EEI_EEI1_MASK (0x2U)/DMA_EEI_EEI1_SHIFT (1U)/DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)/DMA_EEI_EEI2_MASK (0x4U)/DMA_EEI_EEI2_SHIFT (2U)/DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)/DMA_EEI_EEI3_MASK (0x8U)/DMA_EEI_EEI3_SHIFT (3U)/DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)/DMA_EEI_EEI4_MASK (0x10U)/DMA_EEI_EEI4_SHIFT (4U)/DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)/DMA_EEI_EEI5_MASK (0x20U)/DMA_EEI_EEI5_SHIFT (5U)/DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)/DMA_EEI_EEI6_MASK (0x40U)/DMA_EEI_EEI6_SHIFT (6U)/DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)/DMA_EEI_EEI7_MASK (0x80U)0DMA_EEI_EEI7_SHIFT (7U)0DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)0DMA_EEI_EEI8_MASK (0x100U)0DMA_EEI_EEI8_SHIFT (8U)0DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)0DMA_EEI_EEI9_MASK (0x200U)0DMA_EEI_EEI9_SHIFT (9U)0DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)0DMA_EEI_EEI10_MASK (0x400U)0DMA_EEI_EEI10_SHIFT (10U)0DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)0DMA_EEI_EEI11_MASK (0x800U)0DMA_EEI_EEI11_SHIFT (11U)0DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)0DMA_EEI_EEI12_MASK (0x1000U)0DMA_EEI_EEI12_SHIFT (12U)0DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)0DMA_EEI_EEI13_MASK (0x2000U)0DMA_EEI_EEI13_SHIFT (13U)0DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)0DMA_EEI_EEI14_MASK (0x4000U)0DMA_EEI_EEI14_SHIFT (14U)0DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)0DMA_EEI_EEI15_MASK (0x8000U)0DMA_EEI_EEI15_SHIFT (15U)0DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)0DMA_EEI_EEI16_MASK (0x10000U)0DMA_EEI_EEI16_SHIFT (16U)0DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)0DMA_EEI_EEI17_MASK (0x20000U)0DMA_EEI_EEI17_SHIFT (17U)0DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)0DMA_EEI_EEI18_MASK (0x40000U)0DMA_EEI_EEI18_SHIFT (18U)0DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)0DMA_EEI_EEI19_MASK (0x80000U)0DMA_EEI_EEI19_SHIFT (19U)0DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)0DMA_EEI_EEI20_MASK (0x100000U)0DMA_EEI_EEI20_SHIFT (20U)0DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)0DMA_EEI_EEI21_MASK (0x200000U)0DMA_EEI_EEI21_SHIFT (21U)0DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)0DMA_EEI_EEI22_MASK (0x400000U)0DMA_EEI_EEI22_SHIFT (22U)0DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)0DMA_EEI_EEI23_MASK (0x800000U)0DMA_EEI_EEI23_SHIFT (23U)0DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)0DMA_EEI_EEI24_MASK (0x1000000U)0DMA_EEI_EEI24_SHIFT (24U)0DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)0DMA_EEI_EEI25_MASK (0x2000000U)0DMA_EEI_EEI25_SHIFT (25U)0DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)0DMA_EEI_EEI26_MASK (0x4000000U)0DMA_EEI_EEI26_SHIFT (26U)0DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)0DMA_EEI_EEI27_MASK (0x8000000U)0DMA_EEI_EEI27_SHIFT (27U)0DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)0DMA_EEI_EEI28_MASK (0x10000000U)0DMA_EEI_EEI28_SHIFT (28U)0DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)0DMA_EEI_EEI29_MASK (0x20000000U)0DMA_EEI_EEI29_SHIFT (29U)0DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)0DMA_EEI_EEI30_MASK (0x40000000U)0DMA_EEI_EEI30_SHIFT (30U)0DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)0DMA_EEI_EEI31_MASK (0x80000000U)0DMA_EEI_EEI31_SHIFT (31U)0DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)0DMA_CEEI_CEEI_MASK (0x1FU)0DMA_CEEI_CEEI_SHIFT (0U)0DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)0DMA_CEEI_CAEE_MASK (0x40U)0DMA_CEEI_CAEE_SHIFT (6U)0DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)0DMA_CEEI_NOP_MASK (0x80U)0DMA_CEEI_NOP_SHIFT (7U)0DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)0DMA_SEEI_SEEI_MASK (0x1FU)0DMA_SEEI_SEEI_SHIFT (0U)0DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)0DMA_SEEI_SAEE_MASK (0x40U)0DMA_SEEI_SAEE_SHIFT (6U)0DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)0DMA_SEEI_NOP_MASK (0x80U)0DMA_SEEI_NOP_SHIFT (7U)0DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)0DMA_CERQ_CERQ_MASK (0x1FU)0DMA_CERQ_CERQ_SHIFT (0U)0DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)0DMA_CERQ_CAER_MASK (0x40U)0DMA_CERQ_CAER_SHIFT (6U)0DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)0DMA_CERQ_NOP_MASK (0x80U)0DMA_CERQ_NOP_SHIFT (7U)0DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)0DMA_SERQ_SERQ_MASK (0x1FU)0DMA_SERQ_SERQ_SHIFT (0U)0DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)0DMA_SERQ_SAER_MASK (0x40U)0DMA_SERQ_SAER_SHIFT (6U)0DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)0DMA_SERQ_NOP_MASK (0x80U)0DMA_SERQ_NOP_SHIFT (7U)0DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)1DMA_CDNE_CDNE_MASK (0x1FU)1DMA_CDNE_CDNE_SHIFT (0U)1DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)1DMA_CDNE_CADN_MASK (0x40U)1DMA_CDNE_CADN_SHIFT (6U)1DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)1DMA_CDNE_NOP_MASK (0x80U)1DMA_CDNE_NOP_SHIFT (7U)1DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)1DMA_SSRT_SSRT_MASK (0x1FU)1DMA_SSRT_SSRT_SHIFT (0U)1DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)1DMA_SSRT_SAST_MASK (0x40U)1DMA_SSRT_SAST_SHIFT (6U)1DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)1DMA_SSRT_NOP_MASK (0x80U)1DMA_SSRT_NOP_SHIFT (7U)1DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)1DMA_CERR_CERR_MASK (0x1FU)1DMA_CERR_CERR_SHIFT (0U)1DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)1DMA_CERR_CAEI_MASK (0x40U)1DMA_CERR_CAEI_SHIFT (6U)1DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)1DMA_CERR_NOP_MASK (0x80U)1DMA_CERR_NOP_SHIFT (7U)1DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)1DMA_CINT_CINT_MASK (0x1FU)1DMA_CINT_CINT_SHIFT (0U)1DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)1DMA_CINT_CAIR_MASK (0x40U)1DMA_CINT_CAIR_SHIFT (6U)1DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)1DMA_CINT_NOP_MASK (0x80U)1DMA_CINT_NOP_SHIFT (7U)1DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)1DMA_INT_INT0_MASK (0x1U)1DMA_INT_INT0_SHIFT (0U)1DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)1DMA_INT_INT1_MASK (0x2U)1DMA_INT_INT1_SHIFT (1U)1DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)1DMA_INT_INT2_MASK (0x4U)1DMA_INT_INT2_SHIFT (2U)1DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)1DMA_INT_INT3_MASK (0x8U)1DMA_INT_INT3_SHIFT (3U)1DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)1DMA_INT_INT4_MASK (0x10U)1DMA_INT_INT4_SHIFT (4U)1DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)1DMA_INT_INT5_MASK (0x20U)1DMA_INT_INT5_SHIFT (5U)1DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)1DMA_INT_INT6_MASK (0x40U)1DMA_INT_INT6_SHIFT (6U)1DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)1DMA_INT_INT7_MASK (0x80U)1DMA_INT_INT7_SHIFT (7U)1DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)1DMA_INT_INT8_MASK (0x100U)1DMA_INT_INT8_SHIFT (8U)1DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)1DMA_INT_INT9_MASK (0x200U)1DMA_INT_INT9_SHIFT (9U)1DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)1DMA_INT_INT10_MASK (0x400U)1DMA_INT_INT10_SHIFT (10U)1DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)1DMA_INT_INT11_MASK (0x800U)1DMA_INT_INT11_SHIFT (11U)1DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)1DMA_INT_INT12_MASK (0x1000U)1DMA_INT_INT12_SHIFT (12U)1DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)1DMA_INT_INT13_MASK (0x2000U)1DMA_INT_INT13_SHIFT (13U)1DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)1DMA_INT_INT14_MASK (0x4000U)1DMA_INT_INT14_SHIFT (14U)1DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)1DMA_INT_INT15_MASK (0x8000U)1DMA_INT_INT15_SHIFT (15U)1DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)1DMA_INT_INT16_MASK (0x10000U)1DMA_INT_INT16_SHIFT (16U)1DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)1DMA_INT_INT17_MASK (0x20000U)1DMA_INT_INT17_SHIFT (17U)1DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)1DMA_INT_INT18_MASK (0x40000U)1DMA_INT_INT18_SHIFT (18U)1DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)1DMA_INT_INT19_MASK (0x80000U)1DMA_INT_INT19_SHIFT (19U)1DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)1DMA_INT_INT20_MASK (0x100000U)1DMA_INT_INT20_SHIFT (20U)1DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)1DMA_INT_INT21_MASK (0x200000U)1DMA_INT_INT21_SHIFT (21U)1DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)1DMA_INT_INT22_MASK (0x400000U)1DMA_INT_INT22_SHIFT (22U)1DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)1DMA_INT_INT23_MASK (0x800000U)1DMA_INT_INT23_SHIFT (23U)1DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)1DMA_INT_INT24_MASK (0x1000000U)1DMA_INT_INT24_SHIFT (24U)2DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)2DMA_INT_INT25_MASK (0x2000000U)2DMA_INT_INT25_SHIFT (25U)2DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)2DMA_INT_INT26_MASK (0x4000000U)2DMA_INT_INT26_SHIFT (26U)2DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)2DMA_INT_INT27_MASK (0x8000000U)2DMA_INT_INT27_SHIFT (27U)2DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)2DMA_INT_INT28_MASK (0x10000000U)2DMA_INT_INT28_SHIFT (28U)2DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)2DMA_INT_INT29_MASK (0x20000000U)2DMA_INT_INT29_SHIFT (29U)2DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)2DMA_INT_INT30_MASK (0x40000000U)2DMA_INT_INT30_SHIFT (30U)2DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)2DMA_INT_INT31_MASK (0x80000000U)2DMA_INT_INT31_SHIFT (31U)2DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)2DMA_ERR_ERR0_MASK (0x1U)2DMA_ERR_ERR0_SHIFT (0U)2DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)2DMA_ERR_ERR1_MASK (0x2U)2DMA_ERR_ERR1_SHIFT (1U)2DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)2DMA_ERR_ERR2_MASK (0x4U)2DMA_ERR_ERR2_SHIFT (2U)2DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)2DMA_ERR_ERR3_MASK (0x8U)2DMA_ERR_ERR3_SHIFT (3U)2DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)2DMA_ERR_ERR4_MASK (0x10U)2DMA_ERR_ERR4_SHIFT (4U)2DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)2DMA_ERR_ERR5_MASK (0x20U)2DMA_ERR_ERR5_SHIFT (5U)2DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)2DMA_ERR_ERR6_MASK (0x40U)2DMA_ERR_ERR6_SHIFT (6U)2DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)2DMA_ERR_ERR7_MASK (0x80U)2DMA_ERR_ERR7_SHIFT (7U)2DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)2DMA_ERR_ERR8_MASK (0x100U)2DMA_ERR_ERR8_SHIFT (8U)2DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)2DMA_ERR_ERR9_MASK (0x200U)2DMA_ERR_ERR9_SHIFT (9U)2DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)2DMA_ERR_ERR10_MASK (0x400U)2DMA_ERR_ERR10_SHIFT (10U)2DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)2DMA_ERR_ERR11_MASK (0x800U)2DMA_ERR_ERR11_SHIFT (11U)2DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)2DMA_ERR_ERR12_MASK (0x1000U)2DMA_ERR_ERR12_SHIFT (12U)2DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)2DMA_ERR_ERR13_MASK (0x2000U)2DMA_ERR_ERR13_SHIFT (13U)2DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)2DMA_ERR_ERR14_MASK (0x4000U)2DMA_ERR_ERR14_SHIFT (14U)2DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)2DMA_ERR_ERR15_MASK (0x8000U)2DMA_ERR_ERR15_SHIFT (15U)2DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)2DMA_ERR_ERR16_MASK (0x10000U)2DMA_ERR_ERR16_SHIFT (16U)2DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)2DMA_ERR_ERR17_MASK (0x20000U)2DMA_ERR_ERR17_SHIFT (17U)2DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)2DMA_ERR_ERR18_MASK (0x40000U)2DMA_ERR_ERR18_SHIFT (18U)2DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)2DMA_ERR_ERR19_MASK (0x80000U)2DMA_ERR_ERR19_SHIFT (19U)2DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)2DMA_ERR_ERR20_MASK (0x100000U)2DMA_ERR_ERR20_SHIFT (20U)2DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)2DMA_ERR_ERR21_MASK (0x200000U)2DMA_ERR_ERR21_SHIFT (21U)2DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)2DMA_ERR_ERR22_MASK (0x400000U)2DMA_ERR_ERR22_SHIFT (22U)2DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)2DMA_ERR_ERR23_MASK (0x800000U)2DMA_ERR_ERR23_SHIFT (23U)2DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)2DMA_ERR_ERR24_MASK (0x1000000U)2DMA_ERR_ERR24_SHIFT (24U)2DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)2DMA_ERR_ERR25_MASK (0x2000000U)2DMA_ERR_ERR25_SHIFT (25U)2DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)2DMA_ERR_ERR26_MASK (0x4000000U)2DMA_ERR_ERR26_SHIFT (26U)2DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)2DMA_ERR_ERR27_MASK (0x8000000U)2DMA_ERR_ERR27_SHIFT (27U)2DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)2DMA_ERR_ERR28_MASK (0x10000000U)2DMA_ERR_ERR28_SHIFT (28U)2DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)2DMA_ERR_ERR29_MASK (0x20000000U)2DMA_ERR_ERR29_SHIFT (29U)2DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)2DMA_ERR_ERR30_MASK (0x40000000U)2DMA_ERR_ERR30_SHIFT (30U)2DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)2DMA_ERR_ERR31_MASK (0x80000000U)2DMA_ERR_ERR31_SHIFT (31U)2DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)2DMA_HRS_HRS0_MASK (0x1U)2DMA_HRS_HRS0_SHIFT (0U)3DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)3DMA_HRS_HRS1_MASK (0x2U)3DMA_HRS_HRS1_SHIFT (1U)3DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)3DMA_HRS_HRS2_MASK (0x4U)3DMA_HRS_HRS2_SHIFT (2U)3DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)3DMA_HRS_HRS3_MASK (0x8U)3DMA_HRS_HRS3_SHIFT (3U)3DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)3DMA_HRS_HRS4_MASK (0x10U)3DMA_HRS_HRS4_SHIFT (4U)3DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)3DMA_HRS_HRS5_MASK (0x20U)3DMA_HRS_HRS5_SHIFT (5U)3DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)3DMA_HRS_HRS6_MASK (0x40U)3DMA_HRS_HRS6_SHIFT (6U)3DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)3DMA_HRS_HRS7_MASK (0x80U)3DMA_HRS_HRS7_SHIFT (7U)3DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)3DMA_HRS_HRS8_MASK (0x100U)3DMA_HRS_HRS8_SHIFT (8U)3DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)3DMA_HRS_HRS9_MASK (0x200U)3DMA_HRS_HRS9_SHIFT (9U)3DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)3DMA_HRS_HRS10_MASK (0x400U)3DMA_HRS_HRS10_SHIFT (10U)3DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)3DMA_HRS_HRS11_MASK (0x800U)3DMA_HRS_HRS11_SHIFT (11U)3DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)3DMA_HRS_HRS12_MASK (0x1000U)3DMA_HRS_HRS12_SHIFT (12U)3DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)3DMA_HRS_HRS13_MASK (0x2000U)3DMA_HRS_HRS13_SHIFT (13U)3DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)3DMA_HRS_HRS14_MASK (0x4000U)3DMA_HRS_HRS14_SHIFT (14U)3DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)3DMA_HRS_HRS15_MASK (0x8000U)3DMA_HRS_HRS15_SHIFT (15U)3DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)3DMA_HRS_HRS16_MASK (0x10000U)3DMA_HRS_HRS16_SHIFT (16U)3DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)3DMA_HRS_HRS17_MASK (0x20000U)3DMA_HRS_HRS17_SHIFT (17U)3DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)3DMA_HRS_HRS18_MASK (0x40000U)3DMA_HRS_HRS18_SHIFT (18U)3DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)3DMA_HRS_HRS19_MASK (0x80000U)3DMA_HRS_HRS19_SHIFT (19U)3DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)3DMA_HRS_HRS20_MASK (0x100000U)3DMA_HRS_HRS20_SHIFT (20U)3DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)3DMA_HRS_HRS21_MASK (0x200000U)3DMA_HRS_HRS21_SHIFT (21U)3DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)3DMA_HRS_HRS22_MASK (0x400000U)3DMA_HRS_HRS22_SHIFT (22U)3DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)3DMA_HRS_HRS23_MASK (0x800000U)3DMA_HRS_HRS23_SHIFT (23U)3DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)3DMA_HRS_HRS24_MASK (0x1000000U)3DMA_HRS_HRS24_SHIFT (24U)3DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)3DMA_HRS_HRS25_MASK (0x2000000U)3DMA_HRS_HRS25_SHIFT (25U)3DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)3DMA_HRS_HRS26_MASK (0x4000000U)3DMA_HRS_HRS26_SHIFT (26U)3DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)3DMA_HRS_HRS27_MASK (0x8000000U)3DMA_HRS_HRS27_SHIFT (27U)3DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)3DMA_HRS_HRS28_MASK (0x10000000U)3DMA_HRS_HRS28_SHIFT (28U)3DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)3DMA_HRS_HRS29_MASK (0x20000000U)3DMA_HRS_HRS29_SHIFT (29U)3DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)3DMA_HRS_HRS30_MASK (0x40000000U)3DMA_HRS_HRS30_SHIFT (30U)3DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)3DMA_HRS_HRS31_MASK (0x80000000U)3DMA_HRS_HRS31_SHIFT (31U)3DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)3DMA_EARS_EDREQ_0_MASK (0x1U)3DMA_EARS_EDREQ_0_SHIFT (0U)3DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)3DMA_EARS_EDREQ_1_MASK (0x2U)3DMA_EARS_EDREQ_1_SHIFT (1U)3DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)3DMA_EARS_EDREQ_2_MASK (0x4U)3DMA_EARS_EDREQ_2_SHIFT (2U)3DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)3DMA_EARS_EDREQ_3_MASK (0x8U)3DMA_EARS_EDREQ_3_SHIFT (3U)3DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)3DMA_EARS_EDREQ_4_MASK (0x10U)3DMA_EARS_EDREQ_4_SHIFT (4U)3DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)3DMA_EARS_EDREQ_5_MASK (0x20U)3DMA_EARS_EDREQ_5_SHIFT (5U)3DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)3DMA_EARS_EDREQ_6_MASK (0x40U)3DMA_EARS_EDREQ_6_SHIFT (6U)3DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)3DMA_EARS_EDREQ_7_MASK (0x80U)3DMA_EARS_EDREQ_7_SHIFT (7U)3DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)3DMA_EARS_EDREQ_8_MASK (0x100U)3DMA_EARS_EDREQ_8_SHIFT (8U)3DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)3DMA_EARS_EDREQ_9_MASK (0x200U)3DMA_EARS_EDREQ_9_SHIFT (9U)3DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)4DMA_EARS_EDREQ_10_MASK (0x400U)4DMA_EARS_EDREQ_10_SHIFT (10U)4DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)4DMA_EARS_EDREQ_11_MASK (0x800U)4DMA_EARS_EDREQ_11_SHIFT (11U)4DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)4DMA_EARS_EDREQ_12_MASK (0x1000U)4DMA_EARS_EDREQ_12_SHIFT (12U)4DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)4DMA_EARS_EDREQ_13_MASK (0x2000U)4DMA_EARS_EDREQ_13_SHIFT (13U)4DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)4DMA_EARS_EDREQ_14_MASK (0x4000U)4DMA_EARS_EDREQ_14_SHIFT (14U)4DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)4DMA_EARS_EDREQ_15_MASK (0x8000U)4DMA_EARS_EDREQ_15_SHIFT (15U)4DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)4DMA_EARS_EDREQ_16_MASK (0x10000U)4DMA_EARS_EDREQ_16_SHIFT (16U)4DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)4DMA_EARS_EDREQ_17_MASK (0x20000U)4DMA_EARS_EDREQ_17_SHIFT (17U)4DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)4DMA_EARS_EDREQ_18_MASK (0x40000U)4DMA_EARS_EDREQ_18_SHIFT (18U)4DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)4DMA_EARS_EDREQ_19_MASK (0x80000U)4DMA_EARS_EDREQ_19_SHIFT (19U)4DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)4DMA_EARS_EDREQ_20_MASK (0x100000U)4DMA_EARS_EDREQ_20_SHIFT (20U)4DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)4DMA_EARS_EDREQ_21_MASK (0x200000U)4DMA_EARS_EDREQ_21_SHIFT (21U)4DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)4DMA_EARS_EDREQ_22_MASK (0x400000U)4DMA_EARS_EDREQ_22_SHIFT (22U)4DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)4DMA_EARS_EDREQ_23_MASK (0x800000U)4DMA_EARS_EDREQ_23_SHIFT (23U)4DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)4DMA_EARS_EDREQ_24_MASK (0x1000000U)4DMA_EARS_EDREQ_24_SHIFT (24U)4DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)4DMA_EARS_EDREQ_25_MASK (0x2000000U)4DMA_EARS_EDREQ_25_SHIFT (25U)4DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)4DMA_EARS_EDREQ_26_MASK (0x4000000U)4DMA_EARS_EDREQ_26_SHIFT (26U)4DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)4DMA_EARS_EDREQ_27_MASK (0x8000000U)4DMA_EARS_EDREQ_27_SHIFT (27U)4DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)4DMA_EARS_EDREQ_28_MASK (0x10000000U)4DMA_EARS_EDREQ_28_SHIFT (28U)4DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)4DMA_EARS_EDREQ_29_MASK (0x20000000U)4DMA_EARS_EDREQ_29_SHIFT (29U)4DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)4DMA_EARS_EDREQ_30_MASK (0x40000000U)4DMA_EARS_EDREQ_30_SHIFT (30U)4DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)4DMA_EARS_EDREQ_31_MASK (0x80000000U)4DMA_EARS_EDREQ_31_SHIFT (31U)4DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)4DMA_DCHPRI3_CHPRI_MASK (0xFU)4DMA_DCHPRI3_CHPRI_SHIFT (0U)4DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)4DMA_DCHPRI3_GRPPRI_MASK (0x30U)4DMA_DCHPRI3_GRPPRI_SHIFT (4U)4DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)4DMA_DCHPRI3_DPA_MASK (0x40U)4DMA_DCHPRI3_DPA_SHIFT (6U)4DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)4DMA_DCHPRI3_ECP_MASK (0x80U)4DMA_DCHPRI3_ECP_SHIFT (7U)4DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)4DMA_DCHPRI2_CHPRI_MASK (0xFU)4DMA_DCHPRI2_CHPRI_SHIFT (0U)4DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)4DMA_DCHPRI2_GRPPRI_MASK (0x30U)4DMA_DCHPRI2_GRPPRI_SHIFT (4U)4DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)4DMA_DCHPRI2_DPA_MASK (0x40U)4DMA_DCHPRI2_DPA_SHIFT (6U)4DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)4DMA_DCHPRI2_ECP_MASK (0x80U)4DMA_DCHPRI2_ECP_SHIFT (7U)4DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)4DMA_DCHPRI1_CHPRI_MASK (0xFU)4DMA_DCHPRI1_CHPRI_SHIFT (0U)4DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)4DMA_DCHPRI1_GRPPRI_MASK (0x30U)4DMA_DCHPRI1_GRPPRI_SHIFT (4U)4DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)4DMA_DCHPRI1_DPA_MASK (0x40U)4DMA_DCHPRI1_DPA_SHIFT (6U)4DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)4DMA_DCHPRI1_ECP_MASK (0x80U)4DMA_DCHPRI1_ECP_SHIFT (7U)4DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)4DMA_DCHPRI0_CHPRI_MASK (0xFU)4DMA_DCHPRI0_CHPRI_SHIFT (0U)4DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)4DMA_DCHPRI0_GRPPRI_MASK (0x30U)4DMA_DCHPRI0_GRPPRI_SHIFT (4U)4DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)4DMA_DCHPRI0_DPA_MASK (0x40U)4DMA_DCHPRI0_DPA_SHIFT (6U)4DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)4DMA_DCHPRI0_ECP_MASK (0x80U)5DMA_DCHPRI0_ECP_SHIFT (7U)5DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)5DMA_DCHPRI7_CHPRI_MASK (0xFU)5DMA_DCHPRI7_CHPRI_SHIFT (0U)5DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)5DMA_DCHPRI7_GRPPRI_MASK (0x30U)5DMA_DCHPRI7_GRPPRI_SHIFT (4U)5DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)5DMA_DCHPRI7_DPA_MASK (0x40U)5DMA_DCHPRI7_DPA_SHIFT (6U)5DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)5DMA_DCHPRI7_ECP_MASK (0x80U)5DMA_DCHPRI7_ECP_SHIFT (7U)5DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)5DMA_DCHPRI6_CHPRI_MASK (0xFU)5DMA_DCHPRI6_CHPRI_SHIFT (0U)5DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)5DMA_DCHPRI6_GRPPRI_MASK (0x30U)5DMA_DCHPRI6_GRPPRI_SHIFT (4U)5DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)5DMA_DCHPRI6_DPA_MASK (0x40U)5DMA_DCHPRI6_DPA_SHIFT (6U)5DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)5DMA_DCHPRI6_ECP_MASK (0x80U)5DMA_DCHPRI6_ECP_SHIFT (7U)5DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)5DMA_DCHPRI5_CHPRI_MASK (0xFU)5DMA_DCHPRI5_CHPRI_SHIFT (0U)5DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)5DMA_DCHPRI5_GRPPRI_MASK (0x30U)5DMA_DCHPRI5_GRPPRI_SHIFT (4U)5DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)5DMA_DCHPRI5_DPA_MASK (0x40U)5DMA_DCHPRI5_DPA_SHIFT (6U)5DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)5DMA_DCHPRI5_ECP_MASK (0x80U)5DMA_DCHPRI5_ECP_SHIFT (7U)5DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)5DMA_DCHPRI4_CHPRI_MASK (0xFU)5DMA_DCHPRI4_CHPRI_SHIFT (0U)5DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)5DMA_DCHPRI4_GRPPRI_MASK (0x30U)5DMA_DCHPRI4_GRPPRI_SHIFT (4U)5DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)5DMA_DCHPRI4_DPA_MASK (0x40U)5DMA_DCHPRI4_DPA_SHIFT (6U)5DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)5DMA_DCHPRI4_ECP_MASK (0x80U)5DMA_DCHPRI4_ECP_SHIFT (7U)5DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)5DMA_DCHPRI11_CHPRI_MASK (0xFU)5DMA_DCHPRI11_CHPRI_SHIFT (0U)5DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)5DMA_DCHPRI11_GRPPRI_MASK (0x30U)5DMA_DCHPRI11_GRPPRI_SHIFT (4U)5DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)5DMA_DCHPRI11_DPA_MASK (0x40U)5DMA_DCHPRI11_DPA_SHIFT (6U)5DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)5DMA_DCHPRI11_ECP_MASK (0x80U)5DMA_DCHPRI11_ECP_SHIFT (7U)5DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)5DMA_DCHPRI10_CHPRI_MASK (0xFU)5DMA_DCHPRI10_CHPRI_SHIFT (0U)5DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)5DMA_DCHPRI10_GRPPRI_MASK (0x30U)5DMA_DCHPRI10_GRPPRI_SHIFT (4U)5DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)5DMA_DCHPRI10_DPA_MASK (0x40U)5DMA_DCHPRI10_DPA_SHIFT (6U)5DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)5DMA_DCHPRI10_ECP_MASK (0x80U)5DMA_DCHPRI10_ECP_SHIFT (7U)5DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)5DMA_DCHPRI9_CHPRI_MASK (0xFU)5DMA_DCHPRI9_CHPRI_SHIFT (0U)5DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)5DMA_DCHPRI9_GRPPRI_MASK (0x30U)5DMA_DCHPRI9_GRPPRI_SHIFT (4U)5DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)5DMA_DCHPRI9_DPA_MASK (0x40U)5DMA_DCHPRI9_DPA_SHIFT (6U)5DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)5DMA_DCHPRI9_ECP_MASK (0x80U)5DMA_DCHPRI9_ECP_SHIFT (7U)5DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)5DMA_DCHPRI8_CHPRI_MASK (0xFU)5DMA_DCHPRI8_CHPRI_SHIFT (0U)5DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)5DMA_DCHPRI8_GRPPRI_MASK (0x30U)5DMA_DCHPRI8_GRPPRI_SHIFT (4U)5DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)5DMA_DCHPRI8_DPA_MASK (0x40U)5DMA_DCHPRI8_DPA_SHIFT (6U)5DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)5DMA_DCHPRI8_ECP_MASK (0x80U)6DMA_DCHPRI8_ECP_SHIFT (7U)6DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)6DMA_DCHPRI15_CHPRI_MASK (0xFU)6DMA_DCHPRI15_CHPRI_SHIFT (0U)6DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)6DMA_DCHPRI15_GRPPRI_MASK (0x30U)6DMA_DCHPRI15_GRPPRI_SHIFT (4U)6DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)6DMA_DCHPRI15_DPA_MASK (0x40U)6DMA_DCHPRI15_DPA_SHIFT (6U)6DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)6DMA_DCHPRI15_ECP_MASK (0x80U)6DMA_DCHPRI15_ECP_SHIFT (7U)6DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)6DMA_DCHPRI14_CHPRI_MASK (0xFU)6DMA_DCHPRI14_CHPRI_SHIFT (0U)6DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)6DMA_DCHPRI14_GRPPRI_MASK (0x30U)6DMA_DCHPRI14_GRPPRI_SHIFT (4U)6DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)6DMA_DCHPRI14_DPA_MASK (0x40U)6DMA_DCHPRI14_DPA_SHIFT (6U)6DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)6DMA_DCHPRI14_ECP_MASK (0x80U)6DMA_DCHPRI14_ECP_SHIFT (7U)6DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)6DMA_DCHPRI13_CHPRI_MASK (0xFU)6DMA_DCHPRI13_CHPRI_SHIFT (0U)6DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)6DMA_DCHPRI13_GRPPRI_MASK (0x30U)6DMA_DCHPRI13_GRPPRI_SHIFT (4U)6DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)6DMA_DCHPRI13_DPA_MASK (0x40U)6DMA_DCHPRI13_DPA_SHIFT (6U)6DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)6DMA_DCHPRI13_ECP_MASK (0x80U)6DMA_DCHPRI13_ECP_SHIFT (7U)6DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)6DMA_DCHPRI12_CHPRI_MASK (0xFU)6DMA_DCHPRI12_CHPRI_SHIFT (0U)6DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)6DMA_DCHPRI12_GRPPRI_MASK (0x30U)6DMA_DCHPRI12_GRPPRI_SHIFT (4U)6DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)6DMA_DCHPRI12_DPA_MASK (0x40U)6DMA_DCHPRI12_DPA_SHIFT (6U)6DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)6DMA_DCHPRI12_ECP_MASK (0x80U)6DMA_DCHPRI12_ECP_SHIFT (7U)6DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)6DMA_DCHPRI19_CHPRI_MASK (0xFU)6DMA_DCHPRI19_CHPRI_SHIFT (0U)6DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)6DMA_DCHPRI19_GRPPRI_MASK (0x30U)6DMA_DCHPRI19_GRPPRI_SHIFT (4U)6DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)6DMA_DCHPRI19_DPA_MASK (0x40U)6DMA_DCHPRI19_DPA_SHIFT (6U)6DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)6DMA_DCHPRI19_ECP_MASK (0x80U)6DMA_DCHPRI19_ECP_SHIFT (7U)6DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)6DMA_DCHPRI18_CHPRI_MASK (0xFU)6DMA_DCHPRI18_CHPRI_SHIFT (0U)6DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)6DMA_DCHPRI18_GRPPRI_MASK (0x30U)6DMA_DCHPRI18_GRPPRI_SHIFT (4U)6DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)6DMA_DCHPRI18_DPA_MASK (0x40U)6DMA_DCHPRI18_DPA_SHIFT (6U)6DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)6DMA_DCHPRI18_ECP_MASK (0x80U)6DMA_DCHPRI18_ECP_SHIFT (7U)6DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)6DMA_DCHPRI17_CHPRI_MASK (0xFU)6DMA_DCHPRI17_CHPRI_SHIFT (0U)6DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)6DMA_DCHPRI17_GRPPRI_MASK (0x30U)6DMA_DCHPRI17_GRPPRI_SHIFT (4U)6DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)6DMA_DCHPRI17_DPA_MASK (0x40U)6DMA_DCHPRI17_DPA_SHIFT (6U)6DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)6DMA_DCHPRI17_ECP_MASK (0x80U)6DMA_DCHPRI17_ECP_SHIFT (7U)6DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)6DMA_DCHPRI16_CHPRI_MASK (0xFU)6DMA_DCHPRI16_CHPRI_SHIFT (0U)6DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)6DMA_DCHPRI16_GRPPRI_MASK (0x30U)6DMA_DCHPRI16_GRPPRI_SHIFT (4U)6DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)6DMA_DCHPRI16_DPA_MASK (0x40U)6DMA_DCHPRI16_DPA_SHIFT (6U)6DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)6DMA_DCHPRI16_ECP_MASK (0x80U)7DMA_DCHPRI16_ECP_SHIFT (7U)7DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)7DMA_DCHPRI23_CHPRI_MASK (0xFU)7DMA_DCHPRI23_CHPRI_SHIFT (0U)7DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)7DMA_DCHPRI23_GRPPRI_MASK (0x30U)7DMA_DCHPRI23_GRPPRI_SHIFT (4U)7DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)7DMA_DCHPRI23_DPA_MASK (0x40U)7DMA_DCHPRI23_DPA_SHIFT (6U)7DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)7DMA_DCHPRI23_ECP_MASK (0x80U)7DMA_DCHPRI23_ECP_SHIFT (7U)7DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)7DMA_DCHPRI22_CHPRI_MASK (0xFU)7DMA_DCHPRI22_CHPRI_SHIFT (0U)7DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)7DMA_DCHPRI22_GRPPRI_MASK (0x30U)7DMA_DCHPRI22_GRPPRI_SHIFT (4U)7DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)7DMA_DCHPRI22_DPA_MASK (0x40U)7DMA_DCHPRI22_DPA_SHIFT (6U)7DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)7DMA_DCHPRI22_ECP_MASK (0x80U)7DMA_DCHPRI22_ECP_SHIFT (7U)7DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)7DMA_DCHPRI21_CHPRI_MASK (0xFU)7DMA_DCHPRI21_CHPRI_SHIFT (0U)7DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)7DMA_DCHPRI21_GRPPRI_MASK (0x30U)7DMA_DCHPRI21_GRPPRI_SHIFT (4U)7DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)7DMA_DCHPRI21_DPA_MASK (0x40U)7DMA_DCHPRI21_DPA_SHIFT (6U)7DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)7DMA_DCHPRI21_ECP_MASK (0x80U)7DMA_DCHPRI21_ECP_SHIFT (7U)7DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)7DMA_DCHPRI20_CHPRI_MASK (0xFU)7DMA_DCHPRI20_CHPRI_SHIFT (0U)7DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)7DMA_DCHPRI20_GRPPRI_MASK (0x30U)7DMA_DCHPRI20_GRPPRI_SHIFT (4U)7DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)7DMA_DCHPRI20_DPA_MASK (0x40U)7DMA_DCHPRI20_DPA_SHIFT (6U)7DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)7DMA_DCHPRI20_ECP_MASK (0x80U)7DMA_DCHPRI20_ECP_SHIFT (7U)7DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)7DMA_DCHPRI27_CHPRI_MASK (0xFU)7DMA_DCHPRI27_CHPRI_SHIFT (0U)7DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)7DMA_DCHPRI27_GRPPRI_MASK (0x30U)7DMA_DCHPRI27_GRPPRI_SHIFT (4U)7DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)7DMA_DCHPRI27_DPA_MASK (0x40U)7DMA_DCHPRI27_DPA_SHIFT (6U)7DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)7DMA_DCHPRI27_ECP_MASK (0x80U)7DMA_DCHPRI27_ECP_SHIFT (7U)7DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)7DMA_DCHPRI26_CHPRI_MASK (0xFU)7DMA_DCHPRI26_CHPRI_SHIFT (0U)7DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)7DMA_DCHPRI26_GRPPRI_MASK (0x30U)7DMA_DCHPRI26_GRPPRI_SHIFT (4U)7DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)7DMA_DCHPRI26_DPA_MASK (0x40U)7DMA_DCHPRI26_DPA_SHIFT (6U)7DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)7DMA_DCHPRI26_ECP_MASK (0x80U)7DMA_DCHPRI26_ECP_SHIFT (7U)7DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)7DMA_DCHPRI25_CHPRI_MASK (0xFU)7DMA_DCHPRI25_CHPRI_SHIFT (0U)7DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)7DMA_DCHPRI25_GRPPRI_MASK (0x30U)7DMA_DCHPRI25_GRPPRI_SHIFT (4U)7DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)7DMA_DCHPRI25_DPA_MASK (0x40U)7DMA_DCHPRI25_DPA_SHIFT (6U)7DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)7DMA_DCHPRI25_ECP_MASK (0x80U)7DMA_DCHPRI25_ECP_SHIFT (7U)7DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)7DMA_DCHPRI24_CHPRI_MASK (0xFU)7DMA_DCHPRI24_CHPRI_SHIFT (0U)7DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)7DMA_DCHPRI24_GRPPRI_MASK (0x30U)7DMA_DCHPRI24_GRPPRI_SHIFT (4U)7DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)7DMA_DCHPRI24_DPA_MASK (0x40U)7DMA_DCHPRI24_DPA_SHIFT (6U)7DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)7DMA_DCHPRI24_ECP_MASK (0x80U)8DMA_DCHPRI24_ECP_SHIFT (7U)8DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)8DMA_DCHPRI31_CHPRI_MASK (0xFU)8DMA_DCHPRI31_CHPRI_SHIFT (0U)8DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)8DMA_DCHPRI31_GRPPRI_MASK (0x30U)8DMA_DCHPRI31_GRPPRI_SHIFT (4U)8DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)8DMA_DCHPRI31_DPA_MASK (0x40U)8DMA_DCHPRI31_DPA_SHIFT (6U)8DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)8DMA_DCHPRI31_ECP_MASK (0x80U)8DMA_DCHPRI31_ECP_SHIFT (7U)8DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)8DMA_DCHPRI30_CHPRI_MASK (0xFU)8DMA_DCHPRI30_CHPRI_SHIFT (0U)8DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)8DMA_DCHPRI30_GRPPRI_MASK (0x30U)8DMA_DCHPRI30_GRPPRI_SHIFT (4U)8DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)8DMA_DCHPRI30_DPA_MASK (0x40U)8DMA_DCHPRI30_DPA_SHIFT (6U)8DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)8DMA_DCHPRI30_ECP_MASK (0x80U)8DMA_DCHPRI30_ECP_SHIFT (7U)8DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)8DMA_DCHPRI29_CHPRI_MASK (0xFU)8DMA_DCHPRI29_CHPRI_SHIFT (0U)8DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)8DMA_DCHPRI29_GRPPRI_MASK (0x30U)8DMA_DCHPRI29_GRPPRI_SHIFT (4U)8DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)8DMA_DCHPRI29_DPA_MASK (0x40U)8DMA_DCHPRI29_DPA_SHIFT (6U)8DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)8DMA_DCHPRI29_ECP_MASK (0x80U)8DMA_DCHPRI29_ECP_SHIFT (7U)8DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)8DMA_DCHPRI28_CHPRI_MASK (0xFU)8DMA_DCHPRI28_CHPRI_SHIFT (0U)8DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)8DMA_DCHPRI28_GRPPRI_MASK (0x30U)8DMA_DCHPRI28_GRPPRI_SHIFT (4U)8DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)8DMA_DCHPRI28_DPA_MASK (0x40U)8DMA_DCHPRI28_DPA_SHIFT (6U)8DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)8DMA_DCHPRI28_ECP_MASK (0x80U)8DMA_DCHPRI28_ECP_SHIFT (7U)8DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)8DMA_DCHMID_MID_MASK (0xFU)8DMA_DCHMID_MID_SHIFT (0U)8DMA_DCHMID_MID(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_MID_SHIFT)) & DMA_DCHMID_MID_MASK)8DMA_DCHMID_PAL_MASK (0x40U)8DMA_DCHMID_PAL_SHIFT (6U)8DMA_DCHMID_PAL(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_PAL_SHIFT)) & DMA_DCHMID_PAL_MASK)8DMA_DCHMID_EMI_MASK (0x80U)8DMA_DCHMID_EMI_SHIFT (7U)8DMA_DCHMID_EMI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_EMI_SHIFT)) & DMA_DCHMID_EMI_MASK)8DMA_DCHMID_COUNT (32U)8DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)8DMA_SADDR_SADDR_SHIFT (0U)8DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)8DMA_SADDR_COUNT (32U)8DMA_SOFF_SOFF_MASK (0xFFFFU)8DMA_SOFF_SOFF_SHIFT (0U)8DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)8DMA_SOFF_COUNT (32U)8DMA_ATTR_DSIZE_MASK (0x7U)8DMA_ATTR_DSIZE_SHIFT (0U)8DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)8DMA_ATTR_DMOD_MASK (0xF8U)8DMA_ATTR_DMOD_SHIFT (3U)8DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)8DMA_ATTR_SSIZE_MASK (0x700U)8DMA_ATTR_SSIZE_SHIFT (8U)8DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)8DMA_ATTR_SMOD_MASK (0xF800U)8DMA_ATTR_SMOD_SHIFT (11U)8DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)8DMA_ATTR_COUNT (32U)8DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)8DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)8DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)9DMA_NBYTES_MLNO_COUNT (32U)9DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)9DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)9DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)9DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)9DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)9DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)9DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)9DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)9DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)9DMA_NBYTES_MLOFFNO_COUNT (32U)9DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)9DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)9DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)9DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)9DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)9DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)9DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)9DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)9DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)9DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)9DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)9DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)9DMA_NBYTES_MLOFFYES_COUNT (32U)9DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)9DMA_SLAST_SLAST_SHIFT (0U)9DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)9DMA_SLAST_COUNT (32U)9DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)9DMA_DADDR_DADDR_SHIFT (0U)9DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)9DMA_DADDR_COUNT (32U)9DMA_DOFF_DOFF_MASK (0xFFFFU)9DMA_DOFF_DOFF_SHIFT (0U)9DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)9DMA_DOFF_COUNT (32U)9DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)9DMA_CITER_ELINKNO_CITER_SHIFT (0U)9DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)9DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)9DMA_CITER_ELINKNO_ELINK_SHIFT (15U)9DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)9DMA_CITER_ELINKNO_COUNT (32U)9DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)9DMA_CITER_ELINKYES_CITER_SHIFT (0U)9DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)9DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)9DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)9DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)9DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)9DMA_CITER_ELINKYES_ELINK_SHIFT (15U)9DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)9DMA_CITER_ELINKYES_COUNT (32U)9DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)9DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)9DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)9DMA_DLAST_SGA_COUNT (32U)9DMA_CSR_START_MASK (0x1U)9DMA_CSR_START_SHIFT (0U)9DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)9DMA_CSR_INTMAJOR_MASK (0x2U)9DMA_CSR_INTMAJOR_SHIFT (1U)9DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)9DMA_CSR_INTHALF_MASK (0x4U)9DMA_CSR_INTHALF_SHIFT (2U)9DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)9DMA_CSR_DREQ_MASK (0x8U)9DMA_CSR_DREQ_SHIFT (3U)9DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)9DMA_CSR_ESG_MASK (0x10U)9DMA_CSR_ESG_SHIFT (4U)9DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)9DMA_CSR_MAJORELINK_MASK (0x20U)9DMA_CSR_MAJORELINK_SHIFT (5U):DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK):DMA_CSR_ACTIVE_MASK (0x40U):DMA_CSR_ACTIVE_SHIFT (6U):DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK):DMA_CSR_DONE_MASK (0x80U):DMA_CSR_DONE_SHIFT (7U):DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK):DMA_CSR_MAJORLINKCH_MASK (0x1F00U):DMA_CSR_MAJORLINKCH_SHIFT (8U):DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK):DMA_CSR_BWC_MASK (0xC000U):DMA_CSR_BWC_SHIFT (14U):DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK):DMA_CSR_COUNT (32U):DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU):DMA_BITER_ELINKNO_BITER_SHIFT (0U):DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK):DMA_BITER_ELINKNO_ELINK_MASK (0x8000U):DMA_BITER_ELINKNO_ELINK_SHIFT (15U):DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK):DMA_BITER_ELINKNO_COUNT (32U):DMA_BITER_ELINKYES_BITER_MASK (0x1FFU):DMA_BITER_ELINKYES_BITER_SHIFT (0U):DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK):DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U):DMA_BITER_ELINKYES_LINKCH_SHIFT (9U):DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK):DMA_BITER_ELINKYES_ELINK_MASK (0x8000U):DMA_BITER_ELINKYES_ELINK_SHIFT (15U):DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK):DMA_BITER_ELINKYES_COUNT (32U):DMA0_BASE (0x400E8000u):DMA0 ((DMA_Type *)DMA0_BASE):DMA_BASE_ADDRS { DMA0_BASE }:DMA_BASE_PTRS { DMA0 }:DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }:DMA_ERROR_IRQS { DMA_ERROR_IRQn }:DMAMUX_CHCFG_SOURCE_MASK (0x7FU):DMAMUX_CHCFG_SOURCE_SHIFT (0U):DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK):DMAMUX_CHCFG_A_ON_MASK (0x20000000U):DMAMUX_CHCFG_A_ON_SHIFT (29U):DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK):DMAMUX_CHCFG_TRIG_MASK (0x40000000U):DMAMUX_CHCFG_TRIG_SHIFT (30U):DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK):DMAMUX_CHCFG_ENBL_MASK (0x80000000U):DMAMUX_CHCFG_ENBL_SHIFT (31U):DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK):DMAMUX_CHCFG_COUNT (32U):DMAMUX_BASE (0x400EC000u):DMAMUX ((DMAMUX_Type *)DMAMUX_BASE):DMAMUX_BASE_ADDRS { DMAMUX_BASE }:DMAMUX_BASE_PTRS { DMAMUX };ENC_CTRL_CMPIE_MASK (0x1U);ENC_CTRL_CMPIE_SHIFT (0U);ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK);ENC_CTRL_CMPIRQ_MASK (0x2U);ENC_CTRL_CMPIRQ_SHIFT (1U);ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK);ENC_CTRL_WDE_MASK (0x4U);ENC_CTRL_WDE_SHIFT (2U);ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK);ENC_CTRL_DIE_MASK (0x8U);ENC_CTRL_DIE_SHIFT (3U);ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK);ENC_CTRL_DIRQ_MASK (0x10U);ENC_CTRL_DIRQ_SHIFT (4U);ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK);ENC_CTRL_XNE_MASK (0x20U);ENC_CTRL_XNE_SHIFT (5U);ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK);ENC_CTRL_XIP_MASK (0x40U);ENC_CTRL_XIP_SHIFT (6U);ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK);ENC_CTRL_XIE_MASK (0x80U);ENC_CTRL_XIE_SHIFT (7U);ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK);ENC_CTRL_XIRQ_MASK (0x100U);ENC_CTRL_XIRQ_SHIFT (8U);ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK);ENC_CTRL_PH1_MASK (0x200U);ENC_CTRL_PH1_SHIFT (9U);ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK);ENC_CTRL_REV_MASK (0x400U);ENC_CTRL_REV_SHIFT (10U);ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK);ENC_CTRL_SWIP_MASK (0x800U);ENC_CTRL_SWIP_SHIFT (11U);ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK);ENC_CTRL_HNE_MASK (0x1000U);ENC_CTRL_HNE_SHIFT (12U);ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK);ENC_CTRL_HIP_MASK (0x2000U);ENC_CTRL_HIP_SHIFT (13U);ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK);ENC_CTRL_HIE_MASK (0x4000U);ENC_CTRL_HIE_SHIFT (14U);ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK);ENC_CTRL_HIRQ_MASK (0x8000U);ENC_CTRL_HIRQ_SHIFT (15U);ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK);ENC_FILT_FILT_PER_MASK (0xFFU);ENC_FILT_FILT_PER_SHIFT (0U);ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK);ENC_FILT_FILT_CNT_MASK (0x700U);ENC_FILT_FILT_CNT_SHIFT (8U);ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK);ENC_WTR_WDOG_MASK (0xFFFFU);ENC_WTR_WDOG_SHIFT (0U);ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK);ENC_POSD_POSD_MASK (0xFFFFU);ENC_POSD_POSD_SHIFT (0U);ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK);ENC_POSDH_POSDH_MASK (0xFFFFU);ENC_POSDH_POSDH_SHIFT (0U)ENET_EIR_TS_TIMER_MASK (0x8000U)>ENET_EIR_TS_TIMER_SHIFT (15U)>ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)>ENET_EIR_TS_AVAIL_MASK (0x10000U)>ENET_EIR_TS_AVAIL_SHIFT (16U)>ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)>ENET_EIR_WAKEUP_MASK (0x20000U)>ENET_EIR_WAKEUP_SHIFT (17U)>ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)>ENET_EIR_PLR_MASK (0x40000U)>ENET_EIR_PLR_SHIFT (18U)>ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)>ENET_EIR_UN_MASK (0x80000U)>ENET_EIR_UN_SHIFT (19U)>ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)>ENET_EIR_RL_MASK (0x100000U)>ENET_EIR_RL_SHIFT (20U)>ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)>ENET_EIR_LC_MASK (0x200000U)>ENET_EIR_LC_SHIFT (21U)>ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)>ENET_EIR_EBERR_MASK (0x400000U)>ENET_EIR_EBERR_SHIFT (22U)>ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)>ENET_EIR_MII_MASK (0x800000U)>ENET_EIR_MII_SHIFT (23U)>ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)>ENET_EIR_RXB_MASK (0x1000000U)>ENET_EIR_RXB_SHIFT (24U)>ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)>ENET_EIR_RXF_MASK (0x2000000U)>ENET_EIR_RXF_SHIFT (25U)>ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)>ENET_EIR_TXB_MASK (0x4000000U)>ENET_EIR_TXB_SHIFT (26U)>ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)>ENET_EIR_TXF_MASK (0x8000000U)?ENET_EIR_TXF_SHIFT (27U)?ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)?ENET_EIR_GRA_MASK (0x10000000U)?ENET_EIR_GRA_SHIFT (28U)?ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)?ENET_EIR_BABT_MASK (0x20000000U)?ENET_EIR_BABT_SHIFT (29U)?ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)?ENET_EIR_BABR_MASK (0x40000000U)?ENET_EIR_BABR_SHIFT (30U)?ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)?ENET_EIMR_TS_TIMER_MASK (0x8000U)?ENET_EIMR_TS_TIMER_SHIFT (15U)?ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)?ENET_EIMR_TS_AVAIL_MASK (0x10000U)?ENET_EIMR_TS_AVAIL_SHIFT (16U)?ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)?ENET_EIMR_WAKEUP_MASK (0x20000U)?ENET_EIMR_WAKEUP_SHIFT (17U)?ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)?ENET_EIMR_PLR_MASK (0x40000U)?ENET_EIMR_PLR_SHIFT (18U)?ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)?ENET_EIMR_UN_MASK (0x80000U)?ENET_EIMR_UN_SHIFT (19U)?ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)?ENET_EIMR_RL_MASK (0x100000U)?ENET_EIMR_RL_SHIFT (20U)?ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)?ENET_EIMR_LC_MASK (0x200000U)?ENET_EIMR_LC_SHIFT (21U)?ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)?ENET_EIMR_EBERR_MASK (0x400000U)?ENET_EIMR_EBERR_SHIFT (22U)?ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)?ENET_EIMR_MII_MASK (0x800000U)?ENET_EIMR_MII_SHIFT (23U)?ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)?ENET_EIMR_RXB_MASK (0x1000000U)?ENET_EIMR_RXB_SHIFT (24U)?ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)?ENET_EIMR_RXF_MASK (0x2000000U)?ENET_EIMR_RXF_SHIFT (25U)?ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)?ENET_EIMR_TXB_MASK (0x4000000U)?ENET_EIMR_TXB_SHIFT (26U)?ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)?ENET_EIMR_TXF_MASK (0x8000000U)?ENET_EIMR_TXF_SHIFT (27U)?ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)?ENET_EIMR_GRA_MASK (0x10000000U)?ENET_EIMR_GRA_SHIFT (28U)?ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)?ENET_EIMR_BABT_MASK (0x20000000U)?ENET_EIMR_BABT_SHIFT (29U)?ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)?ENET_EIMR_BABR_MASK (0x40000000U)?ENET_EIMR_BABR_SHIFT (30U)?ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)?ENET_RDAR_RDAR_MASK (0x1000000U)?ENET_RDAR_RDAR_SHIFT (24U)?ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)?ENET_TDAR_TDAR_MASK (0x1000000U)?ENET_TDAR_TDAR_SHIFT (24U)?ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)?ENET_ECR_RESET_MASK (0x1U)?ENET_ECR_RESET_SHIFT (0U)?ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)?ENET_ECR_ETHEREN_MASK (0x2U)?ENET_ECR_ETHEREN_SHIFT (1U)?ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)?ENET_ECR_MAGICEN_MASK (0x4U)?ENET_ECR_MAGICEN_SHIFT (2U)?ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)?ENET_ECR_SLEEP_MASK (0x8U)?ENET_ECR_SLEEP_SHIFT (3U)?ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)?ENET_ECR_EN1588_MASK (0x10U)?ENET_ECR_EN1588_SHIFT (4U)?ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)?ENET_ECR_DBGEN_MASK (0x40U)?ENET_ECR_DBGEN_SHIFT (6U)?ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)?ENET_ECR_DBSWP_MASK (0x100U)?ENET_ECR_DBSWP_SHIFT (8U)?ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)?ENET_MMFR_DATA_MASK (0xFFFFU)?ENET_MMFR_DATA_SHIFT (0U)?ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)?ENET_MMFR_TA_MASK (0x30000U)?ENET_MMFR_TA_SHIFT (16U)?ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)?ENET_MMFR_RA_MASK (0x7C0000U)?ENET_MMFR_RA_SHIFT (18U)?ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)?ENET_MMFR_PA_MASK (0xF800000U)?ENET_MMFR_PA_SHIFT (23U)?ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)?ENET_MMFR_OP_MASK (0x30000000U)?ENET_MMFR_OP_SHIFT (28U)?ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)?ENET_MMFR_ST_MASK (0xC0000000U)?ENET_MMFR_ST_SHIFT (30U)?ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)@ENET_MSCR_MII_SPEED_MASK (0x7EU)@ENET_MSCR_MII_SPEED_SHIFT (1U)@ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)@ENET_MSCR_DIS_PRE_MASK (0x80U)@ENET_MSCR_DIS_PRE_SHIFT (7U)@ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)@ENET_MSCR_HOLDTIME_MASK (0x700U)@ENET_MSCR_HOLDTIME_SHIFT (8U)@ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)@ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)@ENET_MIBC_MIB_CLEAR_SHIFT (29U)@ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)@ENET_MIBC_MIB_IDLE_MASK (0x40000000U)@ENET_MIBC_MIB_IDLE_SHIFT (30U)@ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)@ENET_MIBC_MIB_DIS_MASK (0x80000000U)@ENET_MIBC_MIB_DIS_SHIFT (31U)@ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)@ENET_RCR_LOOP_MASK (0x1U)@ENET_RCR_LOOP_SHIFT (0U)@ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)@ENET_RCR_DRT_MASK (0x2U)@ENET_RCR_DRT_SHIFT (1U)@ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)@ENET_RCR_MII_MODE_MASK (0x4U)@ENET_RCR_MII_MODE_SHIFT (2U)@ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)@ENET_RCR_PROM_MASK (0x8U)@ENET_RCR_PROM_SHIFT (3U)@ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)@ENET_RCR_BC_REJ_MASK (0x10U)@ENET_RCR_BC_REJ_SHIFT (4U)@ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)@ENET_RCR_FCE_MASK (0x20U)@ENET_RCR_FCE_SHIFT (5U)@ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)@ENET_RCR_RMII_MODE_MASK (0x100U)@ENET_RCR_RMII_MODE_SHIFT (8U)@ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)@ENET_RCR_RMII_10T_MASK (0x200U)@ENET_RCR_RMII_10T_SHIFT (9U)@ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)@ENET_RCR_PADEN_MASK (0x1000U)@ENET_RCR_PADEN_SHIFT (12U)@ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)@ENET_RCR_PAUFWD_MASK (0x2000U)@ENET_RCR_PAUFWD_SHIFT (13U)@ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)@ENET_RCR_CRCFWD_MASK (0x4000U)@ENET_RCR_CRCFWD_SHIFT (14U)@ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)@ENET_RCR_CFEN_MASK (0x8000U)@ENET_RCR_CFEN_SHIFT (15U)@ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)@ENET_RCR_MAX_FL_MASK (0x3FFF0000U)@ENET_RCR_MAX_FL_SHIFT (16U)@ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)@ENET_RCR_NLC_MASK (0x40000000U)@ENET_RCR_NLC_SHIFT (30U)@ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)@ENET_RCR_GRS_MASK (0x80000000U)@ENET_RCR_GRS_SHIFT (31U)@ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)@ENET_TCR_GTS_MASK (0x1U)@ENET_TCR_GTS_SHIFT (0U)@ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)@ENET_TCR_FDEN_MASK (0x4U)@ENET_TCR_FDEN_SHIFT (2U)@ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)@ENET_TCR_TFC_PAUSE_MASK (0x8U)@ENET_TCR_TFC_PAUSE_SHIFT (3U)@ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)@ENET_TCR_RFC_PAUSE_MASK (0x10U)@ENET_TCR_RFC_PAUSE_SHIFT (4U)@ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)@ENET_TCR_ADDSEL_MASK (0xE0U)@ENET_TCR_ADDSEL_SHIFT (5U)@ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)@ENET_TCR_ADDINS_MASK (0x100U)@ENET_TCR_ADDINS_SHIFT (8U)@ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)@ENET_TCR_CRCFWD_MASK (0x200U)@ENET_TCR_CRCFWD_SHIFT (9U)@ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)@ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)@ENET_PALR_PADDR1_SHIFT (0U)@ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)@ENET_PAUR_TYPE_MASK (0xFFFFU)@ENET_PAUR_TYPE_SHIFT (0U)@ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)@ENET_PAUR_PADDR2_MASK (0xFFFF0000U)@ENET_PAUR_PADDR2_SHIFT (16U)@ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)@ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)@ENET_OPD_PAUSE_DUR_SHIFT (0U)@ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)@ENET_OPD_OPCODE_MASK (0xFFFF0000U)@ENET_OPD_OPCODE_SHIFT (16U)@ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)@ENET_TXIC_ICTT_MASK (0xFFFFU)AENET_TXIC_ICTT_SHIFT (0U)AENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)AENET_TXIC_ICFT_MASK (0xFF00000U)AENET_TXIC_ICFT_SHIFT (20U)AENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)AENET_TXIC_ICCS_MASK (0x40000000U)AENET_TXIC_ICCS_SHIFT (30U)AENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)AENET_TXIC_ICEN_MASK (0x80000000U)AENET_TXIC_ICEN_SHIFT (31U)AENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)AENET_RXIC_ICTT_MASK (0xFFFFU)AENET_RXIC_ICTT_SHIFT (0U)AENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)AENET_RXIC_ICFT_MASK (0xFF00000U)AENET_RXIC_ICFT_SHIFT (20U)AENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)AENET_RXIC_ICCS_MASK (0x40000000U)AENET_RXIC_ICCS_SHIFT (30U)AENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)AENET_RXIC_ICEN_MASK (0x80000000U)AENET_RXIC_ICEN_SHIFT (31U)AENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)AENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)AENET_IAUR_IADDR1_SHIFT (0U)AENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)AENET_IALR_IADDR2_MASK (0xFFFFFFFFU)AENET_IALR_IADDR2_SHIFT (0U)AENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)AENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)AENET_GAUR_GADDR1_SHIFT (0U)AENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)AENET_GALR_GADDR2_MASK (0xFFFFFFFFU)AENET_GALR_GADDR2_SHIFT (0U)AENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)AENET_TFWR_TFWR_MASK (0x3FU)AENET_TFWR_TFWR_SHIFT (0U)AENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)AENET_TFWR_STRFWD_MASK (0x100U)AENET_TFWR_STRFWD_SHIFT (8U)AENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)AENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)AENET_RDSR_R_DES_START_SHIFT (3U)AENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)AENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)AENET_TDSR_X_DES_START_SHIFT (3U)AENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)AENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)AENET_MRBR_R_BUF_SIZE_SHIFT (4U)AENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)AENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)AENET_RSFL_RX_SECTION_FULL_SHIFT (0U)AENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)AENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)AENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)AENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)AENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)AENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)AENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)AENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)AENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)AENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)AENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)AENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)AENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)AENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)AENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)AENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)BENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)BENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)BENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)BENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)BENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)BENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)BENET_TIPG_IPG_MASK (0x1FU)BENET_TIPG_IPG_SHIFT (0U)BENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)BENET_FTRL_TRUNC_FL_MASK (0x3FFFU)BENET_FTRL_TRUNC_FL_SHIFT (0U)BENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)BENET_TACC_SHIFT16_MASK (0x1U)BENET_TACC_SHIFT16_SHIFT (0U)BENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)BENET_TACC_IPCHK_MASK (0x8U)BENET_TACC_IPCHK_SHIFT (3U)BENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)BENET_TACC_PROCHK_MASK (0x10U)BENET_TACC_PROCHK_SHIFT (4U)BENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)BENET_RACC_PADREM_MASK (0x1U)BENET_RACC_PADREM_SHIFT (0U)BENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)BENET_RACC_IPDIS_MASK (0x2U)BENET_RACC_IPDIS_SHIFT (1U)BENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)BENET_RACC_PRODIS_MASK (0x4U)BENET_RACC_PRODIS_SHIFT (2U)BENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)BENET_RACC_LINEDIS_MASK (0x40U)BENET_RACC_LINEDIS_SHIFT (6U)BENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)BENET_RACC_SHIFT16_MASK (0x80U)BENET_RACC_SHIFT16_SHIFT (7U)BENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)BENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)BENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)BENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)BENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)BENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)BENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)BENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)BENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)BENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)BENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)BENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)BENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)BENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)BENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)BENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_JAB_TXPKTS_SHIFT (0U)BENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)BENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_COL_TXPKTS_SHIFT (0U)BENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)BENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)BENET_RMON_T_P64_TXPKTS_SHIFT (0U)BENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)CENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)CENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)CENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)CENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)CENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)CENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)CENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)CENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)CENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)CENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)CENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)CENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)CENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)CENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)CENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)CENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)CENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)CENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)CENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)CENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)CENET_IEEE_T_1COL_COUNT_SHIFT (0U)CENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)CENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)CENET_IEEE_T_MCOL_COUNT_SHIFT (0U)CENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)CENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)CENET_IEEE_T_DEF_COUNT_SHIFT (0U)CENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)CENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)CENET_IEEE_T_LCOL_COUNT_SHIFT (0U)CENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)CENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)CENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)CENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)CENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)CENET_IEEE_T_MACERR_COUNT_SHIFT (0U)CENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)CENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)CENET_IEEE_T_CSERR_COUNT_SHIFT (0U)CENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)CENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)CENET_IEEE_T_SQE_COUNT_SHIFT (0U)CENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)CENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)CENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)CENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)CENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)CENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)CENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)DENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)DENET_RMON_R_PACKETS_COUNT_SHIFT (0U)DENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)DENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)DENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)DENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)DENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)DENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)DENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)DENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)DENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)DENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)DENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)DENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)DENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)DENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)DENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)DENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)DENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)DENET_RMON_R_FRAG_COUNT_SHIFT (0U)DENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)DENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)DENET_RMON_R_JAB_COUNT_SHIFT (0U)DENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)DENET_RMON_R_P64_COUNT_MASK (0xFFFFU)DENET_RMON_R_P64_COUNT_SHIFT (0U)DENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)DENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)DENET_RMON_R_P65TO127_COUNT_SHIFT (0U)DENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)DENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)DENET_RMON_R_P128TO255_COUNT_SHIFT (0U)DENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)DENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)DENET_RMON_R_P256TO511_COUNT_SHIFT (0U)DENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)DENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)DENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)DENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)DENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)DENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)DENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)DENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)DENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)DENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)DENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)DENET_RMON_R_OCTETS_COUNT_SHIFT (0U)DENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)DENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)DENET_IEEE_R_DROP_COUNT_SHIFT (0U)DENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)DENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)DENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)DENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)DENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)DENET_IEEE_R_CRC_COUNT_SHIFT (0U)EENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)EENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)EENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)EENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)EENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)EENET_IEEE_R_MACERR_COUNT_SHIFT (0U)EENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)EENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)EENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)EENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)EENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)EENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)EENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)EENET_ATCR_EN_MASK (0x1U)EENET_ATCR_EN_SHIFT (0U)EENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)EENET_ATCR_OFFEN_MASK (0x4U)EENET_ATCR_OFFEN_SHIFT (2U)EENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)EENET_ATCR_OFFRST_MASK (0x8U)EENET_ATCR_OFFRST_SHIFT (3U)EENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)EENET_ATCR_PEREN_MASK (0x10U)EENET_ATCR_PEREN_SHIFT (4U)EENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)EENET_ATCR_PINPER_MASK (0x80U)EENET_ATCR_PINPER_SHIFT (7U)EENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)EENET_ATCR_RESTART_MASK (0x200U)EENET_ATCR_RESTART_SHIFT (9U)EENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)EENET_ATCR_CAPTURE_MASK (0x800U)EENET_ATCR_CAPTURE_SHIFT (11U)EENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)EENET_ATCR_SLAVE_MASK (0x2000U)EENET_ATCR_SLAVE_SHIFT (13U)EENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)EENET_ATVR_ATIME_MASK (0xFFFFFFFFU)EENET_ATVR_ATIME_SHIFT (0U)EENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)EENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)EENET_ATOFF_OFFSET_SHIFT (0U)EENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)EENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)EENET_ATPER_PERIOD_SHIFT (0U)EENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)EENET_ATCOR_COR_MASK (0x7FFFFFFFU)EENET_ATCOR_COR_SHIFT (0U)EENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)EENET_ATINC_INC_MASK (0x7FU)EENET_ATINC_INC_SHIFT (0U)EENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)EENET_ATINC_INC_CORR_MASK (0x7F00U)EENET_ATINC_INC_CORR_SHIFT (8U)EENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)EENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)EENET_ATSTMP_TIMESTAMP_SHIFT (0U)EENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)EENET_TGSR_TF0_MASK (0x1U)EENET_TGSR_TF0_SHIFT (0U)EENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)EENET_TGSR_TF1_MASK (0x2U)EENET_TGSR_TF1_SHIFT (1U)EENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)EENET_TGSR_TF2_MASK (0x4U)EENET_TGSR_TF2_SHIFT (2U)EENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)EENET_TGSR_TF3_MASK (0x8U)EENET_TGSR_TF3_SHIFT (3U)EENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)EENET_TCSR_TDRE_MASK (0x1U)EENET_TCSR_TDRE_SHIFT (0U)EENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)EENET_TCSR_TMODE_MASK (0x3CU)EENET_TCSR_TMODE_SHIFT (2U)EENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)FENET_TCSR_TIE_MASK (0x40U)FENET_TCSR_TIE_SHIFT (6U)FENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)FENET_TCSR_TF_MASK (0x80U)FENET_TCSR_TF_SHIFT (7U)FENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)FENET_TCSR_TPWC_MASK (0xF800U)FENET_TCSR_TPWC_SHIFT (11U)FENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)FENET_TCSR_COUNT (4U)FENET_TCCR_TCC_MASK (0xFFFFFFFFU)FENET_TCCR_TCC_SHIFT (0U)FENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)FENET_TCCR_COUNT (4U)FENET_BASE (0x402D8000u)FENET ((ENET_Type *)ENET_BASE)FENET_BASE_ADDRS { ENET_BASE }FENET_BASE_PTRS { ENET }FENET_Transmit_IRQS { ENET_IRQn }FENET_Receive_IRQS { ENET_IRQn }FENET_Error_IRQS { ENET_IRQn }FENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }FENET_BUFF_ALIGNMENT (64U)FEWM_CTRL_EWMEN_MASK (0x1U)FEWM_CTRL_EWMEN_SHIFT (0U)FEWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)FEWM_CTRL_ASSIN_MASK (0x2U)FEWM_CTRL_ASSIN_SHIFT (1U)FEWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)FEWM_CTRL_INEN_MASK (0x4U)FEWM_CTRL_INEN_SHIFT (2U)FEWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)FEWM_CTRL_INTEN_MASK (0x8U)FEWM_CTRL_INTEN_SHIFT (3U)FEWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)FEWM_SERV_SERVICE_MASK (0xFFU)FEWM_SERV_SERVICE_SHIFT (0U)FEWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)FEWM_CMPL_COMPAREL_MASK (0xFFU)FEWM_CMPL_COMPAREL_SHIFT (0U)FEWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)FEWM_CMPH_COMPAREH_MASK (0xFFU)FEWM_CMPH_COMPAREH_SHIFT (0U)FEWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)FEWM_CLKCTRL_CLKSEL_MASK (0x3U)FEWM_CLKCTRL_CLKSEL_SHIFT (0U)FEWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)FEWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)GEWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)GEWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)GEWM_BASE (0x400B4000u)GEWM ((EWM_Type *)EWM_BASE)GEWM_BASE_ADDRS { EWM_BASE }GEWM_BASE_PTRS { EWM }GEWM_IRQS { EWM_IRQn }GFLEXIO_VERID_FEATURE_MASK (0xFFFFU)GFLEXIO_VERID_FEATURE_SHIFT (0U)GFLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)GFLEXIO_VERID_MINOR_MASK (0xFF0000U)GFLEXIO_VERID_MINOR_SHIFT (16U)GFLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)GFLEXIO_VERID_MAJOR_MASK (0xFF000000U)GFLEXIO_VERID_MAJOR_SHIFT (24U)GFLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)GFLEXIO_PARAM_SHIFTER_MASK (0xFFU)GFLEXIO_PARAM_SHIFTER_SHIFT (0U)GFLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)GFLEXIO_PARAM_TIMER_MASK (0xFF00U)GFLEXIO_PARAM_TIMER_SHIFT (8U)GFLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)GFLEXIO_PARAM_PIN_MASK (0xFF0000U)GFLEXIO_PARAM_PIN_SHIFT (16U)GFLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)GFLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)GFLEXIO_PARAM_TRIGGER_SHIFT (24U)GFLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)GFLEXIO_CTRL_FLEXEN_MASK (0x1U)GFLEXIO_CTRL_FLEXEN_SHIFT (0U)GFLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)GFLEXIO_CTRL_SWRST_MASK (0x2U)GFLEXIO_CTRL_SWRST_SHIFT (1U)GFLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)GFLEXIO_CTRL_FASTACC_MASK (0x4U)GFLEXIO_CTRL_FASTACC_SHIFT (2U)GFLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)HFLEXIO_CTRL_DBGE_MASK (0x40000000U)HFLEXIO_CTRL_DBGE_SHIFT (30U)HFLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)HFLEXIO_CTRL_DOZEN_MASK (0x80000000U)HFLEXIO_CTRL_DOZEN_SHIFT (31U)HFLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)HFLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)HFLEXIO_PIN_PDI_SHIFT (0U)HFLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)HFLEXIO_SHIFTSTAT_SSF_MASK (0xFU)HFLEXIO_SHIFTSTAT_SSF_SHIFT (0U)HFLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)HFLEXIO_SHIFTERR_SEF_MASK (0xFU)HFLEXIO_SHIFTERR_SEF_SHIFT (0U)HFLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)HFLEXIO_TIMSTAT_TSF_MASK (0xFU)HFLEXIO_TIMSTAT_TSF_SHIFT (0U)HFLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)HFLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)HFLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)HFLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)HFLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)HFLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)HFLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)HFLEXIO_TIMIEN_TEIE_MASK (0xFU)HFLEXIO_TIMIEN_TEIE_SHIFT (0U)HFLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)HFLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)HFLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)HFLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)HFLEXIO_SHIFTSTATE_STATE_MASK (0x7U)HFLEXIO_SHIFTSTATE_STATE_SHIFT (0U)HFLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)HFLEXIO_SHIFTCTL_SMOD_MASK (0x7U)HFLEXIO_SHIFTCTL_SMOD_SHIFT (0U)HFLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)HFLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)HFLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)HFLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)HFLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)HFLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)HFLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)HFLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)HFLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)HFLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)HFLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)HFLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)HFLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)HFLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)HFLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)HFLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)HFLEXIO_SHIFTCTL_COUNT (4U)HFLEXIO_SHIFTCFG_SSTART_MASK (0x3U)HFLEXIO_SHIFTCFG_SSTART_SHIFT (0U)HFLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)HFLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)HFLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)HFLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)HFLEXIO_SHIFTCFG_INSRC_MASK (0x100U)HFLEXIO_SHIFTCFG_INSRC_SHIFT (8U)HFLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)HFLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)HFLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)HFLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)HFLEXIO_SHIFTCFG_COUNT (4U)HFLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)HFLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)HFLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)HFLEXIO_SHIFTBUF_COUNT (4U)HFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)IFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)IFLEXIO_SHIFTBUFBIS_COUNT (4U)IFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)IFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)IFLEXIO_SHIFTBUFBYS_COUNT (4U)IFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)IFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)IFLEXIO_SHIFTBUFBBS_COUNT (4U)IFLEXIO_TIMCTL_TIMOD_MASK (0x3U)IFLEXIO_TIMCTL_TIMOD_SHIFT (0U)IFLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)IFLEXIO_TIMCTL_PINPOL_MASK (0x80U)IFLEXIO_TIMCTL_PINPOL_SHIFT (7U)IFLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)IFLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)IFLEXIO_TIMCTL_PINSEL_SHIFT (8U)IFLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)IFLEXIO_TIMCTL_PINCFG_MASK (0x30000U)IFLEXIO_TIMCTL_PINCFG_SHIFT (16U)IFLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)IFLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)IFLEXIO_TIMCTL_TRGSRC_SHIFT (22U)IFLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)IFLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)IFLEXIO_TIMCTL_TRGPOL_SHIFT (23U)IFLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)IFLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)IFLEXIO_TIMCTL_TRGSEL_SHIFT (24U)IFLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)IFLEXIO_TIMCTL_COUNT (4U)IFLEXIO_TIMCFG_TSTART_MASK (0x2U)IFLEXIO_TIMCFG_TSTART_SHIFT (1U)IFLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)IFLEXIO_TIMCFG_TSTOP_MASK (0x30U)IFLEXIO_TIMCFG_TSTOP_SHIFT (4U)IFLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)IFLEXIO_TIMCFG_TIMENA_MASK (0x700U)IFLEXIO_TIMCFG_TIMENA_SHIFT (8U)IFLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)IFLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)IFLEXIO_TIMCFG_TIMDIS_SHIFT (12U)IFLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)IFLEXIO_TIMCFG_TIMRST_MASK (0x70000U)IFLEXIO_TIMCFG_TIMRST_SHIFT (16U)IFLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)IFLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)IFLEXIO_TIMCFG_TIMDEC_SHIFT (20U)IFLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)IFLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)IFLEXIO_TIMCFG_TIMOUT_SHIFT (24U)IFLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)IFLEXIO_TIMCFG_COUNT (4U)IFLEXIO_TIMCMP_CMP_MASK (0xFFFFU)IFLEXIO_TIMCMP_CMP_SHIFT (0U)IFLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)IFLEXIO_TIMCMP_COUNT (4U)IFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)IFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)IFLEXIO_SHIFTBUFNBS_COUNT (4U)IFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)IFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)IFLEXIO_SHIFTBUFHWS_COUNT (4U)IFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)IFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)IFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)IFLEXIO_SHIFTBUFNIS_COUNT (4U)JFLEXIO1_BASE (0x401AC000u)JFLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)JFLEXIO2_BASE (0x401B0000u)JFLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)JFLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }JFLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }JFLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, NotAvail_IRQn }JFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)JFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)JFLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)JFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)JFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)JFLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)JFLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)JFLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)JFLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)JFLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U)JFLEXRAM_TCM_CTRL_Reserved_SHIFT (3U)JFLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)JFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)JFLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)JFLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U)JFLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)JFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)JFLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)JFLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U)JFLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)JFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)JFLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)JFLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U)JFLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)JFLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U)JFLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)JFLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)JFLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U)JFLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)JFLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)JFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)JFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)JFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)JFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)JFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)JFLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)JFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)JFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)JFLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)JFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)JFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)JFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)JFLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U)JFLEXRAM_INT_STATUS_Reserved_SHIFT (6U)KFLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)KFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)KFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)KFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)KFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)KFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)KFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)KFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)KFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)KFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)KFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)KFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)KFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)KFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)KFLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U)KFLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U)KFLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)KFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U)KFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)KFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U)KFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)KFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)KFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)KFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)KFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)KFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)KFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)KFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)KFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)KFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)KFLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U)KFLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U)KFLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)KFLEXRAM_BASE (0x400B0000u)KFLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)KFLEXRAM_BASE_ADDRS { FLEXRAM_BASE }KFLEXRAM_BASE_PTRS { FLEXRAM }KFLEXRAM_IRQS { FLEXRAM_IRQn }LFLEXSPI_MCR0_SWRESET_MASK (0x1U)LFLEXSPI_MCR0_SWRESET_SHIFT (0U)LFLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)LFLEXSPI_MCR0_MDIS_MASK (0x2U)LFLEXSPI_MCR0_MDIS_SHIFT (1U)LFLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)LFLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)LFLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)LFLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)LFLEXSPI_MCR0_ARDFEN_MASK (0x40U)LFLEXSPI_MCR0_ARDFEN_SHIFT (6U)LFLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)LFLEXSPI_MCR0_ATDFEN_MASK (0x80U)LFLEXSPI_MCR0_ATDFEN_SHIFT (7U)LFLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)LFLEXSPI_MCR0_HSEN_MASK (0x800U)LFLEXSPI_MCR0_HSEN_SHIFT (11U)LFLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)LFLEXSPI_MCR0_DOZEEN_MASK (0x1000U)LFLEXSPI_MCR0_DOZEEN_SHIFT (12U)LFLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)LFLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)LFLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)LFLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)LFLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)LFLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)LFLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)LFLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)LFLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)LFLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)LFLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)LFLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)LFLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)LFLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)LFLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)LFLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)LFLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)LFLEXSPI_MCR1_SEQWAIT_SHIFT (16U)LFLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)LFLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)LFLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)LFLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)LFLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)LFLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)LFLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)LFLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)LFLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)LFLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)LFLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)LFLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)LFLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)LFLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)LFLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)LFLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)LFLEXSPI_AHBCR_APAREN_MASK (0x1U)LFLEXSPI_AHBCR_APAREN_SHIFT (0U)LFLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)LFLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)LFLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)LFLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)LFLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)LFLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)LFLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)LFLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)LFLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)LFLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)LFLEXSPI_AHBCR_READADDROPT_MASK (0x40U)LFLEXSPI_AHBCR_READADDROPT_SHIFT (6U)LFLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)LFLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)LFLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)LFLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)LFLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)LFLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)LFLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)LFLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)LFLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)LFLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)LFLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)LFLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)LFLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)LFLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)LFLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)LFLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)LFLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)LFLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)LFLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)LFLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)LFLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)LFLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)LFLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)LFLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)LFLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)LFLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)LFLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)LFLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)LFLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)LFLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)LFLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)LFLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)LFLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)LFLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)MFLEXSPI_INTR_IPCMDDONE_MASK (0x1U)MFLEXSPI_INTR_IPCMDDONE_SHIFT (0U)MFLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)MFLEXSPI_INTR_IPCMDGE_MASK (0x2U)MFLEXSPI_INTR_IPCMDGE_SHIFT (1U)MFLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)MFLEXSPI_INTR_AHBCMDGE_MASK (0x4U)MFLEXSPI_INTR_AHBCMDGE_SHIFT (2U)MFLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)MFLEXSPI_INTR_IPCMDERR_MASK (0x8U)MFLEXSPI_INTR_IPCMDERR_SHIFT (3U)MFLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)MFLEXSPI_INTR_AHBCMDERR_MASK (0x10U)MFLEXSPI_INTR_AHBCMDERR_SHIFT (4U)MFLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)MFLEXSPI_INTR_IPRXWA_MASK (0x20U)MFLEXSPI_INTR_IPRXWA_SHIFT (5U)MFLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)MFLEXSPI_INTR_IPTXWE_MASK (0x40U)MFLEXSPI_INTR_IPTXWE_SHIFT (6U)MFLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)MFLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)MFLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)MFLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)MFLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)MFLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)MFLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)MFLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)MFLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)MFLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)MFLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)MFLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)MFLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)MFLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)MFLEXSPI_LUTKEY_KEY_SHIFT (0U)MFLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)MFLEXSPI_LUTCR_LOCK_MASK (0x1U)MFLEXSPI_LUTCR_LOCK_SHIFT (0U)MFLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)MFLEXSPI_LUTCR_UNLOCK_MASK (0x2U)MFLEXSPI_LUTCR_UNLOCK_SHIFT (1U)MFLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)MFLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)MFLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)MFLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)MFLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)MFLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)MFLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)MFLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)MFLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)MFLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)MFLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)MFLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)MFLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)MFLEXSPI_AHBRXBUFCR0_COUNT (4U)MFLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)MFLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)MFLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)MFLEXSPI_FLSHCR0_COUNT (4U)MFLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)MFLEXSPI_FLSHCR1_TCSS_SHIFT (0U)MFLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)MFLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)MFLEXSPI_FLSHCR1_TCSH_SHIFT (5U)MFLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)MFLEXSPI_FLSHCR1_WA_MASK (0x400U)MFLEXSPI_FLSHCR1_WA_SHIFT (10U)MFLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)MFLEXSPI_FLSHCR1_CAS_MASK (0x7800U)MFLEXSPI_FLSHCR1_CAS_SHIFT (11U)MFLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)MFLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)MFLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)MFLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)MFLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)MFLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)MFLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)MFLEXSPI_FLSHCR1_COUNT (4U)MFLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)MFLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)MFLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)MFLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)MFLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)MFLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)MFLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)MFLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)MFLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)MFLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)MFLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)MFLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)MFLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)MFLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)MFLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)MFLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)MFLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)MFLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)MFLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)NFLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)NFLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)NFLEXSPI_FLSHCR2_COUNT (4U)NFLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)NFLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)NFLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)NFLEXSPI_FLSHCR4_WMENA_MASK (0x4U)NFLEXSPI_FLSHCR4_WMENA_SHIFT (2U)NFLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)NFLEXSPI_FLSHCR4_WMENB_MASK (0x8U)NFLEXSPI_FLSHCR4_WMENB_SHIFT (3U)NFLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)NFLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)NFLEXSPI_IPCR0_SFAR_SHIFT (0U)NFLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)NFLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)NFLEXSPI_IPCR1_IDATSZ_SHIFT (0U)NFLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)NFLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)NFLEXSPI_IPCR1_ISEQID_SHIFT (16U)NFLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)NFLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)NFLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)NFLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)NFLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)NFLEXSPI_IPCR1_IPAREN_SHIFT (31U)NFLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)NFLEXSPI_IPCMD_TRG_MASK (0x1U)NFLEXSPI_IPCMD_TRG_SHIFT (0U)NFLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)NFLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)NFLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)NFLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)NFLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)NFLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)NFLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)NFLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)NFLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)NFLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)NFLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)NFLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)NFLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)NFLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)NFLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)NFLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)NFLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)NFLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)NFLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)NFLEXSPI_DLLCR_DLLEN_MASK (0x1U)NFLEXSPI_DLLCR_DLLEN_SHIFT (0U)NFLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)NFLEXSPI_DLLCR_DLLRESET_MASK (0x2U)NFLEXSPI_DLLCR_DLLRESET_SHIFT (1U)NFLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)NFLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)NFLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)NFLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)NFLEXSPI_DLLCR_OVRDEN_MASK (0x100U)NFLEXSPI_DLLCR_OVRDEN_SHIFT (8U)NFLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)NFLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)NFLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)NFLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)NFLEXSPI_DLLCR_COUNT (2U)NFLEXSPI_STS0_SEQIDLE_MASK (0x1U)NFLEXSPI_STS0_SEQIDLE_SHIFT (0U)NFLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)NFLEXSPI_STS0_ARBIDLE_MASK (0x2U)NFLEXSPI_STS0_ARBIDLE_SHIFT (1U)NFLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)NFLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)NFLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)NFLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)NFLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)NFLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)NFLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)NFLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)NFLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)NFLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)NFLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)NFLEXSPI_STS1_IPCMDERRID_SHIFT (16U)NFLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)NFLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)NFLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)NFLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)OFLEXSPI_STS2_ASLVLOCK_MASK (0x1U)OFLEXSPI_STS2_ASLVLOCK_SHIFT (0U)OFLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)OFLEXSPI_STS2_AREFLOCK_MASK (0x2U)OFLEXSPI_STS2_AREFLOCK_SHIFT (1U)OFLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)OFLEXSPI_STS2_ASLVSEL_MASK (0xFCU)OFLEXSPI_STS2_ASLVSEL_SHIFT (2U)OFLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)OFLEXSPI_STS2_AREFSEL_MASK (0x3F00U)OFLEXSPI_STS2_AREFSEL_SHIFT (8U)OFLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)OFLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)OFLEXSPI_STS2_BSLVLOCK_SHIFT (16U)OFLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)OFLEXSPI_STS2_BREFLOCK_MASK (0x20000U)OFLEXSPI_STS2_BREFLOCK_SHIFT (17U)OFLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)OFLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)OFLEXSPI_STS2_BSLVSEL_SHIFT (18U)OFLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)OFLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)OFLEXSPI_STS2_BREFSEL_SHIFT (24U)OFLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)OFLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)OFLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)OFLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)OFLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)OFLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)OFLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)OFLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)OFLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)OFLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)OFLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)OFLEXSPI_IPRXFSTS_FILL_SHIFT (0U)OFLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)OFLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)OFLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)OFLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)OFLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)OFLEXSPI_IPTXFSTS_FILL_SHIFT (0U)OFLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)OFLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)OFLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)OFLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)OFLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)OFLEXSPI_RFDR_RXDATA_SHIFT (0U)OFLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)OFLEXSPI_RFDR_COUNT (32U)OFLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)OFLEXSPI_TFDR_TXDATA_SHIFT (0U)OFLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)OFLEXSPI_TFDR_COUNT (32U)OFLEXSPI_LUT_OPERAND0_MASK (0xFFU)OFLEXSPI_LUT_OPERAND0_SHIFT (0U)OFLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)OFLEXSPI_LUT_NUM_PADS0_MASK (0x300U)OFLEXSPI_LUT_NUM_PADS0_SHIFT (8U)OFLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)OFLEXSPI_LUT_OPCODE0_MASK (0xFC00U)OFLEXSPI_LUT_OPCODE0_SHIFT (10U)OFLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)OFLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)OFLEXSPI_LUT_OPERAND1_SHIFT (16U)OFLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)OFLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)OFLEXSPI_LUT_NUM_PADS1_SHIFT (24U)OFLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)OFLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)OFLEXSPI_LUT_OPCODE1_SHIFT (26U)OFLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)OFLEXSPI_LUT_COUNT (64U)OFLEXSPI_BASE (0x402A8000u)OFLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)OFLEXSPI_BASE_ADDRS { FLEXSPI_BASE }OFLEXSPI_BASE_PTRS { FLEXSPI }OFLEXSPI_IRQS { FLEXSPI_IRQn }OFlexSPI_AMBA_BASE (0x60000000U)OFlexSPI_ASFM_BASE (0x00000000U)OFlexSPI_ARDF_BASE (0x7FC00000U)PFlexSPI_ATDF_BASE (0x7F800000U)PGPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)PGPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)PGPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)PGPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)PGPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)PGPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)PGPC_CNTR_PDRAM0_PGE_MASK (0x400000U)PGPC_CNTR_PDRAM0_PGE_SHIFT (22U)PGPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)PGPC_IMR_IMR1_MASK (0xFFFFFFFFU)PGPC_IMR_IMR1_SHIFT (0U)PGPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)PGPC_IMR_IMR2_MASK (0xFFFFFFFFU)PGPC_IMR_IMR2_SHIFT (0U)PGPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)PGPC_IMR_IMR3_MASK (0xFFFFFFFFU)PGPC_IMR_IMR3_SHIFT (0U)PGPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)PGPC_IMR_IMR4_MASK (0xFFFFFFFFU)PGPC_IMR_IMR4_SHIFT (0U)PGPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)PGPC_IMR_COUNT (4U)PGPC_ISR_ISR1_MASK (0xFFFFFFFFU)PGPC_ISR_ISR1_SHIFT (0U)PGPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)PGPC_ISR_ISR2_MASK (0xFFFFFFFFU)PGPC_ISR_ISR2_SHIFT (0U)PGPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)PGPC_ISR_ISR3_MASK (0xFFFFFFFFU)PGPC_ISR_ISR3_SHIFT (0U)PGPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)PGPC_ISR_ISR4_MASK (0xFFFFFFFFU)PGPC_ISR_ISR4_SHIFT (0U)PGPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)PGPC_ISR_COUNT (4U)PGPC_IMR5_IMR5_MASK (0xFFFFFFFFU)PGPC_IMR5_IMR5_SHIFT (0U)PGPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)PGPC_ISR5_ISR4_MASK (0xFFFFFFFFU)PGPC_ISR5_ISR4_SHIFT (0U)PGPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)PGPC_BASE (0x400F4000u)PGPC ((GPC_Type *)GPC_BASE)PGPC_BASE_ADDRS { GPC_BASE }PGPC_BASE_PTRS { GPC }PGPC_IRQS { GPC_IRQn }QGPIO_DR_DR_MASK (0xFFFFFFFFU)QGPIO_DR_DR_SHIFT (0U)QGPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)QGPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)QGPIO_GDIR_GDIR_SHIFT (0U)QGPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)QGPIO_PSR_PSR_MASK (0xFFFFFFFFU)QGPIO_PSR_PSR_SHIFT (0U)QGPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)QGPIO_ICR1_ICR0_MASK (0x3U)QGPIO_ICR1_ICR0_SHIFT (0U)QGPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)QGPIO_ICR1_ICR1_MASK (0xCU)QGPIO_ICR1_ICR1_SHIFT (2U)QGPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)QGPIO_ICR1_ICR2_MASK (0x30U)QGPIO_ICR1_ICR2_SHIFT (4U)QGPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)QGPIO_ICR1_ICR3_MASK (0xC0U)QGPIO_ICR1_ICR3_SHIFT (6U)QGPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)QGPIO_ICR1_ICR4_MASK (0x300U)QGPIO_ICR1_ICR4_SHIFT (8U)QGPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)QGPIO_ICR1_ICR5_MASK (0xC00U)QGPIO_ICR1_ICR5_SHIFT (10U)QGPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)QGPIO_ICR1_ICR6_MASK (0x3000U)QGPIO_ICR1_ICR6_SHIFT (12U)QGPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)QGPIO_ICR1_ICR7_MASK (0xC000U)QGPIO_ICR1_ICR7_SHIFT (14U)QGPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)QGPIO_ICR1_ICR8_MASK (0x30000U)QGPIO_ICR1_ICR8_SHIFT (16U)QGPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)QGPIO_ICR1_ICR9_MASK (0xC0000U)QGPIO_ICR1_ICR9_SHIFT (18U)QGPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)QGPIO_ICR1_ICR10_MASK (0x300000U)QGPIO_ICR1_ICR10_SHIFT (20U)QGPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)QGPIO_ICR1_ICR11_MASK (0xC00000U)QGPIO_ICR1_ICR11_SHIFT (22U)QGPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)QGPIO_ICR1_ICR12_MASK (0x3000000U)QGPIO_ICR1_ICR12_SHIFT (24U)QGPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)QGPIO_ICR1_ICR13_MASK (0xC000000U)QGPIO_ICR1_ICR13_SHIFT (26U)QGPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)QGPIO_ICR1_ICR14_MASK (0x30000000U)QGPIO_ICR1_ICR14_SHIFT (28U)QGPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)QGPIO_ICR1_ICR15_MASK (0xC0000000U)QGPIO_ICR1_ICR15_SHIFT (30U)QGPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)QGPIO_ICR2_ICR16_MASK (0x3U)QGPIO_ICR2_ICR16_SHIFT (0U)QGPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)QGPIO_ICR2_ICR17_MASK (0xCU)QGPIO_ICR2_ICR17_SHIFT (2U)QGPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)QGPIO_ICR2_ICR18_MASK (0x30U)QGPIO_ICR2_ICR18_SHIFT (4U)QGPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)QGPIO_ICR2_ICR19_MASK (0xC0U)QGPIO_ICR2_ICR19_SHIFT (6U)QGPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)QGPIO_ICR2_ICR20_MASK (0x300U)QGPIO_ICR2_ICR20_SHIFT (8U)QGPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)QGPIO_ICR2_ICR21_MASK (0xC00U)QGPIO_ICR2_ICR21_SHIFT (10U)QGPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)QGPIO_ICR2_ICR22_MASK (0x3000U)QGPIO_ICR2_ICR22_SHIFT (12U)QGPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)RGPIO_ICR2_ICR23_MASK (0xC000U)RGPIO_ICR2_ICR23_SHIFT (14U)RGPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)RGPIO_ICR2_ICR24_MASK (0x30000U)RGPIO_ICR2_ICR24_SHIFT (16U)RGPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)RGPIO_ICR2_ICR25_MASK (0xC0000U)RGPIO_ICR2_ICR25_SHIFT (18U)RGPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)RGPIO_ICR2_ICR26_MASK (0x300000U)RGPIO_ICR2_ICR26_SHIFT (20U)RGPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)RGPIO_ICR2_ICR27_MASK (0xC00000U)RGPIO_ICR2_ICR27_SHIFT (22U)RGPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)RGPIO_ICR2_ICR28_MASK (0x3000000U)RGPIO_ICR2_ICR28_SHIFT (24U)RGPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)RGPIO_ICR2_ICR29_MASK (0xC000000U)RGPIO_ICR2_ICR29_SHIFT (26U)RGPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)RGPIO_ICR2_ICR30_MASK (0x30000000U)RGPIO_ICR2_ICR30_SHIFT (28U)RGPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)RGPIO_ICR2_ICR31_MASK (0xC0000000U)RGPIO_ICR2_ICR31_SHIFT (30U)RGPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)RGPIO_IMR_IMR_MASK (0xFFFFFFFFU)RGPIO_IMR_IMR_SHIFT (0U)RGPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)RGPIO_ISR_ISR_MASK (0xFFFFFFFFU)RGPIO_ISR_ISR_SHIFT (0U)RGPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)RGPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)RGPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)RGPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)RGPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)RGPIO_DR_SET_DR_SET_SHIFT (0U)RGPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)RGPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)RGPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)RGPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)RGPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)RGPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)RGPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)RGPIO1_BASE (0x401B8000u)RGPIO1 ((GPIO_Type *)GPIO1_BASE)RGPIO2_BASE (0x401BC000u)RGPIO2 ((GPIO_Type *)GPIO2_BASE)RGPIO3_BASE (0x401C0000u)RGPIO3 ((GPIO_Type *)GPIO3_BASE)RGPIO5_BASE (0x400C0000u)RGPIO5 ((GPIO_Type *)GPIO5_BASE)RGPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, 0u, GPIO5_BASE }RGPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, (GPIO_Type *)0u, GPIO5 }RGPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }RGPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, NotAvail_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn }SGPT_CR_EN_MASK (0x1U)SGPT_CR_EN_SHIFT (0U)SGPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)SGPT_CR_ENMOD_MASK (0x2U)SGPT_CR_ENMOD_SHIFT (1U)SGPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)SGPT_CR_DBGEN_MASK (0x4U)SGPT_CR_DBGEN_SHIFT (2U)SGPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)SGPT_CR_WAITEN_MASK (0x8U)SGPT_CR_WAITEN_SHIFT (3U)SGPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)SGPT_CR_DOZEEN_MASK (0x10U)SGPT_CR_DOZEEN_SHIFT (4U)SGPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)SGPT_CR_STOPEN_MASK (0x20U)SGPT_CR_STOPEN_SHIFT (5U)SGPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)SGPT_CR_CLKSRC_MASK (0x1C0U)SGPT_CR_CLKSRC_SHIFT (6U)SGPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)SGPT_CR_FRR_MASK (0x200U)SGPT_CR_FRR_SHIFT (9U)SGPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)SGPT_CR_EN_24M_MASK (0x400U)SGPT_CR_EN_24M_SHIFT (10U)SGPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)SGPT_CR_SWR_MASK (0x8000U)SGPT_CR_SWR_SHIFT (15U)SGPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)SGPT_CR_IM1_MASK (0x30000U)SGPT_CR_IM1_SHIFT (16U)SGPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)SGPT_CR_IM2_MASK (0xC0000U)SGPT_CR_IM2_SHIFT (18U)SGPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)SGPT_CR_OM1_MASK (0x700000U)SGPT_CR_OM1_SHIFT (20U)SGPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)SGPT_CR_OM2_MASK (0x3800000U)SGPT_CR_OM2_SHIFT (23U)SGPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)SGPT_CR_OM3_MASK (0x1C000000U)SGPT_CR_OM3_SHIFT (26U)SGPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)SGPT_CR_FO1_MASK (0x20000000U)SGPT_CR_FO1_SHIFT (29U)SGPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)SGPT_CR_FO2_MASK (0x40000000U)SGPT_CR_FO2_SHIFT (30U)SGPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)SGPT_CR_FO3_MASK (0x80000000U)SGPT_CR_FO3_SHIFT (31U)SGPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)SGPT_PR_PRESCALER_MASK (0xFFFU)SGPT_PR_PRESCALER_SHIFT (0U)SGPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)SGPT_PR_PRESCALER24M_MASK (0xF000U)SGPT_PR_PRESCALER24M_SHIFT (12U)SGPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)SGPT_SR_OF1_MASK (0x1U)SGPT_SR_OF1_SHIFT (0U)SGPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)SGPT_SR_OF2_MASK (0x2U)SGPT_SR_OF2_SHIFT (1U)SGPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)SGPT_SR_OF3_MASK (0x4U)SGPT_SR_OF3_SHIFT (2U)SGPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)SGPT_SR_IF1_MASK (0x8U)SGPT_SR_IF1_SHIFT (3U)SGPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)SGPT_SR_IF2_MASK (0x10U)SGPT_SR_IF2_SHIFT (4U)SGPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)SGPT_SR_ROV_MASK (0x20U)SGPT_SR_ROV_SHIFT (5U)SGPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)SGPT_IR_OF1IE_MASK (0x1U)SGPT_IR_OF1IE_SHIFT (0U)SGPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)SGPT_IR_OF2IE_MASK (0x2U)SGPT_IR_OF2IE_SHIFT (1U)SGPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)SGPT_IR_OF3IE_MASK (0x4U)SGPT_IR_OF3IE_SHIFT (2U)SGPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)SGPT_IR_IF1IE_MASK (0x8U)SGPT_IR_IF1IE_SHIFT (3U)SGPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)SGPT_IR_IF2IE_MASK (0x10U)SGPT_IR_IF2IE_SHIFT (4U)SGPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)SGPT_IR_ROVIE_MASK (0x20U)SGPT_IR_ROVIE_SHIFT (5U)SGPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)SGPT_OCR_COMP_MASK (0xFFFFFFFFU)SGPT_OCR_COMP_SHIFT (0U)SGPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)TGPT_OCR_COUNT (3U)TGPT_ICR_CAPT_MASK (0xFFFFFFFFU)TGPT_ICR_CAPT_SHIFT (0U)TGPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)TGPT_ICR_COUNT (2U)TGPT_CNT_COUNT_MASK (0xFFFFFFFFU)TGPT_CNT_COUNT_SHIFT (0U)TGPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)TGPT1_BASE (0x401EC000u)TGPT1 ((GPT_Type *)GPT1_BASE)TGPT2_BASE (0x401F0000u)TGPT2 ((GPT_Type *)GPT2_BASE)TGPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }TGPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }TGPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }TI2S_VERID_FEATURE_MASK (0xFFFFU)TI2S_VERID_FEATURE_SHIFT (0U)TI2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)TI2S_VERID_MINOR_MASK (0xFF0000U)TI2S_VERID_MINOR_SHIFT (16U)TI2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)TI2S_VERID_MAJOR_MASK (0xFF000000U)TI2S_VERID_MAJOR_SHIFT (24U)TI2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)TI2S_PARAM_DATALINE_MASK (0xFU)TI2S_PARAM_DATALINE_SHIFT (0U)TI2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)TI2S_PARAM_FIFO_MASK (0xF00U)TI2S_PARAM_FIFO_SHIFT (8U)TI2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)TI2S_PARAM_FRAME_MASK (0xF0000U)TI2S_PARAM_FRAME_SHIFT (16U)TI2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)TI2S_TCSR_FRDE_MASK (0x1U)TI2S_TCSR_FRDE_SHIFT (0U)TI2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)TI2S_TCSR_FWDE_MASK (0x2U)TI2S_TCSR_FWDE_SHIFT (1U)TI2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)TI2S_TCSR_FRIE_MASK (0x100U)UI2S_TCSR_FRIE_SHIFT (8U)UI2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)UI2S_TCSR_FWIE_MASK (0x200U)UI2S_TCSR_FWIE_SHIFT (9U)UI2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)UI2S_TCSR_FEIE_MASK (0x400U)UI2S_TCSR_FEIE_SHIFT (10U)UI2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)UI2S_TCSR_SEIE_MASK (0x800U)UI2S_TCSR_SEIE_SHIFT (11U)UI2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)UI2S_TCSR_WSIE_MASK (0x1000U)UI2S_TCSR_WSIE_SHIFT (12U)UI2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)UI2S_TCSR_FRF_MASK (0x10000U)UI2S_TCSR_FRF_SHIFT (16U)UI2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)UI2S_TCSR_FWF_MASK (0x20000U)UI2S_TCSR_FWF_SHIFT (17U)UI2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)UI2S_TCSR_FEF_MASK (0x40000U)UI2S_TCSR_FEF_SHIFT (18U)UI2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)UI2S_TCSR_SEF_MASK (0x80000U)UI2S_TCSR_SEF_SHIFT (19U)UI2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)UI2S_TCSR_WSF_MASK (0x100000U)UI2S_TCSR_WSF_SHIFT (20U)UI2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)UI2S_TCSR_SR_MASK (0x1000000U)UI2S_TCSR_SR_SHIFT (24U)UI2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)UI2S_TCSR_FR_MASK (0x2000000U)UI2S_TCSR_FR_SHIFT (25U)UI2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)UI2S_TCSR_BCE_MASK (0x10000000U)UI2S_TCSR_BCE_SHIFT (28U)UI2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)UI2S_TCSR_DBGE_MASK (0x20000000U)UI2S_TCSR_DBGE_SHIFT (29U)UI2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)UI2S_TCSR_STOPE_MASK (0x40000000U)UI2S_TCSR_STOPE_SHIFT (30U)UI2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)UI2S_TCSR_TE_MASK (0x80000000U)UI2S_TCSR_TE_SHIFT (31U)UI2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)UI2S_TCR1_TFW_MASK (0x1FU)UI2S_TCR1_TFW_SHIFT (0U)UI2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)UI2S_TCR2_DIV_MASK (0xFFU)UI2S_TCR2_DIV_SHIFT (0U)UI2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)UI2S_TCR2_BCD_MASK (0x1000000U)UI2S_TCR2_BCD_SHIFT (24U)UI2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)UI2S_TCR2_BCP_MASK (0x2000000U)UI2S_TCR2_BCP_SHIFT (25U)UI2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)UI2S_TCR2_MSEL_MASK (0xC000000U)UI2S_TCR2_MSEL_SHIFT (26U)UI2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)UI2S_TCR2_BCI_MASK (0x10000000U)UI2S_TCR2_BCI_SHIFT (28U)UI2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)UI2S_TCR2_BCS_MASK (0x20000000U)UI2S_TCR2_BCS_SHIFT (29U)UI2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)UI2S_TCR2_SYNC_MASK (0xC0000000U)UI2S_TCR2_SYNC_SHIFT (30U)UI2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)UI2S_TCR3_WDFL_MASK (0x1FU)UI2S_TCR3_WDFL_SHIFT (0U)UI2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)UI2S_TCR3_TCE_MASK (0xF0000U)UI2S_TCR3_TCE_SHIFT (16U)UI2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)UI2S_TCR3_CFR_MASK (0xF000000U)UI2S_TCR3_CFR_SHIFT (24U)UI2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)UI2S_TCR4_FSD_MASK (0x1U)UI2S_TCR4_FSD_SHIFT (0U)UI2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)UI2S_TCR4_FSP_MASK (0x2U)UI2S_TCR4_FSP_SHIFT (1U)UI2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)UI2S_TCR4_ONDEM_MASK (0x4U)UI2S_TCR4_ONDEM_SHIFT (2U)UI2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)UI2S_TCR4_FSE_MASK (0x8U)UI2S_TCR4_FSE_SHIFT (3U)UI2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)UI2S_TCR4_MF_MASK (0x10U)UI2S_TCR4_MF_SHIFT (4U)UI2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)UI2S_TCR4_CHMOD_MASK (0x20U)UI2S_TCR4_CHMOD_SHIFT (5U)UI2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)UI2S_TCR4_SYWD_MASK (0x1F00U)UI2S_TCR4_SYWD_SHIFT (8U)UI2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)UI2S_TCR4_FRSZ_MASK (0x1F0000U)UI2S_TCR4_FRSZ_SHIFT (16U)UI2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)UI2S_TCR4_FPACK_MASK (0x3000000U)UI2S_TCR4_FPACK_SHIFT (24U)UI2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)UI2S_TCR4_FCOMB_MASK (0xC000000U)UI2S_TCR4_FCOMB_SHIFT (26U)UI2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)UI2S_TCR4_FCONT_MASK (0x10000000U)UI2S_TCR4_FCONT_SHIFT (28U)VI2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)VI2S_TCR5_FBT_MASK (0x1F00U)VI2S_TCR5_FBT_SHIFT (8U)VI2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)VI2S_TCR5_W0W_MASK (0x1F0000U)VI2S_TCR5_W0W_SHIFT (16U)VI2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)VI2S_TCR5_WNW_MASK (0x1F000000U)VI2S_TCR5_WNW_SHIFT (24U)VI2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)VI2S_TDR_TDR_MASK (0xFFFFFFFFU)VI2S_TDR_TDR_SHIFT (0U)VI2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)VI2S_TDR_COUNT (4U)VI2S_TFR_RFP_MASK (0x3FU)VI2S_TFR_RFP_SHIFT (0U)VI2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)VI2S_TFR_WFP_MASK (0x3F0000U)VI2S_TFR_WFP_SHIFT (16U)VI2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)VI2S_TFR_WCP_MASK (0x80000000U)VI2S_TFR_WCP_SHIFT (31U)VI2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)VI2S_TFR_COUNT (4U)VI2S_TMR_TWM_MASK (0xFFFFFFFFU)VI2S_TMR_TWM_SHIFT (0U)VI2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)VI2S_RCSR_FRDE_MASK (0x1U)VI2S_RCSR_FRDE_SHIFT (0U)VI2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)VI2S_RCSR_FWDE_MASK (0x2U)VI2S_RCSR_FWDE_SHIFT (1U)VI2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)VI2S_RCSR_FRIE_MASK (0x100U)VI2S_RCSR_FRIE_SHIFT (8U)VI2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)VI2S_RCSR_FWIE_MASK (0x200U)VI2S_RCSR_FWIE_SHIFT (9U)VI2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)VI2S_RCSR_FEIE_MASK (0x400U)VI2S_RCSR_FEIE_SHIFT (10U)VI2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)VI2S_RCSR_SEIE_MASK (0x800U)VI2S_RCSR_SEIE_SHIFT (11U)VI2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)VI2S_RCSR_WSIE_MASK (0x1000U)VI2S_RCSR_WSIE_SHIFT (12U)VI2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)VI2S_RCSR_FRF_MASK (0x10000U)VI2S_RCSR_FRF_SHIFT (16U)VI2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)VI2S_RCSR_FWF_MASK (0x20000U)VI2S_RCSR_FWF_SHIFT (17U)VI2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)VI2S_RCSR_FEF_MASK (0x40000U)VI2S_RCSR_FEF_SHIFT (18U)VI2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)VI2S_RCSR_SEF_MASK (0x80000U)VI2S_RCSR_SEF_SHIFT (19U)VI2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)VI2S_RCSR_WSF_MASK (0x100000U)VI2S_RCSR_WSF_SHIFT (20U)VI2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)VI2S_RCSR_SR_MASK (0x1000000U)VI2S_RCSR_SR_SHIFT (24U)VI2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)VI2S_RCSR_FR_MASK (0x2000000U)VI2S_RCSR_FR_SHIFT (25U)VI2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)VI2S_RCSR_BCE_MASK (0x10000000U)VI2S_RCSR_BCE_SHIFT (28U)VI2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)VI2S_RCSR_DBGE_MASK (0x20000000U)VI2S_RCSR_DBGE_SHIFT (29U)VI2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)VI2S_RCSR_STOPE_MASK (0x40000000U)VI2S_RCSR_STOPE_SHIFT (30U)VI2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)VI2S_RCSR_RE_MASK (0x80000000U)VI2S_RCSR_RE_SHIFT (31U)VI2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)VI2S_RCR1_RFW_MASK (0x1FU)VI2S_RCR1_RFW_SHIFT (0U)VI2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)VI2S_RCR2_DIV_MASK (0xFFU)VI2S_RCR2_DIV_SHIFT (0U)VI2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)VI2S_RCR2_BCD_MASK (0x1000000U)VI2S_RCR2_BCD_SHIFT (24U)VI2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)VI2S_RCR2_BCP_MASK (0x2000000U)VI2S_RCR2_BCP_SHIFT (25U)VI2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)VI2S_RCR2_MSEL_MASK (0xC000000U)VI2S_RCR2_MSEL_SHIFT (26U)VI2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)WI2S_RCR2_BCI_MASK (0x10000000U)WI2S_RCR2_BCI_SHIFT (28U)WI2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)WI2S_RCR2_BCS_MASK (0x20000000U)WI2S_RCR2_BCS_SHIFT (29U)WI2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)WI2S_RCR2_SYNC_MASK (0xC0000000U)WI2S_RCR2_SYNC_SHIFT (30U)WI2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)WI2S_RCR3_WDFL_MASK (0x1FU)WI2S_RCR3_WDFL_SHIFT (0U)WI2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)WI2S_RCR3_RCE_MASK (0xF0000U)WI2S_RCR3_RCE_SHIFT (16U)WI2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)WI2S_RCR3_CFR_MASK (0xF000000U)WI2S_RCR3_CFR_SHIFT (24U)WI2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)WI2S_RCR4_FSD_MASK (0x1U)WI2S_RCR4_FSD_SHIFT (0U)WI2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)WI2S_RCR4_FSP_MASK (0x2U)WI2S_RCR4_FSP_SHIFT (1U)WI2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)WI2S_RCR4_ONDEM_MASK (0x4U)WI2S_RCR4_ONDEM_SHIFT (2U)WI2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)WI2S_RCR4_FSE_MASK (0x8U)WI2S_RCR4_FSE_SHIFT (3U)WI2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)WI2S_RCR4_MF_MASK (0x10U)WI2S_RCR4_MF_SHIFT (4U)WI2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)WI2S_RCR4_SYWD_MASK (0x1F00U)WI2S_RCR4_SYWD_SHIFT (8U)WI2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)WI2S_RCR4_FRSZ_MASK (0x1F0000U)WI2S_RCR4_FRSZ_SHIFT (16U)WI2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)WI2S_RCR4_FPACK_MASK (0x3000000U)WI2S_RCR4_FPACK_SHIFT (24U)WI2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)WI2S_RCR4_FCOMB_MASK (0xC000000U)WI2S_RCR4_FCOMB_SHIFT (26U)WI2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)WI2S_RCR4_FCONT_MASK (0x10000000U)WI2S_RCR4_FCONT_SHIFT (28U)WI2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)WI2S_RCR5_FBT_MASK (0x1F00U)WI2S_RCR5_FBT_SHIFT (8U)WI2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)WI2S_RCR5_W0W_MASK (0x1F0000U)WI2S_RCR5_W0W_SHIFT (16U)WI2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)WI2S_RCR5_WNW_MASK (0x1F000000U)WI2S_RCR5_WNW_SHIFT (24U)WI2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)WI2S_RDR_RDR_MASK (0xFFFFFFFFU)WI2S_RDR_RDR_SHIFT (0U)WI2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)WI2S_RDR_COUNT (4U)WI2S_RFR_RFP_MASK (0x3FU)WI2S_RFR_RFP_SHIFT (0U)WI2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)WI2S_RFR_RCP_MASK (0x8000U)WI2S_RFR_RCP_SHIFT (15U)WI2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)WI2S_RFR_WFP_MASK (0x3F0000U)WI2S_RFR_WFP_SHIFT (16U)WI2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)WI2S_RFR_COUNT (4U)WI2S_RMR_RWM_MASK (0xFFFFFFFFU)WI2S_RMR_RWM_SHIFT (0U)WI2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)WSAI1_BASE (0x40384000u)WSAI1 ((I2S_Type *)SAI1_BASE)WSAI2_BASE (0x40388000u)WSAI2 ((I2S_Type *)SAI2_BASE)WSAI3_BASE (0x4038C000u)WSAI3 ((I2S_Type *)SAI3_BASE)WI2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }WI2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }XI2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }XI2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }XIOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)XIOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)XIOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)XIOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)XIOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)XIOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)XIOMUXC_SW_MUX_CTL_PAD_COUNT (93U)XIOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)XIOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)XIOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)XIOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)XIOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)XIOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)XIOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)XIOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)XIOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)XIOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)XIOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)XIOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)XIOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)XIOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)XIOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)XIOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)XIOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)XIOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)XIOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)XIOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)XIOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)XIOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)XIOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)XIOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)XIOMUXC_SW_PAD_CTL_PAD_COUNT (93U)XIOMUXC_SELECT_INPUT_DAISY_MASK (0x7U)XIOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)XIOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)XIOMUXC_SELECT_INPUT_COUNT (114U)XIOMUXC_BASE (0x401F8000u)XIOMUXC ((IOMUXC_Type *)IOMUXC_BASE)XIOMUXC_BASE_ADDRS { IOMUXC_BASE }XIOMUXC_BASE_PTRS { IOMUXC }YIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)YIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)YIOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)YIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)YIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)YIOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)YIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)YIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)YIOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)YIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)YIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)YIOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)YIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)YIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)YIOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)YIOMUXC_GPR_GPR1_GINT_MASK (0x1000U)YIOMUXC_GPR_GPR1_GINT_SHIFT (12U)YIOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)YIOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)YIOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)YIOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)YIOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)YIOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)YIOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)YIOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)YIOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)YIOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)YIOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)YIOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)YIOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)YIOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)YIOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)YIOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)YIOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)YIOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)YIOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)YIOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)YIOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)YIOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)YIOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)YIOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)YIOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)YIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)YIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)YIOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)YIOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)YIOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)YIOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)YIOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U)YIOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U)YIOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK)YIOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)YIOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)YIOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)YIOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)YIOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)YIOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)YIOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)YIOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)YIOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)YIOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)YIOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)YIOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)YIOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)YIOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)YIOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)YIOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)YIOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)YIOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)YIOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)YIOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)YIOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)YIOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)YIOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)YIOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)YIOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)YIOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)YIOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)YIOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)YIOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)YIOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)YIOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)YIOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)YIOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)YIOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)ZIOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)ZIOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)ZIOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)ZIOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)ZIOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)ZIOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)ZIOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)ZIOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)ZIOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)ZIOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)ZIOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)ZIOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)ZIOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)ZIOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)ZIOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)ZIOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)ZIOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)ZIOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)ZIOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)ZIOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)ZIOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)ZIOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)ZIOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)ZIOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)ZIOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)ZIOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)ZIOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)ZIOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)ZIOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)ZIOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)ZIOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)ZIOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)ZIOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)ZIOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)ZIOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)ZIOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)ZIOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)ZIOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)ZIOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)ZIOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)ZIOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)ZIOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)ZIOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)ZIOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)ZIOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)ZIOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)ZIOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)ZIOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)ZIOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)ZIOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)ZIOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)ZIOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)ZIOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)ZIOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)ZIOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)ZIOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)ZIOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)ZIOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)[IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)[IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)[IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)[IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)[IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)[IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)[IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)[IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)[IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)[IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)[IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)[IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)[IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)[IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)[IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)[IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)[IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)[IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)[IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)[IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)[IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)[IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)[IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)[IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)[IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)[IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)[IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)[IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)[IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)[IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)[IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)[IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)[IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)[IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)[IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)[IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)[IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)[IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)[IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)[IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)[IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)[IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)[IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)[IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)[IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)[IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)[IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)[IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)[IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)[IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)[IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)[IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)[IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)[IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)[IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)[IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)[IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)[IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)[IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)[IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)[IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)\IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)\IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)\IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)\IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)\IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)\IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)\IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)\IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)\IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)\IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)\IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)\IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)\IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)\IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)\IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)\IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)\IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)\IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)\IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)\IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)\IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)\IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)\IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)\IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)\IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)\IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)\IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)\IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)\IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)\IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)\IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)\IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)\IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)\IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)\IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)\IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)\IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)\IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)\IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)\IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)\IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)\IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)\IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)\IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)\IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)\IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)\IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)\IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)\IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)\IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)\IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)\IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)\IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)\IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)\IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)\IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)\IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)\IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)\IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)\IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)\IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)\IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)\IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)\IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)\IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)\IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)\IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)\IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)\IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)\IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)\IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)\IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)\IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)\IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)\IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)\IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)\IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)\IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)\IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)\IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)\IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)\IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)\IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)\IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)\IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)\IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)\IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)\IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)\IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)\IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)\IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)]IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)]IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x7E00U)]IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)]IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)]IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)]IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)]IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)]IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)]IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)]IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)]IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)]IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)]IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)]IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)]IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)]IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)]IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)]IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)]IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)]IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)]IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)]IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)]IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)]IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)]IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)]IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)]IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)]IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)]IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)]IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)]IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)]IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)]IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)]IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)]IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)]IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)]IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)]IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)]IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)]IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)]IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)]IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)]IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)]IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)]IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)]IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)]IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)]IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)]IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)]IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)]IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)]IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)]IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)]IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)]IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)]IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)]IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)]IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)]IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)]IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)]IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)]IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)]IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)]IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)]IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)]IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)]IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)]IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)]IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)]IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)]IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)^IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)^IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)^IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)^IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)^IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)^IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)^IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)^IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)^IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)^IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)^IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)^IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)^IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U)^IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U)^IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)^IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFU)^IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)^IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)^IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)^IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)^IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)^IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)^IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)^IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)^IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)^IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)^IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)^IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)^IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)^IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)^IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)^IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)^IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)^IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)^IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)^IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)^IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)^IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)^IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)^IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)^IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)^IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)^IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)^IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)^IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)^IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK)^IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)^IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)^IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)^IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)^IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)^IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U)^IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK)^IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)^IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)^IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)^IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)^IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)^IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)^IOMUXC_GPR_BASE (0x400AC000u)^IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)^IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }^IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)`IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)`IOMUXC_SNVS_BASE (0x400A8000u)`IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)`IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }`IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }aIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)aIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)aIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)aIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)aIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)aIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)aIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)aIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)aIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)aIOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)aIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)aIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)aIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)aIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)aIOMUXC_SNVS_GPR_BASE (0x400A4000u)aIOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)aIOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }aIOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }aKPP_KPCR_KRE_MASK (0xFFU)aKPP_KPCR_KRE_SHIFT (0U)aKPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)aKPP_KPCR_KCO_MASK (0xFF00U)aKPP_KPCR_KCO_SHIFT (8U)aKPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)aKPP_KPSR_KPKD_MASK (0x1U)aKPP_KPSR_KPKD_SHIFT (0U)aKPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)aKPP_KPSR_KPKR_MASK (0x2U)aKPP_KPSR_KPKR_SHIFT (1U)aKPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)aKPP_KPSR_KDSC_MASK (0x4U)aKPP_KPSR_KDSC_SHIFT (2U)aKPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)aKPP_KPSR_KRSS_MASK (0x8U)aKPP_KPSR_KRSS_SHIFT (3U)aKPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)aKPP_KPSR_KDIE_MASK (0x100U)aKPP_KPSR_KDIE_SHIFT (8U)aKPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)aKPP_KPSR_KRIE_MASK (0x200U)aKPP_KPSR_KRIE_SHIFT (9U)aKPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)aKPP_KDDR_KRDD_MASK (0xFFU)bKPP_KDDR_KRDD_SHIFT (0U)bKPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)bKPP_KDDR_KCDD_MASK (0xFF00U)bKPP_KDDR_KCDD_SHIFT (8U)bKPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)bKPP_KPDR_KRD_MASK (0xFFU)bKPP_KPDR_KRD_SHIFT (0U)bKPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)bKPP_KPDR_KCD_MASK (0xFF00U)bKPP_KPDR_KCD_SHIFT (8U)bKPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)bKPP_BASE (0x401FC000u)bKPP ((KPP_Type *)KPP_BASE)bKPP_BASE_ADDRS { KPP_BASE }bKPP_BASE_PTRS { KPP }bKPP_IRQS { KPP_IRQn }bLPI2C_VERID_FEATURE_MASK (0xFFFFU)bLPI2C_VERID_FEATURE_SHIFT (0U)bLPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)bLPI2C_VERID_MINOR_MASK (0xFF0000U)bLPI2C_VERID_MINOR_SHIFT (16U)bLPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)bLPI2C_VERID_MAJOR_MASK (0xFF000000U)bLPI2C_VERID_MAJOR_SHIFT (24U)bLPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)bLPI2C_PARAM_MTXFIFO_MASK (0xFU)bLPI2C_PARAM_MTXFIFO_SHIFT (0U)bLPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)bLPI2C_PARAM_MRXFIFO_MASK (0xF00U)bLPI2C_PARAM_MRXFIFO_SHIFT (8U)bLPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)bLPI2C_MCR_MEN_MASK (0x1U)cLPI2C_MCR_MEN_SHIFT (0U)cLPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)cLPI2C_MCR_RST_MASK (0x2U)cLPI2C_MCR_RST_SHIFT (1U)cLPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)cLPI2C_MCR_DOZEN_MASK (0x4U)cLPI2C_MCR_DOZEN_SHIFT (2U)cLPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)cLPI2C_MCR_DBGEN_MASK (0x8U)cLPI2C_MCR_DBGEN_SHIFT (3U)cLPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)cLPI2C_MCR_RTF_MASK (0x100U)cLPI2C_MCR_RTF_SHIFT (8U)cLPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)cLPI2C_MCR_RRF_MASK (0x200U)cLPI2C_MCR_RRF_SHIFT (9U)cLPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)cLPI2C_MSR_TDF_MASK (0x1U)cLPI2C_MSR_TDF_SHIFT (0U)cLPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)cLPI2C_MSR_RDF_MASK (0x2U)cLPI2C_MSR_RDF_SHIFT (1U)cLPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)cLPI2C_MSR_EPF_MASK (0x100U)cLPI2C_MSR_EPF_SHIFT (8U)cLPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)cLPI2C_MSR_SDF_MASK (0x200U)cLPI2C_MSR_SDF_SHIFT (9U)cLPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)cLPI2C_MSR_NDF_MASK (0x400U)cLPI2C_MSR_NDF_SHIFT (10U)cLPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)cLPI2C_MSR_ALF_MASK (0x800U)cLPI2C_MSR_ALF_SHIFT (11U)cLPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)cLPI2C_MSR_FEF_MASK (0x1000U)cLPI2C_MSR_FEF_SHIFT (12U)cLPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)cLPI2C_MSR_PLTF_MASK (0x2000U)cLPI2C_MSR_PLTF_SHIFT (13U)cLPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)cLPI2C_MSR_DMF_MASK (0x4000U)cLPI2C_MSR_DMF_SHIFT (14U)cLPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)cLPI2C_MSR_MBF_MASK (0x1000000U)cLPI2C_MSR_MBF_SHIFT (24U)cLPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)cLPI2C_MSR_BBF_MASK (0x2000000U)cLPI2C_MSR_BBF_SHIFT (25U)cLPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)cLPI2C_MIER_TDIE_MASK (0x1U)cLPI2C_MIER_TDIE_SHIFT (0U)cLPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)cLPI2C_MIER_RDIE_MASK (0x2U)cLPI2C_MIER_RDIE_SHIFT (1U)cLPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)cLPI2C_MIER_EPIE_MASK (0x100U)cLPI2C_MIER_EPIE_SHIFT (8U)cLPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)cLPI2C_MIER_SDIE_MASK (0x200U)cLPI2C_MIER_SDIE_SHIFT (9U)cLPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)cLPI2C_MIER_NDIE_MASK (0x400U)cLPI2C_MIER_NDIE_SHIFT (10U)cLPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)cLPI2C_MIER_ALIE_MASK (0x800U)cLPI2C_MIER_ALIE_SHIFT (11U)cLPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)cLPI2C_MIER_FEIE_MASK (0x1000U)cLPI2C_MIER_FEIE_SHIFT (12U)cLPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)cLPI2C_MIER_PLTIE_MASK (0x2000U)cLPI2C_MIER_PLTIE_SHIFT (13U)cLPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)cLPI2C_MIER_DMIE_MASK (0x4000U)cLPI2C_MIER_DMIE_SHIFT (14U)cLPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)cLPI2C_MDER_TDDE_MASK (0x1U)cLPI2C_MDER_TDDE_SHIFT (0U)cLPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)cLPI2C_MDER_RDDE_MASK (0x2U)cLPI2C_MDER_RDDE_SHIFT (1U)cLPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)cLPI2C_MCFGR0_HREN_MASK (0x1U)cLPI2C_MCFGR0_HREN_SHIFT (0U)cLPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)cLPI2C_MCFGR0_HRPOL_MASK (0x2U)cLPI2C_MCFGR0_HRPOL_SHIFT (1U)cLPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)cLPI2C_MCFGR0_HRSEL_MASK (0x4U)cLPI2C_MCFGR0_HRSEL_SHIFT (2U)cLPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)cLPI2C_MCFGR0_CIRFIFO_MASK (0x100U)cLPI2C_MCFGR0_CIRFIFO_SHIFT (8U)cLPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)cLPI2C_MCFGR0_RDMO_MASK (0x200U)cLPI2C_MCFGR0_RDMO_SHIFT (9U)cLPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)cLPI2C_MCFGR1_PRESCALE_MASK (0x7U)cLPI2C_MCFGR1_PRESCALE_SHIFT (0U)cLPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)cLPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)cLPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)cLPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)cLPI2C_MCFGR1_IGNACK_MASK (0x200U)cLPI2C_MCFGR1_IGNACK_SHIFT (9U)cLPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)cLPI2C_MCFGR1_TIMECFG_MASK (0x400U)dLPI2C_MCFGR1_TIMECFG_SHIFT (10U)dLPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)dLPI2C_MCFGR1_MATCFG_MASK (0x70000U)dLPI2C_MCFGR1_MATCFG_SHIFT (16U)dLPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)dLPI2C_MCFGR1_PINCFG_MASK (0x7000000U)dLPI2C_MCFGR1_PINCFG_SHIFT (24U)dLPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)dLPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)dLPI2C_MCFGR2_BUSIDLE_SHIFT (0U)dLPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)dLPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)dLPI2C_MCFGR2_FILTSCL_SHIFT (16U)dLPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)dLPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)dLPI2C_MCFGR2_FILTSDA_SHIFT (24U)dLPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)dLPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)dLPI2C_MCFGR3_PINLOW_SHIFT (8U)dLPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)dLPI2C_MDMR_MATCH0_MASK (0xFFU)dLPI2C_MDMR_MATCH0_SHIFT (0U)dLPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)dLPI2C_MDMR_MATCH1_MASK (0xFF0000U)dLPI2C_MDMR_MATCH1_SHIFT (16U)dLPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)dLPI2C_MCCR0_CLKLO_MASK (0x3FU)dLPI2C_MCCR0_CLKLO_SHIFT (0U)dLPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)dLPI2C_MCCR0_CLKHI_MASK (0x3F00U)dLPI2C_MCCR0_CLKHI_SHIFT (8U)dLPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)dLPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)dLPI2C_MCCR0_SETHOLD_SHIFT (16U)dLPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)dLPI2C_MCCR0_DATAVD_MASK (0x3F000000U)dLPI2C_MCCR0_DATAVD_SHIFT (24U)dLPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)dLPI2C_MCCR1_CLKLO_MASK (0x3FU)dLPI2C_MCCR1_CLKLO_SHIFT (0U)dLPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)dLPI2C_MCCR1_CLKHI_MASK (0x3F00U)dLPI2C_MCCR1_CLKHI_SHIFT (8U)dLPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)dLPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)dLPI2C_MCCR1_SETHOLD_SHIFT (16U)dLPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)dLPI2C_MCCR1_DATAVD_MASK (0x3F000000U)dLPI2C_MCCR1_DATAVD_SHIFT (24U)dLPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)dLPI2C_MFCR_TXWATER_MASK (0x3U)dLPI2C_MFCR_TXWATER_SHIFT (0U)dLPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)dLPI2C_MFCR_RXWATER_MASK (0x30000U)dLPI2C_MFCR_RXWATER_SHIFT (16U)dLPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)dLPI2C_MFSR_TXCOUNT_MASK (0x7U)dLPI2C_MFSR_TXCOUNT_SHIFT (0U)dLPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)dLPI2C_MFSR_RXCOUNT_MASK (0x70000U)dLPI2C_MFSR_RXCOUNT_SHIFT (16U)dLPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)dLPI2C_MTDR_DATA_MASK (0xFFU)dLPI2C_MTDR_DATA_SHIFT (0U)dLPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)dLPI2C_MTDR_CMD_MASK (0x700U)dLPI2C_MTDR_CMD_SHIFT (8U)dLPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)dLPI2C_MRDR_DATA_MASK (0xFFU)dLPI2C_MRDR_DATA_SHIFT (0U)dLPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)dLPI2C_MRDR_RXEMPTY_MASK (0x4000U)dLPI2C_MRDR_RXEMPTY_SHIFT (14U)dLPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)dLPI2C_SCR_SEN_MASK (0x1U)dLPI2C_SCR_SEN_SHIFT (0U)dLPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)dLPI2C_SCR_RST_MASK (0x2U)dLPI2C_SCR_RST_SHIFT (1U)dLPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)dLPI2C_SCR_FILTEN_MASK (0x10U)dLPI2C_SCR_FILTEN_SHIFT (4U)dLPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)dLPI2C_SCR_FILTDZ_MASK (0x20U)dLPI2C_SCR_FILTDZ_SHIFT (5U)dLPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)dLPI2C_SCR_RTF_MASK (0x100U)dLPI2C_SCR_RTF_SHIFT (8U)eLPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)eLPI2C_SCR_RRF_MASK (0x200U)eLPI2C_SCR_RRF_SHIFT (9U)eLPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)eLPI2C_SSR_TDF_MASK (0x1U)eLPI2C_SSR_TDF_SHIFT (0U)eLPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)eLPI2C_SSR_RDF_MASK (0x2U)eLPI2C_SSR_RDF_SHIFT (1U)eLPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)eLPI2C_SSR_AVF_MASK (0x4U)eLPI2C_SSR_AVF_SHIFT (2U)eLPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)eLPI2C_SSR_TAF_MASK (0x8U)eLPI2C_SSR_TAF_SHIFT (3U)eLPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)eLPI2C_SSR_RSF_MASK (0x100U)eLPI2C_SSR_RSF_SHIFT (8U)eLPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)eLPI2C_SSR_SDF_MASK (0x200U)eLPI2C_SSR_SDF_SHIFT (9U)eLPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)eLPI2C_SSR_BEF_MASK (0x400U)eLPI2C_SSR_BEF_SHIFT (10U)eLPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)eLPI2C_SSR_FEF_MASK (0x800U)eLPI2C_SSR_FEF_SHIFT (11U)eLPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)eLPI2C_SSR_AM0F_MASK (0x1000U)eLPI2C_SSR_AM0F_SHIFT (12U)eLPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)eLPI2C_SSR_AM1F_MASK (0x2000U)eLPI2C_SSR_AM1F_SHIFT (13U)eLPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)eLPI2C_SSR_GCF_MASK (0x4000U)eLPI2C_SSR_GCF_SHIFT (14U)eLPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)eLPI2C_SSR_SARF_MASK (0x8000U)eLPI2C_SSR_SARF_SHIFT (15U)eLPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)eLPI2C_SSR_SBF_MASK (0x1000000U)eLPI2C_SSR_SBF_SHIFT (24U)eLPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)eLPI2C_SSR_BBF_MASK (0x2000000U)eLPI2C_SSR_BBF_SHIFT (25U)eLPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)eLPI2C_SIER_TDIE_MASK (0x1U)eLPI2C_SIER_TDIE_SHIFT (0U)eLPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)eLPI2C_SIER_RDIE_MASK (0x2U)eLPI2C_SIER_RDIE_SHIFT (1U)eLPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)eLPI2C_SIER_AVIE_MASK (0x4U)eLPI2C_SIER_AVIE_SHIFT (2U)eLPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)eLPI2C_SIER_TAIE_MASK (0x8U)eLPI2C_SIER_TAIE_SHIFT (3U)eLPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)eLPI2C_SIER_RSIE_MASK (0x100U)eLPI2C_SIER_RSIE_SHIFT (8U)eLPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)eLPI2C_SIER_SDIE_MASK (0x200U)eLPI2C_SIER_SDIE_SHIFT (9U)eLPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)eLPI2C_SIER_BEIE_MASK (0x400U)eLPI2C_SIER_BEIE_SHIFT (10U)eLPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)eLPI2C_SIER_FEIE_MASK (0x800U)eLPI2C_SIER_FEIE_SHIFT (11U)eLPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)eLPI2C_SIER_AM0IE_MASK (0x1000U)eLPI2C_SIER_AM0IE_SHIFT (12U)eLPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)eLPI2C_SIER_AM1F_MASK (0x2000U)eLPI2C_SIER_AM1F_SHIFT (13U)eLPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)eLPI2C_SIER_GCIE_MASK (0x4000U)eLPI2C_SIER_GCIE_SHIFT (14U)eLPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)eLPI2C_SIER_SARIE_MASK (0x8000U)eLPI2C_SIER_SARIE_SHIFT (15U)eLPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)eLPI2C_SDER_TDDE_MASK (0x1U)eLPI2C_SDER_TDDE_SHIFT (0U)eLPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)eLPI2C_SDER_RDDE_MASK (0x2U)eLPI2C_SDER_RDDE_SHIFT (1U)eLPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)eLPI2C_SDER_AVDE_MASK (0x4U)eLPI2C_SDER_AVDE_SHIFT (2U)eLPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)eLPI2C_SCFGR1_ADRSTALL_MASK (0x1U)eLPI2C_SCFGR1_ADRSTALL_SHIFT (0U)eLPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)eLPI2C_SCFGR1_RXSTALL_MASK (0x2U)eLPI2C_SCFGR1_RXSTALL_SHIFT (1U)eLPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)eLPI2C_SCFGR1_TXDSTALL_MASK (0x4U)eLPI2C_SCFGR1_TXDSTALL_SHIFT (2U)eLPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)eLPI2C_SCFGR1_ACKSTALL_MASK (0x8U)eLPI2C_SCFGR1_ACKSTALL_SHIFT (3U)eLPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)eLPI2C_SCFGR1_GCEN_MASK (0x100U)eLPI2C_SCFGR1_GCEN_SHIFT (8U)eLPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)eLPI2C_SCFGR1_SAEN_MASK (0x200U)eLPI2C_SCFGR1_SAEN_SHIFT (9U)eLPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)eLPI2C_SCFGR1_TXCFG_MASK (0x400U)eLPI2C_SCFGR1_TXCFG_SHIFT (10U)eLPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)fLPI2C_SCFGR1_RXCFG_MASK (0x800U)fLPI2C_SCFGR1_RXCFG_SHIFT (11U)fLPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)fLPI2C_SCFGR1_IGNACK_MASK (0x1000U)fLPI2C_SCFGR1_IGNACK_SHIFT (12U)fLPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)fLPI2C_SCFGR1_HSMEN_MASK (0x2000U)fLPI2C_SCFGR1_HSMEN_SHIFT (13U)fLPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)fLPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)fLPI2C_SCFGR1_ADDRCFG_SHIFT (16U)fLPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)fLPI2C_SCFGR2_CLKHOLD_MASK (0xFU)fLPI2C_SCFGR2_CLKHOLD_SHIFT (0U)fLPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)fLPI2C_SCFGR2_DATAVD_MASK (0x3F00U)fLPI2C_SCFGR2_DATAVD_SHIFT (8U)fLPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)fLPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)fLPI2C_SCFGR2_FILTSCL_SHIFT (16U)fLPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)fLPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)fLPI2C_SCFGR2_FILTSDA_SHIFT (24U)fLPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)fLPI2C_SAMR_ADDR0_MASK (0x7FEU)fLPI2C_SAMR_ADDR0_SHIFT (1U)fLPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)fLPI2C_SAMR_ADDR1_MASK (0x7FE0000U)fLPI2C_SAMR_ADDR1_SHIFT (17U)fLPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)fLPI2C_SASR_RADDR_MASK (0x7FFU)fLPI2C_SASR_RADDR_SHIFT (0U)fLPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)fLPI2C_SASR_ANV_MASK (0x4000U)fLPI2C_SASR_ANV_SHIFT (14U)fLPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)fLPI2C_STAR_TXNACK_MASK (0x1U)fLPI2C_STAR_TXNACK_SHIFT (0U)fLPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)fLPI2C_STDR_DATA_MASK (0xFFU)fLPI2C_STDR_DATA_SHIFT (0U)fLPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)fLPI2C_SRDR_DATA_MASK (0xFFU)fLPI2C_SRDR_DATA_SHIFT (0U)fLPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)fLPI2C_SRDR_RXEMPTY_MASK (0x4000U)fLPI2C_SRDR_RXEMPTY_SHIFT (14U)fLPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)fLPI2C_SRDR_SOF_MASK (0x8000U)fLPI2C_SRDR_SOF_SHIFT (15U)fLPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)fLPI2C1_BASE (0x403F0000u)fLPI2C1 ((LPI2C_Type *)LPI2C1_BASE)fLPI2C2_BASE (0x403F4000u)fLPI2C2 ((LPI2C_Type *)LPI2C2_BASE)fLPI2C3_BASE (0x403F8000u)fLPI2C3 ((LPI2C_Type *)LPI2C3_BASE)fLPI2C4_BASE (0x403FC000u)fLPI2C4 ((LPI2C_Type *)LPI2C4_BASE)fLPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }fLPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }fLPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }gLPSPI_VERID_FEATURE_MASK (0xFFFFU)gLPSPI_VERID_FEATURE_SHIFT (0U)gLPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)gLPSPI_VERID_MINOR_MASK (0xFF0000U)gLPSPI_VERID_MINOR_SHIFT (16U)gLPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)gLPSPI_VERID_MAJOR_MASK (0xFF000000U)gLPSPI_VERID_MAJOR_SHIFT (24U)gLPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)gLPSPI_PARAM_TXFIFO_MASK (0xFFU)gLPSPI_PARAM_TXFIFO_SHIFT (0U)gLPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)gLPSPI_PARAM_RXFIFO_MASK (0xFF00U)gLPSPI_PARAM_RXFIFO_SHIFT (8U)gLPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)gLPSPI_PARAM_PCSNUM_MASK (0xFF0000U)gLPSPI_PARAM_PCSNUM_SHIFT (16U)gLPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)gLPSPI_CR_MEN_MASK (0x1U)gLPSPI_CR_MEN_SHIFT (0U)gLPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)gLPSPI_CR_RST_MASK (0x2U)gLPSPI_CR_RST_SHIFT (1U)gLPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)gLPSPI_CR_DOZEN_MASK (0x4U)gLPSPI_CR_DOZEN_SHIFT (2U)gLPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)gLPSPI_CR_DBGEN_MASK (0x8U)gLPSPI_CR_DBGEN_SHIFT (3U)gLPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)gLPSPI_CR_RTF_MASK (0x100U)gLPSPI_CR_RTF_SHIFT (8U)gLPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)gLPSPI_CR_RRF_MASK (0x200U)gLPSPI_CR_RRF_SHIFT (9U)gLPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)gLPSPI_SR_TDF_MASK (0x1U)gLPSPI_SR_TDF_SHIFT (0U)gLPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)gLPSPI_SR_RDF_MASK (0x2U)gLPSPI_SR_RDF_SHIFT (1U)gLPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)gLPSPI_SR_WCF_MASK (0x100U)gLPSPI_SR_WCF_SHIFT (8U)gLPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)gLPSPI_SR_FCF_MASK (0x200U)gLPSPI_SR_FCF_SHIFT (9U)gLPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)gLPSPI_SR_TCF_MASK (0x400U)gLPSPI_SR_TCF_SHIFT (10U)gLPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)gLPSPI_SR_TEF_MASK (0x800U)gLPSPI_SR_TEF_SHIFT (11U)gLPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)gLPSPI_SR_REF_MASK (0x1000U)gLPSPI_SR_REF_SHIFT (12U)gLPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)gLPSPI_SR_DMF_MASK (0x2000U)gLPSPI_SR_DMF_SHIFT (13U)gLPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)gLPSPI_SR_MBF_MASK (0x1000000U)gLPSPI_SR_MBF_SHIFT (24U)gLPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)gLPSPI_IER_TDIE_MASK (0x1U)gLPSPI_IER_TDIE_SHIFT (0U)gLPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)gLPSPI_IER_RDIE_MASK (0x2U)gLPSPI_IER_RDIE_SHIFT (1U)gLPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)gLPSPI_IER_WCIE_MASK (0x100U)gLPSPI_IER_WCIE_SHIFT (8U)gLPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)gLPSPI_IER_FCIE_MASK (0x200U)gLPSPI_IER_FCIE_SHIFT (9U)gLPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)gLPSPI_IER_TCIE_MASK (0x400U)gLPSPI_IER_TCIE_SHIFT (10U)gLPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)gLPSPI_IER_TEIE_MASK (0x800U)gLPSPI_IER_TEIE_SHIFT (11U)gLPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)gLPSPI_IER_REIE_MASK (0x1000U)hLPSPI_IER_REIE_SHIFT (12U)hLPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)hLPSPI_IER_DMIE_MASK (0x2000U)hLPSPI_IER_DMIE_SHIFT (13U)hLPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)hLPSPI_DER_TDDE_MASK (0x1U)hLPSPI_DER_TDDE_SHIFT (0U)hLPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)hLPSPI_DER_RDDE_MASK (0x2U)hLPSPI_DER_RDDE_SHIFT (1U)hLPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)hLPSPI_CFGR0_HREN_MASK (0x1U)hLPSPI_CFGR0_HREN_SHIFT (0U)hLPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)hLPSPI_CFGR0_HRPOL_MASK (0x2U)hLPSPI_CFGR0_HRPOL_SHIFT (1U)hLPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)hLPSPI_CFGR0_HRSEL_MASK (0x4U)hLPSPI_CFGR0_HRSEL_SHIFT (2U)hLPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)hLPSPI_CFGR0_CIRFIFO_MASK (0x100U)hLPSPI_CFGR0_CIRFIFO_SHIFT (8U)hLPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)hLPSPI_CFGR0_RDMO_MASK (0x200U)hLPSPI_CFGR0_RDMO_SHIFT (9U)hLPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)hLPSPI_CFGR1_MASTER_MASK (0x1U)hLPSPI_CFGR1_MASTER_SHIFT (0U)hLPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)hLPSPI_CFGR1_SAMPLE_MASK (0x2U)hLPSPI_CFGR1_SAMPLE_SHIFT (1U)hLPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)hLPSPI_CFGR1_AUTOPCS_MASK (0x4U)hLPSPI_CFGR1_AUTOPCS_SHIFT (2U)hLPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)hLPSPI_CFGR1_NOSTALL_MASK (0x8U)hLPSPI_CFGR1_NOSTALL_SHIFT (3U)hLPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)hLPSPI_CFGR1_PCSPOL_MASK (0xF00U)hLPSPI_CFGR1_PCSPOL_SHIFT (8U)hLPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)hLPSPI_CFGR1_MATCFG_MASK (0x70000U)hLPSPI_CFGR1_MATCFG_SHIFT (16U)hLPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)hLPSPI_CFGR1_PINCFG_MASK (0x3000000U)hLPSPI_CFGR1_PINCFG_SHIFT (24U)hLPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)hLPSPI_CFGR1_OUTCFG_MASK (0x4000000U)hLPSPI_CFGR1_OUTCFG_SHIFT (26U)hLPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)hLPSPI_CFGR1_PCSCFG_MASK (0x8000000U)hLPSPI_CFGR1_PCSCFG_SHIFT (27U)hLPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)hLPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)hLPSPI_DMR0_MATCH0_SHIFT (0U)hLPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)hLPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)hLPSPI_DMR1_MATCH1_SHIFT (0U)hLPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)hLPSPI_CCR_SCKDIV_MASK (0xFFU)hLPSPI_CCR_SCKDIV_SHIFT (0U)hLPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)hLPSPI_CCR_DBT_MASK (0xFF00U)hLPSPI_CCR_DBT_SHIFT (8U)hLPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)hLPSPI_CCR_PCSSCK_MASK (0xFF0000U)hLPSPI_CCR_PCSSCK_SHIFT (16U)hLPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)hLPSPI_CCR_SCKPCS_MASK (0xFF000000U)hLPSPI_CCR_SCKPCS_SHIFT (24U)hLPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)hLPSPI_FCR_TXWATER_MASK (0xFU)hLPSPI_FCR_TXWATER_SHIFT (0U)hLPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)hLPSPI_FCR_RXWATER_MASK (0xF0000U)hLPSPI_FCR_RXWATER_SHIFT (16U)hLPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)hLPSPI_FSR_TXCOUNT_MASK (0x1FU)hLPSPI_FSR_TXCOUNT_SHIFT (0U)hLPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)hLPSPI_FSR_RXCOUNT_MASK (0x1F0000U)hLPSPI_FSR_RXCOUNT_SHIFT (16U)hLPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)hLPSPI_TCR_FRAMESZ_MASK (0xFFFU)hLPSPI_TCR_FRAMESZ_SHIFT (0U)hLPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)hLPSPI_TCR_WIDTH_MASK (0x30000U)hLPSPI_TCR_WIDTH_SHIFT (16U)hLPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)hLPSPI_TCR_TXMSK_MASK (0x40000U)hLPSPI_TCR_TXMSK_SHIFT (18U)hLPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)iLPSPI_TCR_RXMSK_MASK (0x80000U)iLPSPI_TCR_RXMSK_SHIFT (19U)iLPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)iLPSPI_TCR_CONTC_MASK (0x100000U)iLPSPI_TCR_CONTC_SHIFT (20U)iLPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)iLPSPI_TCR_CONT_MASK (0x200000U)iLPSPI_TCR_CONT_SHIFT (21U)iLPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)iLPSPI_TCR_BYSW_MASK (0x400000U)iLPSPI_TCR_BYSW_SHIFT (22U)iLPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)iLPSPI_TCR_LSBF_MASK (0x800000U)iLPSPI_TCR_LSBF_SHIFT (23U)iLPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)iLPSPI_TCR_PCS_MASK (0x3000000U)iLPSPI_TCR_PCS_SHIFT (24U)iLPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)iLPSPI_TCR_PRESCALE_MASK (0x38000000U)iLPSPI_TCR_PRESCALE_SHIFT (27U)iLPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)iLPSPI_TCR_CPHA_MASK (0x40000000U)iLPSPI_TCR_CPHA_SHIFT (30U)iLPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)iLPSPI_TCR_CPOL_MASK (0x80000000U)iLPSPI_TCR_CPOL_SHIFT (31U)iLPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)iLPSPI_TDR_DATA_MASK (0xFFFFFFFFU)iLPSPI_TDR_DATA_SHIFT (0U)iLPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)iLPSPI_RSR_SOF_MASK (0x1U)iLPSPI_RSR_SOF_SHIFT (0U)iLPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)iLPSPI_RSR_RXEMPTY_MASK (0x2U)iLPSPI_RSR_RXEMPTY_SHIFT (1U)iLPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)iLPSPI_RDR_DATA_MASK (0xFFFFFFFFU)iLPSPI_RDR_DATA_SHIFT (0U)iLPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)iLPSPI1_BASE (0x40394000u)iLPSPI1 ((LPSPI_Type *)LPSPI1_BASE)iLPSPI2_BASE (0x40398000u)iLPSPI2 ((LPSPI_Type *)LPSPI2_BASE)iLPSPI3_BASE (0x4039C000u)iLPSPI3 ((LPSPI_Type *)LPSPI3_BASE)iLPSPI4_BASE (0x403A0000u)iLPSPI4 ((LPSPI_Type *)LPSPI4_BASE)iLPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }iLPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }iLPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }iLPUART_VERID_FEATURE_MASK (0xFFFFU)iLPUART_VERID_FEATURE_SHIFT (0U)iLPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)iLPUART_VERID_MINOR_MASK (0xFF0000U)jLPUART_VERID_MINOR_SHIFT (16U)jLPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)jLPUART_VERID_MAJOR_MASK (0xFF000000U)jLPUART_VERID_MAJOR_SHIFT (24U)jLPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)jLPUART_PARAM_TXFIFO_MASK (0xFFU)jLPUART_PARAM_TXFIFO_SHIFT (0U)jLPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)jLPUART_PARAM_RXFIFO_MASK (0xFF00U)jLPUART_PARAM_RXFIFO_SHIFT (8U)jLPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)jLPUART_GLOBAL_RST_MASK (0x2U)jLPUART_GLOBAL_RST_SHIFT (1U)jLPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)jLPUART_PINCFG_TRGSEL_MASK (0x3U)jLPUART_PINCFG_TRGSEL_SHIFT (0U)jLPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)jLPUART_BAUD_SBR_MASK (0x1FFFU)jLPUART_BAUD_SBR_SHIFT (0U)jLPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)jLPUART_BAUD_SBNS_MASK (0x2000U)jLPUART_BAUD_SBNS_SHIFT (13U)jLPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)jLPUART_BAUD_RXEDGIE_MASK (0x4000U)jLPUART_BAUD_RXEDGIE_SHIFT (14U)jLPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)jLPUART_BAUD_LBKDIE_MASK (0x8000U)jLPUART_BAUD_LBKDIE_SHIFT (15U)jLPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)jLPUART_BAUD_RESYNCDIS_MASK (0x10000U)jLPUART_BAUD_RESYNCDIS_SHIFT (16U)jLPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)jLPUART_BAUD_BOTHEDGE_MASK (0x20000U)jLPUART_BAUD_BOTHEDGE_SHIFT (17U)jLPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)jLPUART_BAUD_MATCFG_MASK (0xC0000U)jLPUART_BAUD_MATCFG_SHIFT (18U)jLPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)jLPUART_BAUD_RIDMAE_MASK (0x100000U)jLPUART_BAUD_RIDMAE_SHIFT (20U)jLPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)jLPUART_BAUD_RDMAE_MASK (0x200000U)jLPUART_BAUD_RDMAE_SHIFT (21U)jLPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)jLPUART_BAUD_TDMAE_MASK (0x800000U)jLPUART_BAUD_TDMAE_SHIFT (23U)jLPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)jLPUART_BAUD_OSR_MASK (0x1F000000U)jLPUART_BAUD_OSR_SHIFT (24U)jLPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)jLPUART_BAUD_M10_MASK (0x20000000U)jLPUART_BAUD_M10_SHIFT (29U)jLPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)jLPUART_BAUD_MAEN2_MASK (0x40000000U)jLPUART_BAUD_MAEN2_SHIFT (30U)jLPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)jLPUART_BAUD_MAEN1_MASK (0x80000000U)jLPUART_BAUD_MAEN1_SHIFT (31U)jLPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)jLPUART_STAT_MA2F_MASK (0x4000U)jLPUART_STAT_MA2F_SHIFT (14U)jLPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)jLPUART_STAT_MA1F_MASK (0x8000U)jLPUART_STAT_MA1F_SHIFT (15U)jLPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)jLPUART_STAT_PF_MASK (0x10000U)jLPUART_STAT_PF_SHIFT (16U)jLPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)jLPUART_STAT_FE_MASK (0x20000U)jLPUART_STAT_FE_SHIFT (17U)jLPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)jLPUART_STAT_NF_MASK (0x40000U)jLPUART_STAT_NF_SHIFT (18U)jLPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)jLPUART_STAT_OR_MASK (0x80000U)jLPUART_STAT_OR_SHIFT (19U)jLPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)jLPUART_STAT_IDLE_MASK (0x100000U)jLPUART_STAT_IDLE_SHIFT (20U)jLPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)jLPUART_STAT_RDRF_MASK (0x200000U)jLPUART_STAT_RDRF_SHIFT (21U)jLPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)jLPUART_STAT_TC_MASK (0x400000U)jLPUART_STAT_TC_SHIFT (22U)jLPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)jLPUART_STAT_TDRE_MASK (0x800000U)jLPUART_STAT_TDRE_SHIFT (23U)jLPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)jLPUART_STAT_RAF_MASK (0x1000000U)jLPUART_STAT_RAF_SHIFT (24U)jLPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)jLPUART_STAT_LBKDE_MASK (0x2000000U)jLPUART_STAT_LBKDE_SHIFT (25U)jLPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)jLPUART_STAT_BRK13_MASK (0x4000000U)jLPUART_STAT_BRK13_SHIFT (26U)jLPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)jLPUART_STAT_RWUID_MASK (0x8000000U)jLPUART_STAT_RWUID_SHIFT (27U)jLPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)jLPUART_STAT_RXINV_MASK (0x10000000U)jLPUART_STAT_RXINV_SHIFT (28U)jLPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)jLPUART_STAT_MSBF_MASK (0x20000000U)jLPUART_STAT_MSBF_SHIFT (29U)jLPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)jLPUART_STAT_RXEDGIF_MASK (0x40000000U)kLPUART_STAT_RXEDGIF_SHIFT (30U)kLPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)kLPUART_STAT_LBKDIF_MASK (0x80000000U)kLPUART_STAT_LBKDIF_SHIFT (31U)kLPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)kLPUART_CTRL_PT_MASK (0x1U)kLPUART_CTRL_PT_SHIFT (0U)kLPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)kLPUART_CTRL_PE_MASK (0x2U)kLPUART_CTRL_PE_SHIFT (1U)kLPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)kLPUART_CTRL_ILT_MASK (0x4U)kLPUART_CTRL_ILT_SHIFT (2U)kLPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)kLPUART_CTRL_WAKE_MASK (0x8U)kLPUART_CTRL_WAKE_SHIFT (3U)kLPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)kLPUART_CTRL_M_MASK (0x10U)kLPUART_CTRL_M_SHIFT (4U)kLPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)kLPUART_CTRL_RSRC_MASK (0x20U)kLPUART_CTRL_RSRC_SHIFT (5U)kLPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)kLPUART_CTRL_DOZEEN_MASK (0x40U)kLPUART_CTRL_DOZEEN_SHIFT (6U)kLPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)kLPUART_CTRL_LOOPS_MASK (0x80U)kLPUART_CTRL_LOOPS_SHIFT (7U)kLPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)kLPUART_CTRL_IDLECFG_MASK (0x700U)kLPUART_CTRL_IDLECFG_SHIFT (8U)kLPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)kLPUART_CTRL_M7_MASK (0x800U)kLPUART_CTRL_M7_SHIFT (11U)kLPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)kLPUART_CTRL_MA2IE_MASK (0x4000U)kLPUART_CTRL_MA2IE_SHIFT (14U)kLPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)kLPUART_CTRL_MA1IE_MASK (0x8000U)kLPUART_CTRL_MA1IE_SHIFT (15U)kLPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)kLPUART_CTRL_SBK_MASK (0x10000U)kLPUART_CTRL_SBK_SHIFT (16U)kLPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)kLPUART_CTRL_RWU_MASK (0x20000U)kLPUART_CTRL_RWU_SHIFT (17U)kLPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)kLPUART_CTRL_RE_MASK (0x40000U)kLPUART_CTRL_RE_SHIFT (18U)kLPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)kLPUART_CTRL_TE_MASK (0x80000U)kLPUART_CTRL_TE_SHIFT (19U)kLPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)kLPUART_CTRL_ILIE_MASK (0x100000U)kLPUART_CTRL_ILIE_SHIFT (20U)kLPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)kLPUART_CTRL_RIE_MASK (0x200000U)kLPUART_CTRL_RIE_SHIFT (21U)kLPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)kLPUART_CTRL_TCIE_MASK (0x400000U)kLPUART_CTRL_TCIE_SHIFT (22U)kLPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)kLPUART_CTRL_TIE_MASK (0x800000U)kLPUART_CTRL_TIE_SHIFT (23U)kLPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)kLPUART_CTRL_PEIE_MASK (0x1000000U)kLPUART_CTRL_PEIE_SHIFT (24U)kLPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)kLPUART_CTRL_FEIE_MASK (0x2000000U)kLPUART_CTRL_FEIE_SHIFT (25U)kLPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)kLPUART_CTRL_NEIE_MASK (0x4000000U)kLPUART_CTRL_NEIE_SHIFT (26U)kLPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)kLPUART_CTRL_ORIE_MASK (0x8000000U)kLPUART_CTRL_ORIE_SHIFT (27U)kLPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)kLPUART_CTRL_TXINV_MASK (0x10000000U)kLPUART_CTRL_TXINV_SHIFT (28U)kLPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)kLPUART_CTRL_TXDIR_MASK (0x20000000U)kLPUART_CTRL_TXDIR_SHIFT (29U)kLPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)kLPUART_CTRL_R9T8_MASK (0x40000000U)kLPUART_CTRL_R9T8_SHIFT (30U)kLPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)kLPUART_CTRL_R8T9_MASK (0x80000000U)kLPUART_CTRL_R8T9_SHIFT (31U)kLPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)kLPUART_DATA_R0T0_MASK (0x1U)kLPUART_DATA_R0T0_SHIFT (0U)kLPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)kLPUART_DATA_R1T1_MASK (0x2U)kLPUART_DATA_R1T1_SHIFT (1U)kLPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)kLPUART_DATA_R2T2_MASK (0x4U)kLPUART_DATA_R2T2_SHIFT (2U)kLPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)kLPUART_DATA_R3T3_MASK (0x8U)kLPUART_DATA_R3T3_SHIFT (3U)kLPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)kLPUART_DATA_R4T4_MASK (0x10U)kLPUART_DATA_R4T4_SHIFT (4U)kLPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)kLPUART_DATA_R5T5_MASK (0x20U)kLPUART_DATA_R5T5_SHIFT (5U)kLPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)kLPUART_DATA_R6T6_MASK (0x40U)kLPUART_DATA_R6T6_SHIFT (6U)kLPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)kLPUART_DATA_R7T7_MASK (0x80U)kLPUART_DATA_R7T7_SHIFT (7U)kLPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)kLPUART_DATA_R8T8_MASK (0x100U)kLPUART_DATA_R8T8_SHIFT (8U)kLPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)kLPUART_DATA_R9T9_MASK (0x200U)kLPUART_DATA_R9T9_SHIFT (9U)kLPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)kLPUART_DATA_IDLINE_MASK (0x800U)lLPUART_DATA_IDLINE_SHIFT (11U)lLPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)lLPUART_DATA_RXEMPT_MASK (0x1000U)lLPUART_DATA_RXEMPT_SHIFT (12U)lLPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)lLPUART_DATA_FRETSC_MASK (0x2000U)lLPUART_DATA_FRETSC_SHIFT (13U)lLPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)lLPUART_DATA_PARITYE_MASK (0x4000U)lLPUART_DATA_PARITYE_SHIFT (14U)lLPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)lLPUART_DATA_NOISY_MASK (0x8000U)lLPUART_DATA_NOISY_SHIFT (15U)lLPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)lLPUART_MATCH_MA1_MASK (0x3FFU)lLPUART_MATCH_MA1_SHIFT (0U)lLPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)lLPUART_MATCH_MA2_MASK (0x3FF0000U)lLPUART_MATCH_MA2_SHIFT (16U)lLPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)lLPUART_MODIR_TXCTSE_MASK (0x1U)lLPUART_MODIR_TXCTSE_SHIFT (0U)lLPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)lLPUART_MODIR_TXRTSE_MASK (0x2U)lLPUART_MODIR_TXRTSE_SHIFT (1U)lLPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)lLPUART_MODIR_TXRTSPOL_MASK (0x4U)lLPUART_MODIR_TXRTSPOL_SHIFT (2U)lLPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)lLPUART_MODIR_RXRTSE_MASK (0x8U)lLPUART_MODIR_RXRTSE_SHIFT (3U)lLPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)lLPUART_MODIR_TXCTSC_MASK (0x10U)lLPUART_MODIR_TXCTSC_SHIFT (4U)lLPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)lLPUART_MODIR_TXCTSSRC_MASK (0x20U)lLPUART_MODIR_TXCTSSRC_SHIFT (5U)lLPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)lLPUART_MODIR_RTSWATER_MASK (0x300U)lLPUART_MODIR_RTSWATER_SHIFT (8U)lLPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)lLPUART_MODIR_TNP_MASK (0x30000U)lLPUART_MODIR_TNP_SHIFT (16U)lLPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)lLPUART_MODIR_IREN_MASK (0x40000U)lLPUART_MODIR_IREN_SHIFT (18U)lLPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)lLPUART_FIFO_RXFIFOSIZE_MASK (0x7U)lLPUART_FIFO_RXFIFOSIZE_SHIFT (0U)lLPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)lLPUART_FIFO_RXFE_MASK (0x8U)lLPUART_FIFO_RXFE_SHIFT (3U)lLPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)lLPUART_FIFO_TXFIFOSIZE_MASK (0x70U)lLPUART_FIFO_TXFIFOSIZE_SHIFT (4U)lLPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)lLPUART_FIFO_TXFE_MASK (0x80U)lLPUART_FIFO_TXFE_SHIFT (7U)lLPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)lLPUART_FIFO_RXUFE_MASK (0x100U)lLPUART_FIFO_RXUFE_SHIFT (8U)lLPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)lLPUART_FIFO_TXOFE_MASK (0x200U)lLPUART_FIFO_TXOFE_SHIFT (9U)lLPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)lLPUART_FIFO_RXIDEN_MASK (0x1C00U)lLPUART_FIFO_RXIDEN_SHIFT (10U)lLPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)lLPUART_FIFO_RXFLUSH_MASK (0x4000U)lLPUART_FIFO_RXFLUSH_SHIFT (14U)lLPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)lLPUART_FIFO_TXFLUSH_MASK (0x8000U)lLPUART_FIFO_TXFLUSH_SHIFT (15U)lLPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)lLPUART_FIFO_RXUF_MASK (0x10000U)lLPUART_FIFO_RXUF_SHIFT (16U)lLPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)lLPUART_FIFO_TXOF_MASK (0x20000U)lLPUART_FIFO_TXOF_SHIFT (17U)lLPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)lLPUART_FIFO_RXEMPT_MASK (0x400000U)lLPUART_FIFO_RXEMPT_SHIFT (22U)lLPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)lLPUART_FIFO_TXEMPT_MASK (0x800000U)lLPUART_FIFO_TXEMPT_SHIFT (23U)lLPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)lLPUART_WATER_TXWATER_MASK (0x3U)lLPUART_WATER_TXWATER_SHIFT (0U)lLPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)lLPUART_WATER_TXCOUNT_MASK (0x700U)lLPUART_WATER_TXCOUNT_SHIFT (8U)lLPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)lLPUART_WATER_RXWATER_MASK (0x30000U)lLPUART_WATER_RXWATER_SHIFT (16U)lLPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)lLPUART_WATER_RXCOUNT_MASK (0x7000000U)lLPUART_WATER_RXCOUNT_SHIFT (24U)lLPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)lLPUART1_BASE (0x40184000u)lLPUART1 ((LPUART_Type *)LPUART1_BASE)mLPUART2_BASE (0x40188000u)mLPUART2 ((LPUART_Type *)LPUART2_BASE)mLPUART3_BASE (0x4018C000u)mLPUART3 ((LPUART_Type *)LPUART3_BASE)mLPUART4_BASE (0x40190000u)mLPUART4 ((LPUART_Type *)LPUART4_BASE)mLPUART5_BASE (0x40194000u)mLPUART5 ((LPUART_Type *)LPUART5_BASE)mLPUART6_BASE (0x40198000u)mLPUART6 ((LPUART_Type *)LPUART6_BASE)mLPUART7_BASE (0x4019C000u)mLPUART7 ((LPUART_Type *)LPUART7_BASE)mLPUART8_BASE (0x401A0000u)mLPUART8 ((LPUART_Type *)LPUART8_BASE)mLPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }mLPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }mLPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }nOCOTP_CTRL_ADDR_MASK (0x3FU)nOCOTP_CTRL_ADDR_SHIFT (0U)nOCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)nOCOTP_CTRL_BUSY_MASK (0x100U)nOCOTP_CTRL_BUSY_SHIFT (8U)nOCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)nOCOTP_CTRL_ERROR_MASK (0x200U)nOCOTP_CTRL_ERROR_SHIFT (9U)nOCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)nOCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)nOCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)nOCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)nOCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)nOCOTP_CTRL_WR_UNLOCK_SHIFT (16U)nOCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)nOCOTP_CTRL_SET_ADDR_MASK (0x3FU)nOCOTP_CTRL_SET_ADDR_SHIFT (0U)nOCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)nOCOTP_CTRL_SET_BUSY_MASK (0x100U)nOCOTP_CTRL_SET_BUSY_SHIFT (8U)nOCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)nOCOTP_CTRL_SET_ERROR_MASK (0x200U)nOCOTP_CTRL_SET_ERROR_SHIFT (9U)nOCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)nOCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)nOCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)nOCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)nOCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)nOCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)nOCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)nOCOTP_CTRL_CLR_ADDR_MASK (0x3FU)nOCOTP_CTRL_CLR_ADDR_SHIFT (0U)nOCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)nOCOTP_CTRL_CLR_BUSY_MASK (0x100U)nOCOTP_CTRL_CLR_BUSY_SHIFT (8U)nOCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)nOCOTP_CTRL_CLR_ERROR_MASK (0x200U)nOCOTP_CTRL_CLR_ERROR_SHIFT (9U)nOCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)nOCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)nOCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)nOCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)nOCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)nOCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)nOCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)nOCOTP_CTRL_TOG_ADDR_MASK (0x3FU)nOCOTP_CTRL_TOG_ADDR_SHIFT (0U)nOCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)nOCOTP_CTRL_TOG_BUSY_MASK (0x100U)nOCOTP_CTRL_TOG_BUSY_SHIFT (8U)nOCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)nOCOTP_CTRL_TOG_ERROR_MASK (0x200U)nOCOTP_CTRL_TOG_ERROR_SHIFT (9U)nOCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)nOCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)nOCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)nOCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)nOCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)nOCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)nOCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)nOCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)nOCOTP_TIMING_STROBE_PROG_SHIFT (0U)nOCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)nOCOTP_TIMING_RELAX_MASK (0xF000U)nOCOTP_TIMING_RELAX_SHIFT (12U)nOCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)nOCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)nOCOTP_TIMING_STROBE_READ_SHIFT (16U)nOCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)nOCOTP_TIMING_WAIT_MASK (0xFC00000U)nOCOTP_TIMING_WAIT_SHIFT (22U)nOCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)nOCOTP_DATA_DATA_MASK (0xFFFFFFFFU)oOCOTP_DATA_DATA_SHIFT (0U)oOCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)oOCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)oOCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)oOCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)oOCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)oOCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)oOCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)oOCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)oOCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)oOCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)oOCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)oOCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)oOCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)oOCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)oOCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)oOCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)oOCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)oOCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)oOCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)oOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)oOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)oOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)oOCOTP_SCS_HAB_JDE_MASK (0x1U)oOCOTP_SCS_HAB_JDE_SHIFT (0U)oOCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)oOCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)oOCOTP_SCS_SPARE_SHIFT (1U)oOCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)oOCOTP_SCS_LOCK_MASK (0x80000000U)oOCOTP_SCS_LOCK_SHIFT (31U)oOCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)oOCOTP_SCS_SET_HAB_JDE_MASK (0x1U)oOCOTP_SCS_SET_HAB_JDE_SHIFT (0U)oOCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)oOCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)oOCOTP_SCS_SET_SPARE_SHIFT (1U)oOCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)oOCOTP_SCS_SET_LOCK_MASK (0x80000000U)oOCOTP_SCS_SET_LOCK_SHIFT (31U)oOCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)oOCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)oOCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)oOCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)oOCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)oOCOTP_SCS_CLR_SPARE_SHIFT (1U)oOCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)oOCOTP_SCS_CLR_LOCK_MASK (0x80000000U)oOCOTP_SCS_CLR_LOCK_SHIFT (31U)oOCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)oOCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)oOCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)oOCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)oOCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)oOCOTP_SCS_TOG_SPARE_SHIFT (1U)oOCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)oOCOTP_SCS_TOG_LOCK_MASK (0x80000000U)oOCOTP_SCS_TOG_LOCK_SHIFT (31U)oOCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)oOCOTP_VERSION_STEP_MASK (0xFFFFU)oOCOTP_VERSION_STEP_SHIFT (0U)oOCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)oOCOTP_VERSION_MINOR_MASK (0xFF0000U)oOCOTP_VERSION_MINOR_SHIFT (16U)oOCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)oOCOTP_VERSION_MAJOR_MASK (0xFF000000U)oOCOTP_VERSION_MAJOR_SHIFT (24U)oOCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)oOCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)oOCOTP_TIMING2_RELAX_PROG_SHIFT (0U)oOCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)oOCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)oOCOTP_TIMING2_RELAX_READ_SHIFT (16U)oOCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)oOCOTP_TIMING2_RELAX1_MASK (0x1FC00000U)oOCOTP_TIMING2_RELAX1_SHIFT (22U)oOCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK)oOCOTP_LOCK_TESTER_MASK (0x3U)oOCOTP_LOCK_TESTER_SHIFT (0U)oOCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)oOCOTP_LOCK_BOOT_CFG_MASK (0xCU)oOCOTP_LOCK_BOOT_CFG_SHIFT (2U)oOCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)oOCOTP_LOCK_MEM_TRIM_MASK (0x30U)oOCOTP_LOCK_MEM_TRIM_SHIFT (4U)oOCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)oOCOTP_LOCK_SJC_RESP_MASK (0x40U)oOCOTP_LOCK_SJC_RESP_SHIFT (6U)pOCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)pOCOTP_LOCK_MAC_ADDR_MASK (0x300U)pOCOTP_LOCK_MAC_ADDR_SHIFT (8U)pOCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)pOCOTP_LOCK_GP1_MASK (0xC00U)pOCOTP_LOCK_GP1_SHIFT (10U)pOCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)pOCOTP_LOCK_GP2_MASK (0x3000U)pOCOTP_LOCK_GP2_SHIFT (12U)pOCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)pOCOTP_LOCK_SRK_MASK (0x4000U)pOCOTP_LOCK_SRK_SHIFT (14U)pOCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK)pOCOTP_LOCK_OTPMK_MSB_MASK (0x8000U)pOCOTP_LOCK_OTPMK_MSB_SHIFT (15U)pOCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK)pOCOTP_LOCK_SW_GP1_MASK (0x10000U)pOCOTP_LOCK_SW_GP1_SHIFT (16U)pOCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)pOCOTP_LOCK_OTPMK_LSB_MASK (0x20000U)pOCOTP_LOCK_OTPMK_LSB_SHIFT (17U)pOCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK)pOCOTP_LOCK_ANALOG_MASK (0xC0000U)pOCOTP_LOCK_ANALOG_SHIFT (18U)pOCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)pOCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)pOCOTP_LOCK_OTPMK_CRC_SHIFT (20U)pOCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)pOCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)pOCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)pOCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)pOCOTP_LOCK_MISC_CONF_MASK (0x400000U)pOCOTP_LOCK_MISC_CONF_SHIFT (22U)pOCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)pOCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)pOCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)pOCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)pOCOTP_LOCK_GP3_MASK (0xC000000U)pOCOTP_LOCK_GP3_SHIFT (26U)pOCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)pOCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)pOCOTP_LOCK_FIELD_RETURN_SHIFT (28U)pOCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)pOCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG0_BITS_SHIFT (0U)pOCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)pOCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG1_BITS_SHIFT (0U)pOCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)pOCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG2_BITS_SHIFT (0U)pOCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)pOCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG3_BITS_SHIFT (0U)pOCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)pOCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG4_BITS_SHIFT (0U)pOCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)pOCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG5_BITS_SHIFT (0U)pOCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)pOCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)pOCOTP_CFG6_BITS_SHIFT (0U)pOCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)pOCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM0_BITS_SHIFT (0U)pOCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)pOCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM1_BITS_SHIFT (0U)pOCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)pOCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM2_BITS_SHIFT (0U)pOCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)pOCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM3_BITS_SHIFT (0U)pOCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)pOCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)pOCOTP_MEM4_BITS_SHIFT (0U)pOCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)qOCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)qOCOTP_ANA0_BITS_SHIFT (0U)qOCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)qOCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)qOCOTP_ANA1_BITS_SHIFT (0U)qOCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)qOCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)qOCOTP_ANA2_BITS_SHIFT (0U)qOCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)qOCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK0_BITS_SHIFT (0U)qOCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)qOCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK1_BITS_SHIFT (0U)qOCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)qOCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK2_BITS_SHIFT (0U)qOCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)qOCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK3_BITS_SHIFT (0U)qOCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)qOCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK4_BITS_SHIFT (0U)qOCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)qOCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK5_BITS_SHIFT (0U)qOCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)qOCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK6_BITS_SHIFT (0U)qOCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)qOCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)qOCOTP_SRK7_BITS_SHIFT (0U)qOCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)qOCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)qOCOTP_SJC_RESP0_BITS_SHIFT (0U)qOCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)qOCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)qOCOTP_SJC_RESP1_BITS_SHIFT (0U)qOCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)qOCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)qOCOTP_MAC0_BITS_SHIFT (0U)qOCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)qOCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)qOCOTP_MAC1_BITS_SHIFT (0U)qOCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)qOCOTP_GP3_BITS_MASK (0xFFFFFFFFU)qOCOTP_GP3_BITS_SHIFT (0U)qOCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)qOCOTP_GP1_BITS_MASK (0xFFFFFFFFU)qOCOTP_GP1_BITS_SHIFT (0U)qOCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)qOCOTP_GP2_BITS_MASK (0xFFFFFFFFU)qOCOTP_GP2_BITS_SHIFT (0U)qOCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)rOCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP1_BITS_SHIFT (0U)rOCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)rOCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP20_BITS_SHIFT (0U)rOCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)rOCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP21_BITS_SHIFT (0U)rOCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)rOCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP22_BITS_SHIFT (0U)rOCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)rOCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)rOCOTP_SW_GP23_BITS_SHIFT (0U)rOCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)rOCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)rOCOTP_MISC_CONF0_BITS_SHIFT (0U)rOCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)rOCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)rOCOTP_MISC_CONF1_BITS_SHIFT (0U)rOCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)rOCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)rOCOTP_SRK_REVOKE_BITS_SHIFT (0U)rOCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)rOCOTP_BASE (0x401F4000u)rOCOTP ((OCOTP_Type *)OCOTP_BASE)rOCOTP_BASE_ADDRS { OCOTP_BASE }rOCOTP_BASE_PTRS { OCOTP }rPGC_MEGA_CTRL_PCR_MASK (0x1U)rPGC_MEGA_CTRL_PCR_SHIFT (0U)rPGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)rPGC_MEGA_PUPSCR_SW_MASK (0x3FU)rPGC_MEGA_PUPSCR_SW_SHIFT (0U)rPGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)rPGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)rPGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)rPGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)rPGC_MEGA_PDNSCR_ISO_MASK (0x3FU)sPGC_MEGA_PDNSCR_ISO_SHIFT (0U)sPGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)sPGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)sPGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)sPGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)sPGC_MEGA_SR_PSR_MASK (0x1U)sPGC_MEGA_SR_PSR_SHIFT (0U)sPGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)sPGC_CPU_CTRL_PCR_MASK (0x1U)sPGC_CPU_CTRL_PCR_SHIFT (0U)sPGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)sPGC_CPU_PUPSCR_SW_MASK (0x3FU)sPGC_CPU_PUPSCR_SW_SHIFT (0U)sPGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)sPGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)sPGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)sPGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)sPGC_CPU_PDNSCR_ISO_MASK (0x3FU)sPGC_CPU_PDNSCR_ISO_SHIFT (0U)sPGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)sPGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)sPGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)sPGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)sPGC_CPU_SR_PSR_MASK (0x1U)sPGC_CPU_SR_PSR_SHIFT (0U)sPGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)sPGC_BASE (0x400F4000u)sPGC ((PGC_Type *)PGC_BASE)sPGC_BASE_ADDRS { PGC_BASE }sPGC_BASE_PTRS { PGC }sPIT_MCR_FRZ_MASK (0x1U)sPIT_MCR_FRZ_SHIFT (0U)sPIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)sPIT_MCR_MDIS_MASK (0x2U)sPIT_MCR_MDIS_SHIFT (1U)sPIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)sPIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)sPIT_LTMR64H_LTH_SHIFT (0U)sPIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)sPIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)sPIT_LTMR64L_LTL_SHIFT (0U)sPIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)tPIT_LDVAL_TSV_MASK (0xFFFFFFU)tPIT_LDVAL_TSV_SHIFT (0U)tPIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)tPIT_LDVAL_COUNT (4U)tPIT_CVAL_TVL_MASK (0xFFFFFFFFU)tPIT_CVAL_TVL_SHIFT (0U)tPIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)tPIT_CVAL_COUNT (4U)tPIT_TCTRL_TEN_MASK (0x1U)tPIT_TCTRL_TEN_SHIFT (0U)tPIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)tPIT_TCTRL_TIE_MASK (0x2U)tPIT_TCTRL_TIE_SHIFT (1U)tPIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)tPIT_TCTRL_CHN_MASK (0x4U)tPIT_TCTRL_CHN_SHIFT (2U)tPIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)tPIT_TCTRL_COUNT (4U)tPIT_TFLG_TIF_MASK (0x1U)tPIT_TFLG_TIF_SHIFT (0U)tPIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)tPIT_TFLG_COUNT (4U)tPIT_BASE (0x40084000u)tPIT ((PIT_Type *)PIT_BASE)tPIT_BASE_ADDRS { PIT_BASE }tPIT_BASE_PTRS { PIT }tPIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }tPMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)tPMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)tPMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)tPMU_REG_1P1_ENABLE_BO_MASK (0x2U)tPMU_REG_1P1_ENABLE_BO_SHIFT (1U)tPMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)tPMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)tPMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)uPMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)uPMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)uPMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)uPMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)uPMU_REG_1P1_BO_OFFSET_MASK (0x70U)uPMU_REG_1P1_BO_OFFSET_SHIFT (4U)uPMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)uPMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)uPMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)uPMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)uPMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)uPMU_REG_1P1_BO_VDD1P1_SHIFT (16U)uPMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)uPMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)uPMU_REG_1P1_OK_VDD1P1_SHIFT (17U)uPMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)uPMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)uPMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)uPMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)uPMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)uPMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)uPMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)uPMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)uPMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)uPMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)uPMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)uPMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)uPMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)uPMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)uPMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)uPMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)uPMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)uPMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)uPMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)uPMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)uPMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)uPMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)uPMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)uPMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)uPMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)uPMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)uPMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)uPMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)uPMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)uPMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)uPMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)uPMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)uPMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)uPMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)uPMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)uPMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)uPMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)uPMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)uPMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)uPMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)uPMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)uPMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)uPMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)uPMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)uPMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)uPMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)uPMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)uPMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)uPMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)uPMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)uPMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)uPMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)uPMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)uPMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)uPMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)uPMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)uPMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)uPMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)uPMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)uPMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)uPMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)uPMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)uPMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)uPMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)uPMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)uPMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)uPMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)uPMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)uPMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)uPMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)uPMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)uPMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)uPMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)uPMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)uPMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)uPMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)uPMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)uPMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)uPMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)uPMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)uPMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)uPMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)uPMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)uPMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)uPMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)uPMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)uPMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)uPMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)uPMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)uPMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)uPMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)uPMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)uPMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)uPMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)uPMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)uPMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)uPMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)vPMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)vPMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)vPMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)vPMU_REG_3P0_ENABLE_BO_MASK (0x2U)vPMU_REG_3P0_ENABLE_BO_SHIFT (1U)vPMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)vPMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)vPMU_REG_3P0_BO_OFFSET_MASK (0x70U)vPMU_REG_3P0_BO_OFFSET_SHIFT (4U)vPMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)vPMU_REG_3P0_VBUS_SEL_MASK (0x80U)vPMU_REG_3P0_VBUS_SEL_SHIFT (7U)vPMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)vPMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)vPMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)vPMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)vPMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)vPMU_REG_3P0_BO_VDD3P0_SHIFT (16U)vPMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)vPMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)vPMU_REG_3P0_OK_VDD3P0_SHIFT (17U)vPMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)vPMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)vPMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)vPMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)vPMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)vPMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)vPMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)vPMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)vPMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)vPMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)vPMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)vPMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)vPMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)vPMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)vPMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)vPMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)vPMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)vPMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)vPMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)vPMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)vPMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)vPMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)vPMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)vPMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)vPMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)vPMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)vPMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)vPMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)vPMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)vPMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)vPMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)vPMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)vPMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)vPMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)vPMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)vPMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)vPMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)vPMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)vPMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)vPMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)vPMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)vPMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)vPMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)vPMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)vPMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)vPMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)vPMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)vPMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)vPMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)vPMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)vPMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)vPMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)vPMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)vPMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)vPMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)vPMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)vPMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)vPMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)vPMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)vPMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)vPMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)vPMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)vPMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)vPMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)vPMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)vPMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)vPMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)vPMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)vPMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)vPMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)vPMU_REG_2P5_ENABLE_BO_MASK (0x2U)vPMU_REG_2P5_ENABLE_BO_SHIFT (1U)vPMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)vPMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)vPMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)vPMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)vPMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)vPMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)vPMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)vPMU_REG_2P5_BO_OFFSET_MASK (0x70U)vPMU_REG_2P5_BO_OFFSET_SHIFT (4U)vPMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)vPMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)wPMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)wPMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)wPMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)wPMU_REG_2P5_BO_VDD2P5_SHIFT (16U)wPMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)wPMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)wPMU_REG_2P5_OK_VDD2P5_SHIFT (17U)wPMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)wPMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)wPMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)wPMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)wPMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)wPMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)wPMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)wPMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)wPMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)wPMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)wPMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)wPMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)wPMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)wPMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)wPMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)wPMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)wPMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)wPMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)wPMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)wPMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)wPMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)wPMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)wPMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)wPMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)wPMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)wPMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)wPMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)wPMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)wPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)wPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)wPMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)wPMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)wPMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)wPMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)wPMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)wPMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)wPMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)wPMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)wPMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)wPMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)wPMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)wPMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)wPMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)wPMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)wPMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)wPMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)wPMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)wPMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)wPMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)wPMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)wPMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)wPMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)wPMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)wPMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)wPMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)wPMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)wPMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)wPMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)wPMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)wPMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)wPMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)wPMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)wPMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)wPMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)wPMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)wPMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)wPMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)wPMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)wPMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)wPMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)wPMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)wPMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)wPMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)wPMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)wPMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)wPMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)wPMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)wPMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)wPMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)wPMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)wPMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)wPMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)wPMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)wPMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)wPMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)wPMU_REG_CORE_REG0_TARG_MASK (0x1FU)wPMU_REG_CORE_REG0_TARG_SHIFT (0U)wPMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)wPMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)wPMU_REG_CORE_REG0_ADJ_SHIFT (5U)wPMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)wPMU_REG_CORE_REG1_TARG_MASK (0x3E00U)wPMU_REG_CORE_REG1_TARG_SHIFT (9U)wPMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)wPMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)wPMU_REG_CORE_REG1_ADJ_SHIFT (14U)wPMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)wPMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)wPMU_REG_CORE_REG2_TARG_SHIFT (18U)wPMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)wPMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)wPMU_REG_CORE_REG2_ADJ_SHIFT (23U)wPMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)wPMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)wPMU_REG_CORE_RAMP_RATE_SHIFT (27U)xPMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)xPMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)xPMU_REG_CORE_FET_ODRIVE_SHIFT (29U)xPMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)xPMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)xPMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)xPMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)xPMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)xPMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)xPMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)xPMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)xPMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)xPMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)xPMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)xPMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)xPMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)xPMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)xPMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)xPMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)xPMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)xPMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)xPMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)xPMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)xPMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)xPMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)xPMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)xPMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)xPMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)xPMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)xPMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)xPMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)xPMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)xPMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)xPMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)xPMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)xPMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)xPMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)xPMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)xPMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)xPMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)xPMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)xPMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)xPMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)xPMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)xPMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)xPMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)xPMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)xPMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)xPMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)xPMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)xPMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)xPMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)xPMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)xPMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)xPMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)xPMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)xPMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)xPMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)xPMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)xPMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)xPMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)xPMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)xPMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)xPMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)xPMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)xPMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)xPMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)xPMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)xPMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)xPMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)xPMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)xPMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)xPMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)xPMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)xPMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)xPMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)xPMU_MISC0_REFTOP_PWD_MASK (0x1U)xPMU_MISC0_REFTOP_PWD_SHIFT (0U)xPMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)xPMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)xPMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)xPMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)xPMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)xPMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)xPMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)xPMU_MISC0_REFTOP_VBGUP_MASK (0x80U)xPMU_MISC0_REFTOP_VBGUP_SHIFT (7U)xPMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)xPMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)xPMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)xPMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)xPMU_MISC0_RTC_RINGOSC_EN_MASK (0x1000U)xPMU_MISC0_RTC_RINGOSC_EN_SHIFT (12U)xPMU_MISC0_RTC_RINGOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_RINGOSC_EN_SHIFT)) & PMU_MISC0_RTC_RINGOSC_EN_MASK)xPMU_MISC0_OSC_I_MASK (0x6000U)xPMU_MISC0_OSC_I_SHIFT (13U)xPMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)xPMU_MISC0_OSC_XTALOK_MASK (0x8000U)xPMU_MISC0_OSC_XTALOK_SHIFT (15U)xPMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)xPMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)xPMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)xPMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)xPMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)xPMU_MISC0_CLKGATE_CTRL_SHIFT (25U)xPMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)xPMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)xPMU_MISC0_CLKGATE_DELAY_SHIFT (26U)xPMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)xPMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)xPMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)xPMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)yPMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)yPMU_MISC0_XTAL_24M_PWD_SHIFT (30U)yPMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)yPMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)yPMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)yPMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)yPMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)yPMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)yPMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)yPMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)yPMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)yPMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)yPMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)yPMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)yPMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)yPMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)yPMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)yPMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)yPMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)yPMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)yPMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)yPMU_MISC0_SET_RTC_RINGOSC_EN_MASK (0x1000U)yPMU_MISC0_SET_RTC_RINGOSC_EN_SHIFT (12U)yPMU_MISC0_SET_RTC_RINGOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_RINGOSC_EN_SHIFT)) & PMU_MISC0_SET_RTC_RINGOSC_EN_MASK)yPMU_MISC0_SET_OSC_I_MASK (0x6000U)yPMU_MISC0_SET_OSC_I_SHIFT (13U)yPMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)yPMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)yPMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)yPMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)yPMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)yPMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)yPMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)yPMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)yPMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)yPMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)yPMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)yPMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)yPMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)yPMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)yPMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)yPMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)yPMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)yPMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)yPMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)yPMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)yPMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)yPMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)yPMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)yPMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)yPMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)yPMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)yPMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)yPMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)yPMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)yPMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)yPMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)yPMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)yPMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)yPMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)yPMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)yPMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)yPMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)yPMU_MISC0_CLR_RTC_RINGOSC_EN_MASK (0x1000U)yPMU_MISC0_CLR_RTC_RINGOSC_EN_SHIFT (12U)yPMU_MISC0_CLR_RTC_RINGOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_RINGOSC_EN_SHIFT)) & PMU_MISC0_CLR_RTC_RINGOSC_EN_MASK)yPMU_MISC0_CLR_OSC_I_MASK (0x6000U)yPMU_MISC0_CLR_OSC_I_SHIFT (13U)yPMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)yPMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)yPMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)yPMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)yPMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)yPMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)yPMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)yPMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)yPMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)yPMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)yPMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)yPMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)yPMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)yPMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)yPMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)yPMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)yPMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)yPMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)yPMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)yPMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)yPMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)yPMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)yPMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)yPMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)yPMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)yPMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)yPMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)yPMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)yPMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)yPMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)yPMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)yPMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)yPMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)yPMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)yPMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)yPMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)yPMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)yPMU_MISC0_TOG_RTC_RINGOSC_EN_MASK (0x1000U)yPMU_MISC0_TOG_RTC_RINGOSC_EN_SHIFT (12U)yPMU_MISC0_TOG_RTC_RINGOSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_RINGOSC_EN_SHIFT)) & PMU_MISC0_TOG_RTC_RINGOSC_EN_MASK)yPMU_MISC0_TOG_OSC_I_MASK (0x6000U)yPMU_MISC0_TOG_OSC_I_SHIFT (13U)yPMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)yPMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)yPMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)yPMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)yPMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)yPMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)zPMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)zPMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)zPMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)zPMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)zPMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)zPMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)zPMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)zPMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)zPMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)zPMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)zPMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)zPMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)zPMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)zPMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)zPMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)zPMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)zPMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)zPMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)zPMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)zPMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)zPMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)zPMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)zPMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)zPMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)zPMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)zPMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)zPMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)zPMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)zPMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)zPMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)zPMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)zPMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)zPMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)zPMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)zPMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)zPMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)zPMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)zPMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)zPMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)zPMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)zPMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)zPMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)zPMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)zPMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)zPMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)zPMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)zPMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)zPMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)zPMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)zPMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)zPMU_MISC1_IRQ_ANA_BO_SHIFT (30U)zPMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)zPMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)zPMU_MISC1_IRQ_DIG_BO_SHIFT (31U)zPMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)zPMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)zPMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)zPMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)zPMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)zPMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)zPMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)zPMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)zPMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)zPMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)zPMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)zPMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)zPMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)zPMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)zPMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)zPMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)zPMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)zPMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)zPMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)zPMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)zPMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)zPMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)zPMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)zPMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)zPMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)zPMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)zPMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)zPMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)zPMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)zPMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)zPMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)zPMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)zPMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)zPMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)zPMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)zPMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)zPMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)zPMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)zPMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)zPMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)zPMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)zPMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)zPMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)zPMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)zPMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)zPMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)zPMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)zPMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)zPMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)zPMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)zPMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)zPMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)zPMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)zPMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)zPMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)zPMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)zPMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)zPMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)zPMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)zPMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)zPMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)zPMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U){PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U){PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK){PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U){PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U){PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK){PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U){PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U){PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK){PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U){PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U){PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK){PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U){PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U){PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK){PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U){PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U){PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK){PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU){PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U){PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK){PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U){PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U){PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK){PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U){PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U){PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK){PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U){PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U){PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK){PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U){PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U){PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK){PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U){PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U){PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK){PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U){PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U){PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK){PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U){PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U){PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK){PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U){PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U){PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK){PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U){PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U){PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK){PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U){PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U){PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK){PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U){PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U){PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK){PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U){PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U){PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK){PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U){PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U){PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK){PMU_MISC2_REG0_BO_STATUS_MASK (0x8U){PMU_MISC2_REG0_BO_STATUS_SHIFT (3U){PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK){PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U){PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U){PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK){PMU_MISC2_PLL3_disable_MASK (0x80U){PMU_MISC2_PLL3_disable_SHIFT (7U){PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK){PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U){PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U){PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK){PMU_MISC2_REG1_BO_STATUS_MASK (0x800U){PMU_MISC2_REG1_BO_STATUS_SHIFT (11U){PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK){PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U){PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U){PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK){PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U){PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U){PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK){PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U){PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U){PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK){PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U){PMU_MISC2_REG2_BO_STATUS_SHIFT (19U){PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK){PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U){PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U){PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK){PMU_MISC2_REG2_OK_MASK (0x400000U){PMU_MISC2_REG2_OK_SHIFT (22U){PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK){PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U){PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U){PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK){PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U){PMU_MISC2_REG0_STEP_TIME_SHIFT (24U){PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK){PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U){PMU_MISC2_REG1_STEP_TIME_SHIFT (26U){PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK){PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U){PMU_MISC2_REG2_STEP_TIME_SHIFT (28U){PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK){PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U){PMU_MISC2_VIDEO_DIV_SHIFT (30U){PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK){PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U){PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U){PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK){PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U){PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U){PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK){PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U){PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U){PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)|PMU_MISC2_SET_PLL3_disable_MASK (0x80U)|PMU_MISC2_SET_PLL3_disable_SHIFT (7U)|PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)|PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)|PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)|PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)|PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)|PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)|PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)|PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)|PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)|PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)|PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)|PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)|PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)|PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)|PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)|PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)|PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)|PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)|PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)|PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)|PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)|PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)|PMU_MISC2_SET_REG2_OK_MASK (0x400000U)|PMU_MISC2_SET_REG2_OK_SHIFT (22U)|PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)|PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)|PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)|PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)|PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)|PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)|PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)|PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)|PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)|PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)|PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)|PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)|PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)|PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)|PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)|PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)|PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)|PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)|PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)|PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)|PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)|PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)|PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)|PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)|PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)|PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)|PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)|PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)|PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)|PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)|PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)|PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)|PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)|PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)|PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)|PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)|PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)|PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)|PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)|PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)|PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)|PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)|PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)|PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)|PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)|PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)|PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)|PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)|PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)|PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)|PMU_MISC2_CLR_REG2_OK_SHIFT (22U)|PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)|PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)|PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)|PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)|PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)|PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)|PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)|PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)|PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)|PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)|PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)|PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)|PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)|PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)|PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)|PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)|PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)|PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)|PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)|PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)|PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)|PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)|PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)|PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)|PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)|PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)|PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)|PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)|PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)|PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)|PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)|PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)|PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)|PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)|PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)|PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)|PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)|PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)|PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)|PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)|PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)|PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)|PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)}PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)}PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)}PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)}PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)}PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)}PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)}PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)}PMU_MISC2_TOG_REG2_OK_SHIFT (22U)}PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)}PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)}PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)}PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)}PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)}PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)}PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)}PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)}PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)}PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)}PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)}PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)}PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)}PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)}PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)}PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)}PMU_BASE (0x400D8000u)}PMU ((PMU_Type *)PMU_BASE)}PMU_BASE_ADDRS { PMU_BASE }}PMU_BASE_PTRS { PMU }~PWM_CNT_CNT_MASK (0xFFFFU)~PWM_CNT_CNT_SHIFT (0U)~PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)~PWM_CNT_COUNT (4U)~PWM_INIT_INIT_MASK (0xFFFFU)~PWM_INIT_INIT_SHIFT (0U)~PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)~PWM_INIT_COUNT (4U)~PWM_CTRL2_CLK_SEL_MASK (0x3U)~PWM_CTRL2_CLK_SEL_SHIFT (0U)~PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)~PWM_CTRL2_RELOAD_SEL_MASK (0x4U)~PWM_CTRL2_RELOAD_SEL_SHIFT (2U)~PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)~PWM_CTRL2_FORCE_SEL_MASK (0x38U)~PWM_CTRL2_FORCE_SEL_SHIFT (3U)~PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)~PWM_CTRL2_FORCE_MASK (0x40U)~PWM_CTRL2_FORCE_SHIFT (6U)~PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)~PWM_CTRL2_FRCEN_MASK (0x80U)~PWM_CTRL2_FRCEN_SHIFT (7U)~PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)~PWM_CTRL2_INIT_SEL_MASK (0x300U)~PWM_CTRL2_INIT_SEL_SHIFT (8U)~PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)~PWM_CTRL2_PWMX_INIT_MASK (0x400U)~PWM_CTRL2_PWMX_INIT_SHIFT (10U)~PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)~PWM_CTRL2_PWM45_INIT_MASK (0x800U)~PWM_CTRL2_PWM45_INIT_SHIFT (11U)~PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)~PWM_CTRL2_PWM23_INIT_MASK (0x1000U)~PWM_CTRL2_PWM23_INIT_SHIFT (12U)~PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)~PWM_CTRL2_INDEP_MASK (0x2000U)~PWM_CTRL2_INDEP_SHIFT (13U)~PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)~PWM_CTRL2_WAITEN_MASK (0x4000U)~PWM_CTRL2_WAITEN_SHIFT (14U)~PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)~PWM_CTRL2_DBGEN_MASK (0x8000U)~PWM_CTRL2_DBGEN_SHIFT (15U)~PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)~PWM_CTRL2_COUNT (4U)~PWM_CTRL_DBLEN_MASK (0x1U)~PWM_CTRL_DBLEN_SHIFT (0U)~PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)~PWM_CTRL_DBLX_MASK (0x2U)~PWM_CTRL_DBLX_SHIFT (1U)~PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)~PWM_CTRL_LDMOD_MASK (0x4U)~PWM_CTRL_LDMOD_SHIFT (2U)~PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)~PWM_CTRL_SPLIT_MASK (0x8U)~PWM_CTRL_SPLIT_SHIFT (3U)~PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)~PWM_CTRL_PRSC_MASK (0x70U)~PWM_CTRL_PRSC_SHIFT (4U)~PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)~PWM_CTRL_COMPMODE_MASK (0x80U)~PWM_CTRL_COMPMODE_SHIFT (7U)~PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)~PWM_CTRL_DT_MASK (0x300U)~PWM_CTRL_DT_SHIFT (8U)~PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)~PWM_CTRL_FULL_MASK (0x400U)~PWM_CTRL_FULL_SHIFT (10U)~PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)~PWM_CTRL_HALF_MASK (0x800U)~PWM_CTRL_HALF_SHIFT (11U)~PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)~PWM_CTRL_LDFQ_MASK (0xF000U)~PWM_CTRL_LDFQ_SHIFT (12U)~PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)~PWM_CTRL_COUNT (4U)~PWM_VAL0_VAL0_MASK (0xFFFFU)~PWM_VAL0_VAL0_SHIFT (0U)~PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)~PWM_VAL0_COUNT (4U)~PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)~PWM_FRACVAL1_FRACVAL1_SHIFT (11U)~PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)~PWM_FRACVAL1_COUNT (4U)~PWM_VAL1_VAL1_MASK (0xFFFFU)~PWM_VAL1_VAL1_SHIFT (0U)~PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)~PWM_VAL1_COUNT (4U)PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)PWM_FRACVAL2_FRACVAL2_SHIFT (11U)PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)PWM_FRACVAL2_COUNT (4U)PWM_VAL2_VAL2_MASK (0xFFFFU)PWM_VAL2_VAL2_SHIFT (0U)PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)PWM_VAL2_COUNT (4U)PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)PWM_FRACVAL3_FRACVAL3_SHIFT (11U)PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)PWM_FRACVAL3_COUNT (4U)PWM_VAL3_VAL3_MASK (0xFFFFU)PWM_VAL3_VAL3_SHIFT (0U)PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)PWM_VAL3_COUNT (4U)PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)PWM_FRACVAL4_FRACVAL4_SHIFT (11U)PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)PWM_FRACVAL4_COUNT (4U)PWM_VAL4_VAL4_MASK (0xFFFFU)PWM_VAL4_VAL4_SHIFT (0U)PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)PWM_VAL4_COUNT (4U)PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)PWM_FRACVAL5_FRACVAL5_SHIFT (11U)PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)PWM_FRACVAL5_COUNT (4U)PWM_VAL5_VAL5_MASK (0xFFFFU)PWM_VAL5_VAL5_SHIFT (0U)PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)PWM_VAL5_COUNT (4U)PWM_FRCTRL_FRAC1_EN_MASK (0x2U)PWM_FRCTRL_FRAC1_EN_SHIFT (1U)PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)PWM_FRCTRL_FRAC23_EN_MASK (0x4U)PWM_FRCTRL_FRAC23_EN_SHIFT (2U)PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)PWM_FRCTRL_FRAC45_EN_MASK (0x10U)PWM_FRCTRL_FRAC45_EN_SHIFT (4U)PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)PWM_FRCTRL_FRAC_PU_MASK (0x100U)PWM_FRCTRL_FRAC_PU_SHIFT (8U)PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)PWM_FRCTRL_TEST_MASK (0x8000U)PWM_FRCTRL_TEST_SHIFT (15U)PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)PWM_FRCTRL_COUNT (4U)PWM_OCTRL_PWMXFS_MASK (0x3U)PWM_OCTRL_PWMXFS_SHIFT (0U)PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)PWM_OCTRL_PWMBFS_MASK (0xCU)PWM_OCTRL_PWMBFS_SHIFT (2U)PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)PWM_OCTRL_PWMAFS_MASK (0x30U)PWM_OCTRL_PWMAFS_SHIFT (4U)PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)PWM_OCTRL_POLX_MASK (0x100U)PWM_OCTRL_POLX_SHIFT (8U)PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)PWM_OCTRL_POLB_MASK (0x200U)PWM_OCTRL_POLB_SHIFT (9U)PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)PWM_OCTRL_POLA_MASK (0x400U)PWM_OCTRL_POLA_SHIFT (10U)PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)PWM_OCTRL_PWMX_IN_MASK (0x2000U)PWM_OCTRL_PWMX_IN_SHIFT (13U)PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)PWM_OCTRL_PWMB_IN_MASK (0x4000U)PWM_OCTRL_PWMB_IN_SHIFT (14U)PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)PWM_OCTRL_PWMA_IN_MASK (0x8000U)PWM_OCTRL_PWMA_IN_SHIFT (15U)PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)PWM_OCTRL_COUNT (4U)PWM_STS_CMPF_MASK (0x3FU)PWM_STS_CMPF_SHIFT (0U)PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)PWM_STS_CFX0_MASK (0x40U)PWM_STS_CFX0_SHIFT (6U)PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)PWM_STS_CFX1_MASK (0x80U)PWM_STS_CFX1_SHIFT (7U)PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)PWM_STS_CFB0_MASK (0x100U)PWM_STS_CFB0_SHIFT (8U)PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)PWM_STS_CFB1_MASK (0x200U)PWM_STS_CFB1_SHIFT (9U)PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)PWM_STS_CFA0_MASK (0x400U)PWM_STS_CFA0_SHIFT (10U)PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)PWM_STS_CFA1_MASK (0x800U)PWM_STS_CFA1_SHIFT (11U)PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)PWM_STS_RF_MASK (0x1000U)PWM_STS_RF_SHIFT (12U)PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)PWM_STS_REF_MASK (0x2000U)PWM_STS_REF_SHIFT (13U)PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)PWM_STS_RUF_MASK (0x4000U)PWM_STS_RUF_SHIFT (14U)PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)PWM_STS_COUNT (4U)PWM_INTEN_CMPIE_MASK (0x3FU)PWM_INTEN_CMPIE_SHIFT (0U)PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)PWM_INTEN_CX0IE_MASK (0x40U)PWM_INTEN_CX0IE_SHIFT (6U)PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)PWM_INTEN_CX1IE_MASK (0x80U)PWM_INTEN_CX1IE_SHIFT (7U)PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)PWM_INTEN_CB0IE_MASK (0x100U)PWM_INTEN_CB0IE_SHIFT (8U)PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)PWM_INTEN_CB1IE_MASK (0x200U)PWM_INTEN_CB1IE_SHIFT (9U)PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)PWM_INTEN_CA0IE_MASK (0x400U)PWM_INTEN_CA0IE_SHIFT (10U)PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)PWM_INTEN_CA1IE_MASK (0x800U)€PWM_INTEN_CA1IE_SHIFT (11U)ÀPWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)ĀPWM_INTEN_RIE_MASK (0x1000U)ŀPWM_INTEN_RIE_SHIFT (12U)ƀPWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)ǀPWM_INTEN_REIE_MASK (0x2000U)ȀPWM_INTEN_REIE_SHIFT (13U)ɀPWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)̀PWM_INTEN_COUNT (4U)рPWM_DMAEN_CX0DE_MASK (0x1U)ҀPWM_DMAEN_CX0DE_SHIFT (0U)ӀPWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)ԀPWM_DMAEN_CX1DE_MASK (0x2U)ՀPWM_DMAEN_CX1DE_SHIFT (1U)րPWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)׀PWM_DMAEN_CB0DE_MASK (0x4U)؀PWM_DMAEN_CB0DE_SHIFT (2U)ـPWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)ڀPWM_DMAEN_CB1DE_MASK (0x8U)ۀPWM_DMAEN_CB1DE_SHIFT (3U)܀PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)݀PWM_DMAEN_CA0DE_MASK (0x10U)ހPWM_DMAEN_CA0DE_SHIFT (4U)߀PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)PWM_DMAEN_CA1DE_MASK (0x20U)PWM_DMAEN_CA1DE_SHIFT (5U)PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)PWM_DMAEN_CAPTDE_MASK (0xC0U)PWM_DMAEN_CAPTDE_SHIFT (6U)PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)PWM_DMAEN_FAND_MASK (0x100U)PWM_DMAEN_FAND_SHIFT (8U)PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)PWM_DMAEN_VALDE_MASK (0x200U)PWM_DMAEN_VALDE_SHIFT (9U)PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)PWM_DMAEN_COUNT (4U)PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)PWM_TCTRL_TRGFRQ_MASK (0x1000U)PWM_TCTRL_TRGFRQ_SHIFT (12U)PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)PWM_TCTRL_PWBOT1_MASK (0x4000U)PWM_TCTRL_PWBOT1_SHIFT (14U)PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)PWM_TCTRL_PWAOT0_MASK (0x8000U)PWM_TCTRL_PWAOT0_SHIFT (15U)PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)PWM_TCTRL_COUNT (4U)PWM_DISMAP_DIS0A_MASK (0xFU)PWM_DISMAP_DIS0A_SHIFT (0U)PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)PWM_DISMAP_DIS1A_MASK (0xFU)PWM_DISMAP_DIS1A_SHIFT (0U)PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)PWM_DISMAP_DIS0B_MASK (0xF0U)PWM_DISMAP_DIS0B_SHIFT (4U)PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)PWM_DISMAP_DIS1B_MASK (0xF0U)PWM_DISMAP_DIS1B_SHIFT (4U)PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)PWM_DISMAP_DIS1X_MASK (0xF00U)PWM_DISMAP_DIS1X_SHIFT (8U)PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)PWM_DISMAP_DIS0X_MASK (0xF00U)PWM_DISMAP_DIS0X_SHIFT (8U)PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)PWM_DISMAP_COUNT (4U)PWM_DISMAP_COUNT2 (2U)PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)PWM_DTCNT0_DTCNT0_SHIFT (0U)PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)PWM_DTCNT0_COUNT (4U)PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)PWM_DTCNT1_DTCNT1_SHIFT (0U)PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)PWM_DTCNT1_COUNT (4U)PWM_CAPTCTRLA_ARMA_MASK (0x1U)PWM_CAPTCTRLA_ARMA_SHIFT (0U)PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)PWM_CAPTCTRLA_EDGA0_MASK (0xCU)PWM_CAPTCTRLA_EDGA0_SHIFT (2U)PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)PWM_CAPTCTRLA_EDGA1_MASK (0x30U)PWM_CAPTCTRLA_EDGA1_SHIFT (4U)PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)ÁPWM_CAPTCTRLA_INP_SELA_SHIFT (6U)āPWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)ŁPWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)ƁPWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)ǁPWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)ȁPWM_CAPTCTRLA_CFAWM_MASK (0x300U)ɁPWM_CAPTCTRLA_CFAWM_SHIFT (8U)ʁPWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)ˁPWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)́PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)́PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)΁PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)ρPWM_CAPTCTRLA_CA1CNT_SHIFT (13U)ЁPWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)ԁPWM_CAPTCTRLA_COUNT (4U)؁PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)فPWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)ځPWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)ہPWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)܁PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)݁PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)PWM_CAPTCOMPA_COUNT (4U)PWM_CAPTCTRLB_ARMB_MASK (0x1U)PWM_CAPTCTRLB_ARMB_SHIFT (0U)PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)PWM_CAPTCTRLB_EDGB0_MASK (0xCU)PWM_CAPTCTRLB_EDGB0_SHIFT (2U)PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)PWM_CAPTCTRLB_EDGB1_MASK (0x30U)PWM_CAPTCTRLB_EDGB1_SHIFT (4U)PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)PWM_CAPTCTRLB_CFBWM_MASK (0x300U)PWM_CAPTCTRLB_CFBWM_SHIFT (8U)PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)PWM_CAPTCTRLB_COUNT (4U)PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)PWM_CAPTCOMPB_COUNT (4U)PWM_CAPTCTRLX_ARMX_MASK (0x1U)PWM_CAPTCTRLX_ARMX_SHIFT (0U)PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)PWM_CAPTCTRLX_EDGX0_MASK (0xCU)PWM_CAPTCTRLX_EDGX0_SHIFT (2U)PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)PWM_CAPTCTRLX_EDGX1_MASK (0x30U)PWM_CAPTCTRLX_EDGX1_SHIFT (4U)PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)PWM_CAPTCTRLX_CFXWM_MASK (0x300U)PWM_CAPTCTRLX_CFXWM_SHIFT (8U)PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)PWM_CAPTCTRLX_COUNT (4U)PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)PWM_CAPTCOMPX_COUNT (4U)ÂPWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)ĂPWM_CVAL0_CAPTVAL0_SHIFT (0U)łPWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)ɂPWM_CVAL0_COUNT (4U)͂PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)΂PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)ςPWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)ӂPWM_CVAL0CYC_COUNT (4U)ׂPWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)؂PWM_CVAL1_CAPTVAL1_SHIFT (0U)قPWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)݂PWM_CVAL1_COUNT (4U)PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)PWM_CVAL1CYC_COUNT (4U)PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)PWM_CVAL2_CAPTVAL2_SHIFT (0U)PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)PWM_CVAL2_COUNT (4U)PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)PWM_CVAL2CYC_COUNT (4U)PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)PWM_CVAL3_CAPTVAL3_SHIFT (0U)PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)PWM_CVAL3_COUNT (4U)PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)PWM_CVAL3CYC_COUNT (4U)PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)PWM_CVAL4_CAPTVAL4_SHIFT (0U)PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)PWM_CVAL4_COUNT (4U)PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)PWM_CVAL4CYC_COUNT (4U)PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)PWM_CVAL5_CAPTVAL5_SHIFT (0U)PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)PWM_CVAL5_COUNT (4U)PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)PWM_CVAL5CYC_COUNT (4U)PWM_OUTEN_PWMX_EN_MASK (0xFU)PWM_OUTEN_PWMX_EN_SHIFT (0U)PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)PWM_OUTEN_PWMB_EN_MASK (0xF0U)PWM_OUTEN_PWMB_EN_SHIFT (4U)PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)PWM_OUTEN_PWMA_EN_MASK (0xF00U)ƒPWM_OUTEN_PWMA_EN_SHIFT (8U)ÃPWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)ȃPWM_MASK_MASKX_MASK (0xFU)ɃPWM_MASK_MASKX_SHIFT (0U)ʃPWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)˃PWM_MASK_MASKB_MASK (0xF0U)̃PWM_MASK_MASKB_SHIFT (4U)̓PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)΃PWM_MASK_MASKA_MASK (0xF00U)σPWM_MASK_MASKA_SHIFT (8U)ЃPWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)уPWM_MASK_UPDATE_MASK_MASK (0xF000U)҃PWM_MASK_UPDATE_MASK_SHIFT (12U)ӃPWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)؃PWM_SWCOUT_SM0OUT45_MASK (0x1U)كPWM_SWCOUT_SM0OUT45_SHIFT (0U)ڃPWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)ۃPWM_SWCOUT_SM0OUT23_MASK (0x2U)܃PWM_SWCOUT_SM0OUT23_SHIFT (1U)݃PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)ރPWM_SWCOUT_SM1OUT45_MASK (0x4U)߃PWM_SWCOUT_SM1OUT45_SHIFT (2U)PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)PWM_SWCOUT_SM1OUT23_MASK (0x8U)PWM_SWCOUT_SM1OUT23_SHIFT (3U)PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)PWM_SWCOUT_SM2OUT45_MASK (0x10U)PWM_SWCOUT_SM2OUT45_SHIFT (4U)PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)PWM_SWCOUT_SM2OUT23_MASK (0x20U)PWM_SWCOUT_SM2OUT23_SHIFT (5U)PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)PWM_SWCOUT_SM3OUT45_MASK (0x40U)PWM_SWCOUT_SM3OUT45_SHIFT (6U)PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)PWM_SWCOUT_SM3OUT23_MASK (0x80U)PWM_SWCOUT_SM3OUT23_SHIFT (7U)PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)PWM_MCTRL_LDOK_MASK (0xFU)PWM_MCTRL_LDOK_SHIFT (0U)PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)PWM_MCTRL_CLDOK_MASK (0xF0U)PWM_MCTRL_CLDOK_SHIFT (4U)PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)PWM_MCTRL_RUN_MASK (0xF00U)PWM_MCTRL_RUN_SHIFT (8U)PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)PWM_MCTRL_IPOL_MASK (0xF000U)PWM_MCTRL_IPOL_SHIFT (12U)PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)PWM_MCTRL2_MONPLL_MASK (0x3U)PWM_MCTRL2_MONPLL_SHIFT (0U)PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)PWM_FCTRL_FIE_MASK (0xFU)PWM_FCTRL_FIE_SHIFT (0U)PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)PWM_FCTRL_FSAFE_MASK (0xF0U)PWM_FCTRL_FSAFE_SHIFT (4U)PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)PWM_FCTRL_FAUTO_MASK (0xF00U)PWM_FCTRL_FAUTO_SHIFT (8U)PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)PWM_FCTRL_FLVL_MASK (0xF000U)PWM_FCTRL_FLVL_SHIFT (12U)PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)PWM_FSTS_FFLAG_MASK (0xFU)PWM_FSTS_FFLAG_SHIFT (0U)PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)PWM_FSTS_FFULL_MASK (0xF0U)PWM_FSTS_FFULL_SHIFT (4U)PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)PWM_FSTS_FFPIN_MASK (0xF00U)PWM_FSTS_FFPIN_SHIFT (8U)PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)PWM_FSTS_FHALF_MASK (0xF000U)PWM_FSTS_FHALF_SHIFT (12U)„PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)DŽPWM_FFILT_FILT_PER_MASK (0xFFU)ȄPWM_FFILT_FILT_PER_SHIFT (0U)ɄPWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)ʄPWM_FFILT_FILT_CNT_MASK (0x700U)˄PWM_FFILT_FILT_CNT_SHIFT (8U)̄PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)̈́PWM_FFILT_GSTR_MASK (0x8000U)΄PWM_FFILT_GSTR_SHIFT (15U)τPWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)ԄPWM_FTST_FTEST_MASK (0x1U)ՄPWM_FTST_FTEST_SHIFT (0U)քPWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)ۄPWM_FCTRL2_NOCOMB_MASK (0xFU)܄PWM_FCTRL2_NOCOMB_SHIFT (0U)݄PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)PWM1_BASE (0x403DC000u)PWM1 ((PWM_Type *)PWM1_BASE)PWM2_BASE (0x403E0000u)PWM2 ((PWM_Type *)PWM2_BASE)PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE }PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2 }PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn }PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn }ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)ROMC_ROMPATCHD_DATAX_SHIFT (0U)ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)ROMC_ROMPATCHD_COUNT (8U)ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)ROMC_ROMPATCHA_THUMBX_MASK (0x1U)ROMC_ROMPATCHA_THUMBX_SHIFT (0U)ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)ROMC_ROMPATCHA_ADDRX_SHIFT (1U)ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)ÅROMC_ROMPATCHA_COUNT (16U)DžROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)ȅROMC_ROMPATCHSR_SOURCE_SHIFT (0U)ɅROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)ʅROMC_ROMPATCHSR_SW_MASK (0x20000U)˅ROMC_ROMPATCHSR_SW_SHIFT (17U)̅ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)ׅROMC_BASE (0x40180000u)مROMC ((ROMC_Type *)ROMC_BASE)ۅROMC_BASE_ADDRS { ROMC_BASE }݅ROMC_BASE_PTRS { ROMC }RTWDOG_CS_STOP_MASK (0x1U)RTWDOG_CS_STOP_SHIFT (0U)RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)RTWDOG_CS_WAIT_MASK (0x2U)RTWDOG_CS_WAIT_SHIFT (1U)RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)RTWDOG_CS_DBG_MASK (0x4U)RTWDOG_CS_DBG_SHIFT (2U)RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)RTWDOG_CS_TST_MASK (0x18U)RTWDOG_CS_TST_SHIFT (3U)RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)RTWDOG_CS_UPDATE_MASK (0x20U)RTWDOG_CS_UPDATE_SHIFT (5U)RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)RTWDOG_CS_INT_MASK (0x40U)RTWDOG_CS_INT_SHIFT (6U)RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)RTWDOG_CS_EN_MASK (0x80U)RTWDOG_CS_EN_SHIFT (7U)RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)RTWDOG_CS_CLK_MASK (0x300U)RTWDOG_CS_CLK_SHIFT (8U)RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)RTWDOG_CS_RCS_MASK (0x400U)RTWDOG_CS_RCS_SHIFT (10U)RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)RTWDOG_CS_ULK_MASK (0x800U)RTWDOG_CS_ULK_SHIFT (11U)RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)RTWDOG_CS_PRES_MASK (0x1000U)RTWDOG_CS_PRES_SHIFT (12U)RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)RTWDOG_CS_CMD32EN_MASK (0x2000U)RTWDOG_CS_CMD32EN_SHIFT (13U)RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)RTWDOG_CS_FLG_MASK (0x4000U)RTWDOG_CS_FLG_SHIFT (14U)RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)RTWDOG_CS_WIN_MASK (0x8000U)RTWDOG_CS_WIN_SHIFT (15U)RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)RTWDOG_CNT_CNTLOW_MASK (0xFFU)RTWDOG_CNT_CNTLOW_SHIFT (0U)RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)RTWDOG_CNT_CNTHIGH_SHIFT (8U)RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)†RTWDOG_WIN_WINLOW_MASK (0xFFU)ÆRTWDOG_WIN_WINLOW_SHIFT (0U)ĆRTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)ņRTWDOG_WIN_WINHIGH_MASK (0xFF00U)ƆRTWDOG_WIN_WINHIGH_SHIFT (8U)džRTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)҆RTWDOG_BASE (0x400BC000u)ԆRTWDOG ((RTWDOG_Type *)RTWDOG_BASE)ֆRTWDOG_BASE_ADDRS { RTWDOG_BASE }؆RTWDOG_BASE_PTRS { RTWDOG }چRTWDOG_IRQS { RTWDOG_IRQn }܆RTWDOG_UPDATE_KEY (0xD928C520U)݆RTWDOG_REFRESH_KEY (0xB480A602U)SEMC_MCR_SWRST_MASK (0x1U)SEMC_MCR_SWRST_SHIFT (0U)SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)SEMC_MCR_MDIS_MASK (0x2U)SEMC_MCR_MDIS_SHIFT (1U)SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)SEMC_MCR_DQSMD_MASK (0x4U)SEMC_MCR_DQSMD_SHIFT (2U)SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)SEMC_MCR_WPOL0_MASK (0x40U)SEMC_MCR_WPOL0_SHIFT (6U)SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)SEMC_MCR_WPOL1_MASK (0x80U)SEMC_MCR_WPOL1_SHIFT (7U)SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)SEMC_MCR_CTO_MASK (0xFF0000U)SEMC_MCR_CTO_SHIFT (16U)SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)‡SEMC_MCR_BTO_MASK (0x1F000000U)ÇSEMC_MCR_BTO_SHIFT (24U)ćSEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)ɇSEMC_IOCR_MUX_A8_MASK (0x7U)ʇSEMC_IOCR_MUX_A8_SHIFT (0U)ˇSEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)̇SEMC_IOCR_MUX_CSX0_MASK (0x38U)͇SEMC_IOCR_MUX_CSX0_SHIFT (3U)·SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)χSEMC_IOCR_MUX_CSX1_MASK (0x1C0U)ЇSEMC_IOCR_MUX_CSX1_SHIFT (6U)чSEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)҇SEMC_IOCR_MUX_CSX2_MASK (0xE00U)ӇSEMC_IOCR_MUX_CSX2_SHIFT (9U)ԇSEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)ՇSEMC_IOCR_MUX_CSX3_MASK (0x7000U)ևSEMC_IOCR_MUX_CSX3_SHIFT (12U)ׇSEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)؇SEMC_IOCR_MUX_RDY_MASK (0x38000U)هSEMC_IOCR_MUX_RDY_SHIFT (15U)ڇSEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)߇SEMC_BMCR0_WQOS_MASK (0xFU)SEMC_BMCR0_WQOS_SHIFT (0U)SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)SEMC_BMCR0_WAGE_MASK (0xF0U)SEMC_BMCR0_WAGE_SHIFT (4U)SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)SEMC_BMCR0_WSH_MASK (0xFF00U)SEMC_BMCR0_WSH_SHIFT (8U)SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)SEMC_BMCR0_WRWS_MASK (0xFF0000U)SEMC_BMCR0_WRWS_SHIFT (16U)SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)SEMC_BMCR1_WQOS_MASK (0xFU)SEMC_BMCR1_WQOS_SHIFT (0U)SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)SEMC_BMCR1_WAGE_MASK (0xF0U)SEMC_BMCR1_WAGE_SHIFT (4U)SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)SEMC_BMCR1_WPH_MASK (0xFF00U)SEMC_BMCR1_WPH_SHIFT (8U)SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)SEMC_BMCR1_WRWS_MASK (0xFF0000U)SEMC_BMCR1_WRWS_SHIFT (16U)SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)SEMC_BMCR1_WBR_MASK (0xFF000000U)SEMC_BMCR1_WBR_SHIFT (24U)SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)SEMC_BR_VLD_MASK (0x1U)SEMC_BR_VLD_SHIFT (0U)SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)SEMC_BR_MS_MASK (0x3EU)SEMC_BR_MS_SHIFT (1U)SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)SEMC_BR_BA_MASK (0xFFFFF000U)SEMC_BR_BA_SHIFT (12U)SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)SEMC_BR_COUNT (9U)SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)SEMC_INTEN_IPCMDERREN_MASK (0x2U)SEMC_INTEN_IPCMDERREN_SHIFT (1U)SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)SEMC_INTEN_AXICMDERREN_MASK (0x4U)SEMC_INTEN_AXICMDERREN_SHIFT (2U)SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)SEMC_INTEN_AXIBUSERREN_MASK (0x8U)SEMC_INTEN_AXIBUSERREN_SHIFT (3U)SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)SEMC_INTEN_NDNOPENDEN_MASK (0x20U)SEMC_INTEN_NDNOPENDEN_SHIFT (5U)SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)SEMC_INTR_IPCMDDONE_MASK (0x1U)SEMC_INTR_IPCMDDONE_SHIFT (0U)SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)SEMC_INTR_IPCMDERR_MASK (0x2U)SEMC_INTR_IPCMDERR_SHIFT (1U)SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)SEMC_INTR_AXICMDERR_MASK (0x4U)SEMC_INTR_AXICMDERR_SHIFT (2U)SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)SEMC_INTR_AXIBUSERR_MASK (0x8U)SEMC_INTR_AXIBUSERR_SHIFT (3U)SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)SEMC_INTR_NDPAGEEND_MASK (0x10U)SEMC_INTR_NDPAGEEND_SHIFT (4U)SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)SEMC_INTR_NDNOPEND_MASK (0x20U)SEMC_INTR_NDNOPEND_SHIFT (5U)SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)SEMC_SDRAMCR0_PS_MASK (0x1U)SEMC_SDRAMCR0_PS_SHIFT (0U)SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)SEMC_SDRAMCR0_BL_MASK (0x70U)ˆSEMC_SDRAMCR0_BL_SHIFT (4U)ÈSEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)ĈSEMC_SDRAMCR0_COL_MASK (0x300U)ňSEMC_SDRAMCR0_COL_SHIFT (8U)ƈSEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)LjSEMC_SDRAMCR0_CL_MASK (0xC00U)ȈSEMC_SDRAMCR0_CL_SHIFT (10U)ɈSEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)ΈSEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)ψSEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)ЈSEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)шSEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)҈SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)ӈSEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)ԈSEMC_SDRAMCR1_RFRC_MASK (0x1F00U)ՈSEMC_SDRAMCR1_RFRC_SHIFT (8U)ֈSEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)׈SEMC_SDRAMCR1_WRC_MASK (0xE000U)؈SEMC_SDRAMCR1_WRC_SHIFT (13U)وSEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)ڈSEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)ۈSEMC_SDRAMCR1_CKEOFF_SHIFT (16U)܈SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)݈SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)ވSEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)߈SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)SEMC_SDRAMCR2_SRRC_MASK (0xFFU)SEMC_SDRAMCR2_SRRC_SHIFT (0U)SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)SEMC_SDRAMCR2_REF2REF_SHIFT (8U)SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)SEMC_SDRAMCR2_ITO_SHIFT (24U)SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)SEMC_SDRAMCR3_REN_MASK (0x1U)SEMC_SDRAMCR3_REN_SHIFT (0U)SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)SEMC_SDRAMCR3_REBL_MASK (0xEU)SEMC_SDRAMCR3_REBL_SHIFT (1U)SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)SEMC_SDRAMCR3_RT_MASK (0xFF0000U)SEMC_SDRAMCR3_RT_SHIFT (16U)SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)SEMC_SDRAMCR3_UT_MASK (0xFF000000U)SEMC_SDRAMCR3_UT_SHIFT (24U)SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)SEMC_NANDCR0_PS_MASK (0x1U)SEMC_NANDCR0_PS_SHIFT (0U)SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)SEMC_NANDCR0_BL_MASK (0x70U)SEMC_NANDCR0_BL_SHIFT (4U)SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)SEMC_NANDCR0_EDO_MASK (0x80U)SEMC_NANDCR0_EDO_SHIFT (7U)SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)SEMC_NANDCR0_COL_MASK (0x700U)SEMC_NANDCR0_COL_SHIFT (8U)SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)SEMC_NANDCR1_CES_MASK (0xFU)SEMC_NANDCR1_CES_SHIFT (0U)SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)SEMC_NANDCR1_CEH_MASK (0xF0U)SEMC_NANDCR1_CEH_SHIFT (4U)SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)SEMC_NANDCR1_WEL_MASK (0xF00U)SEMC_NANDCR1_WEL_SHIFT (8U)SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)SEMC_NANDCR1_WEH_MASK (0xF000U)SEMC_NANDCR1_WEH_SHIFT (12U)SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)SEMC_NANDCR1_REL_MASK (0xF0000U)SEMC_NANDCR1_REL_SHIFT (16U)SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)SEMC_NANDCR1_REH_MASK (0xF00000U)SEMC_NANDCR1_REH_SHIFT (20U)SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)SEMC_NANDCR1_TA_MASK (0xF000000U)SEMC_NANDCR1_TA_SHIFT (24U)SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)SEMC_NANDCR1_CEITV_MASK (0xF0000000U)SEMC_NANDCR1_CEITV_SHIFT (28U)SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)SEMC_NANDCR2_TWHR_MASK (0x3FU)SEMC_NANDCR2_TWHR_SHIFT (0U)SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)SEMC_NANDCR2_TRHW_MASK (0xFC0U)SEMC_NANDCR2_TRHW_SHIFT (6U)SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)SEMC_NANDCR2_TADL_MASK (0x3F000U)SEMC_NANDCR2_TADL_SHIFT (12U)SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)SEMC_NANDCR2_TRR_MASK (0xFC0000U)SEMC_NANDCR2_TRR_SHIFT (18U)SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)SEMC_NANDCR2_TWB_MASK (0x3F000000U)SEMC_NANDCR2_TWB_SHIFT (24U)SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)ƉSEMC_NANDCR3_NDOPT1_MASK (0x1U)ljSEMC_NANDCR3_NDOPT1_SHIFT (0U)ȉSEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)ɉSEMC_NANDCR3_NDOPT2_MASK (0x2U)ʉSEMC_NANDCR3_NDOPT2_SHIFT (1U)ˉSEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)̉SEMC_NANDCR3_NDOPT3_MASK (0x4U)͉SEMC_NANDCR3_NDOPT3_SHIFT (2U)ΉSEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)ӉSEMC_NORCR0_PS_MASK (0x1U)ԉSEMC_NORCR0_PS_SHIFT (0U)ՉSEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)։SEMC_NORCR0_BL_MASK (0x70U)׉SEMC_NORCR0_BL_SHIFT (4U)؉SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)ىSEMC_NORCR0_AM_MASK (0x300U)ډSEMC_NORCR0_AM_SHIFT (8U)ۉSEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)܉SEMC_NORCR0_ADVP_MASK (0x400U)݉SEMC_NORCR0_ADVP_SHIFT (10U)މSEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)߉SEMC_NORCR0_COL_MASK (0xF000U)SEMC_NORCR0_COL_SHIFT (12U)SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)SEMC_NORCR1_CES_MASK (0xFU)SEMC_NORCR1_CES_SHIFT (0U)SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)SEMC_NORCR1_CEH_MASK (0xF0U)SEMC_NORCR1_CEH_SHIFT (4U)SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)SEMC_NORCR1_AS_MASK (0xF00U)SEMC_NORCR1_AS_SHIFT (8U)SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)SEMC_NORCR1_AH_MASK (0xF000U)SEMC_NORCR1_AH_SHIFT (12U)SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)SEMC_NORCR1_WEL_MASK (0xF0000U)SEMC_NORCR1_WEL_SHIFT (16U)SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)SEMC_NORCR1_WEH_MASK (0xF00000U)SEMC_NORCR1_WEH_SHIFT (20U)SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)SEMC_NORCR1_REL_MASK (0xF000000U)SEMC_NORCR1_REL_SHIFT (24U)SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)SEMC_NORCR1_REH_MASK (0xF0000000U)SEMC_NORCR1_REH_SHIFT (28U)SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)SEMC_NORCR2_WDS_MASK (0xFU)SEMC_NORCR2_WDS_SHIFT (0U)SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)SEMC_NORCR2_WDH_MASK (0xF0U)SEMC_NORCR2_WDH_SHIFT (4U)SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)SEMC_NORCR2_TA_MASK (0xF00U)SEMC_NORCR2_TA_SHIFT (8U)SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)SEMC_NORCR2_AWDH_MASK (0xF000U)SEMC_NORCR2_AWDH_SHIFT (12U)SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)SEMC_NORCR2_LC_MASK (0xF0000U)SEMC_NORCR2_LC_SHIFT (16U)SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)SEMC_NORCR2_RD_MASK (0xF00000U)SEMC_NORCR2_RD_SHIFT (20U)SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)SEMC_NORCR2_CEITV_MASK (0xF000000U)SEMC_NORCR2_CEITV_SHIFT (24U)SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)SEMC_SRAMCR0_PS_MASK (0x1U)SEMC_SRAMCR0_PS_SHIFT (0U)SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)SEMC_SRAMCR0_BL_MASK (0x70U)SEMC_SRAMCR0_BL_SHIFT (4U)SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)SEMC_SRAMCR0_AM_MASK (0x300U)SEMC_SRAMCR0_AM_SHIFT (8U)SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)SEMC_SRAMCR0_ADVP_MASK (0x400U)SEMC_SRAMCR0_ADVP_SHIFT (10U)SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)SEMC_SRAMCR0_COL_MASK (0xF000U)SEMC_SRAMCR0_COL_SHIFT (12U)SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)SEMC_SRAMCR1_CES_MASK (0xFU)SEMC_SRAMCR1_CES_SHIFT (0U)SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)SEMC_SRAMCR1_CEH_MASK (0xF0U)SEMC_SRAMCR1_CEH_SHIFT (4U)SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)SEMC_SRAMCR1_AS_MASK (0xF00U)SEMC_SRAMCR1_AS_SHIFT (8U)SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)SEMC_SRAMCR1_AH_MASK (0xF000U)SEMC_SRAMCR1_AH_SHIFT (12U)SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)SEMC_SRAMCR1_WEL_MASK (0xF0000U)SEMC_SRAMCR1_WEL_SHIFT (16U)SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)SEMC_SRAMCR1_WEH_MASK (0xF00000U)SEMC_SRAMCR1_WEH_SHIFT (20U)SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)SEMC_SRAMCR1_REL_MASK (0xF000000U)SEMC_SRAMCR1_REL_SHIFT (24U)ŠSEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)ÊSEMC_SRAMCR1_REH_MASK (0xF0000000U)ĊSEMC_SRAMCR1_REH_SHIFT (28U)ŊSEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)ʊSEMC_SRAMCR2_WDS_MASK (0xFU)ˊSEMC_SRAMCR2_WDS_SHIFT (0U)̊SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)͊SEMC_SRAMCR2_WDH_MASK (0xF0U)ΊSEMC_SRAMCR2_WDH_SHIFT (4U)ϊSEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)ЊSEMC_SRAMCR2_TA_MASK (0xF00U)ъSEMC_SRAMCR2_TA_SHIFT (8U)ҊSEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)ӊSEMC_SRAMCR2_AWDH_MASK (0xF000U)ԊSEMC_SRAMCR2_AWDH_SHIFT (12U)ՊSEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)֊SEMC_SRAMCR2_LC_MASK (0xF0000U)׊SEMC_SRAMCR2_LC_SHIFT (16U)؊SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)يSEMC_SRAMCR2_RD_MASK (0xF00000U)ڊSEMC_SRAMCR2_RD_SHIFT (20U)ۊSEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)܊SEMC_SRAMCR2_CEITV_MASK (0xF000000U)݊SEMC_SRAMCR2_CEITV_SHIFT (24U)ފSEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)SEMC_DBICR0_PS_MASK (0x1U)SEMC_DBICR0_PS_SHIFT (0U)SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)SEMC_DBICR0_BL_MASK (0x70U)SEMC_DBICR0_BL_SHIFT (4U)SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)SEMC_DBICR0_COL_MASK (0xF000U)SEMC_DBICR0_COL_SHIFT (12U)SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)SEMC_DBICR1_CES_MASK (0xFU)SEMC_DBICR1_CES_SHIFT (0U)SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)SEMC_DBICR1_CEH_MASK (0xF0U)SEMC_DBICR1_CEH_SHIFT (4U)SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)SEMC_DBICR1_WEL_MASK (0xF00U)SEMC_DBICR1_WEL_SHIFT (8U)SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)SEMC_DBICR1_WEH_MASK (0xF000U)SEMC_DBICR1_WEH_SHIFT (12U)SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)SEMC_DBICR1_REL_MASK (0xF0000U)SEMC_DBICR1_REL_SHIFT (16U)SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)SEMC_DBICR1_REH_MASK (0xF00000U)SEMC_DBICR1_REH_SHIFT (20U)SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)SEMC_DBICR1_CEITV_MASK (0xF000000U)SEMC_DBICR1_CEITV_SHIFT (24U)SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)SEMC_IPCR0_SA_SHIFT (0U)SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)SEMC_IPCR1_DATSZ_MASK (0x7U)SEMC_IPCR1_DATSZ_SHIFT (0U)SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)SEMC_IPCR2_BM0_MASK (0x1U)SEMC_IPCR2_BM0_SHIFT (0U)SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)SEMC_IPCR2_BM1_MASK (0x2U)SEMC_IPCR2_BM1_SHIFT (1U)SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)SEMC_IPCR2_BM2_MASK (0x4U)SEMC_IPCR2_BM2_SHIFT (2U)SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)SEMC_IPCR2_BM3_MASK (0x8U)SEMC_IPCR2_BM3_SHIFT (3U)SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)SEMC_IPCMD_CMD_MASK (0xFFFFU)SEMC_IPCMD_CMD_SHIFT (0U)SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)SEMC_IPCMD_KEY_MASK (0xFFFF0000U)SEMC_IPCMD_KEY_SHIFT (16U)SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)SEMC_IPTXDAT_DAT_SHIFT (0U)SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)SEMC_IPRXDAT_DAT_SHIFT (0U)SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)SEMC_STS0_IDLE_MASK (0x1U)SEMC_STS0_IDLE_SHIFT (0U)SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)‹SEMC_STS0_NARDY_MASK (0x2U)ËSEMC_STS0_NARDY_SHIFT (1U)ċSEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)ɋSEMC_STS2_NDWRPEND_MASK (0x8U)ʋSEMC_STS2_NDWRPEND_SHIFT (3U)ˋSEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)ЋSEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)ыSEMC_STS12_NDADDR_SHIFT (0U)ҋSEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)݋SEMC_BASE (0x402F0000u)ߋSEMC ((SEMC_Type *)SEMC_BASE)SEMC_BASE_ADDRS { SEMC_BASE }SEMC_BASE_PTRS { SEMC }SEMC_IRQS { SEMC_IRQn }SNVS_HPLR_ZMK_WSL_MASK (0x1U)SNVS_HPLR_ZMK_WSL_SHIFT (0U)SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)SNVS_HPLR_ZMK_RSL_MASK (0x2U)SNVS_HPLR_ZMK_RSL_SHIFT (1U)SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)SNVS_HPLR_SRTC_SL_MASK (0x4U)SNVS_HPLR_SRTC_SL_SHIFT (2U)SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)SNVS_HPLR_LPCALB_SL_MASK (0x8U)SNVS_HPLR_LPCALB_SL_SHIFT (3U)SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)SNVS_HPLR_MC_SL_MASK (0x10U)SNVS_HPLR_MC_SL_SHIFT (4U)SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)SNVS_HPLR_GPR_SL_MASK (0x20U)SNVS_HPLR_GPR_SL_SHIFT (5U)SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)SNVS_HPLR_LPSVCR_SL_MASK (0x40U)SNVS_HPLR_LPSVCR_SL_SHIFT (6U)SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)SNVS_HPLR_LPTDCR_SL_MASK (0x100U)SNVS_HPLR_LPTDCR_SL_SHIFT (8U)SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)SNVS_HPLR_MKS_SL_MASK (0x200U)SNVS_HPLR_MKS_SL_SHIFT (9U)SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)ŒSNVS_HPLR_HPSVCR_L_MASK (0x10000U)ÌSNVS_HPLR_HPSVCR_L_SHIFT (16U)ČSNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)ŌSNVS_HPLR_HPSICR_L_MASK (0x20000U)ƌSNVS_HPLR_HPSICR_L_SHIFT (17U)njSNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)ȌSNVS_HPLR_HAC_L_MASK (0x40000U)ɌSNVS_HPLR_HAC_L_SHIFT (18U)ʌSNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)όSNVS_HPCOMR_SSM_ST_MASK (0x1U)ЌSNVS_HPCOMR_SSM_ST_SHIFT (0U)ьSNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)ҌSNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)ӌSNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)ԌSNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)ՌSNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)֌SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)׌SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)،SNVS_HPCOMR_LP_SWR_MASK (0x10U)ٌSNVS_HPCOMR_LP_SWR_SHIFT (4U)ڌSNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)یSNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)܌SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)݌SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)ތSNVS_HPCOMR_SW_SV_MASK (0x100U)ߌSNVS_HPCOMR_SW_SV_SHIFT (8U)SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)SNVS_HPCOMR_SW_FSV_MASK (0x200U)SNVS_HPCOMR_SW_FSV_SHIFT (9U)SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)SNVS_HPCOMR_SW_LPSV_MASK (0x400U)SNVS_HPCOMR_SW_LPSV_SHIFT (10U)SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)SNVS_HPCOMR_MKS_EN_MASK (0x2000U)SNVS_HPCOMR_MKS_EN_SHIFT (13U)SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)SNVS_HPCOMR_HAC_EN_MASK (0x10000U)SNVS_HPCOMR_HAC_EN_SHIFT (16U)SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)SNVS_HPCOMR_HAC_STOP_SHIFT (19U)SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)SNVS_HPCR_RTC_EN_MASK (0x1U)SNVS_HPCR_RTC_EN_SHIFT (0U)SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)SNVS_HPCR_HPTA_EN_MASK (0x2U)SNVS_HPCR_HPTA_EN_SHIFT (1U)SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)SNVS_HPCR_DIS_PI_MASK (0x4U)SNVS_HPCR_DIS_PI_SHIFT (2U)SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)SNVS_HPCR_PI_EN_MASK (0x8U)SNVS_HPCR_PI_EN_SHIFT (3U)SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)SNVS_HPCR_PI_FREQ_MASK (0xF0U)SNVS_HPCR_PI_FREQ_SHIFT (4U)SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)SNVS_HPCR_HPCALB_EN_MASK (0x100U)SNVS_HPCR_HPCALB_EN_SHIFT (8U)SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)SNVS_HPCR_HPCALB_VAL_SHIFT (10U)SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)SNVS_HPCR_HP_TS_MASK (0x10000U)SNVS_HPCR_HP_TS_SHIFT (16U)SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)SNVS_HPCR_BTN_CONFIG_SHIFT (24U)SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)SNVS_HPCR_BTN_MASK_MASK (0x8000000U)SNVS_HPCR_BTN_MASK_SHIFT (27U)SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)SNVS_HPSICR_SV0_EN_MASK (0x1U)SNVS_HPSICR_SV0_EN_SHIFT (0U)SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)SNVS_HPSICR_SV1_EN_MASK (0x2U)SNVS_HPSICR_SV1_EN_SHIFT (1U)SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)SNVS_HPSICR_SV2_EN_MASK (0x4U)SNVS_HPSICR_SV2_EN_SHIFT (2U)SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)SNVS_HPSICR_SV3_EN_MASK (0x8U)SNVS_HPSICR_SV3_EN_SHIFT (3U)SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)SNVS_HPSICR_SV4_EN_MASK (0x10U)SNVS_HPSICR_SV4_EN_SHIFT (4U)SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)SNVS_HPSICR_SV5_EN_MASK (0x20U)SNVS_HPSICR_SV5_EN_SHIFT (5U)SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)SNVS_HPSICR_LPSVI_EN_SHIFT (31U)SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)SNVS_HPSVCR_SV0_CFG_MASK (0x1U)SNVS_HPSVCR_SV0_CFG_SHIFT (0U)SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)SNVS_HPSVCR_SV1_CFG_MASK (0x2U)SNVS_HPSVCR_SV1_CFG_SHIFT (1U)SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)SNVS_HPSVCR_SV2_CFG_MASK (0x4U)SNVS_HPSVCR_SV2_CFG_SHIFT (2U)ÍSNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)čSNVS_HPSVCR_SV3_CFG_MASK (0x8U)ōSNVS_HPSVCR_SV3_CFG_SHIFT (3U)ƍSNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)ǍSNVS_HPSVCR_SV4_CFG_MASK (0x10U)ȍSNVS_HPSVCR_SV4_CFG_SHIFT (4U)ɍSNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)ʍSNVS_HPSVCR_SV5_CFG_MASK (0x60U)ˍSNVS_HPSVCR_SV5_CFG_SHIFT (5U)̍SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)͍SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)΍SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)ύSNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)ԍSNVS_HPSR_HPTA_MASK (0x1U)ՍSNVS_HPSR_HPTA_SHIFT (0U)֍SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)׍SNVS_HPSR_PI_MASK (0x2U)؍SNVS_HPSR_PI_SHIFT (1U)ٍSNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)ڍSNVS_HPSR_LPDIS_MASK (0x10U)ۍSNVS_HPSR_LPDIS_SHIFT (4U)܍SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)ݍSNVS_HPSR_BTN_MASK (0x40U)ލSNVS_HPSR_BTN_SHIFT (6U)ߍSNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)SNVS_HPSR_BI_MASK (0x80U)SNVS_HPSR_BI_SHIFT (7U)SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)SNVS_HPSR_SSM_STATE_MASK (0xF00U)SNVS_HPSR_SSM_STATE_SHIFT (8U)SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)SNVS_HPSR_ZMK_ZERO_SHIFT (31U)SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)SNVS_HPSVSR_SV0_MASK (0x1U)SNVS_HPSVSR_SV0_SHIFT (0U)SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)SNVS_HPSVSR_SV1_MASK (0x2U)SNVS_HPSVSR_SV1_SHIFT (1U)SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)SNVS_HPSVSR_SV2_MASK (0x4U)SNVS_HPSVSR_SV2_SHIFT (2U)SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)SNVS_HPSVSR_SV3_MASK (0x8U)SNVS_HPSVSR_SV3_SHIFT (3U)SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)SNVS_HPSVSR_SV4_MASK (0x10U)SNVS_HPSVSR_SV4_SHIFT (4U)SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)SNVS_HPSVSR_SV5_MASK (0x20U)SNVS_HPSVSR_SV5_SHIFT (5U)SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)SNVS_HPSVSR_SW_SV_MASK (0x2000U)SNVS_HPSVSR_SW_SV_SHIFT (13U)SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)SNVS_HPSVSR_SW_FSV_MASK (0x4000U)SNVS_HPSVSR_SW_FSV_SHIFT (14U)SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)SNVS_HPSVSR_SW_LPSV_SHIFT (15U)SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)SNVS_HPRTCMR_RTC_MASK (0x7FFFU)SNVS_HPRTCMR_RTC_SHIFT (0U)SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)SNVS_HPRTCLR_RTC_SHIFT (0U)SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)SNVS_HPTAMR_HPTA_MS_SHIFT (0U)SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)ŽSNVS_HPTALR_HPTA_LS_SHIFT (0U)ÎSNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)ȎSNVS_LPLR_ZMK_WHL_MASK (0x1U)ɎSNVS_LPLR_ZMK_WHL_SHIFT (0U)ʎSNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)ˎSNVS_LPLR_ZMK_RHL_MASK (0x2U)̎SNVS_LPLR_ZMK_RHL_SHIFT (1U)͎SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)ΎSNVS_LPLR_SRTC_HL_MASK (0x4U)ώSNVS_LPLR_SRTC_HL_SHIFT (2U)ЎSNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)юSNVS_LPLR_LPCALB_HL_MASK (0x8U)ҎSNVS_LPLR_LPCALB_HL_SHIFT (3U)ӎSNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)ԎSNVS_LPLR_MC_HL_MASK (0x10U)ՎSNVS_LPLR_MC_HL_SHIFT (4U)֎SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)׎SNVS_LPLR_GPR_HL_MASK (0x20U)؎SNVS_LPLR_GPR_HL_SHIFT (5U)َSNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)ڎSNVS_LPLR_LPSVCR_HL_MASK (0x40U)ێSNVS_LPLR_LPSVCR_HL_SHIFT (6U)܎SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)ݎSNVS_LPLR_LPTDCR_HL_MASK (0x100U)ގSNVS_LPLR_LPTDCR_HL_SHIFT (8U)ߎSNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)SNVS_LPLR_MKS_HL_MASK (0x200U)SNVS_LPLR_MKS_HL_SHIFT (9U)SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)SNVS_LPCR_SRTC_ENV_MASK (0x1U)SNVS_LPCR_SRTC_ENV_SHIFT (0U)SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)SNVS_LPCR_LPTA_EN_MASK (0x2U)SNVS_LPCR_LPTA_EN_SHIFT (1U)SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)SNVS_LPCR_MC_ENV_MASK (0x4U)SNVS_LPCR_MC_ENV_SHIFT (2U)SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)SNVS_LPCR_LPWUI_EN_MASK (0x8U)SNVS_LPCR_LPWUI_EN_SHIFT (3U)SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)SNVS_LPCR_DP_EN_MASK (0x20U)SNVS_LPCR_DP_EN_SHIFT (5U)SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)SNVS_LPCR_TOP_MASK (0x40U)SNVS_LPCR_TOP_SHIFT (6U)SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)SNVS_LPCR_LPCALB_EN_MASK (0x100U)SNVS_LPCR_LPCALB_EN_SHIFT (8U)SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)SNVS_LPCR_LPCALB_VAL_SHIFT (10U)SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)SNVS_LPCR_DEBOUNCE_SHIFT (18U)SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)SNVS_LPCR_ON_TIME_MASK (0x300000U)SNVS_LPCR_ON_TIME_SHIFT (20U)SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)SNVS_LPCR_PK_EN_MASK (0x400000U)SNVS_LPCR_PK_EN_SHIFT (22U)SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)SNVS_LPSVCR_SV0_EN_MASK (0x1U)SNVS_LPSVCR_SV0_EN_SHIFT (0U)SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)SNVS_LPSVCR_SV1_EN_MASK (0x2U)SNVS_LPSVCR_SV1_EN_SHIFT (1U)SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)SNVS_LPSVCR_SV2_EN_MASK (0x4U)SNVS_LPSVCR_SV2_EN_SHIFT (2U)SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)SNVS_LPSVCR_SV3_EN_MASK (0x8U)SNVS_LPSVCR_SV3_EN_SHIFT (3U)SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)SNVS_LPSVCR_SV4_EN_MASK (0x10U)SNVS_LPSVCR_SV4_EN_SHIFT (4U)SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)SNVS_LPSVCR_SV5_EN_MASK (0x20U)SNVS_LPSVCR_SV5_EN_SHIFT (5U)SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)ďSNVS_LPTDCR_SRTCR_EN_MASK (0x2U)ŏSNVS_LPTDCR_SRTCR_EN_SHIFT (1U)ƏSNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)ǏSNVS_LPTDCR_MCR_EN_MASK (0x4U)ȏSNVS_LPTDCR_MCR_EN_SHIFT (2U)ɏSNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)ʏSNVS_LPTDCR_ET1_EN_MASK (0x200U)ˏSNVS_LPTDCR_ET1_EN_SHIFT (9U)̏SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)͏SNVS_LPTDCR_ET1P_MASK (0x800U)ΏSNVS_LPTDCR_ET1P_SHIFT (11U)ϏSNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)ЏSNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)яSNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)ҏSNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)ӏSNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)ԏSNVS_LPTDCR_POR_OBSERV_SHIFT (15U)ՏSNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)֏SNVS_LPTDCR_OSCB_MASK (0x10000000U)׏SNVS_LPTDCR_OSCB_SHIFT (28U)؏SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)ݏSNVS_LPSR_LPTA_MASK (0x1U)ޏSNVS_LPSR_LPTA_SHIFT (0U)ߏSNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)SNVS_LPSR_SRTCR_MASK (0x2U)SNVS_LPSR_SRTCR_SHIFT (1U)SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)SNVS_LPSR_MCR_MASK (0x4U)SNVS_LPSR_MCR_SHIFT (2U)SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)SNVS_LPSR_PGD_MASK (0x8U)SNVS_LPSR_PGD_SHIFT (3U)SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)SNVS_LPSR_ET1D_MASK (0x200U)SNVS_LPSR_ET1D_SHIFT (9U)SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)SNVS_LPSR_ESVD_MASK (0x10000U)SNVS_LPSR_ESVD_SHIFT (16U)SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)SNVS_LPSR_EO_MASK (0x20000U)SNVS_LPSR_EO_SHIFT (17U)SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)SNVS_LPSR_SPO_MASK (0x40000U)SNVS_LPSR_SPO_SHIFT (18U)SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)SNVS_LPSR_SED_MASK (0x100000U)SNVS_LPSR_SED_SHIFT (20U)SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)SNVS_LPSR_LPNS_MASK (0x40000000U)SNVS_LPSR_LPNS_SHIFT (30U)SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)SNVS_LPSR_LPS_MASK (0x80000000U)SNVS_LPSR_LPS_SHIFT (31U)SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)SNVS_LPSRTCMR_SRTC_SHIFT (0U)SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)SNVS_LPSRTCLR_SRTC_SHIFT (0U)SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)SNVS_LPTAR_LPTA_SHIFT (0U)SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)SNVS_LPPGDR_PGD_SHIFT (0U)SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)SNVS_LPZMKR_ZMK_SHIFT (0U)SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)SNVS_LPZMKR_COUNT (8U)SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)ƐSNVS_LPGPR_ALIAS_COUNT (4U)ʐSNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)ːSNVS_LPGPR_GPR_SHIFT (0U)̐SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)АSNVS_LPGPR_COUNT (4U)ԐSNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)ՐSNVS_HPVIDR1_MINOR_REV_SHIFT (0U)֐SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)אSNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)ؐSNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)ِSNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)ڐSNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)ېSNVS_HPVIDR1_IP_ID_SHIFT (16U)ܐSNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)SNVS_HPVIDR2_ECO_REV_SHIFT (8U)SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)SNVS_HPVIDR2_IP_ERA_SHIFT (24U)SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)SNVS_BASE (0x400D4000u)SNVS ((SNVS_Type *)SNVS_BASE)SNVS_BASE_ADDRS { SNVS_BASE }SNVS_BASE_PTRS { SNVS }SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }SPDIF_SCR_USRC_SEL_MASK (0x3U)SPDIF_SCR_USRC_SEL_SHIFT (0U)SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)SPDIF_SCR_TXSEL_MASK (0x1CU)SPDIF_SCR_TXSEL_SHIFT (2U)SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)SPDIF_SCR_VALCTRL_MASK (0x20U)SPDIF_SCR_VALCTRL_SHIFT (5U)SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)SPDIF_SCR_DMA_TX_EN_MASK (0x100U)SPDIF_SCR_DMA_TX_EN_SHIFT (8U)SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)‘SPDIF_SCR_DMA_RX_EN_MASK (0x200U)ÑSPDIF_SCR_DMA_RX_EN_SHIFT (9U)đSPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)őSPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)ƑSPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)ǑSPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)ȑSPDIF_SCR_SOFT_RESET_MASK (0x1000U)ɑSPDIF_SCR_SOFT_RESET_SHIFT (12U)ʑSPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)ˑSPDIF_SCR_LOW_POWER_MASK (0x2000U)̑SPDIF_SCR_LOW_POWER_SHIFT (13U)͑SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)ΑSPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)ϑSPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)БSPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)ёSPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)ґSPDIF_SCR_TXAUTOSYNC_SHIFT (17U)ӑSPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)ԑSPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)ՑSPDIF_SCR_RXAUTOSYNC_SHIFT (18U)֑SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)בSPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)ؑSPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)ّSPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)ڑSPDIF_SCR_RXFIFO_RST_MASK (0x200000U)ۑSPDIF_SCR_RXFIFO_RST_SHIFT (21U)ܑSPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)ݑSPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)ޑSPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)ߑSPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)SPDIF_SRCD_USYNCMODE_MASK (0x2U)SPDIF_SRCD_USYNCMODE_SHIFT (1U)SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)SPDIF_SRPC_GAINSEL_MASK (0x38U)SPDIF_SRPC_GAINSEL_SHIFT (3U)SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)SPDIF_SRPC_LOCK_MASK (0x40U)SPDIF_SRPC_LOCK_SHIFT (6U)SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)SPDIF_SIE_RXFIFOFUL_MASK (0x1U)SPDIF_SIE_RXFIFOFUL_SHIFT (0U)SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)SPDIF_SIE_TXEM_MASK (0x2U)SPDIF_SIE_TXEM_SHIFT (1U)SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)SPDIF_SIE_LOCKLOSS_MASK (0x4U)SPDIF_SIE_LOCKLOSS_SHIFT (2U)SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)SPDIF_SIE_RXFIFORESYN_MASK (0x8U)SPDIF_SIE_RXFIFORESYN_SHIFT (3U)SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)SPDIF_SIE_UQERR_MASK (0x20U)SPDIF_SIE_UQERR_SHIFT (5U)SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)SPDIF_SIE_UQSYNC_MASK (0x40U)SPDIF_SIE_UQSYNC_SHIFT (6U)SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)SPDIF_SIE_QRXOV_MASK (0x80U)SPDIF_SIE_QRXOV_SHIFT (7U)SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)SPDIF_SIE_QRXFUL_MASK (0x100U)SPDIF_SIE_QRXFUL_SHIFT (8U)SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)SPDIF_SIE_URXOV_MASK (0x200U)SPDIF_SIE_URXOV_SHIFT (9U)SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)SPDIF_SIE_URXFUL_MASK (0x400U)SPDIF_SIE_URXFUL_SHIFT (10U)SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)SPDIF_SIE_BITERR_MASK (0x4000U)SPDIF_SIE_BITERR_SHIFT (14U)SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)SPDIF_SIE_SYMERR_MASK (0x8000U)SPDIF_SIE_SYMERR_SHIFT (15U)SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)SPDIF_SIE_VALNOGOOD_MASK (0x10000U)SPDIF_SIE_VALNOGOOD_SHIFT (16U)SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)SPDIF_SIE_CNEW_MASK (0x20000U)SPDIF_SIE_CNEW_SHIFT (17U)SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)SPDIF_SIE_TXRESYN_MASK (0x40000U)SPDIF_SIE_TXRESYN_SHIFT (18U)SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)SPDIF_SIE_TXUNOV_MASK (0x80000U)SPDIF_SIE_TXUNOV_SHIFT (19U)SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)SPDIF_SIE_LOCK_MASK (0x100000U)SPDIF_SIE_LOCK_SHIFT (20U)SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)SPDIF_SIC_LOCKLOSS_MASK (0x4U)SPDIF_SIC_LOCKLOSS_SHIFT (2U)SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)SPDIF_SIC_RXFIFORESYN_MASK (0x8U)SPDIF_SIC_RXFIFORESYN_SHIFT (3U)SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)SPDIF_SIC_UQERR_MASK (0x20U)SPDIF_SIC_UQERR_SHIFT (5U)SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)SPDIF_SIC_UQSYNC_MASK (0x40U)’SPDIF_SIC_UQSYNC_SHIFT (6U)ÒSPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)ĒSPDIF_SIC_QRXOV_MASK (0x80U)ŒSPDIF_SIC_QRXOV_SHIFT (7U)ƒSPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)ǒSPDIF_SIC_URXOV_MASK (0x200U)ȒSPDIF_SIC_URXOV_SHIFT (9U)ɒSPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)ʒSPDIF_SIC_BITERR_MASK (0x4000U)˒SPDIF_SIC_BITERR_SHIFT (14U)̒SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)͒SPDIF_SIC_SYMERR_MASK (0x8000U)ΒSPDIF_SIC_SYMERR_SHIFT (15U)ϒSPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)ВSPDIF_SIC_VALNOGOOD_MASK (0x10000U)ђSPDIF_SIC_VALNOGOOD_SHIFT (16U)ҒSPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)ӒSPDIF_SIC_CNEW_MASK (0x20000U)ԒSPDIF_SIC_CNEW_SHIFT (17U)ՒSPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)֒SPDIF_SIC_TXRESYN_MASK (0x40000U)גSPDIF_SIC_TXRESYN_SHIFT (18U)ؒSPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)ْSPDIF_SIC_TXUNOV_MASK (0x80000U)ڒSPDIF_SIC_TXUNOV_SHIFT (19U)ےSPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)ܒSPDIF_SIC_LOCK_MASK (0x100000U)ݒSPDIF_SIC_LOCK_SHIFT (20U)ޒSPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)SPDIF_SIS_RXFIFOFUL_MASK (0x1U)SPDIF_SIS_RXFIFOFUL_SHIFT (0U)SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)SPDIF_SIS_TXEM_MASK (0x2U)SPDIF_SIS_TXEM_SHIFT (1U)SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)SPDIF_SIS_LOCKLOSS_MASK (0x4U)SPDIF_SIS_LOCKLOSS_SHIFT (2U)SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)SPDIF_SIS_RXFIFORESYN_MASK (0x8U)SPDIF_SIS_RXFIFORESYN_SHIFT (3U)SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)SPDIF_SIS_UQERR_MASK (0x20U)SPDIF_SIS_UQERR_SHIFT (5U)SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)SPDIF_SIS_UQSYNC_MASK (0x40U)SPDIF_SIS_UQSYNC_SHIFT (6U)SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)SPDIF_SIS_QRXOV_MASK (0x80U)SPDIF_SIS_QRXOV_SHIFT (7U)SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)SPDIF_SIS_QRXFUL_MASK (0x100U)SPDIF_SIS_QRXFUL_SHIFT (8U)SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)SPDIF_SIS_URXOV_MASK (0x200U)SPDIF_SIS_URXOV_SHIFT (9U)SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)SPDIF_SIS_URXFUL_MASK (0x400U)SPDIF_SIS_URXFUL_SHIFT (10U)SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)SPDIF_SIS_BITERR_MASK (0x4000U)SPDIF_SIS_BITERR_SHIFT (14U)SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)SPDIF_SIS_SYMERR_MASK (0x8000U)SPDIF_SIS_SYMERR_SHIFT (15U)SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)SPDIF_SIS_VALNOGOOD_MASK (0x10000U)SPDIF_SIS_VALNOGOOD_SHIFT (16U)SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)SPDIF_SIS_CNEW_MASK (0x20000U)SPDIF_SIS_CNEW_SHIFT (17U)SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)SPDIF_SIS_TXRESYN_MASK (0x40000U)SPDIF_SIS_TXRESYN_SHIFT (18U)SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)SPDIF_SIS_TXUNOV_MASK (0x80000U)SPDIF_SIS_TXUNOV_SHIFT (19U)SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)SPDIF_SIS_LOCK_MASK (0x100000U)SPDIF_SIS_LOCK_SHIFT (20U)SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)SPDIF_SRL_RXDATALEFT_SHIFT (0U)SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)SPDIF_SRR_RXDATARIGHT_SHIFT (0U)SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)SPDIF_SRU_RXUCHANNEL_SHIFT (0U)SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)“SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)ǓSPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)ȓSPDIF_STL_TXDATALEFT_SHIFT (0U)ɓSPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)ΓSPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)ϓSPDIF_STR_TXDATARIGHT_SHIFT (0U)ГSPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)ՓSPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)֓SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)דSPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)ܓSPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)ݓSPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)ޓSPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)SPDIF_SRFM_FREQMEAS_SHIFT (0U)SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)SPDIF_STC_TXCLK_DF_MASK (0x7FU)SPDIF_STC_TXCLK_DF_SHIFT (0U)SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)SPDIF_STC_SYSCLK_DF_SHIFT (11U)SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)SPDIF_BASE (0x40380000u)SPDIF ((SPDIF_Type *)SPDIF_BASE)SPDIF_BASE_ADDRS { SPDIF_BASE }SPDIF_BASE_PTRS { SPDIF }SPDIF_IRQS { SPDIF_IRQn }SRC_SCR_LOCKUP_RST_MASK (0x10U)SRC_SCR_LOCKUP_RST_SHIFT (4U)SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK)SRC_SCR_MASK_WDOG_RST_MASK (0x780U)SRC_SCR_MASK_WDOG_RST_SHIFT (7U)SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)SRC_SCR_CORE0_RST_MASK (0x2000U)SRC_SCR_CORE0_RST_SHIFT (13U)SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)SRC_SCR_CORE0_DBG_RST_SHIFT (17U)SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)ÔSRC_SBMR1_BOOT_CFG1_MASK (0xFFU)ĔSRC_SBMR1_BOOT_CFG1_SHIFT (0U)ŔSRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)ƔSRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)ǔSRC_SBMR1_BOOT_CFG2_SHIFT (8U)ȔSRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)ɔSRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)ʔSRC_SBMR1_BOOT_CFG3_SHIFT (16U)˔SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)̔SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)͔SRC_SBMR1_BOOT_CFG4_SHIFT (24U)ΔSRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)ӔSRC_SRSR_IPP_RESET_B_MASK (0x1U)ԔSRC_SRSR_IPP_RESET_B_SHIFT (0U)ՔSRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)֔SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)הSRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)ؔSRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)ٔSRC_SRSR_CSU_RESET_B_MASK (0x4U)ڔSRC_SRSR_CSU_RESET_B_SHIFT (2U)۔SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)ܔSRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)ݔSRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)ޔSRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)ߔSRC_SRSR_WDOG_RST_B_MASK (0x10U)SRC_SRSR_WDOG_RST_B_SHIFT (4U)SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)SRC_SRSR_JTAG_RST_B_MASK (0x20U)SRC_SRSR_JTAG_RST_B_SHIFT (5U)SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)SRC_SRSR_JTAG_SW_RST_MASK (0x40U)SRC_SRSR_JTAG_SW_RST_SHIFT (6U)SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)SRC_SRSR_WDOG3_RST_B_MASK (0x80U)SRC_SRSR_WDOG3_RST_B_SHIFT (7U)SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)SRC_SBMR2_SEC_CONFIG_MASK (0x3U)SRC_SBMR2_SEC_CONFIG_SHIFT (0U)SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)SRC_SBMR2_BMOD_MASK (0x3000000U)SRC_SBMR2_BMOD_SHIFT (24U)SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)SRC_GPR_COUNT (10U)SRC_BASE (0x400F8000u)SRC ((SRC_Type *)SRC_BASE)SRC_BASE_ADDRS { SRC_BASE }SRC_BASE_PTRS { SRC }SRC_IRQS { SRC_IRQn }SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASKSRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFTSRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASKSRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFTSRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASKSRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFTSRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASKSRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFTSRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASKSRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFTSRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)SRC_SRSR_W1C_BITS_MASK (SRC_SRSR_WDOG3_RST_B_MASK | SRC_SRSR_JTAG_SW_RST_MASK | SRC_SRSR_JTAG_RST_B_MASK | SRC_SRSR_WDOG_RST_B_MASK | SRC_SRSR_IPP_USER_RESET_B_MASK | SRC_SRSR_CSU_RESET_B_MASK | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK | SRC_SRSR_IPP_RESET_B_MASK)TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)ŖTEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)ƖTEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)ǖTEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)̖TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)͖TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)ΖTEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)ϖTEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)ЖTEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)іTEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)֖TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)זTEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)ؖTEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)ٖTEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)ږTEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)ۖTEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)TEMPMON_BASE (0x400D8000u)TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)TEMPMON_BASE_ADDRS { TEMPMON_BASE }TEMPMON_BASE_PTRS { TEMPMON }TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)TMR_COMP1_COMPARISON_1_SHIFT (0U)TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)TMR_COMP1_COUNT (4U)TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)TMR_COMP2_COMPARISON_2_SHIFT (0U)TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)TMR_COMP2_COUNT (4U)ėTMR_CAPT_CAPTURE_MASK (0xFFFFU)ŗTMR_CAPT_CAPTURE_SHIFT (0U)ƗTMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)ʗTMR_CAPT_COUNT (4U)ΗTMR_LOAD_LOAD_MASK (0xFFFFU)ϗTMR_LOAD_LOAD_SHIFT (0U)ЗTMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)ԗTMR_LOAD_COUNT (4U)ؗTMR_HOLD_HOLD_MASK (0xFFFFU)ٗTMR_HOLD_HOLD_SHIFT (0U)ڗTMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)ޗTMR_HOLD_COUNT (4U)TMR_CNTR_COUNTER_MASK (0xFFFFU)TMR_CNTR_COUNTER_SHIFT (0U)TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)TMR_CNTR_COUNT (4U)TMR_CTRL_OUTMODE_MASK (0x7U)TMR_CTRL_OUTMODE_SHIFT (0U)TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)TMR_CTRL_COINIT_MASK (0x8U)TMR_CTRL_COINIT_SHIFT (3U)TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)TMR_CTRL_DIR_MASK (0x10U)TMR_CTRL_DIR_SHIFT (4U)TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)TMR_CTRL_LENGTH_MASK (0x20U)TMR_CTRL_LENGTH_SHIFT (5U)TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)TMR_CTRL_ONCE_MASK (0x40U)TMR_CTRL_ONCE_SHIFT (6U)TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)TMR_CTRL_SCS_MASK (0x180U)TMR_CTRL_SCS_SHIFT (7U)TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)TMR_CTRL_PCS_MASK (0x1E00U)TMR_CTRL_PCS_SHIFT (9U)TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)TMR_CTRL_CM_MASK (0xE000U)TMR_CTRL_CM_SHIFT (13U)TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)TMR_CTRL_COUNT (4U)TMR_SCTRL_OEN_MASK (0x1U)TMR_SCTRL_OEN_SHIFT (0U)TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)TMR_SCTRL_OPS_MASK (0x2U)TMR_SCTRL_OPS_SHIFT (1U)TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)TMR_SCTRL_FORCE_MASK (0x4U)TMR_SCTRL_FORCE_SHIFT (2U)TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)TMR_SCTRL_VAL_MASK (0x8U)TMR_SCTRL_VAL_SHIFT (3U)TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)TMR_SCTRL_EEOF_MASK (0x10U)TMR_SCTRL_EEOF_SHIFT (4U)TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)TMR_SCTRL_MSTR_MASK (0x20U)TMR_SCTRL_MSTR_SHIFT (5U)TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)TMR_SCTRL_INPUT_MASK (0x100U)TMR_SCTRL_INPUT_SHIFT (8U)TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)TMR_SCTRL_IPS_MASK (0x200U)TMR_SCTRL_IPS_SHIFT (9U)TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)TMR_SCTRL_IEFIE_MASK (0x400U)TMR_SCTRL_IEFIE_SHIFT (10U)TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)TMR_SCTRL_IEF_MASK (0x800U)TMR_SCTRL_IEF_SHIFT (11U)TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)TMR_SCTRL_TOFIE_MASK (0x1000U)TMR_SCTRL_TOFIE_SHIFT (12U)TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)TMR_SCTRL_TOF_MASK (0x2000U)TMR_SCTRL_TOF_SHIFT (13U)TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)TMR_SCTRL_TCFIE_MASK (0x4000U)TMR_SCTRL_TCFIE_SHIFT (14U)TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)TMR_SCTRL_TCF_MASK (0x8000U)TMR_SCTRL_TCF_SHIFT (15U)TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)TMR_SCTRL_COUNT (4U)TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)ŘTMR_CMPLD1_COUNT (4U)ɘTMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)ʘTMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)˘TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)ϘTMR_CMPLD2_COUNT (4U)ӘTMR_CSCTRL_CL1_MASK (0x3U)ԘTMR_CSCTRL_CL1_SHIFT (0U)՘TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)֘TMR_CSCTRL_CL2_MASK (0xCU)טTMR_CSCTRL_CL2_SHIFT (2U)ؘTMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)٘TMR_CSCTRL_TCF1_MASK (0x10U)ژTMR_CSCTRL_TCF1_SHIFT (4U)ۘTMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)ܘTMR_CSCTRL_TCF2_MASK (0x20U)ݘTMR_CSCTRL_TCF2_SHIFT (5U)ޘTMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)ߘTMR_CSCTRL_TCF1EN_MASK (0x40U)TMR_CSCTRL_TCF1EN_SHIFT (6U)TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)TMR_CSCTRL_TCF2EN_MASK (0x80U)TMR_CSCTRL_TCF2EN_SHIFT (7U)TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)TMR_CSCTRL_UP_MASK (0x200U)TMR_CSCTRL_UP_SHIFT (9U)TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)TMR_CSCTRL_TCI_MASK (0x400U)TMR_CSCTRL_TCI_SHIFT (10U)TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)TMR_CSCTRL_ROC_MASK (0x800U)TMR_CSCTRL_ROC_SHIFT (11U)TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)TMR_CSCTRL_ALT_LOAD_SHIFT (12U)TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)TMR_CSCTRL_FAULT_MASK (0x2000U)TMR_CSCTRL_FAULT_SHIFT (13U)TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)TMR_CSCTRL_DBG_EN_MASK (0xC000U)TMR_CSCTRL_DBG_EN_SHIFT (14U)TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)TMR_CSCTRL_COUNT (4U)TMR_FILT_FILT_PER_MASK (0xFFU)TMR_FILT_FILT_PER_SHIFT (0U)TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)TMR_FILT_FILT_CNT_MASK (0x700U)TMR_FILT_FILT_CNT_SHIFT (8U)TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)TMR_FILT_COUNT (4U)TMR_DMA_IEFDE_MASK (0x1U)TMR_DMA_IEFDE_SHIFT (0U)TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)TMR_DMA_CMPLD1DE_MASK (0x2U)TMR_DMA_CMPLD1DE_SHIFT (1U)TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)TMR_DMA_CMPLD2DE_MASK (0x4U)TMR_DMA_CMPLD2DE_SHIFT (2U)TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)TMR_DMA_COUNT (4U)TMR_ENBL_ENBL_MASK (0xFU)TMR_ENBL_ENBL_SHIFT (0U)TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)TMR_ENBL_COUNT (4U)TMR1_BASE (0x401DC000u)TMR1 ((TMR_Type *)TMR1_BASE)TMR2_BASE (0x401E0000u)TMR2 ((TMR_Type *)TMR2_BASE)TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE }TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2 }TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn }TRNG_MCTL_SAMP_MODE_MASK (0x3U)TRNG_MCTL_SAMP_MODE_SHIFT (0U)TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)TRNG_MCTL_OSC_DIV_MASK (0xCU)TRNG_MCTL_OSC_DIV_SHIFT (2U)TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)TRNG_MCTL_UNUSED4_MASK (0x10U)TRNG_MCTL_UNUSED4_SHIFT (4U)TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)TRNG_MCTL_TRNG_ACC_MASK (0x20U)TRNG_MCTL_TRNG_ACC_SHIFT (5U)TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)TRNG_MCTL_RST_DEF_MASK (0x40U)TRNG_MCTL_RST_DEF_SHIFT (6U)TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)TRNG_MCTL_FOR_SCLK_MASK (0x80U)TRNG_MCTL_FOR_SCLK_SHIFT (7U)TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)TRNG_MCTL_FCT_FAIL_MASK (0x100U)TRNG_MCTL_FCT_FAIL_SHIFT (8U)TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)TRNG_MCTL_FCT_VAL_MASK (0x200U)TRNG_MCTL_FCT_VAL_SHIFT (9U)TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)TRNG_MCTL_ENT_VAL_MASK (0x400U)TRNG_MCTL_ENT_VAL_SHIFT (10U)TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)TRNG_MCTL_TST_OUT_MASK (0x800U)TRNG_MCTL_TST_OUT_SHIFT (11U)TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)TRNG_MCTL_ERR_MASK (0x1000U)TRNG_MCTL_ERR_SHIFT (12U)TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)TRNG_MCTL_TSTOP_OK_MASK (0x2000U)TRNG_MCTL_TSTOP_OK_SHIFT (13U)TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)TRNG_MCTL_LRUN_CONT_MASK (0x4000U)TRNG_MCTL_LRUN_CONT_SHIFT (14U)TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)TRNG_MCTL_PRGM_MASK (0x10000U)TRNG_MCTL_PRGM_SHIFT (16U)TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)šTRNG_SCMISC_LRUN_MAX_MASK (0xFFU)ÚTRNG_SCMISC_LRUN_MAX_SHIFT (0U)ĚTRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)ŚTRNG_SCMISC_RTY_CT_MASK (0xF0000U)ƚTRNG_SCMISC_RTY_CT_SHIFT (16U)ǚTRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)̚TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)͚TRNG_PKRRNG_PKR_RNG_SHIFT (0U)ΚTRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)ӚTRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)ԚTRNG_PKRMAX_PKR_MAX_SHIFT (0U)՚TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)ښTRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)ۚTRNG_PKRSQ_PKR_SQ_SHIFT (0U)ܚTRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)TRNG_SDCTL_ENT_DLY_SHIFT (16U)TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)TRNG_SBLIM_SB_LIM_MASK (0x3FFU)TRNG_SBLIM_SB_LIM_SHIFT (0U)TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)TRNG_TOTSAM_TOT_SAM_SHIFT (0U)TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)TRNG_FRQCNT_FRQ_CT_SHIFT (0U)TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)TRNG_SCMC_MONO_CT_MASK (0xFFFFU)TRNG_SCMC_MONO_CT_SHIFT (0U)TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)TRNG_SCML_MONO_MAX_MASK (0xFFFFU)TRNG_SCML_MONO_MAX_SHIFT (0U)TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)TRNG_SCML_MONO_RNG_SHIFT (16U)TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)TRNG_SCR1C_R1_0_CT_SHIFT (0U)TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)TRNG_SCR1C_R1_1_CT_SHIFT (16U)TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)TRNG_SCR1L_RUN1_MAX_SHIFT (0U)TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)TRNG_SCR1L_RUN1_RNG_SHIFT (16U)TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)TRNG_SCR2C_R2_0_CT_SHIFT (0U)TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)TRNG_SCR2C_R2_1_CT_SHIFT (16U)TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)TRNG_SCR2L_RUN2_MAX_SHIFT (0U)TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)TRNG_SCR2L_RUN2_RNG_SHIFT (16U)›TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)ǛTRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)țTRNG_SCR3C_R3_0_CT_SHIFT (0U)ɛTRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)ʛTRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)˛TRNG_SCR3C_R3_1_CT_SHIFT (16U)̛TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)ћTRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)қTRNG_SCR3L_RUN3_MAX_SHIFT (0U)ӛTRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)ԛTRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)՛TRNG_SCR3L_RUN3_RNG_SHIFT (16U)֛TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)ۛTRNG_SCR4C_R4_0_CT_MASK (0xFFFU)ܛTRNG_SCR4C_R4_0_CT_SHIFT (0U)ݛTRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)ޛTRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)ߛTRNG_SCR4C_R4_1_CT_SHIFT (16U)TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)TRNG_SCR4L_RUN4_MAX_SHIFT (0U)TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)TRNG_SCR4L_RUN4_RNG_SHIFT (16U)TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)TRNG_SCR5C_R5_0_CT_SHIFT (0U)TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)TRNG_SCR5C_R5_1_CT_SHIFT (16U)TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)TRNG_SCR5L_RUN5_MAX_SHIFT (0U)TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)TRNG_SCR5L_RUN5_RNG_SHIFT (16U)TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)TRNG_STATUS_TF1BR0_MASK (0x1U)TRNG_STATUS_TF1BR0_SHIFT (0U)TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)TRNG_STATUS_TF1BR1_MASK (0x2U)TRNG_STATUS_TF1BR1_SHIFT (1U)TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)TRNG_STATUS_TF2BR0_MASK (0x4U)TRNG_STATUS_TF2BR0_SHIFT (2U)TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)TRNG_STATUS_TF2BR1_MASK (0x8U)TRNG_STATUS_TF2BR1_SHIFT (3U)TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)TRNG_STATUS_TF3BR0_MASK (0x10U)TRNG_STATUS_TF3BR0_SHIFT (4U)TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)TRNG_STATUS_TF3BR1_MASK (0x20U)TRNG_STATUS_TF3BR1_SHIFT (5U)TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)TRNG_STATUS_TF4BR0_MASK (0x40U)TRNG_STATUS_TF4BR0_SHIFT (6U)TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)TRNG_STATUS_TF4BR1_MASK (0x80U)TRNG_STATUS_TF4BR1_SHIFT (7U)TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)TRNG_STATUS_TF5BR0_MASK (0x100U)TRNG_STATUS_TF5BR0_SHIFT (8U)TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)TRNG_STATUS_TF5BR1_MASK (0x200U)TRNG_STATUS_TF5BR1_SHIFT (9U)TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)TRNG_STATUS_TF6PBR0_MASK (0x400U)TRNG_STATUS_TF6PBR0_SHIFT (10U)TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)TRNG_STATUS_TF6PBR1_MASK (0x800U)TRNG_STATUS_TF6PBR1_SHIFT (11U)TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)TRNG_STATUS_TFSB_MASK (0x1000U)TRNG_STATUS_TFSB_SHIFT (12U)TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)TRNG_STATUS_TFLR_MASK (0x2000U)TRNG_STATUS_TFLR_SHIFT (13U)TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)TRNG_STATUS_TFP_MASK (0x4000U)œTRNG_STATUS_TFP_SHIFT (14U)ÜTRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)ĜTRNG_STATUS_TFMB_MASK (0x8000U)ŜTRNG_STATUS_TFMB_SHIFT (15U)ƜTRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)ǜTRNG_STATUS_RETRY_CT_MASK (0xF0000U)ȜTRNG_STATUS_RETRY_CT_SHIFT (16U)ɜTRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)ΜTRNG_ENT_ENT_MASK (0xFFFFFFFFU)ϜTRNG_ENT_ENT_SHIFT (0U)МTRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)ԜTRNG_ENT_COUNT (16U)؜TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)ٜTRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)ڜTRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)ۜTRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)ܜTRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)ݜTRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)TRNG_SEC_CFG_UNUSED0_MASK (0x1U)TRNG_SEC_CFG_UNUSED0_SHIFT (0U)TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)TRNG_SEC_CFG_UNUSED2_MASK (0x4U)TRNG_SEC_CFG_UNUSED2_SHIFT (2U)TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)TRNG_INT_CTRL_HW_ERR_MASK (0x1U)TRNG_INT_CTRL_HW_ERR_SHIFT (0U)TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)TRNG_INT_CTRL_UNUSED_SHIFT (3U)TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)ŝTRNG_INT_MASK_HW_ERR_MASK (0x1U)ƝTRNG_INT_MASK_HW_ERR_SHIFT (0U)ǝTRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)ȝTRNG_INT_MASK_ENT_VAL_MASK (0x2U)ɝTRNG_INT_MASK_ENT_VAL_SHIFT (1U)ʝTRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)˝TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)̝TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)͝TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)ҝTRNG_INT_STATUS_HW_ERR_MASK (0x1U)ӝTRNG_INT_STATUS_HW_ERR_SHIFT (0U)ԝTRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)՝TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)֝TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)םTRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)؝TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)ٝTRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)ڝTRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)ߝTRNG_VID1_MIN_REV_MASK (0xFFU)TRNG_VID1_MIN_REV_SHIFT (0U)TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)TRNG_VID1_MAJ_REV_MASK (0xFF00U)TRNG_VID1_MAJ_REV_SHIFT (8U)TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)TRNG_VID1_IP_ID_MASK (0xFFFF0000U)TRNG_VID1_IP_ID_SHIFT (16U)TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)TRNG_VID2_CONFIG_OPT_MASK (0xFFU)TRNG_VID2_CONFIG_OPT_SHIFT (0U)TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)TRNG_VID2_ECO_REV_MASK (0xFF00U)TRNG_VID2_ECO_REV_SHIFT (8U)TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)TRNG_VID2_INTG_OPT_MASK (0xFF0000U)TRNG_VID2_INTG_OPT_SHIFT (16U)TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)TRNG_VID2_ERA_MASK (0xFF000000U)TRNG_VID2_ERA_SHIFT (24U)TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)TRNG_BASE (0x400CC000u)TRNG ((TRNG_Type *)TRNG_BASE)TRNG_BASE_ADDRS { TRNG_BASE }TRNG_BASE_PTRS { TRNG }TRNG_IRQS { TRNG_IRQn }ߞUSB_ID_ID_MASK (0x3FU)USB_ID_ID_SHIFT (0U)USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)USB_ID_NID_MASK (0x3F00U)USB_ID_NID_SHIFT (8U)USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)USB_ID_REVISION_MASK (0xFF0000U)USB_ID_REVISION_SHIFT (16U)USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)USB_HWGENERAL_PHYW_MASK (0x30U)USB_HWGENERAL_PHYW_SHIFT (4U)USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)USB_HWGENERAL_PHYM_MASK (0x1C0U)USB_HWGENERAL_PHYM_SHIFT (6U)USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)USB_HWGENERAL_SM_MASK (0x600U)USB_HWGENERAL_SM_SHIFT (9U)USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)USB_HWHOST_HC_MASK (0x1U)USB_HWHOST_HC_SHIFT (0U)USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)USB_HWHOST_NPORT_MASK (0xEU)USB_HWHOST_NPORT_SHIFT (1U)USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)USB_HWDEVICE_DC_MASK (0x1U)USB_HWDEVICE_DC_SHIFT (0U)USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)USB_HWDEVICE_DEVEP_MASK (0x3EU)USB_HWDEVICE_DEVEP_SHIFT (1U)USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)USB_HWTXBUF_TXBURST_MASK (0xFFU)USB_HWTXBUF_TXBURST_SHIFT (0U)USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)USB_HWTXBUF_TXCHANADD_SHIFT (16U)USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)USB_HWRXBUF_RXBURST_MASK (0xFFU)USB_HWRXBUF_RXBURST_SHIFT (0U)USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)USB_HWRXBUF_RXADD_MASK (0xFF00U)USB_HWRXBUF_RXADD_SHIFT (8U)USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER0LD_GPTLD_SHIFT (0U)USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER1LD_GPTLD_SHIFT (0U)USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)ŸUSB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)ßUSB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)ğUSB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)şUSB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)ƟUSB_GPTIMER1CTRL_GPTRST_SHIFT (30U)ǟUSB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)ȟUSB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)ɟUSB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)ʟUSB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)ϟUSB_SBUSCFG_AHBBRST_MASK (0x7U)ПUSB_SBUSCFG_AHBBRST_SHIFT (0U)џUSB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)֟USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)ןUSB_CAPLENGTH_CAPLENGTH_SHIFT (0U)؟USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)ݟUSB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)ޟUSB_HCIVERSION_HCIVERSION_SHIFT (0U)ߟUSB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)USB_HCSPARAMS_N_PORTS_MASK (0xFU)USB_HCSPARAMS_N_PORTS_SHIFT (0U)USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)USB_HCSPARAMS_PPC_MASK (0x10U)USB_HCSPARAMS_PPC_SHIFT (4U)USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)USB_HCSPARAMS_N_PCC_MASK (0xF00U)USB_HCSPARAMS_N_PCC_SHIFT (8U)USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)USB_HCSPARAMS_N_CC_MASK (0xF000U)USB_HCSPARAMS_N_CC_SHIFT (12U)USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)USB_HCSPARAMS_PI_MASK (0x10000U)USB_HCSPARAMS_PI_SHIFT (16U)USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)USB_HCSPARAMS_N_PTT_MASK (0xF00000U)USB_HCSPARAMS_N_PTT_SHIFT (20U)USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)USB_HCSPARAMS_N_TT_MASK (0xF000000U)USB_HCSPARAMS_N_TT_SHIFT (24U)USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)USB_HCCPARAMS_ADC_MASK (0x1U)USB_HCCPARAMS_ADC_SHIFT (0U)USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)USB_HCCPARAMS_PFL_MASK (0x2U)USB_HCCPARAMS_PFL_SHIFT (1U)USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)USB_HCCPARAMS_ASP_MASK (0x4U)USB_HCCPARAMS_ASP_SHIFT (2U)USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)USB_HCCPARAMS_IST_MASK (0xF0U)USB_HCCPARAMS_IST_SHIFT (4U)USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)USB_HCCPARAMS_EECP_MASK (0xFF00U)USB_HCCPARAMS_EECP_SHIFT (8U)USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)USB_DCIVERSION_DCIVERSION_SHIFT (0U)USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)USB_DCCPARAMS_DEN_MASK (0x1FU)USB_DCCPARAMS_DEN_SHIFT (0U)USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)USB_DCCPARAMS_DC_MASK (0x80U)USB_DCCPARAMS_DC_SHIFT (7U)USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)USB_DCCPARAMS_HC_MASK (0x100U)USB_DCCPARAMS_HC_SHIFT (8U)USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)USB_USBCMD_RS_MASK (0x1U)USB_USBCMD_RS_SHIFT (0U)USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)USB_USBCMD_RST_MASK (0x2U)USB_USBCMD_RST_SHIFT (1U)USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)USB_USBCMD_FS_1_MASK (0xCU)USB_USBCMD_FS_1_SHIFT (2U)USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)USB_USBCMD_PSE_MASK (0x10U)USB_USBCMD_PSE_SHIFT (4U)USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)USB_USBCMD_ASE_MASK (0x20U)USB_USBCMD_ASE_SHIFT (5U)USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)USB_USBCMD_IAA_MASK (0x40U)USB_USBCMD_IAA_SHIFT (6U)USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)USB_USBCMD_ASP_MASK (0x300U)USB_USBCMD_ASP_SHIFT (8U)USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)USB_USBCMD_ASPE_MASK (0x800U)USB_USBCMD_ASPE_SHIFT (11U)USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)USB_USBCMD_ATDTW_MASK (0x1000U)USB_USBCMD_ATDTW_SHIFT (12U)USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)USB_USBCMD_SUTW_MASK (0x2000U)USB_USBCMD_SUTW_SHIFT (13U)USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) USB_USBCMD_FS_2_MASK (0x8000U)àUSB_USBCMD_FS_2_SHIFT (15U)ĠUSB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)ŠUSB_USBCMD_ITC_MASK (0xFF0000U)ƠUSB_USBCMD_ITC_SHIFT (16U)ǠUSB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)̠USB_USBSTS_UI_MASK (0x1U)͠USB_USBSTS_UI_SHIFT (0U)ΠUSB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)ϠUSB_USBSTS_UEI_MASK (0x2U)РUSB_USBSTS_UEI_SHIFT (1U)ѠUSB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)ҠUSB_USBSTS_PCI_MASK (0x4U)ӠUSB_USBSTS_PCI_SHIFT (2U)ԠUSB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)ՠUSB_USBSTS_FRI_MASK (0x8U)֠USB_USBSTS_FRI_SHIFT (3U)נUSB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)ؠUSB_USBSTS_SEI_MASK (0x10U)٠USB_USBSTS_SEI_SHIFT (4U)ڠUSB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)۠USB_USBSTS_AAI_MASK (0x20U)ܠUSB_USBSTS_AAI_SHIFT (5U)ݠUSB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)ޠUSB_USBSTS_URI_MASK (0x40U)ߠUSB_USBSTS_URI_SHIFT (6U)USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)USB_USBSTS_SRI_MASK (0x80U)USB_USBSTS_SRI_SHIFT (7U)USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)USB_USBSTS_SLI_MASK (0x100U)USB_USBSTS_SLI_SHIFT (8U)USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)USB_USBSTS_ULPII_MASK (0x400U)USB_USBSTS_ULPII_SHIFT (10U)USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)USB_USBSTS_HCH_MASK (0x1000U)USB_USBSTS_HCH_SHIFT (12U)USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)USB_USBSTS_RCL_MASK (0x2000U)USB_USBSTS_RCL_SHIFT (13U)USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)USB_USBSTS_PS_MASK (0x4000U)USB_USBSTS_PS_SHIFT (14U)USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)USB_USBSTS_AS_MASK (0x8000U)USB_USBSTS_AS_SHIFT (15U)USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)USB_USBSTS_NAKI_MASK (0x10000U)USB_USBSTS_NAKI_SHIFT (16U)USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)USB_USBSTS_TI0_MASK (0x1000000U)USB_USBSTS_TI0_SHIFT (24U)USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)USB_USBSTS_TI1_MASK (0x2000000U)USB_USBSTS_TI1_SHIFT (25U)USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)USB_USBINTR_UE_MASK (0x1U)USB_USBINTR_UE_SHIFT (0U)USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)USB_USBINTR_UEE_MASK (0x2U)USB_USBINTR_UEE_SHIFT (1U)USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)USB_USBINTR_PCE_MASK (0x4U)USB_USBINTR_PCE_SHIFT (2U)USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)USB_USBINTR_FRE_MASK (0x8U)USB_USBINTR_FRE_SHIFT (3U)USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)USB_USBINTR_SEE_MASK (0x10U)USB_USBINTR_SEE_SHIFT (4U)USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)USB_USBINTR_AAE_MASK (0x20U)USB_USBINTR_AAE_SHIFT (5U)USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)USB_USBINTR_URE_MASK (0x40U)USB_USBINTR_URE_SHIFT (6U)USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)USB_USBINTR_SRE_MASK (0x80U)USB_USBINTR_SRE_SHIFT (7U)USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)USB_USBINTR_SLE_MASK (0x100U)USB_USBINTR_SLE_SHIFT (8U)USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)USB_USBINTR_ULPIE_MASK (0x400U)USB_USBINTR_ULPIE_SHIFT (10U)USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)USB_USBINTR_NAKE_MASK (0x10000U)USB_USBINTR_NAKE_SHIFT (16U)USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)USB_USBINTR_UAIE_MASK (0x40000U)USB_USBINTR_UAIE_SHIFT (18U)USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)USB_USBINTR_UPIE_MASK (0x80000U)USB_USBINTR_UPIE_SHIFT (19U)USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)USB_USBINTR_TIE0_MASK (0x1000000U)USB_USBINTR_TIE0_SHIFT (24U)USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)USB_USBINTR_TIE1_MASK (0x2000000U)USB_USBINTR_TIE1_SHIFT (25U)USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)USB_FRINDEX_FRINDEX_MASK (0x3FFFU)USB_FRINDEX_FRINDEX_SHIFT (0U)USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)USB_DEVICEADDR_USBADRA_MASK (0x1000000U)USB_DEVICEADDR_USBADRA_SHIFT (24U)USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)USB_DEVICEADDR_USBADR_MASK (0xFE000000U)USB_DEVICEADDR_USBADR_SHIFT (25U)USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)šUSB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)ơUSB_PERIODICLISTBASE_BASEADR_SHIFT (12U)ǡUSB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)̡USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)͡USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)ΡUSB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)ӡUSB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)ԡUSB_ENDPTLISTADDR_EPBASE_SHIFT (11U)աUSB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)ڡUSB_BURSTSIZE_RXPBURST_MASK (0xFFU)ۡUSB_BURSTSIZE_RXPBURST_SHIFT (0U)ܡUSB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)ݡUSB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)ޡUSB_BURSTSIZE_TXPBURST_SHIFT (8U)ߡUSB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)USB_ENDPTNAK_EPRN_MASK (0xFFU)USB_ENDPTNAK_EPRN_SHIFT (0U)USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)USB_ENDPTNAK_EPTN_MASK (0xFF0000U)USB_ENDPTNAK_EPTN_SHIFT (16U)USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)USB_ENDPTNAKEN_EPRNE_SHIFT (0U)USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)USB_ENDPTNAKEN_EPTNE_SHIFT (16U)USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)USB_CONFIGFLAG_CF_MASK (0x1U)USB_CONFIGFLAG_CF_SHIFT (0U)USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)USB_PORTSC1_CCS_MASK (0x1U)USB_PORTSC1_CCS_SHIFT (0U)USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)USB_PORTSC1_CSC_MASK (0x2U)USB_PORTSC1_CSC_SHIFT (1U)USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)USB_PORTSC1_PE_MASK (0x4U)USB_PORTSC1_PE_SHIFT (2U)USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)USB_PORTSC1_PEC_MASK (0x8U)USB_PORTSC1_PEC_SHIFT (3U)USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)USB_PORTSC1_OCA_MASK (0x10U)USB_PORTSC1_OCA_SHIFT (4U)USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)USB_PORTSC1_OCC_MASK (0x20U)USB_PORTSC1_OCC_SHIFT (5U)USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)USB_PORTSC1_FPR_MASK (0x40U)USB_PORTSC1_FPR_SHIFT (6U)USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)USB_PORTSC1_SUSP_MASK (0x80U)USB_PORTSC1_SUSP_SHIFT (7U)USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)USB_PORTSC1_PR_MASK (0x100U)USB_PORTSC1_PR_SHIFT (8U)USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)USB_PORTSC1_HSP_MASK (0x200U)USB_PORTSC1_HSP_SHIFT (9U)USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)USB_PORTSC1_LS_MASK (0xC00U)USB_PORTSC1_LS_SHIFT (10U)USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)USB_PORTSC1_PP_MASK (0x1000U)USB_PORTSC1_PP_SHIFT (12U)USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)USB_PORTSC1_PO_MASK (0x2000U)USB_PORTSC1_PO_SHIFT (13U)USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)USB_PORTSC1_PIC_MASK (0xC000U)USB_PORTSC1_PIC_SHIFT (14U)USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)USB_PORTSC1_PTC_MASK (0xF0000U)USB_PORTSC1_PTC_SHIFT (16U)USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)USB_PORTSC1_WKCN_MASK (0x100000U)USB_PORTSC1_WKCN_SHIFT (20U)USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)USB_PORTSC1_WKDC_MASK (0x200000U)USB_PORTSC1_WKDC_SHIFT (21U)USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)USB_PORTSC1_WKOC_MASK (0x400000U)USB_PORTSC1_WKOC_SHIFT (22U)USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)¢USB_PORTSC1_PHCD_MASK (0x800000U)âUSB_PORTSC1_PHCD_SHIFT (23U)ĢUSB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)ŢUSB_PORTSC1_PFSC_MASK (0x1000000U)ƢUSB_PORTSC1_PFSC_SHIFT (24U)ǢUSB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)ȢUSB_PORTSC1_PTS_2_MASK (0x2000000U)ɢUSB_PORTSC1_PTS_2_SHIFT (25U)ʢUSB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)ˢUSB_PORTSC1_PSPD_MASK (0xC000000U)̢USB_PORTSC1_PSPD_SHIFT (26U)͢USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)΢USB_PORTSC1_PTW_MASK (0x10000000U)ϢUSB_PORTSC1_PTW_SHIFT (28U)ТUSB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)ѢUSB_PORTSC1_STS_MASK (0x20000000U)ҢUSB_PORTSC1_STS_SHIFT (29U)ӢUSB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)ԢUSB_PORTSC1_PTS_1_MASK (0xC0000000U)բUSB_PORTSC1_PTS_1_SHIFT (30U)֢USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)ۢUSB_OTGSC_VD_MASK (0x1U)ܢUSB_OTGSC_VD_SHIFT (0U)ݢUSB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)ޢUSB_OTGSC_VC_MASK (0x2U)ߢUSB_OTGSC_VC_SHIFT (1U)USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)USB_OTGSC_OT_MASK (0x8U)USB_OTGSC_OT_SHIFT (3U)USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)USB_OTGSC_DP_MASK (0x10U)USB_OTGSC_DP_SHIFT (4U)USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)USB_OTGSC_IDPU_MASK (0x20U)USB_OTGSC_IDPU_SHIFT (5U)USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)USB_OTGSC_ID_MASK (0x100U)USB_OTGSC_ID_SHIFT (8U)USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)USB_OTGSC_AVV_MASK (0x200U)USB_OTGSC_AVV_SHIFT (9U)USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)USB_OTGSC_ASV_MASK (0x400U)USB_OTGSC_ASV_SHIFT (10U)USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)USB_OTGSC_BSV_MASK (0x800U)USB_OTGSC_BSV_SHIFT (11U)USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)USB_OTGSC_BSE_MASK (0x1000U)USB_OTGSC_BSE_SHIFT (12U)USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)USB_OTGSC_TOG_1MS_MASK (0x2000U)USB_OTGSC_TOG_1MS_SHIFT (13U)USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)USB_OTGSC_DPS_MASK (0x4000U)USB_OTGSC_DPS_SHIFT (14U)USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)USB_OTGSC_IDIS_MASK (0x10000U)USB_OTGSC_IDIS_SHIFT (16U)USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)USB_OTGSC_AVVIS_MASK (0x20000U)USB_OTGSC_AVVIS_SHIFT (17U)USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)USB_OTGSC_ASVIS_MASK (0x40000U)USB_OTGSC_ASVIS_SHIFT (18U)USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)USB_OTGSC_BSVIS_MASK (0x80000U)USB_OTGSC_BSVIS_SHIFT (19U)USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)USB_OTGSC_BSEIS_MASK (0x100000U)USB_OTGSC_BSEIS_SHIFT (20U)USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)USB_OTGSC_STATUS_1MS_MASK (0x200000U)USB_OTGSC_STATUS_1MS_SHIFT (21U)USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)USB_OTGSC_DPIS_MASK (0x400000U)USB_OTGSC_DPIS_SHIFT (22U)USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)USB_OTGSC_IDIE_MASK (0x1000000U)USB_OTGSC_IDIE_SHIFT (24U)USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)USB_OTGSC_AVVIE_MASK (0x2000000U)USB_OTGSC_AVVIE_SHIFT (25U)USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)USB_OTGSC_ASVIE_MASK (0x4000000U)USB_OTGSC_ASVIE_SHIFT (26U)USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)USB_OTGSC_BSVIE_MASK (0x8000000U)USB_OTGSC_BSVIE_SHIFT (27U)USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)USB_OTGSC_BSEIE_MASK (0x10000000U)USB_OTGSC_BSEIE_SHIFT (28U)USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)USB_OTGSC_EN_1MS_MASK (0x20000000U)USB_OTGSC_EN_1MS_SHIFT (29U)USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)USB_OTGSC_DPIE_MASK (0x40000000U)USB_OTGSC_DPIE_SHIFT (30U)USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)USB_USBMODE_CM_MASK (0x3U)USB_USBMODE_CM_SHIFT (0U)USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)USB_USBMODE_ES_MASK (0x4U)USB_USBMODE_ES_SHIFT (2U)USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)USB_USBMODE_SLOM_MASK (0x8U)USB_USBMODE_SLOM_SHIFT (3U)USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)USB_USBMODE_SDIS_MASK (0x10U)USB_USBMODE_SDIS_SHIFT (4U)USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)ģUSB_ENDPTPRIME_PERB_MASK (0xFFU)ţUSB_ENDPTPRIME_PERB_SHIFT (0U)ƣUSB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)ǣUSB_ENDPTPRIME_PETB_MASK (0xFF0000U)ȣUSB_ENDPTPRIME_PETB_SHIFT (16U)ɣUSB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)ΣUSB_ENDPTFLUSH_FERB_MASK (0xFFU)ϣUSB_ENDPTFLUSH_FERB_SHIFT (0U)УUSB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)ѣUSB_ENDPTFLUSH_FETB_MASK (0xFF0000U)ңUSB_ENDPTFLUSH_FETB_SHIFT (16U)ӣUSB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)أUSB_ENDPTSTAT_ERBR_MASK (0xFFU)٣USB_ENDPTSTAT_ERBR_SHIFT (0U)ڣUSB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)ۣUSB_ENDPTSTAT_ETBR_MASK (0xFF0000U)ܣUSB_ENDPTSTAT_ETBR_SHIFT (16U)ݣUSB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)USB_ENDPTCTRL0_RXS_MASK (0x1U)USB_ENDPTCTRL0_RXS_SHIFT (0U)USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)USB_ENDPTCTRL0_RXT_MASK (0xCU)USB_ENDPTCTRL0_RXT_SHIFT (2U)USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)USB_ENDPTCTRL0_RXE_MASK (0x80U)USB_ENDPTCTRL0_RXE_SHIFT (7U)USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)USB_ENDPTCTRL0_TXS_MASK (0x10000U)USB_ENDPTCTRL0_TXS_SHIFT (16U)USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)USB_ENDPTCTRL0_TXT_MASK (0xC0000U)USB_ENDPTCTRL0_TXT_SHIFT (18U)USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)USB_ENDPTCTRL0_TXE_MASK (0x800000U)USB_ENDPTCTRL0_TXE_SHIFT (23U)USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)USB_ENDPTCTRL_RXS_MASK (0x1U)USB_ENDPTCTRL_RXS_SHIFT (0U)USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)USB_ENDPTCTRL_RXD_MASK (0x2U)USB_ENDPTCTRL_RXD_SHIFT (1U)USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)USB_ENDPTCTRL_RXT_MASK (0xCU)USB_ENDPTCTRL_RXT_SHIFT (2U)USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)USB_ENDPTCTRL_RXI_MASK (0x20U)USB_ENDPTCTRL_RXI_SHIFT (5U)USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)USB_ENDPTCTRL_RXR_MASK (0x40U)USB_ENDPTCTRL_RXR_SHIFT (6U)USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)USB_ENDPTCTRL_RXE_MASK (0x80U)USB_ENDPTCTRL_RXE_SHIFT (7U)USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)USB_ENDPTCTRL_TXS_MASK (0x10000U)USB_ENDPTCTRL_TXS_SHIFT (16U)USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)USB_ENDPTCTRL_TXD_MASK (0x20000U)USB_ENDPTCTRL_TXD_SHIFT (17U)USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)USB_ENDPTCTRL_TXT_MASK (0xC0000U)USB_ENDPTCTRL_TXT_SHIFT (18U)USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)USB_ENDPTCTRL_TXI_MASK (0x200000U)USB_ENDPTCTRL_TXI_SHIFT (21U)USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)USB_ENDPTCTRL_TXR_MASK (0x400000U)USB_ENDPTCTRL_TXR_SHIFT (22U)USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)USB_ENDPTCTRL_TXE_MASK (0x800000U)USB_ENDPTCTRL_TXE_SHIFT (23U)USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)USB_ENDPTCTRL_COUNT (7U)USB_BASE (0x402E0000u)USB ((USB_Type *)USB_BASE)USB_BASE_ADDRS { 0u, USB_BASE }USB_BASE_PTRS { (USB_Type *)0u, USB }USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn }GPTIMER0CTL GPTIMER0CTRLGPTIMER1CTL GPTIMER1CTRLUSB_SBUSCFG SBUSCFGEPLISTADDR ENDPTLISTADDREPSETUPSR ENDPTSETUPSTAT¤EPPRIME ENDPTPRIMEäEPFLUSH ENDPTFLUSHĤEPSR ENDPTSTATŤEPCOMPLETE ENDPTCOMPLETEƤEPCR ENDPTCTRLǤEPCR0 ENDPTCTRL0ȤUSBHS_ID_ID_MASK USB_ID_ID_MASKɤUSBHS_ID_ID_SHIFT USB_ID_ID_SHIFTʤUSBHS_ID_ID(x) USB_ID_ID(x)ˤUSBHS_ID_NID_MASK USB_ID_NID_MASK̤USBHS_ID_NID_SHIFT USB_ID_NID_SHIFTͤUSBHS_ID_NID(x) USB_ID_NID(x)ΤUSBHS_ID_REVISION_MASK USB_ID_REVISION_MASKϤUSBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFTФUSBHS_ID_REVISION(x) USB_ID_REVISION(x)ѤUSBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASKҤUSBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFTӤUSBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)ԤUSBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASKդUSBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT֤USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)פUSBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASKؤUSBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT٤USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)ڤUSBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASKۤUSBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFTܤUSBHS_HWHOST_HC(x) USB_HWHOST_HC(x)ݤUSBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASKޤUSBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFTߤUSBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASKUSBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFTUSBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASKUSBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFTUSBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASKUSBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFTUSBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASKUSBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFTUSBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASKUSBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFTUSBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASKUSBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFTUSBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASKUSBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFTUSBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASKUSBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFTUSBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASKUSBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFTUSBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASKUSBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFTUSBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASKUSBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFTUSBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASKUSBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFTUSBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASKUSBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFTUSBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASKUSBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFTUSBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASKUSBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFTUSBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASKUSBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFTUSBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASKUSBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFTUSBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASKUSBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFTUSBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASKUSBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFTUSBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASKUSBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFTUSBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASKUSBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFTUSBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASKUSBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFTUSBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASKUSBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFTUSBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASKUSBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFTUSBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASKUSBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFTUSBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASKUSBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFTUSBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASKUSBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFTUSBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASKUSBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFTUSBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASKUSBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFTUSBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASKUSBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFTUSBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASKUSBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFTUSBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASKUSBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFTUSBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK¥USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFTåUSBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)ĥUSBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASKťUSBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFTƥUSBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)ǥUSBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASKȥUSBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFTɥUSBHS_USBCMD_RS(x) USB_USBCMD_RS(x)ʥUSBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK˥USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT̥USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)ͥUSBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASKΥUSBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFTϥUSBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)ХUSBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASKѥUSBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFTҥUSBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)ӥUSBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASKԥUSBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFTեUSBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)֥USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASKץUSBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFTإUSBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)٥USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASKڥUSBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFTۥUSBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)ܥUSBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASKݥUSBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFTޥUSBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)ߥUSBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASKUSBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFTUSBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASKUSBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFTUSBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASKUSBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFTUSBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASKUSBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFTUSBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASKUSBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFTUSBHS_USBSTS_UI(x) USB_USBSTS_UI(x)USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASKUSBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFTUSBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASKUSBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFTUSBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASKUSBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFTUSBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASKUSBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFTUSBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASKUSBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFTUSBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASKUSBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFTUSBHS_USBSTS_URI(x) USB_USBSTS_URI(x)USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASKUSBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFTUSBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASKUSBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFTUSBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASKUSBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFTUSBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASKUSBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFTUSBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASKUSBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFTUSBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASKUSBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFTUSBHS_USBSTS_PS(x) USB_USBSTS_PS(x)USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASKUSBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFTUSBHS_USBSTS_AS(x) USB_USBSTS_AS(x)USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASKUSBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFTUSBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASKUSBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFTUSBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASKUSBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFTUSBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASKUSBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFTUSBHS_USBINTR_UE(x) USB_USBINTR_UE(x)USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASKUSBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFTUSBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASKUSBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFTUSBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASKUSBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFTUSBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASKUSBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFTUSBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASKUSBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFTUSBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASKUSBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFTUSBHS_USBINTR_URE(x) USB_USBINTR_URE(x)USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASKUSBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFTUSBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASKUSBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFTUSBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASKUSBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFTUSBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASKUSBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFTUSBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASKUSBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFTUSBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)¦USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASKæUSBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFTĦUSBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)ŦUSBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASKƦUSBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFTǦUSBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)ȦUSBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASKɦUSBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFTʦUSBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)˦USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK̦USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFTͦUSBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)ΦUSBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASKϦUSBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFTЦUSBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)ѦUSBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASKҦUSBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFTӦUSBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)ԦUSBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASKզUSBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT֦USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)צUSBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASKئUSBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT٦USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)ڦUSBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASKۦUSBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFTܦUSBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)ݦUSBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASKަUSBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFTߦUSBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASKUSBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFTUSBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASKUSBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFTUSBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASKUSBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFTUSBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASKUSBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFTUSBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASKUSBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFTUSBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASKUSBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFTUSBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASKUSBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFTUSBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASKUSBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFTUSBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASKUSBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFTUSBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASKUSBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFTUSBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASKUSBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFTUSBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASKUSBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFTUSBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASKUSBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFTUSBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASKUSBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFTUSBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASKUSBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFTUSBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASKUSBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFTUSBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASKUSBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFTUSBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASKUSBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFTUSBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASKUSBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFTUSBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASKUSBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFTUSBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASKUSBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFTUSBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASKUSBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFTUSBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASKUSBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFTUSBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASKUSBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFTUSBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASKUSBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFTUSBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASKUSBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFTUSBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASKUSBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFTUSBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASKUSBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFTUSBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASKUSBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFTUSBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASKUSBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFTUSBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASKUSBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFTUSBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASKUSBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFTUSBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASKUSBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT§USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)çUSBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASKħUSBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFTŧUSBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)ƧUSBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASKǧUSBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFTȧUSBHS_OTGSC_VD(x) USB_OTGSC_VD(x)ɧUSBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASKʧUSBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT˧USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)̧USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASKͧUSBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFTΧUSBHS_OTGSC_OT(x) USB_OTGSC_OT(x)ϧUSBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASKЧUSBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFTѧUSBHS_OTGSC_DP(x) USB_OTGSC_DP(x)ҧUSBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASKӧUSBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFTԧUSBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)էUSBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK֧USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFTקUSBHS_OTGSC_ID(x) USB_OTGSC_ID(x)اUSBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK٧USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFTڧUSBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)ۧUSBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASKܧUSBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFTݧUSBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)ާUSBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASKߧUSBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFTUSBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASKUSBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFTUSBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASKUSBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFTUSBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASKUSBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFTUSBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASKUSBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFTUSBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASKUSBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFTUSBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASKUSBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFTUSBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASKUSBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFTUSBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASKUSBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFTUSBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASKUSBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFTUSBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASKUSBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFTUSBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASKUSBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFTUSBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASKUSBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFTUSBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASKUSBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFTUSBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASKUSBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFTUSBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASKUSBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFTUSBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASKUSBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFTUSBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASKUSBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFTUSBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASKUSBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFTUSBHS_USBMODE_CM(x) USB_USBMODE_CM(x)USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASKUSBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFTUSBHS_USBMODE_ES(x) USB_USBMODE_ES(x)USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASKUSBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFTUSBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASKUSBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFTUSBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASKUSBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFTUSBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASKUSBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFTUSBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASKUSBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFTUSBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASKUSBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFTUSBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASKUSBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFTUSBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASKUSBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFTUSBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASKUSBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFTUSBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASKUSBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFTUSBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASKUSBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFTUSBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASKUSBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFTUSBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASKUSBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFTUSBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK¨USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFTèUSBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)ĨUSBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASKŨUSBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFTƨUSBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)ǨUSBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASKȨUSBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFTɨUSBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)ʨUSBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK˨USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT̨USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)ͨUSBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASKΨUSBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFTϨUSBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)ШUSBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASKѨUSBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFTҨUSBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)ӨUSBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASKԨUSBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFTըUSBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)֨USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASKרUSBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFTبUSBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)٨USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASKڨUSBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFTۨUSBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)ܨUSBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASKݨUSBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFTިUSBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)ߨUSBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASKUSBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFTUSBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASKUSBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFTUSBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASKUSBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFTUSBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASKUSBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFTUSBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASKUSBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFTUSBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASKUSBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFTUSBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNTUSBHS_Type USB_TypeUSBHS_BASE_ADDRS USB_BASEUSBHS_IRQS USB_OTG1_IRQnUSBHS_IRQHandler USB_OTG1_IRQHandlerUSBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)ȩUSBNC_BASE (0x402E0000u)ʩUSBNC ((USBNC_Type *)USBNC_BASE)̩USBNC_BASE_ADDRS { 0u, USBNC_BASE }ΩUSBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC }USBPHY_PWD_RSVD0_MASK (0x3FFU)USBPHY_PWD_RSVD0_SHIFT (0U)USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)USBPHY_PWD_TXPWDFS_MASK (0x400U)USBPHY_PWD_TXPWDFS_SHIFT (10U)USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)USBPHY_PWD_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)USBPHY_PWD_RSVD1_MASK (0x1E000U)USBPHY_PWD_RSVD1_SHIFT (13U)USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)USBPHY_PWD_RXPWDENV_MASK (0x20000U)USBPHY_PWD_RXPWDENV_SHIFT (17U)USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)USBPHY_PWD_RXPWDRX_MASK (0x100000U)USBPHY_PWD_RXPWDRX_SHIFT (20U)USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)USBPHY_PWD_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_RSVD2_SHIFT (21U)USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)USBPHY_PWD_SET_RSVD0_SHIFT (0U)USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)USBPHY_PWD_SET_RSVD1_SHIFT (13U)USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)ªUSBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)êUSBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)ĪUSBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)ŪUSBPHY_PWD_SET_RXPWDRX_SHIFT (20U)ƪUSBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)ǪUSBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)ȪUSBPHY_PWD_SET_RSVD2_SHIFT (21U)ɪUSBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)ΪUSBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)ϪUSBPHY_PWD_CLR_RSVD0_SHIFT (0U)ЪUSBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)ѪUSBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)ҪUSBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)ӪUSBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)ԪUSBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)ժUSBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)֪USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)תUSBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)تUSBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)٪USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)ڪUSBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)۪USBPHY_PWD_CLR_RSVD1_SHIFT (13U)ܪUSBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)ݪUSBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)ުUSBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)ߪUSBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_CLR_RSVD2_SHIFT (21U)USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)USBPHY_PWD_TOG_RSVD0_SHIFT (0U)USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)USBPHY_PWD_TOG_RSVD1_SHIFT (13U)USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_TOG_RSVD2_SHIFT (21U)USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)USBPHY_TX_D_CAL_MASK (0xFU)USBPHY_TX_D_CAL_SHIFT (0U)USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)USBPHY_TX_RSVD0_MASK (0xF0U)USBPHY_TX_RSVD0_SHIFT (4U)USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)USBPHY_TX_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TXCAL45DN_SHIFT (8U)USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)USBPHY_TX_RSVD1_MASK (0xF000U)USBPHY_TX_RSVD1_SHIFT (12U)USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)USBPHY_TX_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TXCAL45DP_SHIFT (16U)USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)USBPHY_TX_RSVD2_MASK (0x3F00000U)USBPHY_TX_RSVD2_SHIFT (20U)USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_RSVD5_MASK (0xE0000000U)USBPHY_TX_RSVD5_SHIFT (29U)USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)USBPHY_TX_SET_D_CAL_MASK (0xFU)USBPHY_TX_SET_D_CAL_SHIFT (0U)USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)USBPHY_TX_SET_RSVD0_MASK (0xF0U)USBPHY_TX_SET_RSVD0_SHIFT (4U)USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)USBPHY_TX_SET_RSVD1_MASK (0xF000U)USBPHY_TX_SET_RSVD1_SHIFT (12U)USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)USBPHY_TX_SET_RSVD2_SHIFT (20U)USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)«USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)ëUSBPHY_TX_SET_RSVD5_MASK (0xE0000000U)īUSBPHY_TX_SET_RSVD5_SHIFT (29U)ūUSBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)ʫUSBPHY_TX_CLR_D_CAL_MASK (0xFU)˫USBPHY_TX_CLR_D_CAL_SHIFT (0U)̫USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)ͫUSBPHY_TX_CLR_RSVD0_MASK (0xF0U)ΫUSBPHY_TX_CLR_RSVD0_SHIFT (4U)ϫUSBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)ЫUSBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)ѫUSBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)ҫUSBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)ӫUSBPHY_TX_CLR_RSVD1_MASK (0xF000U)ԫUSBPHY_TX_CLR_RSVD1_SHIFT (12U)իUSBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)֫USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)׫USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)ثUSBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)٫USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)ګUSBPHY_TX_CLR_RSVD2_SHIFT (20U)۫USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)ܫUSBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)ݫUSBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)ޫUSBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)߫USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)USBPHY_TX_CLR_RSVD5_SHIFT (29U)USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)USBPHY_TX_TOG_D_CAL_MASK (0xFU)USBPHY_TX_TOG_D_CAL_SHIFT (0U)USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)USBPHY_TX_TOG_RSVD0_MASK (0xF0U)USBPHY_TX_TOG_RSVD0_SHIFT (4U)USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)USBPHY_TX_TOG_RSVD1_MASK (0xF000U)USBPHY_TX_TOG_RSVD1_SHIFT (12U)USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)USBPHY_TX_TOG_RSVD2_SHIFT (20U)USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)USBPHY_TX_TOG_RSVD5_SHIFT (29U)USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)USBPHY_RX_ENVADJ_MASK (0x7U)USBPHY_RX_ENVADJ_SHIFT (0U)USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)USBPHY_RX_RSVD0_MASK (0x8U)USBPHY_RX_RSVD0_SHIFT (3U)USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)USBPHY_RX_DISCONADJ_MASK (0x70U)USBPHY_RX_DISCONADJ_SHIFT (4U)USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)USBPHY_RX_RSVD1_MASK (0x3FFF80U)USBPHY_RX_RSVD1_SHIFT (7U)USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)USBPHY_RX_RXDBYPASS_MASK (0x400000U)USBPHY_RX_RXDBYPASS_SHIFT (22U)USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)USBPHY_RX_RSVD2_MASK (0xFF800000U)USBPHY_RX_RSVD2_SHIFT (23U)USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)USBPHY_RX_SET_ENVADJ_MASK (0x7U)USBPHY_RX_SET_ENVADJ_SHIFT (0U)USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)USBPHY_RX_SET_RSVD0_MASK (0x8U)USBPHY_RX_SET_RSVD0_SHIFT (3U)USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)USBPHY_RX_SET_DISCONADJ_MASK (0x70U)USBPHY_RX_SET_DISCONADJ_SHIFT (4U)USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)USBPHY_RX_SET_RSVD1_SHIFT (7U)USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)USBPHY_RX_SET_RSVD2_SHIFT (23U)USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)USBPHY_RX_CLR_ENVADJ_MASK (0x7U)USBPHY_RX_CLR_ENVADJ_SHIFT (0U)USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)USBPHY_RX_CLR_RSVD0_MASK (0x8U)USBPHY_RX_CLR_RSVD0_SHIFT (3U)USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)USBPHY_RX_CLR_RSVD1_SHIFT (7U)USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)USBPHY_RX_CLR_RSVD2_SHIFT (23U)USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)ĬUSBPHY_RX_TOG_ENVADJ_MASK (0x7U)ŬUSBPHY_RX_TOG_ENVADJ_SHIFT (0U)ƬUSBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)ǬUSBPHY_RX_TOG_RSVD0_MASK (0x8U)ȬUSBPHY_RX_TOG_RSVD0_SHIFT (3U)ɬUSBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)ʬUSBPHY_RX_TOG_DISCONADJ_MASK (0x70U)ˬUSBPHY_RX_TOG_DISCONADJ_SHIFT (4U)̬USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)ͬUSBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)άUSBPHY_RX_TOG_RSVD1_SHIFT (7U)ϬUSBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)ЬUSBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)ѬUSBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)ҬUSBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)ӬUSBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)ԬUSBPHY_RX_TOG_RSVD2_SHIFT (23U)լUSBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)ڬUSBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)۬USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)ܬUSBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)ݬUSBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)ެUSBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)߬USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)USBPHY_CTRL_RSVD1_MASK (0x6000000U)USBPHY_CTRL_RSVD1_SHIFT (25U)USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)USBPHY_CTRL_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SFTRST_SHIFT (31U)USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)­USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)íUSBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)ĭUSBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)ŭUSBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)ƭUSBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)ǭUSBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)ȭUSBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)ɭUSBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)ʭUSBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)˭USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)̭USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)ͭUSBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)έUSBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)ϭUSBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)ЭUSBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)ѭUSBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)ҭUSBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)ӭUSBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)ԭUSBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)խUSBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)֭USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)׭USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)حUSBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)٭USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)ڭUSBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)ۭUSBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)ܭUSBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)ݭUSBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)ޭUSBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)߭USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)USBPHY_CTRL_SET_RSVD1_SHIFT (25U)USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SET_SFTRST_SHIFT (31U)USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)®USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)îUSBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)ĮUSBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)ŮUSBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)ƮUSBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)ǮUSBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)ȮUSBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)ɮUSBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)ʮUSBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)ˮUSBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)̮USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)ͮUSBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)ήUSBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)ϮUSBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)ЮUSBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)ѮUSBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)ҮUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)ӮUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)ԮUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)ծUSBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)֮USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)׮USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)خUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)ٮUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)ڮUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)ۮUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)ܮUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)ݮUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)ޮUSBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)߮USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)¯USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)ïUSBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)įUSBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)ůUSBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)ƯUSBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)ǯUSBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)ȯUSBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)ɯUSBPHY_CTRL_TOG_RSVD1_SHIFT (25U)ʯUSBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)˯USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)̯USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)ͯUSBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)ίUSBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)ϯUSBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)ЯUSBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)ѯUSBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)үUSBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)ӯUSBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)ԯUSBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)կUSBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)֯USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)ׯUSBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)دUSBPHY_CTRL_TOG_SFTRST_SHIFT (31U)ٯUSBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)ޯUSBPHY_STATUS_RSVD0_MASK (0x7U)߯USBPHY_STATUS_RSVD0_SHIFT (0U)USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)USBPHY_STATUS_RSVD1_MASK (0x30U)USBPHY_STATUS_RSVD1_SHIFT (4U)USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)USBPHY_STATUS_RSVD2_MASK (0x80U)USBPHY_STATUS_RSVD2_SHIFT (7U)USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)USBPHY_STATUS_RSVD3_MASK (0x200U)USBPHY_STATUS_RSVD3_SHIFT (9U)USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)USBPHY_STATUS_RSVD4_SHIFT (11U)USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_RSVD0_SHIFT (6U)USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_RSVD1_SHIFT (13U)USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_RSVD2_SHIFT (21U)USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)USBPHY_DEBUG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_RSVD3_SHIFT (31U)USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)°USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)ðUSBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)İUSBPHY_DEBUG_SET_RSVD1_SHIFT (13U)ŰUSBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)ưUSBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)ǰUSBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)ȰUSBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)ɰUSBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)ʰUSBPHY_DEBUG_SET_RSVD2_SHIFT (21U)˰USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)̰USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)ͰUSBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)ΰUSBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)ϰUSBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)аUSBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)ѰUSBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)ҰUSBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)ӰUSBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)԰USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)հUSBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)ְUSBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)װUSBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)ذUSBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)ٰUSBPHY_DEBUG_SET_RSVD3_SHIFT (31U)ڰUSBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)߰USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)±USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)ñUSBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)ıUSBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)űUSBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)ƱUSBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)DZUSBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)ȱUSBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)ɱUSBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)αUSBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)ϱUSBPHY_DEBUG1_RSVD0_SHIFT (0U)бUSBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)ѱUSBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)ұUSBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)ӱUSBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)ԱUSBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)ձUSBPHY_DEBUG1_RSVD1_SHIFT (15U)ֱUSBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)۱USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)ܱUSBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)ݱUSBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)ޱUSBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)߱USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)USBPHY_VERSION_STEP_MASK (0xFFFFU)USBPHY_VERSION_STEP_SHIFT (0U)USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)USBPHY_VERSION_MINOR_MASK (0xFF0000U)USBPHY_VERSION_MINOR_SHIFT (16U)USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)USBPHY_VERSION_MAJOR_MASK (0xFF000000U)USBPHY_VERSION_MAJOR_SHIFT (24U)USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)USBPHY_BASE (0x400D9000u)USBPHY ((USBPHY_Type *)USBPHY_BASE)USBPHY_BASE_ADDRS { 0u, USBPHY_BASE }USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY }USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn }USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASKUSBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFTUSBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASKUSBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFTUSBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)زUSB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)ٲUSB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)ڲUSB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)۲USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)ܲUSB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)ݲUSB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)޲USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)߲USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_COUNT (2U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)USB_ANALOG_CHRG_DETECT_COUNT (2U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)ijUSB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)ųUSB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)ƳUSB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)dzUSB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)ȳUSB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)ɳUSB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)ʳUSB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)˳USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)̳USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)гUSB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)ԳUSB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)ճUSB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)ֳUSB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)׳USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)سUSB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)ٳUSB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)ڳUSB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)۳USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)ܳUSB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_COUNT (2U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_SET_COUNT (2U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_CLR_COUNT (2U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)´USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)ƴUSB_ANALOG_MISC_TOG_COUNT (2U)ʴUSB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)˴USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)̴USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)״USB_ANALOG_BASE (0x400D8000u)ٴUSB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)۴USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }ݴUSB_ANALOG_BASE_PTRS { USB_ANALOG }USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)USDHC_BLK_ATT_BLKCNT_SHIFT (16U)USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)USDHC_CMD_ARG_CMDARG_SHIFT (0U)USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)µUSDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)õUSDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)ĵUSDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)ŵUSDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)ʵUSDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)˵USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)̵USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)ѵUSDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)ҵUSDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)ӵUSDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)صUSDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)ٵUSDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)ڵUSDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)ߵUSDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)USDHC_PRES_STATE_CIHB_MASK (0x1U)USDHC_PRES_STATE_CIHB_SHIFT (0U)USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)USDHC_PRES_STATE_CDIHB_MASK (0x2U)USDHC_PRES_STATE_CDIHB_SHIFT (1U)USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)USDHC_PRES_STATE_DLA_MASK (0x4U)USDHC_PRES_STATE_DLA_SHIFT (2U)USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)USDHC_PRES_STATE_SDSTB_MASK (0x8U)USDHC_PRES_STATE_SDSTB_SHIFT (3U)USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)USDHC_PRES_STATE_IPGOFF_MASK (0x10U)USDHC_PRES_STATE_IPGOFF_SHIFT (4U)USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)USDHC_PRES_STATE_HCKOFF_MASK (0x20U)USDHC_PRES_STATE_HCKOFF_SHIFT (5U)USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)USDHC_PRES_STATE_PEROFF_MASK (0x40U)USDHC_PRES_STATE_PEROFF_SHIFT (6U)USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)USDHC_PRES_STATE_SDOFF_MASK (0x80U)USDHC_PRES_STATE_SDOFF_SHIFT (7U)USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)USDHC_PRES_STATE_WTA_MASK (0x100U)USDHC_PRES_STATE_WTA_SHIFT (8U)USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)USDHC_PRES_STATE_RTA_MASK (0x200U)USDHC_PRES_STATE_RTA_SHIFT (9U)USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)USDHC_PRES_STATE_BWEN_MASK (0x400U)USDHC_PRES_STATE_BWEN_SHIFT (10U)USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)USDHC_PRES_STATE_BREN_MASK (0x800U)USDHC_PRES_STATE_BREN_SHIFT (11U)USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)USDHC_PRES_STATE_RTR_MASK (0x1000U)USDHC_PRES_STATE_RTR_SHIFT (12U)USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)USDHC_PRES_STATE_TSCD_MASK (0x8000U)USDHC_PRES_STATE_TSCD_SHIFT (15U)USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)USDHC_PRES_STATE_CINST_MASK (0x10000U)USDHC_PRES_STATE_CINST_SHIFT (16U)USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)USDHC_PRES_STATE_CDPL_MASK (0x40000U)USDHC_PRES_STATE_CDPL_SHIFT (18U)USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)USDHC_PRES_STATE_WPSPL_MASK (0x80000U)USDHC_PRES_STATE_WPSPL_SHIFT (19U)USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)USDHC_PRES_STATE_CLSL_MASK (0x800000U)USDHC_PRES_STATE_CLSL_SHIFT (23U)USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)USDHC_PRES_STATE_DLSL_SHIFT (24U)USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)USDHC_PROT_CTRL_LCTL_MASK (0x1U)USDHC_PROT_CTRL_LCTL_SHIFT (0U)USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)USDHC_PROT_CTRL_DTW_MASK (0x6U)USDHC_PROT_CTRL_DTW_SHIFT (1U)USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)USDHC_PROT_CTRL_D3CD_MASK (0x8U)USDHC_PROT_CTRL_D3CD_SHIFT (3U)USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)USDHC_PROT_CTRL_EMODE_MASK (0x30U)USDHC_PROT_CTRL_EMODE_SHIFT (4U)USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)USDHC_PROT_CTRL_CDTL_MASK (0x40U)USDHC_PROT_CTRL_CDTL_SHIFT (6U)USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)USDHC_PROT_CTRL_CDSS_MASK (0x80U)USDHC_PROT_CTRL_CDSS_SHIFT (7U)USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)USDHC_PROT_CTRL_DMASEL_MASK (0x300U)USDHC_PROT_CTRL_DMASEL_SHIFT (8U)USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)¶USDHC_PROT_CTRL_CREQ_MASK (0x20000U)öUSDHC_PROT_CTRL_CREQ_SHIFT (17U)ĶUSDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)ŶUSDHC_PROT_CTRL_RWCTL_MASK (0x40000U)ƶUSDHC_PROT_CTRL_RWCTL_SHIFT (18U)ǶUSDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)ȶUSDHC_PROT_CTRL_IABG_MASK (0x80000U)ɶUSDHC_PROT_CTRL_IABG_SHIFT (19U)ʶUSDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)˶USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)̶USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)ͶUSDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)ζUSDHC_PROT_CTRL_WECINT_MASK (0x1000000U)϶USDHC_PROT_CTRL_WECINT_SHIFT (24U)жUSDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)ѶUSDHC_PROT_CTRL_WECINS_MASK (0x2000000U)ҶUSDHC_PROT_CTRL_WECINS_SHIFT (25U)ӶUSDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)ԶUSDHC_PROT_CTRL_WECRM_MASK (0x4000000U)նUSDHC_PROT_CTRL_WECRM_SHIFT (26U)ֶUSDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)׶USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)ضUSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)ٶUSDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)ڶUSDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)۶USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)ܶUSDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)USDHC_SYS_CTRL_DVS_MASK (0xF0U)USDHC_SYS_CTRL_DVS_SHIFT (4U)USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)USDHC_SYS_CTRL_DTOCV_SHIFT (16U)USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)USDHC_SYS_CTRL_RSTA_SHIFT (24U)USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)USDHC_SYS_CTRL_RSTC_SHIFT (25U)USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)USDHC_SYS_CTRL_RSTD_SHIFT (26U)USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)USDHC_SYS_CTRL_INITA_MASK (0x8000000U)USDHC_SYS_CTRL_INITA_SHIFT (27U)USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)USDHC_SYS_CTRL_RSTT_SHIFT (28U)USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)USDHC_INT_STATUS_CC_MASK (0x1U)USDHC_INT_STATUS_CC_SHIFT (0U)USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)USDHC_INT_STATUS_TC_MASK (0x2U)USDHC_INT_STATUS_TC_SHIFT (1U)USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)USDHC_INT_STATUS_BGE_MASK (0x4U)USDHC_INT_STATUS_BGE_SHIFT (2U)USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)USDHC_INT_STATUS_DINT_MASK (0x8U)USDHC_INT_STATUS_DINT_SHIFT (3U)USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)USDHC_INT_STATUS_BWR_MASK (0x10U)USDHC_INT_STATUS_BWR_SHIFT (4U)USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)USDHC_INT_STATUS_BRR_MASK (0x20U)USDHC_INT_STATUS_BRR_SHIFT (5U)USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)USDHC_INT_STATUS_CINS_MASK (0x40U)USDHC_INT_STATUS_CINS_SHIFT (6U)USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)USDHC_INT_STATUS_CRM_MASK (0x80U)USDHC_INT_STATUS_CRM_SHIFT (7U)USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)USDHC_INT_STATUS_CINT_MASK (0x100U)USDHC_INT_STATUS_CINT_SHIFT (8U)USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)USDHC_INT_STATUS_RTE_MASK (0x1000U)USDHC_INT_STATUS_RTE_SHIFT (12U)USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)USDHC_INT_STATUS_TP_MASK (0x4000U)USDHC_INT_STATUS_TP_SHIFT (14U)USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)USDHC_INT_STATUS_CTOE_MASK (0x10000U)USDHC_INT_STATUS_CTOE_SHIFT (16U)USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)USDHC_INT_STATUS_CCE_MASK (0x20000U)USDHC_INT_STATUS_CCE_SHIFT (17U)USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)USDHC_INT_STATUS_CEBE_MASK (0x40000U)USDHC_INT_STATUS_CEBE_SHIFT (18U)USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)USDHC_INT_STATUS_CIE_MASK (0x80000U)USDHC_INT_STATUS_CIE_SHIFT (19U)USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)USDHC_INT_STATUS_DTOE_MASK (0x100000U)USDHC_INT_STATUS_DTOE_SHIFT (20U)USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)USDHC_INT_STATUS_DCE_MASK (0x200000U)USDHC_INT_STATUS_DCE_SHIFT (21U)USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)USDHC_INT_STATUS_DEBE_MASK (0x400000U)USDHC_INT_STATUS_DEBE_SHIFT (22U)USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)USDHC_INT_STATUS_AC12E_MASK (0x1000000U)USDHC_INT_STATUS_AC12E_SHIFT (24U)USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)USDHC_INT_STATUS_TNE_MASK (0x4000000U)USDHC_INT_STATUS_TNE_SHIFT (26U)USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)USDHC_INT_STATUS_DMAE_MASK (0x10000000U)USDHC_INT_STATUS_DMAE_SHIFT (28U)USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)÷USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)ķUSDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)ŷUSDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)ƷUSDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)ǷUSDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)ȷUSDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)ɷUSDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)ʷUSDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)˷USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)̷USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)ͷUSDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)ηUSDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)ϷUSDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)зUSDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)ѷUSDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)ҷUSDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)ӷUSDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)ԷUSDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)շUSDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)ַUSDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)׷USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)طUSDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)ٷUSDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)ڷUSDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)۷USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)ܷUSDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)ݷUSDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)޷USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)߷USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)¸USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)øUSDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)ĸUSDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)ɸUSDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)ʸUSDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)˸USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)̸USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)͸USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)θUSDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)ϸUSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)иUSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)ѸUSDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)ҸUSDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)ӸUSDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)ԸUSDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)ոUSDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)ָUSDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)׸USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)ظUSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)ٸUSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)ڸUSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)۸USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)ܸUSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)ݸUSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)޸USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)߸USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)USDHC_WTMK_LVL_RD_WML_SHIFT (0U)USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)USDHC_WTMK_LVL_WR_WML_SHIFT (16U)USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)USDHC_MIX_CTRL_DMAEN_MASK (0x1U)USDHC_MIX_CTRL_DMAEN_SHIFT (0U)USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)USDHC_MIX_CTRL_BCEN_MASK (0x2U)USDHC_MIX_CTRL_BCEN_SHIFT (1U)USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)USDHC_MIX_CTRL_AC12EN_MASK (0x4U)USDHC_MIX_CTRL_AC12EN_SHIFT (2U)USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)USDHC_MIX_CTRL_AC23EN_MASK (0x80U)USDHC_MIX_CTRL_AC23EN_SHIFT (7U)USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)¹USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)ùUSDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)ĹUSDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)ŹUSDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)ƹUSDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)˹USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)̹USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)͹USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)ιUSDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)ϹUSDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)йUSDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)ѹUSDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)ҹUSDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)ӹUSDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)ԹUSDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)չUSDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)ֹUSDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)׹USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)عUSDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)ٹUSDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)ڹUSDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)۹USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)ܹUSDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)ݹUSDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)޹USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)߹USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)ºUSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)úUSDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)ȺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)ɺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)ʺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)˺USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)̺USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)ͺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)κUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)ϺUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)кUSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)ѺUSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)ҺUSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)ӺUSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)ԺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)պUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)ֺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)׺USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)غUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)ٺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)ںUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)ۺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)ܺUSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)ݺUSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)޺USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)ߺUSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)USDHC_VEND_SPEC_VSELECT_MASK (0x2U)USDHC_VEND_SPEC_VSELECT_SHIFT (1U)USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U)USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U)USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK)USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)»USDHC1_BASE (0x402C0000u)ĻUSDHC1 ((USDHC_Type *)USDHC1_BASE)ƻUSDHC2_BASE (0x402C4000u)ȻUSDHC2 ((USDHC_Type *)USDHC2_BASE)ʻUSDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }̻USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }λUSDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }WDOG_WCR_WDZST_MASK (0x1U)WDOG_WCR_WDZST_SHIFT (0U)WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)WDOG_WCR_WDBG_MASK (0x2U)WDOG_WCR_WDBG_SHIFT (1U)WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)WDOG_WCR_WDE_MASK (0x4U)WDOG_WCR_WDE_SHIFT (2U)WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)WDOG_WCR_WDT_MASK (0x8U)WDOG_WCR_WDT_SHIFT (3U)WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)WDOG_WCR_SRS_MASK (0x10U)WDOG_WCR_SRS_SHIFT (4U)WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)WDOG_WCR_WDA_MASK (0x20U)WDOG_WCR_WDA_SHIFT (5U)WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)WDOG_WCR_SRE_MASK (0x40U)WDOG_WCR_SRE_SHIFT (6U)WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)WDOG_WCR_WDW_MASK (0x80U)WDOG_WCR_WDW_SHIFT (7U)WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)WDOG_WCR_WT_MASK (0xFF00U)WDOG_WCR_WT_SHIFT (8U)WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)WDOG_WSR_WSR_MASK (0xFFFFU)WDOG_WSR_WSR_SHIFT (0U)WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)WDOG_WRSR_SFTW_MASK (0x1U)WDOG_WRSR_SFTW_SHIFT (0U)WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)WDOG_WRSR_TOUT_MASK (0x2U)WDOG_WRSR_TOUT_SHIFT (1U)WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)WDOG_WRSR_POR_MASK (0x10U)WDOG_WRSR_POR_SHIFT (4U)WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)WDOG_WICR_WICT_MASK (0xFFU)WDOG_WICR_WICT_SHIFT (0U)WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)WDOG_WICR_WTIS_MASK (0x4000U)WDOG_WICR_WTIS_SHIFT (14U)WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)WDOG_WICR_WIE_MASK (0x8000U)WDOG_WICR_WIE_SHIFT (15U)WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)WDOG_WMCR_PDE_MASK (0x1U)WDOG_WMCR_PDE_SHIFT (0U)WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)WDOG1_BASE (0x400B8000u)WDOG1 ((WDOG_Type *)WDOG1_BASE)üWDOG2_BASE (0x400D0000u)żWDOG2 ((WDOG_Type *)WDOG2_BASE)ǼWDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }ɼWDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }˼WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }XBARA_SEL0_SEL0_MASK (0x7FU)XBARA_SEL0_SEL0_SHIFT (0U)XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)XBARA_SEL0_SEL1_MASK (0x7F00U)XBARA_SEL0_SEL1_SHIFT (8U)XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)XBARA_SEL1_SEL2_MASK (0x7FU)XBARA_SEL1_SEL2_SHIFT (0U)XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)XBARA_SEL1_SEL3_MASK (0x7F00U)XBARA_SEL1_SEL3_SHIFT (8U)XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)½XBARA_SEL2_SEL4_MASK (0x7FU)ýXBARA_SEL2_SEL4_SHIFT (0U)ĽXBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)ŽXBARA_SEL2_SEL5_MASK (0x7F00U)ƽXBARA_SEL2_SEL5_SHIFT (8U)ǽXBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)̽XBARA_SEL3_SEL6_MASK (0x7FU)ͽXBARA_SEL3_SEL6_SHIFT (0U)νXBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)ϽXBARA_SEL3_SEL7_MASK (0x7F00U)нXBARA_SEL3_SEL7_SHIFT (8U)ѽXBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)ֽXBARA_SEL4_SEL8_MASK (0x7FU)׽XBARA_SEL4_SEL8_SHIFT (0U)ؽXBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)ٽXBARA_SEL4_SEL9_MASK (0x7F00U)ڽXBARA_SEL4_SEL9_SHIFT (8U)۽XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)XBARA_SEL5_SEL10_MASK (0x7FU)XBARA_SEL5_SEL10_SHIFT (0U)XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)XBARA_SEL5_SEL11_MASK (0x7F00U)XBARA_SEL5_SEL11_SHIFT (8U)XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)XBARA_SEL6_SEL12_MASK (0x7FU)XBARA_SEL6_SEL12_SHIFT (0U)XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)XBARA_SEL6_SEL13_MASK (0x7F00U)XBARA_SEL6_SEL13_SHIFT (8U)XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)XBARA_SEL7_SEL14_MASK (0x7FU)XBARA_SEL7_SEL14_SHIFT (0U)XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)XBARA_SEL7_SEL15_MASK (0x7F00U)XBARA_SEL7_SEL15_SHIFT (8U)XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)XBARA_SEL8_SEL16_MASK (0x7FU)XBARA_SEL8_SEL16_SHIFT (0U)XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)XBARA_SEL8_SEL17_MASK (0x7F00U)XBARA_SEL8_SEL17_SHIFT (8U)XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)XBARA_SEL9_SEL18_MASK (0x7FU)XBARA_SEL9_SEL18_SHIFT (0U)XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)XBARA_SEL9_SEL19_MASK (0x7F00U)XBARA_SEL9_SEL19_SHIFT (8U)XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)XBARA_SEL10_SEL20_MASK (0x7FU)XBARA_SEL10_SEL20_SHIFT (0U)XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)XBARA_SEL10_SEL21_MASK (0x7F00U)XBARA_SEL10_SEL21_SHIFT (8U)XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)XBARA_SEL11_SEL22_MASK (0x7FU)XBARA_SEL11_SEL22_SHIFT (0U)XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)XBARA_SEL11_SEL23_MASK (0x7F00U)XBARA_SEL11_SEL23_SHIFT (8U)XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)XBARA_SEL12_SEL24_MASK (0x7FU)XBARA_SEL12_SEL24_SHIFT (0U)XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)XBARA_SEL12_SEL25_MASK (0x7F00U)XBARA_SEL12_SEL25_SHIFT (8U)XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)XBARA_SEL13_SEL26_MASK (0x7FU)XBARA_SEL13_SEL26_SHIFT (0U)XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)XBARA_SEL13_SEL27_MASK (0x7F00U)XBARA_SEL13_SEL27_SHIFT (8U)XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)XBARA_SEL14_SEL28_MASK (0x7FU)XBARA_SEL14_SEL28_SHIFT (0U)XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)XBARA_SEL14_SEL29_MASK (0x7F00U)XBARA_SEL14_SEL29_SHIFT (8U)XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)ľXBARA_SEL15_SEL30_MASK (0x7FU)žXBARA_SEL15_SEL30_SHIFT (0U)ƾXBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)ǾXBARA_SEL15_SEL31_MASK (0x7F00U)ȾXBARA_SEL15_SEL31_SHIFT (8U)ɾXBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)ξXBARA_SEL16_SEL32_MASK (0x7FU)ϾXBARA_SEL16_SEL32_SHIFT (0U)оXBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)ѾXBARA_SEL16_SEL33_MASK (0x7F00U)ҾXBARA_SEL16_SEL33_SHIFT (8U)ӾXBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)ؾXBARA_SEL17_SEL34_MASK (0x7FU)پXBARA_SEL17_SEL34_SHIFT (0U)ھXBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)۾XBARA_SEL17_SEL35_MASK (0x7F00U)ܾXBARA_SEL17_SEL35_SHIFT (8U)ݾXBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)XBARA_SEL18_SEL36_MASK (0x7FU)XBARA_SEL18_SEL36_SHIFT (0U)XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)XBARA_SEL18_SEL37_MASK (0x7F00U)XBARA_SEL18_SEL37_SHIFT (8U)XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)XBARA_SEL19_SEL38_MASK (0x7FU)XBARA_SEL19_SEL38_SHIFT (0U)XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)XBARA_SEL19_SEL39_MASK (0x7F00U)XBARA_SEL19_SEL39_SHIFT (8U)XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)XBARA_SEL20_SEL40_MASK (0x7FU)XBARA_SEL20_SEL40_SHIFT (0U)XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)XBARA_SEL20_SEL41_MASK (0x7F00U)XBARA_SEL20_SEL41_SHIFT (8U)XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)XBARA_SEL21_SEL42_MASK (0x7FU)XBARA_SEL21_SEL42_SHIFT (0U)XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)XBARA_SEL21_SEL43_MASK (0x7F00U)XBARA_SEL21_SEL43_SHIFT (8U)XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)XBARA_SEL22_SEL44_MASK (0x7FU)XBARA_SEL22_SEL44_SHIFT (0U)XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)XBARA_SEL22_SEL45_MASK (0x7F00U)XBARA_SEL22_SEL45_SHIFT (8U)XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)XBARA_SEL23_SEL46_MASK (0x7FU)XBARA_SEL23_SEL46_SHIFT (0U)XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)XBARA_SEL23_SEL47_MASK (0x7F00U)XBARA_SEL23_SEL47_SHIFT (8U)XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)XBARA_SEL24_SEL48_MASK (0x7FU)XBARA_SEL24_SEL48_SHIFT (0U)XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)XBARA_SEL24_SEL49_MASK (0x7F00U)XBARA_SEL24_SEL49_SHIFT (8U)XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)XBARA_SEL25_SEL50_MASK (0x7FU)XBARA_SEL25_SEL50_SHIFT (0U)XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)XBARA_SEL25_SEL51_MASK (0x7F00U)XBARA_SEL25_SEL51_SHIFT (8U)XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)XBARA_SEL26_SEL52_MASK (0x7FU)XBARA_SEL26_SEL52_SHIFT (0U)XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)XBARA_SEL26_SEL53_MASK (0x7F00U)XBARA_SEL26_SEL53_SHIFT (8U)XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)XBARA_SEL27_SEL54_MASK (0x7FU)XBARA_SEL27_SEL54_SHIFT (0U)XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)XBARA_SEL27_SEL55_MASK (0x7F00U)XBARA_SEL27_SEL55_SHIFT (8U)XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)ƿXBARA_SEL28_SEL56_MASK (0x7FU)ǿXBARA_SEL28_SEL56_SHIFT (0U)ȿXBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)ɿXBARA_SEL28_SEL57_MASK (0x7F00U)ʿXBARA_SEL28_SEL57_SHIFT (8U)˿XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)пXBARA_SEL29_SEL58_MASK (0x7FU)ѿXBARA_SEL29_SEL58_SHIFT (0U)ҿXBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)ӿXBARA_SEL29_SEL59_MASK (0x7F00U)ԿXBARA_SEL29_SEL59_SHIFT (8U)տXBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)ڿXBARA_SEL30_SEL60_MASK (0x7FU)ۿXBARA_SEL30_SEL60_SHIFT (0U)ܿXBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)ݿXBARA_SEL30_SEL61_MASK (0x7F00U)޿XBARA_SEL30_SEL61_SHIFT (8U)߿XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)XBARA_SEL31_SEL62_MASK (0x7FU)XBARA_SEL31_SEL62_SHIFT (0U)XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)XBARA_SEL31_SEL63_MASK (0x7F00U)XBARA_SEL31_SEL63_SHIFT (8U)XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)XBARA_SEL32_SEL64_MASK (0x7FU)XBARA_SEL32_SEL64_SHIFT (0U)XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)XBARA_SEL32_SEL65_MASK (0x7F00U)XBARA_SEL32_SEL65_SHIFT (8U)XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)XBARA_SEL33_SEL66_MASK (0x7FU)XBARA_SEL33_SEL66_SHIFT (0U)XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)XBARA_SEL33_SEL67_MASK (0x7F00U)XBARA_SEL33_SEL67_SHIFT (8U)XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)XBARA_SEL34_SEL68_MASK (0x7FU)XBARA_SEL34_SEL68_SHIFT (0U)XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)XBARA_SEL34_SEL69_MASK (0x7F00U)XBARA_SEL34_SEL69_SHIFT (8U)XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)XBARA_SEL35_SEL70_MASK (0x7FU)XBARA_SEL35_SEL70_SHIFT (0U)XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)XBARA_SEL35_SEL71_MASK (0x7F00U)XBARA_SEL35_SEL71_SHIFT (8U)XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)XBARA_SEL36_SEL72_MASK (0x7FU)XBARA_SEL36_SEL72_SHIFT (0U)XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)XBARA_SEL36_SEL73_MASK (0x7F00U)XBARA_SEL36_SEL73_SHIFT (8U)XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)XBARA_SEL37_SEL74_MASK (0x7FU)XBARA_SEL37_SEL74_SHIFT (0U)XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)XBARA_SEL37_SEL75_MASK (0x7F00U)XBARA_SEL37_SEL75_SHIFT (8U)XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)XBARA_SEL38_SEL76_MASK (0x7FU)XBARA_SEL38_SEL76_SHIFT (0U)XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)XBARA_SEL38_SEL77_MASK (0x7F00U)XBARA_SEL38_SEL77_SHIFT (8U)XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)XBARA_SEL39_SEL78_MASK (0x7FU)XBARA_SEL39_SEL78_SHIFT (0U)XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)XBARA_SEL39_SEL79_MASK (0x7F00U)XBARA_SEL39_SEL79_SHIFT (8U)XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)XBARA_SEL40_SEL80_MASK (0x7FU)XBARA_SEL40_SEL80_SHIFT (0U)XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)XBARA_SEL40_SEL81_MASK (0x7F00U)XBARA_SEL40_SEL81_SHIFT (8U)XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)XBARA_SEL41_SEL82_MASK (0x7FU)XBARA_SEL41_SEL82_SHIFT (0U)XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)XBARA_SEL41_SEL83_MASK (0x7F00U)XBARA_SEL41_SEL83_SHIFT (8U)XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)XBARA_SEL42_SEL84_MASK (0x7FU)XBARA_SEL42_SEL84_SHIFT (0U)XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)XBARA_SEL42_SEL85_MASK (0x7F00U)XBARA_SEL42_SEL85_SHIFT (8U)XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)XBARA_SEL43_SEL86_MASK (0x7FU)XBARA_SEL43_SEL86_SHIFT (0U)XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)XBARA_SEL43_SEL87_MASK (0x7F00U)XBARA_SEL43_SEL87_SHIFT (8U)XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)XBARA_SEL44_SEL88_MASK (0x7FU)XBARA_SEL44_SEL88_SHIFT (0U)XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)XBARA_SEL44_SEL89_MASK (0x7F00U)XBARA_SEL44_SEL89_SHIFT (8U)XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)XBARA_SEL45_SEL90_MASK (0x7FU)XBARA_SEL45_SEL90_SHIFT (0U)XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)XBARA_SEL45_SEL91_MASK (0x7F00U)XBARA_SEL45_SEL91_SHIFT (8U)XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)XBARA_SEL46_SEL92_MASK (0x7FU)XBARA_SEL46_SEL92_SHIFT (0U)XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)XBARA_SEL46_SEL93_MASK (0x7F00U)XBARA_SEL46_SEL93_SHIFT (8U)XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)XBARA_SEL47_SEL94_MASK (0x7FU)XBARA_SEL47_SEL94_SHIFT (0U)XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)XBARA_SEL47_SEL95_MASK (0x7F00U)XBARA_SEL47_SEL95_SHIFT (8U)XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)XBARA_SEL48_SEL96_MASK (0x7FU)XBARA_SEL48_SEL96_SHIFT (0U)XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)XBARA_SEL48_SEL97_MASK (0x7F00U)XBARA_SEL48_SEL97_SHIFT (8U)XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)XBARA_SEL49_SEL98_MASK (0x7FU)XBARA_SEL49_SEL98_SHIFT (0U)XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)XBARA_SEL49_SEL99_MASK (0x7F00U)XBARA_SEL49_SEL99_SHIFT (8U)XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)XBARA_SEL50_SEL100_MASK (0x7FU)XBARA_SEL50_SEL100_SHIFT (0U)XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)XBARA_SEL50_SEL101_MASK (0x7F00U)XBARA_SEL50_SEL101_SHIFT (8U)XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)XBARA_SEL51_SEL102_MASK (0x7FU)XBARA_SEL51_SEL102_SHIFT (0U)XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)XBARA_SEL51_SEL103_MASK (0x7F00U)XBARA_SEL51_SEL103_SHIFT (8U)XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)XBARA_SEL52_SEL104_MASK (0x7FU)XBARA_SEL52_SEL104_SHIFT (0U)XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)XBARA_SEL52_SEL105_MASK (0x7F00U)XBARA_SEL52_SEL105_SHIFT (8U)XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)XBARA_SEL53_SEL106_MASK (0x7FU)XBARA_SEL53_SEL106_SHIFT (0U)XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)XBARA_SEL53_SEL107_MASK (0x7F00U)XBARA_SEL53_SEL107_SHIFT (8U)XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)XBARA_SEL54_SEL108_MASK (0x7FU)XBARA_SEL54_SEL108_SHIFT (0U)XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)XBARA_SEL54_SEL109_MASK (0x7F00U)XBARA_SEL54_SEL109_SHIFT (8U)XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)XBARA_SEL55_SEL110_MASK (0x7FU)XBARA_SEL55_SEL110_SHIFT (0U)XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)XBARA_SEL55_SEL111_MASK (0x7F00U)XBARA_SEL55_SEL111_SHIFT (8U)XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)XBARA_SEL56_SEL112_MASK (0x7FU)XBARA_SEL56_SEL112_SHIFT (0U)XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)XBARA_SEL56_SEL113_MASK (0x7F00U)XBARA_SEL56_SEL113_SHIFT (8U)XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)XBARA_SEL57_SEL114_MASK (0x7FU)XBARA_SEL57_SEL114_SHIFT (0U)XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)XBARA_SEL57_SEL115_MASK (0x7F00U)XBARA_SEL57_SEL115_SHIFT (8U)XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)XBARA_SEL58_SEL116_MASK (0x7FU)XBARA_SEL58_SEL116_SHIFT (0U)XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)XBARA_SEL58_SEL117_MASK (0x7F00U)XBARA_SEL58_SEL117_SHIFT (8U)XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)XBARA_SEL59_SEL118_MASK (0x7FU)XBARA_SEL59_SEL118_SHIFT (0U)XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)XBARA_SEL59_SEL119_MASK (0x7F00U)XBARA_SEL59_SEL119_SHIFT (8U)XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)XBARA_SEL60_SEL120_MASK (0x7FU)XBARA_SEL60_SEL120_SHIFT (0U)XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)XBARA_SEL60_SEL121_MASK (0x7F00U)XBARA_SEL60_SEL121_SHIFT (8U)XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)XBARA_SEL61_SEL122_MASK (0x7FU)XBARA_SEL61_SEL122_SHIFT (0U)XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)XBARA_SEL61_SEL123_MASK (0x7F00U)XBARA_SEL61_SEL123_SHIFT (8U)XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)XBARA_SEL62_SEL124_MASK (0x7FU)XBARA_SEL62_SEL124_SHIFT (0U)XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)XBARA_SEL62_SEL125_MASK (0x7F00U)XBARA_SEL62_SEL125_SHIFT (8U)XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)XBARA_SEL63_SEL126_MASK (0x7FU)XBARA_SEL63_SEL126_SHIFT (0U)XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)XBARA_SEL63_SEL127_MASK (0x7F00U)XBARA_SEL63_SEL127_SHIFT (8U)XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)XBARA_SEL64_SEL128_MASK (0x7FU)XBARA_SEL64_SEL128_SHIFT (0U)XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)XBARA_SEL64_SEL129_MASK (0x7F00U)XBARA_SEL64_SEL129_SHIFT (8U)XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)XBARA_SEL65_SEL130_MASK (0x7FU)XBARA_SEL65_SEL130_SHIFT (0U)XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)XBARA_SEL65_SEL131_MASK (0x7F00U)XBARA_SEL65_SEL131_SHIFT (8U)XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)XBARA_CTRL0_DEN0_MASK (0x1U)XBARA_CTRL0_DEN0_SHIFT (0U)XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)XBARA_CTRL0_IEN0_MASK (0x2U)XBARA_CTRL0_IEN0_SHIFT (1U)XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)XBARA_CTRL0_EDGE0_MASK (0xCU)XBARA_CTRL0_EDGE0_SHIFT (2U)XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)XBARA_CTRL0_STS0_MASK (0x10U)XBARA_CTRL0_STS0_SHIFT (4U)XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)XBARA_CTRL0_DEN1_MASK (0x100U)XBARA_CTRL0_DEN1_SHIFT (8U)XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)XBARA_CTRL0_IEN1_MASK (0x200U)XBARA_CTRL0_IEN1_SHIFT (9U)XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)XBARA_CTRL0_EDGE1_MASK (0xC00U)XBARA_CTRL0_EDGE1_SHIFT (10U)XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)XBARA_CTRL0_STS1_MASK (0x1000U)XBARA_CTRL0_STS1_SHIFT (12U)XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)XBARA_CTRL1_DEN2_MASK (0x1U)XBARA_CTRL1_DEN2_SHIFT (0U)XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)XBARA_CTRL1_IEN2_MASK (0x2U)XBARA_CTRL1_IEN2_SHIFT (1U)XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)XBARA_CTRL1_EDGE2_MASK (0xCU)XBARA_CTRL1_EDGE2_SHIFT (2U)XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)XBARA_CTRL1_STS2_MASK (0x10U)XBARA_CTRL1_STS2_SHIFT (4U)XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)XBARA_CTRL1_DEN3_MASK (0x100U)XBARA_CTRL1_DEN3_SHIFT (8U)XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)XBARA_CTRL1_IEN3_MASK (0x200U)XBARA_CTRL1_IEN3_SHIFT (9U)XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)XBARA_CTRL1_EDGE3_MASK (0xC00U)XBARA_CTRL1_EDGE3_SHIFT (10U)XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)XBARA_CTRL1_STS3_MASK (0x1000U)XBARA_CTRL1_STS3_SHIFT (12U)XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)XBARA_BASE (0x403BC000u)XBARA ((XBARA_Type *)XBARA_BASE)XBARA_BASE_ADDRS { XBARA_BASE }XBARA_BASE_PTRS { XBARA }XBARB_SEL0_SEL0_MASK (0x3FU)XBARB_SEL0_SEL0_SHIFT (0U)XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)XBARB_SEL0_SEL1_MASK (0x3F00U)XBARB_SEL0_SEL1_SHIFT (8U)XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)XBARB_SEL1_SEL2_MASK (0x3FU)XBARB_SEL1_SEL2_SHIFT (0U)XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)XBARB_SEL1_SEL3_MASK (0x3F00U)XBARB_SEL1_SEL3_SHIFT (8U)XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)XBARB_SEL2_SEL4_MASK (0x3FU)XBARB_SEL2_SEL4_SHIFT (0U)XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)XBARB_SEL2_SEL5_MASK (0x3F00U)XBARB_SEL2_SEL5_SHIFT (8U)XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)XBARB_SEL3_SEL6_MASK (0x3FU)XBARB_SEL3_SEL6_SHIFT (0U)XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)XBARB_SEL3_SEL7_MASK (0x3F00U)XBARB_SEL3_SEL7_SHIFT (8U)XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)XBARB_SEL4_SEL8_MASK (0x3FU)XBARB_SEL4_SEL8_SHIFT (0U)XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)XBARB_SEL4_SEL9_MASK (0x3F00U)XBARB_SEL4_SEL9_SHIFT (8U)XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)XBARB_SEL5_SEL10_MASK (0x3FU)XBARB_SEL5_SEL10_SHIFT (0U)XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)XBARB_SEL5_SEL11_MASK (0x3F00U)XBARB_SEL5_SEL11_SHIFT (8U)XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)XBARB_SEL6_SEL12_MASK (0x3FU)XBARB_SEL6_SEL12_SHIFT (0U)XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)XBARB_SEL6_SEL13_MASK (0x3F00U)XBARB_SEL6_SEL13_SHIFT (8U)XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)XBARB_SEL7_SEL14_MASK (0x3FU)XBARB_SEL7_SEL14_SHIFT (0U)XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)XBARB_SEL7_SEL15_MASK (0x3F00U)XBARB_SEL7_SEL15_SHIFT (8U)XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)XBARB_BASE (0x403C0000u)XBARB ((XBARB_Type *)XBARB_BASE)XBARB_BASE_ADDRS { XBARB_BASE }XBARB_BASE_PTRS { XBARB }XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)XTALOSC24M_BASE (0x400D8000u)XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }XTALOSC24M_BASE_PTRS { XTALOSC24M }NXP_VAL2FLD(field,value) (((value) << (field ## _SHIFT)) & (field ## _MASK))NXP_FLD2VAL(field,value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) __stdint_h  __ARMCLIB_VERSION 5060037__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS sINT8_MIN -128tINT16_MIN -32768uINT32_MIN (~0x7fffffff)vINT64_MIN __INT64_C(~0x7fffffffffffffff)yINT8_MAX 127zINT16_MAX 32767{INT32_MAX 2147483647|INT64_MAX __INT64_C(9223372036854775807)UINT8_MAX 255UINT16_MAX 65535UINT32_MAX 4294967295uUINT64_MAX __UINT64_C(18446744073709551615)INT_LEAST8_MIN -128INT_LEAST16_MIN -32768INT_LEAST32_MIN (~0x7fffffff)INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_LEAST8_MAX 127INT_LEAST16_MAX 32767INT_LEAST32_MAX 2147483647INT_LEAST64_MAX __INT64_C(9223372036854775807)UINT_LEAST8_MAX 255UINT_LEAST16_MAX 65535UINT_LEAST32_MAX 4294967295uUINT_LEAST64_MAX __UINT64_C(18446744073709551615)INT_FAST8_MIN (~0x7fffffff)INT_FAST16_MIN (~0x7fffffff)INT_FAST32_MIN (~0x7fffffff)INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_FAST8_MAX 2147483647INT_FAST16_MAX 2147483647INT_FAST32_MAX 2147483647INT_FAST64_MAX __INT64_C(9223372036854775807)UINT_FAST8_MAX 4294967295uUINT_FAST16_MAX 4294967295uUINT_FAST32_MAX 4294967295uUINT_FAST64_MAX __UINT64_C(18446744073709551615)INTPTR_MIN INT32_MININTPTR_MAX INT32_MAXUINTPTR_MAX UINT32_MAXINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)INTMAX_MAX __ESCAPE__(9223372036854775807ll)UINTMAX_MAX __ESCAPE__(18446744073709551615ull)PTRDIFF_MIN INT32_MINPTRDIFF_MAX INT32_MAXSIG_ATOMIC_MIN (~0x7fffffff)SIG_ATOMIC_MAX 2147483647SIZE_MAX UINT32_MAXWCHAR_MINWCHAR_MAXWCHAR_MIN 0WCHAR_MAX 65535WINT_MIN (~0x7fffffff)WINT_MAX 2147483647INT8_C(x) (x)INT16_C(x) (x)INT32_C(x) (x)INT64_C(x) __INT64_C(x)UINT8_C(x) (x ## u)UINT16_C(x) (x ## u)UINT32_C(x) (x ## u)UINT64_C(x) __UINT64_C(x)INTMAX_C(x) __ESCAPE__(x ## ll)UINTMAX_C(x) __ESCAPE__(x ## ull)__INT64__LONGLONG VERS 1 UNKNOWN 0ONCHIP 1EXT8BIT 2EXT16BIT 3EXT32BIT 4EXTSPI 5SECTOR_NUM 512PAGE_MAX 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flexspi_nor_write_persistentcflexspi_nor_read_persistent^/ flexspi_clock_gate_enable>flexspi_clock_gate_disablerget_core_clock/1g_xtalFreq*g_rtcXtalFreq̗clock_initqflexspi_clock_configflexspi_get_clockflexspi_get_max_supported_freqget_bus_clockflexspi_sw_delay_us<Ip)CLOCK_InitUsb1PllPCLOCK_DeinitUsb1Pll%CLOCK_GetPllFreqCLOCK_GetSysPfdFreqeCLOCK_GetUsb1PfdFreqCLOCK_InitExternalClkXCLOCK_DeinitExternalClkCLOCK_SwitchOscCLOCK_InitRcOsc24MCLOCK_DeinitRcOsc24M CLOCK_GetFreq}CLOCK_InitSysPllCLOCK_DeinitSysPll CLOCK_InitAudioPlliCLOCK_DeinitAudioPllCLOCK_InitEnetPllCLOCK_DeinitEnetPllCLOCK_InitSysPfdpCLOCK_DeinitSysPfdCLOCK_InitUsb1PfdCLOCK_DeinitUsb1PfdGCLOCK_EnableUsbhs0ClockCLOCK_EnableUsbhs0PhyPllClock;CLOCK_DisableUsbhs0PhyPllClock/T g_xtalFreqg_rtcXtalFreqīFlashDevicePInitoUnInitEraseChipEraseSector4ProgramPageDconfig.L0dx  4 H 0<$8""$%4'l'|,,1,122J447777t8998*T6p<9AL9W<*X6LvLt899X8(8@*\)6L8(KD*`p6 H*d6H s 6 d! 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:)80PY8e9p9~999$t$d$d.realdataFlashPrg.c.rev16_text.revsh_text.text.bssFlashDev.c.constdatadevices\\MIMXRT1021\\drivers\\fsl_clock.cdevices\MIMXRT1021\drivers\fsl_clock.cCLOCK_GetPeriphClkFreqCLOCK_GetOscFreq.datai.__ARM_common_switch8i.__ARM_common_ll_muluubsp\\src\\clock_config_MIMXRT1021.cbsp\src\clock_config_MIMXRT1021.cbsp\\src\\hardware_init_MIMXRT1021.cbsp\src\hardware_init_MIMXRT1021.cmiddleware\\flexspi_nor\\flexspi_nor_flash.cmiddleware\flexspi_nor\flexspi_nor_flash.cflexspi_nor_exit_no_cmd_modeflexspi_nor_write_enableflexspi_nor_restore_no_cmd_modeflexspi_nor_wait_busyflexspi_change_serial_clockflexspi_nor_read_sfdpprepare_quad_mode_enable_sequenceprobe_dtr_quad_read_dummy_cyclesparse_sfdpflexspi_nor_read_sfdp_infoflexspi_nor_generate_config_block_hyperflashflexspi_nor_generate_config_block_mxic_octalflashflexspi_nor_generate_config_block_micron_octalflashflexspi_nor_generate_config_block_adesto_octalflashprepare_0_4_4_mode_enable_sequenceflexspi_nor_generate_config_block_using_sfdpflexspi_nor_hyperbus_readflexspi_nor_hyperbus_writemiddleware\\flexspi\\fsl_flexspi.cmiddleware\flexspi\fsl_flexspi.cflexspi_device_cmd_configflexspi_swresetflexspi_get_module_baseflexspi_wait_until_ip_idleflexspi_device_workmode_configg_flexSpiInstancesdevices\\MIMXRT1021\\system_MIMXRT1021.cdevices\MIMXRT1021\system_MIMXRT1021.cdc.s../clib/division.c../clib/stdlib.c../clib/string.c../clib/memcpset.c.emb_text../clib/division.s../clib/angel/sysapp.c../clib/angel/rt.s../clib/signal.c../clib/angel/sys.s../clib/signal.sBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$RWPI$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2__aeabi_memcpy4__aeabi_memcpy8__asm___10_FlashPrg_c_Init____REV16__asm___11_fsl_clock_c_07a918fd____REV16__asm___25_clock_config_MIMXRT1021_c_efd8dd31____REV16__asm___26_hardware_init_MIMXRT1021_c_753bbbb7____REV16__asm___19_flexspi_nor_flash_c_93f2e184____REV16__asm___13_fsl_flexspi_c_c729c902____REV16__asm___19_system_MIMXRT1021_c_5d646a67____REV16__asm___10_FlashPrg_c_Init____REVSH__asm___11_fsl_clock_c_07a918fd____REVSH__asm___25_clock_config_MIMXRT1021_c_efd8dd31____REVSH__asm___26_hardware_init_MIMXRT1021_c_753bbbb7____REVSH__asm___19_flexspi_nor_flash_c_93f2e184____REVSH__asm___13_fsl_flexspi_c_c729c902____REVSH__asm___19_system_MIMXRT1021_c_5d646a67____REVSHInitUnInitEraseChipEraseSectorProgramPageCLOCK_GetPllFreqCLOCK_GetSysPfdFreqCLOCK_GetUsb1PfdFreqCLOCK_InitExternalClkCLOCK_DeinitExternalClkCLOCK_SwitchOscCLOCK_InitRcOsc24MCLOCK_DeinitRcOsc24MCLOCK_GetFreqCLOCK_InitSysPllCLOCK_DeinitSysPllCLOCK_InitUsb1PllCLOCK_DeinitUsb1PllCLOCK_InitAudioPllCLOCK_DeinitAudioPllCLOCK_InitEnetPllCLOCK_DeinitEnetPllCLOCK_InitSysPfdCLOCK_DeinitSysPfdCLOCK_InitUsb1PfdCLOCK_DeinitUsb1PfdCLOCK_EnableUsbhs0ClockCLOCK_EnableUsbhs0PhyPllClockCLOCK_DisableUsbhs0PhyPllClockclock_initflexspi_clock_gate_enableflexspi_clock_gate_disableflexspi_clock_configflexspi_get_clockflexspi_get_max_supported_freqget_core_clockget_bus_clockflexspi_sw_delay_usflexspi_iomux_configflexspi_set_failsafe_settingflexspi_nor_write_persistentflexspi_nor_read_persistentflexspi_nor_flash_initflexspi_nor_flash_page_programflexspi_nor_flash_erase_allflexspi_nor_flash_erase_sectorflexspi_nor_flash_erase_blockget_page_sector_block_size_from_sfdpflexspi_nor_restore_spi_protocolflexspi_nor_get_configflexspi_nor_flash_eraseflexspi_nor_flash_readflexspi_is_parallel_modeflexspi_is_padsetting_override_enableflexspi_is_differential_clock_enableflexspi_is_word_addressableflexspi_is_ck2_enabledflexspi_is_ddr_mode_enableflexspi_configure_dllflexspi_get_ticksflexspi_config_mcr1flexspi_config_flash_control_registersflexspi_config_ahb_buffersflexspi_clear_sequence_pointerflexspi_command_xferflexspi_update_lutflexspi_device_write_enableflexspi_device_wait_busyflexspi_initflexspi_wait_idleflexspi_clear_cacheflexspi_half_clock_controlSystemInitHookSystemInitSystemCoreClockUpdate__aeabi_uldivmod_ll_udivabortmemcmp_memset_w_memset__aeabi_memclr__rt_memclr__aeabi_memclr4__aeabi_memclr8__rt_memclr_w__aeabi_uidiv__aeabi_uidivmod__aeabi_idiv__aeabi_idivmod_sys_exit__rt_SIGABRT__I$use$semihosting__use_no_semihosting_swi__semihosting_library_function__sig_exit__rt_SIGABRT_inner__default_signal_display_ttywrch__ARM_common_ll_muluu__ARM_common_switch8g_xtalFreqg_rtcXtalFreqSystemCoreClockFlashDeviceconfig@ARMComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]ArmLink --strict --load_addr_map_info --map --symbols --diag_suppress=9931,L6305 --cpu=Cortex-M0 --list=.\MIMXRT1021_QSPI.map --output=.\Output\MIMXRT1021_QSPI.axf --scatter=.\Target.lin --info=summarysizes,sizes,totals,unused,veneers C:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\c_pe.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\fz_ps.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\h_pe.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\m_ps.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\vfpsupport.lInput Comments:flashprg.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\flashprg.o --vfemode=force Input Comments:p1d88-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide flashprg.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flashprg.o --depend=.\output\flashprg.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1021 -I.\devices\MIMXRT1021\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1021DAG5A FlashPrg.cflashdev.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flashdev.o --depend=.\output\flashdev.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1021 -I.\devices\MIMXRT1021\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1021DAG5A FlashDev.cfsl_clock.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\fsl_clock.o --vfemode=force Input Comments:p3ed0-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide fsl_clock.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\fsl_clock.o --depend=.\output\fsl_clock.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1021 -I.\devices\MIMXRT1021\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1021DAG5A devices\MIMXRT1021\drivers\fsl_clock.cclock_config_mimxrt1021.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\clock_config_mimxrt1021.o --vfemode=force Input Comments:p19c-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide clock_config_mimxrt1021.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\clock_config_mimxrt1021.o --depend=.\output\clock_config_mimxrt1021.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1021 -I.\devices\MIMXRT1021\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1021DAG5A bsp\src\clock_config_MIMXRT1021.chardware_init_mimxrt1021.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\hardware_init_mimxrt1021.o --vfemode=force Input Comments:pf38-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide hardware_init_mimxrt1021.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\hardware_init_mimxrt1021.o --depend=.\output\hardware_init_mimxrt1021.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1021 -I.\devices\MIMXRT1021\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1021DAG5A bsp\src\hardware_init_MIMXRT1021.cflexspi_nor_flash.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\flexspi_nor_flash.o --vfemode=force Input Comments:p3fa4-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide flexspi_nor_flash.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flexspi_nor_flash.o --depend=.\output\flexspi_nor_flash.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1021 -I.\devices\MIMXRT1021\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1021DAG5A middleware\flexspi_nor\flexspi_nor_flash.cfsl_flexspi.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\fsl_flexspi.o --vfemode=force Input Comments:p348-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide fsl_flexspi.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\fsl_flexspi.o --depend=.\output\fsl_flexspi.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1021 -I.\devices\MIMXRT1021\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1021DAG5A middleware\flexspi\fsl_flexspi.csystem_mimxrt1021.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\system_mimxrt1021.o --vfemode=force Input Comments:p1aa8-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide system_mimxrt1021.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\system_mimxrt1021.o --depend=.\output\system_mimxrt1021.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1021 -I.\devices\MIMXRT1021\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1021DAG5A devices\MIMXRT1021\system_MIMXRT1021.cPrgCodePrgDataDevDscr.debug_abbrev.debug_frame.debug_info.debug_line.debug_loc.debug_macinfo.debug_pubnames.symtab.strtab.note.comment.shstrtab49;0999 49 99 9999tJ'8P 4,^0@\ALR|FWP!f~%Z v,% ~<%% %%