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NIOPI:;9QI4 R S TUVW1X4I ,Y4I Z4I[4I,\4I]4I 4 ^4I ,4 _4I4 `4I,4 a4I4 b41 ,c41d41,e41f1g1hI iIjIkI 4 lI ,4 mI4 n1 o1p4I ? q4I? < r4I,s4It5Iu;v=w%x<%%.,armcc+|    (armcc+|  (armcc+|  (armcc+|  (armcc+|  (armcc+|   8 T0plA| \0B~0E~0F~ < X0LAz R b$0rAxCnI {A 0VA| h \|0A~0@Az @ \00.Az ^*   D `$0JA{Bvp {A 0DA~0>rA~0*A~     0 DA~0PA~ &  > H  ` j   6  jA} 2 > jA| @  $B~ $ 6 $B~ Z l >A~ >A~ .A~ .A~ D  V  0h  H d0 *A| 0 6A|ArX| 0 dAwBtn{ 0t BAwAn^{0 PAwBt 0AxAvV{0AwAn0vAyAn0fAxAn0AxAn 06A{CrV{$0.AwAhf {A $0.AxC` {A $0AwBu| {A $0vAwAj {A 0FAxB`$0.6AxBp {A 0d0AxBf{$0AxA\{ 0&!AxCR{$0"4AxAD {A 0 &Ax$0&AwBvc {A 0\'ZAwAnj{ 0'pA|Anu|0&(A{CR0)(A}AtQ}0.)$A}At L h \T) \b) \p) \z) \) \) 0)&AyAt{0*>Az$0+rA{Avt {A 0z+AyAra{B,PB~0,$A~0,Ax0.`Az 0.ZA|Crh|$0R/AwBf {A 0b0AxAn^{0$1AyAr02A~0 3A~03$A| 0>3 0N3 0^30n3A{Ar P l4A|04Az(05Axw {AA 06A~06ZB~ 8 0@7 0Z7 0x7 0|7 77F>~ 0808 A~ 808 A~09A~0494A|0h9 A~09A~K0t90AzC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] Դ'H@signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_t8 Pint16_t9 Pint32_t: Pint64_t; Puint8_t> Puint16_t? Puint32_t@ Puint64_tA Pint_least8_tG Pint_least16_tH Pint_least32_tI Pint_least64_tJ Puint_least8_tM Puint_least16_tN Puint_least32_tO Puint_least64_tP Pint_fast8_tU Pint_fast16_tV Pint_fast32_tW Pint_fast64_tX Puint_fast8_t[ Puint_fast16_t\ Puint_fast32_t] Puint_fast64_t^ Pintptr_te Puintptr_tf Pintmax_tj!Puintmax_tk!8 .\devices\MIMXRT1052\MIMXRT1052.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash5?IRQnNotAvail_IRQnNonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnDMA0_DMA16_IRQnDMA1_DMA17_IRQnDMA2_DMA18_IRQnDMA3_DMA19_IRQnDMA4_DMA20_IRQnDMA5_DMA21_IRQnDMA6_DMA22_IRQnDMA7_DMA23_IRQnDMA8_DMA24_IRQnDMA9_DMA25_IRQn DMA10_DMA26_IRQn DMA11_DMA27_IRQn DMA12_DMA28_IRQn DMA13_DMA29_IRQn DMA14_DMA30_IRQnDMA15_DMA31_IRQnDMA_ERROR_IRQnCTI0_ERROR_IRQnCTI1_ERROR_IRQnCORE_IRQnLPUART1_IRQnLPUART2_IRQnLPUART3_IRQnLPUART4_IRQnLPUART5_IRQnLPUART6_IRQnLPUART7_IRQnLPUART8_IRQnLPI2C1_IRQnLPI2C2_IRQnLPI2C3_IRQnLPI2C4_IRQnLPSPI1_IRQn LPSPI2_IRQn!LPSPI3_IRQn"LPSPI4_IRQn#CAN1_IRQn$CAN2_IRQn%FLEXRAM_IRQn&KPP_IRQn'TSC_DIG_IRQn(GPR_IRQ_IRQn)LCDIF_IRQn*CSI_IRQn+PXP_IRQn,WDOG2_IRQn-SNVS_HP_WRAPPER_IRQn.SNVS_HP_WRAPPER_TZ_IRQn/SNVS_LP_WRAPPER_IRQn0CSU_IRQn1DCP_IRQn2DCP_VMI_IRQn3Reserved68_IRQn4TRNG_IRQn5SJC_IRQn6BEE_IRQn7SAI1_IRQn8SAI2_IRQn9SAI3_RX_IRQn:SAI3_TX_IRQn;SPDIF_IRQn<ANATOP_EVENT0_IRQn=ANATOP_EVENT1_IRQn>ANATOP_TAMP_LOW_HIGH_IRQn?ANATOP_TEMP_PANIC_IRQnUSB_PHY1_IRQnUSB_PHY2_IRQnADC1_IRQnADC2_IRQnDCDC_IRQnReserved86_IRQnReserved87_IRQnGPIO1_INT0_IRQnGPIO1_INT1_IRQnGPIO1_INT2_IRQnGPIO1_INT3_IRQnGPIO1_INT4_IRQnGPIO1_INT5_IRQnGPIO1_INT6_IRQnGPIO1_INT7_IRQnGPIO1_Combined_0_15_IRQnGPIO1_Combined_16_31_IRQnGPIO2_Combined_0_15_IRQnGPIO2_Combined_16_31_IRQnGPIO3_Combined_0_15_IRQnGPIO3_Combined_16_31_IRQnGPIO4_Combined_0_15_IRQnGPIO4_Combined_16_31_IRQnGPIO5_Combined_0_15_IRQnGPIO5_Combined_16_31_IRQnFLEXIO1_IRQnFLEXIO2_IRQnWDOG1_IRQnRTWDOG_IRQnEWM_IRQnCCM_1_IRQnCCM_2_IRQnGPC_IRQnSRC_IRQnReserved115_IRQnGPT1_IRQnGPT2_IRQnPWM1_0_IRQnPWM1_1_IRQnPWM1_2_IRQnPWM1_3_IRQnPWM1_FAULT_IRQnReserved123_IRQnFLEXSPI_IRQnSEMC_IRQnUSDHC1_IRQnUSDHC2_IRQnUSB_OTG2_IRQnUSB_OTG1_IRQnENET_IRQnENET_1588_Timer_IRQnXBAR1_IRQ_0_1_IRQnXBAR1_IRQ_2_3_IRQnADC_ETC_IRQ0_IRQnADC_ETC_IRQ1_IRQnADC_ETC_IRQ2_IRQnADC_ETC_ERROR_IRQ_IRQnPIT_IRQnACMP1_IRQnACMP2_IRQnACMP3_IRQnACMP4_IRQnReserved143_IRQnReserved144_IRQnENC1_IRQnENC2_IRQnENC3_IRQnENC4_IRQnTMR1_IRQnTMR2_IRQnTMR3_IRQnTMR4_IRQnPWM2_0_IRQnPWM2_1_IRQnPWM2_2_IRQnPWM2_3_IRQnPWM2_FAULT_IRQnPWM3_0_IRQnPWM3_1_IRQnPWM3_2_IRQnPWM3_3_IRQnPWM3_FAULT_IRQnPWM4_0_IRQnPWM4_1_IRQnPWM4_2_IRQnPWM4_3_IRQnPWM4_FAULT_IRQnReserved168_IRQnReserved169_IRQnReserved170_IRQnReserved171_IRQnReserved172_IRQnReserved173_IRQnSJC_ARM_DEBUG_IRQnNMI_WAKEUP_IRQnPIRQn_Type7_dma_request_sourcekDmaRequestMuxFlexIO1Request0Request1kDmaRequestMuxFlexIO2Request0Request1kDmaRequestMuxLPUART1TxkDmaRequestMuxLPUART1RxkDmaRequestMuxLPUART3TxkDmaRequestMuxLPUART3RxkDmaRequestMuxLPUART5TxkDmaRequestMuxLPUART5RxkDmaRequestMuxLPUART7TxkDmaRequestMuxLPUART7Rx kDmaRequestMuxCSI kDmaRequestMuxLPSPI1Rx kDmaRequestMuxLPSPI1TxkDmaRequestMuxLPSPI3RxkDmaRequestMuxLPSPI3TxkDmaRequestMuxLPI2C1kDmaRequestMuxLPI2C3kDmaRequestMuxSai1RxkDmaRequestMuxSai1TxkDmaRequestMuxSai2RxkDmaRequestMuxSai2TxkDmaRequestMuxADC_ETCkDmaRequestMuxADC1kDmaRequestMuxACMP1kDmaRequestMuxACMP2kDmaRequestMuxFlexSPIRxkDmaRequestMuxFlexSPITxkDmaRequestMuxXBAR1Request0kDmaRequestMuxXBAR1Request1kDmaRequestMuxFlexPWM1CaptureSub0 kDmaRequestMuxFlexPWM1CaptureSub1!kDmaRequestMuxFlexPWM1CaptureSub2"kDmaRequestMuxFlexPWM1CaptureSub3#kDmaRequestMuxFlexPWM1ValueSub0$kDmaRequestMuxFlexPWM1ValueSub1%kDmaRequestMuxFlexPWM1ValueSub2&kDmaRequestMuxFlexPWM1ValueSub3'kDmaRequestMuxFlexPWM3CaptureSub0(kDmaRequestMuxFlexPWM3CaptureSub1)kDmaRequestMuxFlexPWM3CaptureSub2*kDmaRequestMuxFlexPWM3CaptureSub3+kDmaRequestMuxFlexPWM3ValueSub0,kDmaRequestMuxFlexPWM3ValueSub1-kDmaRequestMuxFlexPWM3ValueSub2.kDmaRequestMuxFlexPWM3ValueSub3/kDmaRequestMuxQTIMER1CaptTimer00kDmaRequestMuxQTIMER1CaptTimer11kDmaRequestMuxQTIMER1CaptTimer22kDmaRequestMuxQTIMER1CaptTimer33kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer14kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer05kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer36kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer27kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer18kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer19kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1:kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1;kDmaRequestMuxFlexIO1Request2Request3@kDmaRequestMuxFlexIO2Request2Request3AkDmaRequestMuxLPUART2TxBkDmaRequestMuxLPUART2RxCkDmaRequestMuxLPUART4TxDkDmaRequestMuxLPUART4RxEkDmaRequestMuxLPUART6TxFkDmaRequestMuxLPUART6RxGkDmaRequestMuxLPUART8TxHkDmaRequestMuxLPUART8RxIkDmaRequestMuxPxpKkDmaRequestMuxLCDIFLkDmaRequestMuxLPSPI2RxMkDmaRequestMuxLPSPI2TxNkDmaRequestMuxLPSPI4RxOkDmaRequestMuxLPSPI4TxPkDmaRequestMuxLPI2C2QkDmaRequestMuxLPI2C4RkDmaRequestMuxSai3RxSkDmaRequestMuxSai3TxTkDmaRequestMuxSpdifRxUkDmaRequestMuxSpdifTxVkDmaRequestMuxADC2XkDmaRequestMuxACMP3YkDmaRequestMuxACMP4ZkDmaRequestMuxEnetTimer0\kDmaRequestMuxEnetTimer1]kDmaRequestMuxXBAR1Request2^kDmaRequestMuxXBAR1Request3_kDmaRequestMuxFlexPWM2CaptureSub0`kDmaRequestMuxFlexPWM2CaptureSub1akDmaRequestMuxFlexPWM2CaptureSub2bkDmaRequestMuxFlexPWM2CaptureSub3ckDmaRequestMuxFlexPWM2ValueSub0dkDmaRequestMuxFlexPWM2ValueSub1ekDmaRequestMuxFlexPWM2ValueSub2fkDmaRequestMuxFlexPWM2ValueSub3gkDmaRequestMuxFlexPWM4CaptureSub0hkDmaRequestMuxFlexPWM4CaptureSub1ikDmaRequestMuxFlexPWM4CaptureSub2jkDmaRequestMuxFlexPWM4CaptureSub3kkDmaRequestMuxFlexPWM4ValueSub0lkDmaRequestMuxFlexPWM4ValueSub1mkDmaRequestMuxFlexPWM4ValueSub2nkDmaRequestMuxFlexPWM4ValueSub3okDmaRequestMuxQTIMER2CaptTimer0pkDmaRequestMuxQTIMER2CaptTimer1qkDmaRequestMuxQTIMER2CaptTimer2rkDmaRequestMuxQTIMER2CaptTimer3skDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1tkDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0ukDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3vkDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2wkDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1xkDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1ykDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1zkDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1{Pdma_request_source_tg ]_iomuxc_sw_mux_ctl_padkIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 !kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 "kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 #kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 $kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 %kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 &kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 'kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 (kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 )kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 *kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 +kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 ,kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 -kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 .kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 /kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 0kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 1kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 2kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 3kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 4kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 5kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 6kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 7kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 8kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 9kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 :kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 ;kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 <kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 =kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 >kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 ?kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 @kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 AkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 BkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 CkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 DkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 EkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 FkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 GkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 HkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 IkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 JkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 KkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 LkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 MkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 NkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 OkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 PkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 QkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 RkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 SkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 TkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 UkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 VkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 WkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 XkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 YkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 ZkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 [kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 \kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 ]kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 ^kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 _kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 `kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 akIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 bkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 ckIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 dkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 ekIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 fkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 gkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 hkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 ikIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 jkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 kkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 lkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 mkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 nkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 okIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 pkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 qkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 rkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 skIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 tkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 ukIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 vkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 wkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 xkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 ykIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 zkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 {Piomuxc_sw_mux_ctl_pad_tʃ_iomuxc_sw_pad_ctl_padkIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 !kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 "kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 #kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 $kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 %kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 &kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 'kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 (kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 )kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 *kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 +kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 ,kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 -kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 .kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 /kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 0kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 1kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 2kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 3kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 4kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 5kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 6kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 7kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 8kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 9kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 :kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 ;kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 <kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 =kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 >kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 ?kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 @kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 AkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 BkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 CkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 DkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 EkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 FkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 GkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 HkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 IkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 JkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 KkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 LkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 MkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 NkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 OkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 PkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 QkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 RkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 SkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 TkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 UkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 VkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 WkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 XkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 YkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 ZkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 [kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 \kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 ]kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 ^kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 _kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 `kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 akIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 bkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 ckIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 dkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 ekIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 fkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 gkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 hkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 ikIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 jkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 kkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 lkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 mkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 nkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 okIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 pkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 qkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 rkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 skIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 tkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 ukIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 vkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 wkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 xkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 ykIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 zkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 {Piomuxc_sw_pad_ctl_pad_t/_iomuxc_select_inputkIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT kIOMUXC_CCM_PMIC_READY_SELECT_INPUT kIOMUXC_CSI_DATA02_SELECT_INPUT kIOMUXC_CSI_DATA03_SELECT_INPUT kIOMUXC_CSI_DATA04_SELECT_INPUT kIOMUXC_CSI_DATA05_SELECT_INPUT kIOMUXC_CSI_DATA06_SELECT_INPUT kIOMUXC_CSI_DATA07_SELECT_INPUT kIOMUXC_CSI_DATA08_SELECT_INPUT kIOMUXC_CSI_DATA09_SELECT_INPUT kIOMUXC_CSI_HSYNC_SELECT_INPUT kIOMUXC_CSI_PIXCLK_SELECT_INPUT kIOMUXC_CSI_VSYNC_SELECT_INPUT kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT kIOMUXC_ENET_MDIO_SELECT_INPUT kIOMUXC_ENET0_RXDATA_SELECT_INPUT kIOMUXC_ENET1_RXDATA_SELECT_INPUT kIOMUXC_ENET_RXEN_SELECT_INPUT kIOMUXC_ENET_RXERR_SELECT_INPUT kIOMUXC_ENET0_TIMER_SELECT_INPUT kIOMUXC_ENET_TXCLK_SELECT_INPUT kIOMUXC_FLEXCAN1_RX_SELECT_INPUT kIOMUXC_FLEXCAN2_RX_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT !kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT "kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT #kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT $kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT %kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT &kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT 'kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT (kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT )kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT *kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT +kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT ,kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT -kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT .kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT /kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT 0kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT 1kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT 2kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT 3kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT 4kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT 5kIOMUXC_LPI2C1_SCL_SELECT_INPUT 6kIOMUXC_LPI2C1_SDA_SELECT_INPUT 7kIOMUXC_LPI2C2_SCL_SELECT_INPUT 8kIOMUXC_LPI2C2_SDA_SELECT_INPUT 9kIOMUXC_LPI2C3_SCL_SELECT_INPUT :kIOMUXC_LPI2C3_SDA_SELECT_INPUT ;kIOMUXC_LPI2C4_SCL_SELECT_INPUT <kIOMUXC_LPI2C4_SDA_SELECT_INPUT =kIOMUXC_LPSPI1_PCS0_SELECT_INPUT >kIOMUXC_LPSPI1_SCK_SELECT_INPUT ?kIOMUXC_LPSPI1_SDI_SELECT_INPUT @kIOMUXC_LPSPI1_SDO_SELECT_INPUT AkIOMUXC_LPSPI2_PCS0_SELECT_INPUT BkIOMUXC_LPSPI2_SCK_SELECT_INPUT CkIOMUXC_LPSPI2_SDI_SELECT_INPUT DkIOMUXC_LPSPI2_SDO_SELECT_INPUT EkIOMUXC_LPSPI3_PCS0_SELECT_INPUT FkIOMUXC_LPSPI3_SCK_SELECT_INPUT GkIOMUXC_LPSPI3_SDI_SELECT_INPUT HkIOMUXC_LPSPI3_SDO_SELECT_INPUT IkIOMUXC_LPSPI4_PCS0_SELECT_INPUT JkIOMUXC_LPSPI4_SCK_SELECT_INPUT KkIOMUXC_LPSPI4_SDI_SELECT_INPUT LkIOMUXC_LPSPI4_SDO_SELECT_INPUT MkIOMUXC_LPUART2_RX_SELECT_INPUT NkIOMUXC_LPUART2_TX_SELECT_INPUT OkIOMUXC_LPUART3_CTS_B_SELECT_INPUT PkIOMUXC_LPUART3_RX_SELECT_INPUT QkIOMUXC_LPUART3_TX_SELECT_INPUT RkIOMUXC_LPUART4_RX_SELECT_INPUT SkIOMUXC_LPUART4_TX_SELECT_INPUT TkIOMUXC_LPUART5_RX_SELECT_INPUT UkIOMUXC_LPUART5_TX_SELECT_INPUT VkIOMUXC_LPUART6_RX_SELECT_INPUT WkIOMUXC_LPUART6_TX_SELECT_INPUT XkIOMUXC_LPUART7_RX_SELECT_INPUT YkIOMUXC_LPUART7_TX_SELECT_INPUT ZkIOMUXC_LPUART8_RX_SELECT_INPUT [kIOMUXC_LPUART8_TX_SELECT_INPUT \kIOMUXC_NMI_SELECT_INPUT ]kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT ^kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT _kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT `kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT akIOMUXC_QTIMER3_TIMER0_SELECT_INPUT bkIOMUXC_QTIMER3_TIMER1_SELECT_INPUT ckIOMUXC_QTIMER3_TIMER2_SELECT_INPUT dkIOMUXC_QTIMER3_TIMER3_SELECT_INPUT ekIOMUXC_SAI1_MCLK2_SELECT_INPUT fkIOMUXC_SAI1_RX_BCLK_SELECT_INPUT gkIOMUXC_SAI1_RX_DATA0_SELECT_INPUT hkIOMUXC_SAI1_RX_DATA1_SELECT_INPUT ikIOMUXC_SAI1_RX_DATA2_SELECT_INPUT jkIOMUXC_SAI1_RX_DATA3_SELECT_INPUT kkIOMUXC_SAI1_RX_SYNC_SELECT_INPUT lkIOMUXC_SAI1_TX_BCLK_SELECT_INPUT mkIOMUXC_SAI1_TX_SYNC_SELECT_INPUT nkIOMUXC_SAI2_MCLK2_SELECT_INPUT okIOMUXC_SAI2_RX_BCLK_SELECT_INPUT pkIOMUXC_SAI2_RX_DATA0_SELECT_INPUT qkIOMUXC_SAI2_RX_SYNC_SELECT_INPUT rkIOMUXC_SAI2_TX_BCLK_SELECT_INPUT skIOMUXC_SAI2_TX_SYNC_SELECT_INPUT tkIOMUXC_SPDIF_IN_SELECT_INPUT ukIOMUXC_USB_OTG2_OC_SELECT_INPUT vkIOMUXC_USB_OTG1_OC_SELECT_INPUT wkIOMUXC_USDHC1_CD_B_SELECT_INPUT xkIOMUXC_USDHC1_WP_SELECT_INPUT ykIOMUXC_USDHC2_CLK_SELECT_INPUT zkIOMUXC_USDHC2_CD_B_SELECT_INPUT {kIOMUXC_USDHC2_CMD_SELECT_INPUT |kIOMUXC_USDHC2_DATA0_SELECT_INPUT }kIOMUXC_USDHC2_DATA1_SELECT_INPUT ~kIOMUXC_USDHC2_DATA2_SELECT_INPUT kIOMUXC_USDHC2_DATA3_SELECT_INPUT kIOMUXC_USDHC2_DATA4_SELECT_INPUT kIOMUXC_USDHC2_DATA5_SELECT_INPUT kIOMUXC_USDHC2_DATA6_SELECT_INPUT kIOMUXC_USDHC2_DATA7_SELECT_INPUT kIOMUXC_USDHC2_WP_SELECT_INPUT kIOMUXC_XBAR1_IN02_SELECT_INPUT kIOMUXC_XBAR1_IN03_SELECT_INPUT kIOMUXC_XBAR1_IN04_SELECT_INPUT kIOMUXC_XBAR1_IN05_SELECT_INPUT kIOMUXC_XBAR1_IN06_SELECT_INPUT kIOMUXC_XBAR1_IN07_SELECT_INPUT kIOMUXC_XBAR1_IN08_SELECT_INPUT kIOMUXC_XBAR1_IN09_SELECT_INPUT kIOMUXC_XBAR1_IN17_SELECT_INPUT kIOMUXC_XBAR1_IN18_SELECT_INPUT kIOMUXC_XBAR1_IN20_SELECT_INPUT kIOMUXC_XBAR1_IN22_SELECT_INPUT kIOMUXC_XBAR1_IN23_SELECT_INPUT kIOMUXC_XBAR1_IN24_SELECT_INPUT kIOMUXC_XBAR1_IN14_SELECT_INPUT kIOMUXC_XBAR1_IN15_SELECT_INPUT kIOMUXC_XBAR1_IN16_SELECT_INPUT kIOMUXC_XBAR1_IN25_SELECT_INPUT kIOMUXC_XBAR1_IN19_SELECT_INPUT kIOMUXC_XBAR1_IN21_SELECT_INPUT Piomuxc_select_input_tA_xbar_input_signalkXBARA1_InputLogicLowkXBARA1_InputLogicHighkXBARA1_InputIomuxXbarIn02kXBARA1_InputIomuxXbarIn03kXBARA1_InputIomuxXbarInout04kXBARA1_InputIomuxXbarInout05kXBARA1_InputIomuxXbarInout06kXBARA1_InputIomuxXbarInout07kXBARA1_InputIomuxXbarInout08kXBARA1_InputIomuxXbarInout09 kXBARA1_InputIomuxXbarInout10 kXBARA1_InputIomuxXbarInout11 kXBARA1_InputIomuxXbarInout12 kXBARA1_InputIomuxXbarInout13 kXBARA1_InputIomuxXbarInout14kXBARA1_InputIomuxXbarInout15kXBARA1_InputIomuxXbarInout16kXBARA1_InputIomuxXbarInout17kXBARA1_InputIomuxXbarInout18kXBARA1_InputIomuxXbarInout19kXBARA1_InputIomuxXbarIn20kXBARA1_InputIomuxXbarIn21kXBARA1_InputIomuxXbarIn22kXBARA1_InputIomuxXbarIn23kXBARA1_InputIomuxXbarIn24kXBARA1_InputIomuxXbarIn25kXBARA1_InputAcmp1OutkXBARA1_InputAcmp2OutkXBARA1_InputAcmp3OutkXBARA1_InputAcmp4OutkXBARA1_InputRESERVED30kXBARA1_InputRESERVED31kXBARA1_InputQtimer3Tmr0Output kXBARA1_InputQtimer3Tmr1Output!kXBARA1_InputQtimer3Tmr2Output"kXBARA1_InputQtimer3Tmr3Output#kXBARA1_InputQtimer4Tmr0Output$kXBARA1_InputQtimer4Tmr1Output%kXBARA1_InputQtimer4Tmr2Output&kXBARA1_InputQtimer4Tmr3Output'kXBARA1_InputFlexpwm1Pwm1OutTrig01(kXBARA1_InputFlexpwm1Pwm2OutTrig01)kXBARA1_InputFlexpwm1Pwm3OutTrig01*kXBARA1_InputFlexpwm1Pwm4OutTrig01+kXBARA1_InputFlexpwm2Pwm1OutTrig01,kXBARA1_InputFlexpwm2Pwm2OutTrig01-kXBARA1_InputFlexpwm2Pwm3OutTrig01.kXBARA1_InputFlexpwm2Pwm4OutTrig01/kXBARA1_InputFlexpwm3Pwm1OutTrig010kXBARA1_InputFlexpwm3Pwm2OutTrig011kXBARA1_InputFlexpwm3Pwm3OutTrig012kXBARA1_InputFlexpwm3Pwm4OutTrig013kXBARA1_InputFlexpwm4Pwm1OutTrig014kXBARA1_InputFlexpwm4Pwm2OutTrig015kXBARA1_InputFlexpwm4Pwm3OutTrig016kXBARA1_InputFlexpwm4Pwm4OutTrig017kXBARA1_InputPitTrigger08kXBARA1_InputPitTrigger19kXBARA1_InputPitTrigger2:kXBARA1_InputPitTrigger3;kXBARA1_InputEnc1PosMatch<kXBARA1_InputEnc2PosMatch=kXBARA1_InputEnc3PosMatch>kXBARA1_InputEnc4PosMatch?kXBARA1_InputDmaDone0@kXBARA1_InputDmaDone1AkXBARA1_InputDmaDone2BkXBARA1_InputDmaDone3CkXBARA1_InputDmaDone4DkXBARA1_InputDmaDone5EkXBARA1_InputDmaDone6FkXBARA1_InputDmaDone7GkXBARA1_InputAoi1Out0HkXBARA1_InputAoi1Out1IkXBARA1_InputAoi1Out2JkXBARA1_InputAoi1Out3KkXBARA1_InputAoi2Out0LkXBARA1_InputAoi2Out1MkXBARA1_InputAoi2Out2NkXBARA1_InputAoi2Out3OkXBARA1_InputAdcEtcXbar0Coco0PkXBARA1_InputAdcEtcXbar0Coco1QkXBARA1_InputAdcEtcXbar0Coco2RkXBARA1_InputAdcEtcXbar0Coco3SkXBARA1_InputAdcEtcXbar1Coco0TkXBARA1_InputAdcEtcXbar1Coco1UkXBARA1_InputAdcEtcXbar1Coco2VkXBARA1_InputAdcEtcXbar1Coco3WkXBARB2_InputLogicLowkXBARB2_InputLogicHighkXBARB2_InputRESERVED2kXBARB2_InputRESERVED3kXBARB2_InputRESERVED4kXBARB2_InputRESERVED5kXBARB2_InputAcmp1OutkXBARB2_InputAcmp2OutkXBARB2_InputAcmp3OutkXBARB2_InputAcmp4Out kXBARB2_InputRESERVED10 kXBARB2_InputRESERVED11 kXBARB2_InputQtimer3Tmr0Output kXBARB2_InputQtimer3Tmr1Output kXBARB2_InputQtimer3Tmr2OutputkXBARB2_InputQtimer3Tmr3OutputkXBARB2_InputQtimer4Tmr0OutputkXBARB2_InputQtimer4Tmr1OutputkXBARB2_InputQtimer4Tmr2OutputkXBARB2_InputQtimer4Tmr3OutputkXBARB2_InputFlexpwm1Pwm1OutTrig01kXBARB2_InputFlexpwm1Pwm2OutTrig01kXBARB2_InputFlexpwm1Pwm3OutTrig01kXBARB2_InputFlexpwm1Pwm4OutTrig01kXBARB2_InputFlexpwm2Pwm1OutTrig01kXBARB2_InputFlexpwm2Pwm2OutTrig01kXBARB2_InputFlexpwm2Pwm3OutTrig01kXBARB2_InputFlexpwm2Pwm4OutTrig01kXBARB2_InputFlexpwm3Pwm1OutTrig01kXBARB2_InputFlexpwm3Pwm2OutTrig01kXBARB2_InputFlexpwm3Pwm3OutTrig01kXBARB2_InputFlexpwm3Pwm4OutTrig01kXBARB2_InputFlexpwm4Pwm1OutTrig01 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kXBARB3_InputFlexpwm4Pwm2OutTrig01!kXBARB3_InputFlexpwm4Pwm3OutTrig01"kXBARB3_InputFlexpwm4Pwm4OutTrig01#kXBARB3_InputPitTrigger0$kXBARB3_InputPitTrigger1%kXBARB3_InputAdcEtcXbar0Coco0&kXBARB3_InputAdcEtcXbar0Coco1'kXBARB3_InputAdcEtcXbar0Coco2(kXBARB3_InputAdcEtcXbar0Coco3)kXBARB3_InputAdcEtcXbar1Coco0*kXBARB3_InputAdcEtcXbar1Coco1+kXBARB3_InputAdcEtcXbar1Coco2,kXBARB3_InputAdcEtcXbar1Coco3-kXBARB3_InputEnc1PosMatch.kXBARB3_InputEnc2PosMatch/kXBARB3_InputEnc3PosMatch0kXBARB3_InputEnc4PosMatch1kXBARB3_InputDmaDone02kXBARB3_InputDmaDone13kXBARB3_InputDmaDone24kXBARB3_InputDmaDone35kXBARB3_InputDmaDone46kXBARB3_InputDmaDone57kXBARB3_InputDmaDone68kXBARB3_InputDmaDone79Pxbar_input_signal_tX_xbar_output_signalkXBARA1_OutputDmaChMuxReq30kXBARA1_OutputDmaChMuxReq31kXBARA1_OutputDmaChMuxReq94kXBARA1_OutputDmaChMuxReq95kXBARA1_OutputIomuxXbarInout04kXBARA1_OutputIomuxXbarInout05kXBARA1_OutputIomuxXbarInout06kXBARA1_OutputIomuxXbarInout07kXBARA1_OutputIomuxXbarInout08kXBARA1_OutputIomuxXbarInout09 kXBARA1_OutputIomuxXbarInout10 kXBARA1_OutputIomuxXbarInout11 kXBARA1_OutputIomuxXbarInout12 kXBARA1_OutputIomuxXbarInout13 kXBARA1_OutputIomuxXbarInout14kXBARA1_OutputIomuxXbarInout15kXBARA1_OutputIomuxXbarInout16kXBARA1_OutputIomuxXbarInout17kXBARA1_OutputIomuxXbarInout18kXBARA1_OutputIomuxXbarInout19kXBARA1_OutputAcmp1SamplekXBARA1_OutputAcmp2SamplekXBARA1_OutputAcmp3SamplekXBARA1_OutputAcmp4SamplekXBARA1_OutputRESERVED24kXBARA1_OutputRESERVED25kXBARA1_OutputFlexpwm1Exta0kXBARA1_OutputFlexpwm1Exta1kXBARA1_OutputFlexpwm1Exta2kXBARA1_OutputFlexpwm1Exta3kXBARA1_OutputFlexpwm1ExtSync0kXBARA1_OutputFlexpwm1ExtSync1kXBARA1_OutputFlexpwm1ExtSync2 kXBARA1_OutputFlexpwm1ExtSync3!kXBARA1_OutputFlexpwm1ExtClk"kXBARA1_OutputFlexpwm1Fault0#kXBARA1_OutputFlexpwm1Fault1$kXBARA1_OutputFlexpwm1234Fault2%kXBARA1_OutputFlexpwm1234Fault3&kXBARA1_OutputFlexpwm1ExtForce'kXBARA1_OutputFlexpwm234Exta0(kXBARA1_OutputFlexpwm234Exta1)kXBARA1_OutputFlexpwm234Exta2*kXBARA1_OutputFlexpwm234Exta3+kXBARA1_OutputFlexpwm2ExtSync0,kXBARA1_OutputFlexpwm2ExtSync1-kXBARA1_OutputFlexpwm2ExtSync2.kXBARA1_OutputFlexpwm2ExtSync3/kXBARA1_OutputFlexpwm234ExtClk0kXBARA1_OutputFlexpwm2Fault01kXBARA1_OutputFlexpwm2Fault12kXBARA1_OutputFlexpwm2ExtForce3kXBARA1_OutputFlexpwm3ExtSync04kXBARA1_OutputFlexpwm3ExtSync15kXBARA1_OutputFlexpwm3ExtSync26kXBARA1_OutputFlexpwm3ExtSync37kXBARA1_OutputFlexpwm3Fault08kXBARA1_OutputFlexpwm3Fault19kXBARA1_OutputFlexpwm3ExtForce:kXBARA1_OutputFlexpwm4ExtSync0;kXBARA1_OutputFlexpwm4ExtSync1<kXBARA1_OutputFlexpwm4ExtSync2=kXBARA1_OutputFlexpwm4ExtSync3>kXBARA1_OutputFlexpwm4Fault0?kXBARA1_OutputFlexpwm4Fault1@kXBARA1_OutputFlexpwm4ExtForceAkXBARA1_OutputEnc1PhaseAInputBkXBARA1_OutputEnc1PhaseBInputCkXBARA1_OutputEnc1IndexDkXBARA1_OutputEnc1HomeEkXBARA1_OutputEnc1TriggerFkXBARA1_OutputEnc2PhaseAInputGkXBARA1_OutputEnc2PhaseBInputHkXBARA1_OutputEnc2IndexIkXBARA1_OutputEnc2HomeJkXBARA1_OutputEnc2TriggerKkXBARA1_OutputEnc3PhaseAInputLkXBARA1_OutputEnc3PhaseBInputMkXBARA1_OutputEnc3IndexNkXBARA1_OutputEnc3HomeOkXBARA1_OutputEnc3TriggerPkXBARA1_OutputEnc4PhaseAInputQkXBARA1_OutputEnc4PhaseBInputRkXBARA1_OutputEnc4IndexSkXBARA1_OutputEnc4HomeTkXBARA1_OutputEnc4TriggerUkXBARA1_OutputQtimer1Tmr0InputVkXBARA1_OutputQtimer1Tmr1InputWkXBARA1_OutputQtimer1Tmr2InputXkXBARA1_OutputQtimer1Tmr3InputYkXBARA1_OutputQtimer2Tmr0InputZkXBARA1_OutputQtimer2Tmr1Input[kXBARA1_OutputQtimer2Tmr2Input\kXBARA1_OutputQtimer2Tmr3Input]kXBARA1_OutputQtimer3Tmr0Input^kXBARA1_OutputQtimer3Tmr1Input_kXBARA1_OutputQtimer3Tmr2Input`kXBARA1_OutputQtimer3Tmr3InputakXBARA1_OutputQtimer4Tmr0InputbkXBARA1_OutputQtimer4Tmr1InputckXBARA1_OutputQtimer4Tmr2InputdkXBARA1_OutputQtimer4Tmr3InputekXBARA1_OutputEwmEwmInfkXBARA1_OutputAdcEtcXbar0Trig0gkXBARA1_OutputAdcEtcXbar0Trig1hkXBARA1_OutputAdcEtcXbar0Trig2ikXBARA1_OutputAdcEtcXbar0Trig3jkXBARA1_OutputAdcEtcXbar1Trig0kkXBARA1_OutputAdcEtcXbar1Trig1lkXBARA1_OutputAdcEtcXbar1Trig2mkXBARA1_OutputAdcEtcXbar1Trig3nkXBARA1_OutputLpi2c1TrgInputokXBARA1_OutputLpi2c2TrgInputpkXBARA1_OutputLpi2c3TrgInputqkXBARA1_OutputLpi2c4TrgInputrkXBARA1_OutputLpspi1TrgInputskXBARA1_OutputLpspi2TrgInputtkXBARA1_OutputLpspi3TrgInputukXBARA1_OutputLpspi4TrgInputvkXBARA1_OutputLpuart1TrgInputwkXBARA1_OutputLpuart2TrgInputxkXBARA1_OutputLpuart3TrgInputykXBARA1_OutputLpuart4TrgInputzkXBARA1_OutputLpuart5TrgInput{kXBARA1_OutputLpuart6TrgInput|kXBARA1_OutputLpuart7TrgInput}kXBARA1_OutputLpuart8TrgInput~kXBARA1_OutputFlexio1TriggerIn0kXBARA1_OutputFlexio1TriggerIn1kXBARA1_OutputFlexio2TriggerIn0kXBARA1_OutputFlexio2TriggerIn1kXBARB2_OutputAoi1In00kXBARB2_OutputAoi1In01kXBARB2_OutputAoi1In02kXBARB2_OutputAoi1In03kXBARB2_OutputAoi1In04kXBARB2_OutputAoi1In05kXBARB2_OutputAoi1In06kXBARB2_OutputAoi1In07kXBARB2_OutputAoi1In08kXBARB2_OutputAoi1In09 kXBARB2_OutputAoi1In10 kXBARB2_OutputAoi1In11 kXBARB2_OutputAoi1In12 kXBARB2_OutputAoi1In13 kXBARB2_OutputAoi1In14kXBARB2_OutputAoi1In15kXBARB3_OutputAoi2In00kXBARB3_OutputAoi2In01kXBARB3_OutputAoi2In02kXBARB3_OutputAoi2In03kXBARB3_OutputAoi2In04kXBARB3_OutputAoi2In05kXBARB3_OutputAoi2In06kXBARB3_OutputAoi2In07kXBARB3_OutputAoi2In08kXBARB3_OutputAoi2In09 kXBARB3_OutputAoi2In10 kXBARB3_OutputAoi2In11 kXBARB3_OutputAoi2In12 kXBARB3_OutputAoi2In13 kXBARB3_OutputAoi2In14kXBARB3_OutputAoi2In15Pxbar_output_signal_tr *Ď\ݍDHCӆ#HSP# PR#$CFGD#DGCD#HGSD#LCVD#POFSD#TCALD#XtYYtJPADC_TypeΆ *ΐ(TRIGn_CTRLD#TRIGn_COUNTERD#TRIGn_CHAIN_1_0D#TRIGn_CHAIN_3_2D# TRIGn_CHAIN_5_4D#TRIGn_CHAIN_7_6D#TRIGn_RESULT_1_0P#TRIGn_RESULT_3_2P#TRIGn_RESULT_5_4P# TRIGn_RESULT_7_6P#$*CTRLD#DONE0_1_IRQD#DONE2_ERR_IRQD#DMA_CTRLD# eTRIG#PADC_ETC_TypeN *TMPRD#:;RESERVED_0Ԉ#OPACRD#@OPACR1D#DOPACR2D#HOPACR3D#LOPACR4D#PPAIPSTZ_TypeĈ*BFCRT01p#BFCRT23p#tI*LBFCRT{#PAOI_Typev*HCTRLD#ADDR_OFFSET0D#ADDR_OFFSET1D#AES_KEY0_W0D# AES_KEY0_W1D#AES_KEY0_W2D#AES_KEY0_W3D#STATUSD#CTR_NONCE0_W0D# CTR_NONCE0_W1D#$CTR_NONCE0_W2D#(CTR_NONCE0_W3D#,CTR_NONCE1_W0D#0CTR_NONCE1_W1D#4CTR_NONCE1_W2D#8CTR_NONCE1_W3D#<REGION1_TOPD#@REGION1_BOTD#DPBEE_Type*˖CSD#IDD#WORD0D#WORD1D# *MCRD#CTRL1D#TIMERD#:RESERVED_0v# RXMGMASKD#RX14MASKD#RX15MASKD#ECRD#ESR1D# IMASK2D#$IMASK1D#(IFLAG2D#,IFLAG1D#0CTRL2D#4ESR2P#8:RESERVED_1,#<CRCRP#DRXFGMASKD#HRXFIRP#L:/RESERVED_2s#P?MB#:RESERVED_3# ЙD?RXIMRƌ#:_RESERVED_4ތ#GFWRD#PCAN_TypeK*CCRD#:RESERVED_0-#CSRP#CCSRD# CACRRD#CBCDRD#CBCMRD#CSCMR1D#CSCMR2D# CSCDR1D#$CS1CDRD#(CS2CDRD#,CDCDRD#0:RESERVED_1܍#4CSCDR2D#8CSCDR3D#<:RESERVED_2#@CDHIPRP#HΜ:RESERVED_3B#LCLPCRD#TCISRD#XCIMRD#\CCOSRD#`CGPRD#dCCGR0D#hCCGR1D#lCCGR2D#pCCGR3D#tCCGR4D#xCCGR5D#|CCGR6D#:RESERVED_4#CMEORD#PCCM_Type*˨PLL_ARMD#PLL_ARM_SETD#PLL_ARM_CLRD#PLL_ARM_TOGD# PLL_USB1D#PLL_USB1_SETD#PLL_USB1_CLRD#PLL_USB1_TOGD#PLL_USB2D# PLL_USB2_SETD#$PLL_USB2_CLRD#(PLL_USB2_TOGD#,PLL_SYSD#0PLL_SYS_SETD#4PLL_SYS_CLRD#8PLL_SYS_TOGD#<PLL_SYS_SSD#@: RESERVED_0y#DPLL_SYS_NUMD#P: RESERVED_1#TPLL_SYS_DENOMD#`: RESERVED_2ݐ#dPLL_AUDIOD#pPLL_AUDIO_SETD#tPLL_AUDIO_CLRD#xPLL_AUDIO_TOGD#|PLL_AUDIO_NUMD#: RESERVED_3a#PLL_AUDIO_DENOMD#: RESERVED_4#PLL_VIDEOD#PLL_VIDEO_SETD#PLL_VIDEO_CLRD#PLL_VIDEO_TOGD#PLL_VIDEO_NUMD#: RESERVED_5!#PLL_VIDEO_DENOMD#:RESERVED_6X#PLL_ENETD#PLL_ENET_SETD#PLL_ENET_CLRD#PLL_ENET_TOGD#PFD_480D#PFD_480_SETD#PFD_480_CLRD#PFD_480_TOGD#PFD_528D#PFD_528_SETD#PFD_528_CLRD#PFD_528_TOGD#:?RESERVED_7_#MISC0D#MISC0_SETD#MISC0_CLRD#MISC0_TOGD#MISC1D#MISC1_SETD#MISC1_CLRD#MISC1_TOGD#MISC2D#MISC2_SETD#MISC2_CLRD#MISC2_TOGD#PCCM_ANALOG_Type9*CR0#CR1#FPR#SCR#DACCR#MUXCR#t:PCMP_Typec**PCSICR1D#CSICR2D#CSICR3D#CSISTATFIFOP# CSIRFIFOP#CSIRXCNTD#CSISRD#:RESERVED_05#CSIDMASA_STATFIFOD# CSIDMATS_STATFIFOD#$CSIDMASA_FB1D#(CSIDMASA_FB2D#,CSIFBUF_PARAD#0CSIIMAG_PARAD#4:RESERVED_1Օ#8CSICR18D#HCSICR19D#LPCSI_TypeƔ+*ȭDCSL)#ˬ:RESERVED_0>#HP0D#:RESERVED_1j#SAD#:RESERVED_2#HPCONTROL0D#PCSU_Type#.*REG0D#REG1D#REG2D#REG3D# PDCDC_Typeٖ0*CTRLD#: RESERVED_03#STATD#: RESERVED_1]#CHANNELCTRLD# : RESERVED_2#$CAPABILITY0D#0˯: RESERVED_3#4CAPABILITY1P#@: RESERVED_4#DCONTEXTD#P: RESERVED_5#TKEYD#`Ұ: RESERVED_6F#dKEYDATAD#p: RESERVED_7s#tPACKET0P#: RESERVED_8#PACKET1P#ܱ: RESERVED_9И#PACKET2P#: RESERVED_10#PACKET3P#: RESERVED_11/#PACKET4P#: RESERVED_12_#PACKET5P#: RESERVED_13#PACKET6P#˳:RESERVED_14#CH0CMDPTRD#: RESERVED_15#CH0SEMAD#: RESERVED_16!#CH0STATD#ݴ: RESERVED_17Q#CH0OPTSD#: RESERVED_18#CH1CMDPTRD#: RESERVED_19#CH1SEMAD#: RESERVED_20#CH1STATD#: RESERVED_21#CH1OPTSD#϶: RESERVED_22C#CH2CMDPTRD#: RESERVED_23u#CH2SEMAD#: RESERVED_24#CH2STATD#: RESERVED_25՛#CH2OPTSD#: RESERVED_26#CH3CMDPTRD#ø: RESERVED_277#CH3SEMAD#: RESERVED_28g#CH3STATD#: RESERVED_29#CH3OPTSD#Թ:RESERVED_30ǜ#DBGSELECTD#: RESERVED_31#DBGDATAP#: RESERVED_32*#PAGETABLED#: RESERVED_33\#VERSIONP#PDCP_Type!2SۻNBYTES_MLNODNBYTES_MLOFFNODNBYTES_MLOFFYESDSCITER_ELINKNOpCITER_ELINKYESpSBITER_ELINKNOpBITER_ELINKYESp* SADDRD#SOFFp#ATTRp##SLASTD# DADDRD#DOFFp#۝#DLAST_SGAD#CSRp##*(CRD#ESP#ܽ:RESERVED_0О#ERQD# :RESERVED_1#EEID#CEEI#SEEI#CERQ#SERQ#CDNE#SSRT#CERR#CINT#:RESERVED_2# INTD#$:RESERVED_3#(ERRD#,:RESERVED_4ԟ#0HRSP#4: RESERVED_5#8EARSD#D:RESERVED_6'#HDCHPRI3#DCHPRI2#DCHPRI1#DCHPRI0#DCHPRI7#DCHPRI6#DCHPRI5#DCHPRI4#DCHPRI11#DCHPRI10#DCHPRI9#DCHPRI8#DCHPRI15#DCHPRI14#DCHPRI13#DCHPRI12#DCHPRI19#DCHPRI18#DCHPRI17#DCHPRI16#DCHPRI23#DCHPRI22#DCHPRI21#DCHPRI20#DCHPRI27#DCHPRI26#DCHPRI25#DCHPRI24#DCHPRI31#DCHPRI30#DCHPRI29#DCHPRI28#:RESERVED_7\#1TCD|# PDMA_Type7*DCHCFG#PDMAMUX_TypeB*(CTRLp#FILTp#WTRp#POSDp#POSDH֣#REVp# REVH֣# UPOSp#LPOSp#UPOSH֣#LPOSH֣#UINITp#LINITp#IMR֣#TSTp#CTRL2p#UMODp# LMODp#"UCOMPp#$LCOMPp#&ItУPENC_Type֢B*TCSRD#TCCRD#* :RESERVED_0#EIRD#EIMRD#:RESERVED_1D# RDARD#TDARD#: RESERVED_2z#ECRD#$:RESERVED_3#(MMFRD#@MSCRD#D:RESERVED_4٤#HMIBCD#d:RESERVED_5#hRCRD#:;RESERVED_6-#TCRD#:RESERVED_7X#PALRD#PAURD#OPDD#TXICD#: RESERVED_8#RXICD#:RESERVED_9֥#IAURD#IALRD#GAURD#GALRD#:RESERVED_10)#TFWRD#:7RESERVED_11V#RDSRD#TDSRD#MRBRD#:RESERVED_12#RSFLD#RSEMD#RAEMD#RAFLD#TSEMD#TAEMD#TAFLD#TIPGD#FTRLD#: RESERVED_132#TACCD#RACCD#:7RESERVED_14l#RMON_T_DROPY#RMON_T_PACKETSP#RMON_T_BC_PKTP#RMON_T_MC_PKTP#RMON_T_CRC_ALIGNP#RMON_T_UNDERSIZEP#RMON_T_OVERSIZEP#RMON_T_FRAGP#RMON_T_JABP#RMON_T_COLP#RMON_T_P64P#RMON_T_P65TO127P#RMON_T_P128TO255P#RMON_T_P256TO511P#RMON_T_P512TO1023P#RMON_T_P1024TO2047P#RMON_T_P_GTE2048P#RMON_T_OCTETSP#IEEE_T_DROPY#IEEE_T_FRAME_OKP#IEEE_T_1COLP#IEEE_T_MCOLP#IEEE_T_DEFP#IEEE_T_LCOLP#IEEE_T_EXCOLP#IEEE_T_MACERRP#IEEE_T_CSERRP#IEEE_T_SQEP#IEEE_T_FDXFCP#IEEE_T_OCTETS_OKP#: RESERVED_15(#RMON_R_PACKETSP#RMON_R_BC_PKTP#RMON_R_MC_PKTP#RMON_R_CRC_ALIGNP#RMON_R_UNDERSIZEP#RMON_R_OVERSIZEP#RMON_R_FRAGP#RMON_R_JABP#RMON_R_RESVD_0Y#RMON_R_P64P#RMON_R_P65TO127P#RMON_R_P128TO255P#RMON_R_P256TO511P#RMON_R_P512TO1023P#RMON_R_P1024TO2047P#RMON_R_P_GTE2048P#RMON_R_OCTETSP#IEEE_R_DROPP#IEEE_R_FRAME_OKP#IEEE_R_CRCP#IEEE_R_ALIGNP#IEEE_R_MACERRP#IEEE_R_FDXFCP#IEEE_R_OCTETS_OKP#:RESERVED_16n#ATCRD#ATVRD#ATOFFD#ATPERD#ATCORD#ATINCD#ATSTMPP#:RESERVED_17#TGSRD# CHANNEL# PENET_Type F*CTRL#SERV#CMPL#CMPH#CLKCTRL#CLKPRESCALER#PEWM_TypeKL*VERIDP#PARAMP#CTRLD#PINP# SHIFTSTATD#SHIFTERRD#TIMSTATD#:RESERVED_0#SHIFTSIEND# SHIFTEIEND#$TIMIEND#(:RESERVED_1j#,SHIFTSDEND#0: RESERVED_2#4SHIFTSTATED#@:;RESERVED_3ɮ#DDSHIFTCTL#:oRESERVED_4#DSHIFTCFG!#:RESERVED_5<#DSHIFTBUF\#:oRESERVED_6w#DSHIFTBUFBIS#:oRESERVED_7#DSHIFTBUFBYSӯ#:oRESERVED_8#DSHIFTBUFBBS#:oRESERVED_9.#DTIMCTLM#:oRESERVED_10f#DTIMCFG# :oRESERVED_11# DTIMCMP# :RESERVED_12ذ# DSHIFTBUFNBS# :oRESERVED_13# DSHIFTBUFHWS7#:oRESERVED_14U#DSHIFTBUFNISu#PFLEXIO_TypeM*TCM_CTRLD#OCRAM_MAGIC_ADDRD#DTCM_MAGIC_ADDRD#ITCM_MAGIC_ADDRD# INT_STATUSD#INT_STAT_END#INT_SIG_END#PFLEXRAM_TypeO*MCR0D#MCR1D#MCR2D#AHBCRD# INTEND#INTRD#LUTKEYD#LUTCRD#DAHBRXBUFCR0# :/RESERVED_0ز#0DFLSHCR0#`DFLSHCR1#pDFLSHCR2(#:RESERVED_1B#FLSHCR4D#:RESERVED_2q#IPCR0D#IPCR1D#:RESERVED_3#IPCMDD#:RESERVED_4ٳ#IPRXFCRD#IPTXFCRD#DDLLCR#:RESERVED_50#STS0P#STS1P#STS2P#AHBSPNDSTSP#IPRXFSTSP#IPTXFSTSP#:RESERVED_6#PRFDRʴ#DTFDR#D?LUT#PFLEXSPI_TypePQ*<CNTRD#:RESERVED_05#DIMRS#PISRh#: RESERVED_1}#(IMR5D#4ISR5P#8PGPC_Type$U* DRD#GDIRD#PSRP#ICR1D# ICR2D#IMRD#ISRD#EDGE_SELD#PGPIO_TypeŵU*(CRD#PRD#SRD#IRD# DOCRi#PICR~#CNTP#$PGPT_Type<W*VERIDP#PARAMP#TCSRD#TCR1D# TCR2D#TCR3D#TCR4D#TCR5D#DTDR# :RESERVED_0-#0PTFRK#@:RESERVED_1`#PTMRD#`:#RESERVED_2#dRCSRD#RCR1D#RCR2D#RCR3D#RCR4D#RCR5D#PRDR#:RESERVED_3 #PRFR*#:RESERVED_4@#RMRD#PI2S_TypeY* :RESERVED_0#D{SW_MUX_CTL_PAD#D{SW_PAD_CTL_PAD#DSELECT_INPUT#PIOMUXC_Type}\*hGPR0Y#GPR1D#GPR2D#GPR3D# GPR4D#GPR5D#GPR6D#GPR7D#GPR8D# GPR9Y#$GPR10D#(GPR11D#,GPR12D#0GPR13D#4GPR14D#8GPR15Y#<GPR16D#@GPR17D#DGPR18D#HGPR19D#LGPR20D#PGPR21D#TGPR22D#XGPR23D#\GPR24D#`GPR25D#dPIOMUXC_GPR_Type]*$SW_MUX_CTL_PAD_WAKEUPD#SW_MUX_CTL_PAD_PMIC_ON_REQD#SW_MUX_CTL_PAD_PMIC_STBY_REQD#SW_PAD_CTL_PAD_TEST_MODED# SW_PAD_CTL_PAD_POR_BD#SW_PAD_CTL_PAD_ONOFFD#SW_PAD_CTL_PAD_WAKEUPD#SW_PAD_CTL_PAD_PMIC_ON_REQD#SW_PAD_CTL_PAD_PMIC_STBY_REQD# PIOMUXC_SNVS_Typec*GPR0Y#GPR1Y#GPR2Y#GPR3D# PIOMUXC_SNVS_GPR_Typed*KPCRp#KPSRp#KDDRp#KPDRp#PKPP_Typee*@PIGEON_0D#: RESERVED_0u#PIGEON_1D#: RESERVED_1#PIGEON_2D# :RESERVED_2Ѽ#$*CTRLD#CTRL_SETD#CTRL_CLRD#CTRL_TOGD# CTRL1D#CTRL1_SETD#CTRL1_CLRD#CTRL1_TOGD#CTRL2D# CTRL2_SETD#$CTRL2_CLRD#(CTRL2_TOGD#,TRANSFER_COUNTD#0: RESERVED_0Ƚ#4CUR_BUFD#@: RESERVED_1#DNEXT_BUFD#P:RESERVED_2##TVDCTRL0D#pVDCTRL0_SETD#tVDCTRL0_CLRD#xVDCTRL0_TOGD#|VDCTRL1D#: RESERVED_3#VDCTRL2D#: RESERVED_4Ⱦ#VDCTRL3D#: RESERVED_5#VDCTRL4D#:RESERVED_6&#BM_ERROR_STATD#: RESERVED_7\#CRC_STATD#: RESERVED_8#STATP#:KRESERVED_9#THRESD#:RESERVED_10#PIGEONCTRL0D#PIGEONCTRL0_SETD#PIGEONCTRL0_CLRD#PIGEONCTRL0_TOGD#PIGEONCTRL1D#PIGEONCTRL1_SETD#PIGEONCTRL1_CLRD#PIGEONCTRL1_TOGD#PIGEONCTRL2D#PIGEONCTRL2_SETD#PIGEONCTRL2_CLRD#PIGEONCTRL2_TOGD#:RESERVED_11#ł` PIGEON;#LUT_CTRLD#: RESERVED_12e#LUT0_ADDRD#: RESERVED_13#LUT0_DATAD#Ճ: RESERVED_14#LUT1_ADDRD#: RESERVED_15#LUT1_DATAD#PLCDIF_Typef*VERIDP#PARAMP#:RESERVED_0a#MCRD#MSRD#MIERD#MDERD#MCFGR0D# MCFGR1D#$MCFGR2D#(MCFGR3D#,:RESERVED_1#0MDMRD#@:RESERVED_2#DMCCR0D#HƆ:RESERVED_3:#LMCCR1D#P:RESERVED_4e#TMFCRD#XMFSRP#\MTDRD#`: RESERVED_5#dMRDRP#pއ:RESERVED_6#tSCRD#SSRD#SIERD#SDERD#:RESERVED_7"#SCFGR1D#SCFGR2D#:RESERVED_8_#SAMRD#: RESERVED_9#SASRP#STARD#Љ:RESERVED_10#STDRD#: RESERVED_11#SRDRP#PLPI2C_TypeAo*xVERIDP#PARAMP#݊:RESERVED_0Q#CRD#SRD#IERD#DERD#CFGR0D# CFGR1D#$:RESERVED_1#(DMR0D#0DMR1D#4:RESERVED_2#8CCRD#@:RESERVED_3#DFCRD#XFSRP#\TCRD#`TDRD#d:RESERVED_4\#hRSRP#pRDRP#tPLPSPI_Type2s*Î0VERIDP#PARAMP#GLOBALD#PINCFGD# BAUDD#STATD#CTRLD#DATAD#MATCHD# MODIRD#$FIFOD#(WATERD#,PLPUART_Typeu* CTRLD#CTRL_SETD#CTRL_CLRD#CTRL_TOGD# TIMINGD#: RESERVED_0#DATAD# ݏ: RESERVED_1#$READ_CTRLD#0: RESERVED_2#4READ_FUSE_DATAD#@: RESERVED_34#DSW_STICKYD#P: RESERVED_4c#TSCSD#`SCS_SETD#dSCS_CLRD#hSCS_TOGD#lő:RESERVED_5#pVERSIONP#:kRESERVED_6#TIMING2D#:RESERVED_7#LOCKD#ϒ: RESERVED_8C#CFG0D#: RESERVED_9o#CFG1D#: RESERVED_10#CFG2D#ԓ: RESERVED_11#CFG3D#: RESERVED_12#CFG4D#: RESERVED_13"#CFG5D#۔: RESERVED_14O#CFG6D#: RESERVED_15|#MEM0D# : RESERVED_16# MEM1D# : RESERVED_17# MEM2D# : RESERVED_18# MEM3D# : RESERVED_190# MEM4D# : RESERVED_20]# ANA0D# : RESERVED_21# ANA1D# ×: RESERVED_22# ANA2D# :RESERVED_23# SRK0D# : RESERVED_24# SRK1D# ˘: RESERVED_25?# SRK2D# : RESERVED_26l# SRK3D# : RESERVED_27# SRK4D# ҙ: RESERVED_28# SRK5D# : RESERVED_29# SRK6D# : RESERVED_30 # SRK7D# ٚ: RESERVED_31M# SJC_RESP0D# : RESERVED_32# SJC_RESP1D# : RESERVED_33# MAC0D# : RESERVED_34# MAC1D# : RESERVED_35 # GP3D# Ü:RESERVED_367# GP1D# : RESERVED_37c# GP2D# : RESERVED_38# SW_GP1D# ʝ: RESERVED_39# SW_GP20D# : RESERVED_40# SW_GP21D# : RESERVED_41# SW_GP22D# ڞ: RESERVED_42N# SW_GP23D# : RESERVED_43~# MISC_CONF0D# : RESERVED_44# MISC_CONF1D# : RESERVED_45# SRK_REVOKED# POCOTP_TypeWy*:RESERVED_01#MEGA_CTRLD#MEGA_PUPSCRD#MEGA_PDNSCRD#MEGA_SRD#:oRESERVED_1#CPU_CTRLD#CPU_PUPSCRD#CPU_PDNSCRD#CPU_SRD#PPGC_Type+}*ɢLDVALD#CVALP#TCTRLD#TFLGD# *ӣMCRD#:RESERVED_0Z#LTMR64HP#LTMR64LP#:RESERVED_1#£CHANNEL#PPIT_TypeI~*:RESERVED_0#REG_1P1D#REG_1P1_SETD#REG_1P1_CLRD#REG_1P1_TOGD#REG_3P0D#REG_3P0_SETD#REG_3P0_CLRD#REG_3P0_TOGD#REG_2P5D#REG_2P5_SETD#REG_2P5_CLRD#REG_2P5_TOGD#REG_CORED#REG_CORE_SETD#REG_CORE_CLRD#REG_CORE_TOGD#MISC0D#MISC0_SETD#MISC0_CLRD#MISC0_TOGD#MISC1D#MISC1_SETD#MISC1_CLRD#MISC1_TOGD#MISC2D#MISC2_SETD#MISC2_CLRD#MISC2_TOGD#PPMU_Type*`CNT֣#INITp#CTRL2p#CTRLp#ܨ:RESERVED_0P#VAL0p# FRACVAL1p# VAL1p#FRACVAL2p#VAL2p#FRACVAL3p#VAL3p#FRACVAL4p#VAL4p#FRACVAL5p#VAL5p#FRCTRLp# OCTRLp#"STSp#$INTENp#&DMAENp#(TCTRLp#*ݪpDISMAPS#,DTCNT0p#0DTCNT1p#2CAPTCTRLAp#4CAPTCOMPAp#6CAPTCTRLBp#8CAPTCOMPBp#:CAPTCTRLXp#<CAPTCOMPXp#>CVAL0֣#@CVAL0CYC֣#BCVAL1֣#DCVAL1CYC֣#FCVAL2֣#HCVAL2CYC֣#JCVAL3֣#LCVAL3CYC֣#NCVAL4֣#PCVAL4CYC֣#RCVAL5֣#TCVAL5CYC֣#V:RESERVED_1#X*ʭSM#OUTENp#MASKp#SWCOUTp#DTSRCSELp#MCTRLp#MCTRL2p#FCTRLp#FSTSp#FFILTp#FTSTp#FCTRL2p#PPWM_Type*CTRLD#CTRL_SETD#CTRL_CLRD#CTRL_TOGD# STATD#STAT_SETD#STAT_CLRD#STAT_TOGD#OUT_CTRLD# OUT_CTRL_SETD#$OUT_CTRL_CLRD#(OUT_CTRL_TOGD#,OUT_BUFD#0: RESERVED_0]#4OUT_BUF2D#@: RESERVED_1#DOUT_PITCHD#PƱ: RESERVED_2#TOUT_LRCD#`: RESERVED_3#dOUT_PS_ULCD#p: RESERVED_4#tOUT_PS_LRCD#Բ: RESERVED_5H#OUT_AS_ULCD#: RESERVED_6z#OUT_AS_LRCD#: RESERVED_7#PS_CTRLD#PS_CTRL_SETD#PS_CTRL_CLRD#PS_CTRL_TOGD#PS_BUFD#: RESERVED_8&#PS_UBUFD#: RESERVED_9U#PS_VBUFD#: RESERVED_10#PS_PITCHD#: RESERVED_11#PS_BACKGROUNDD#: RESERVED_12#PS_SCALED#: RESERVED_13#PS_OFFSETD#ڶ: RESERVED_14N#PS_CLRKEYLOWD#: RESERVED_15#PS_CLRKEYHIGHD#ŷ: RESERVED_16#AS_CTRLD#: RESERVED_17#AS_BUFD#: RESERVED_18#AS_PITCHD#ո: RESERVED_19I#AS_CLRKEYLOWD#: RESERVED_20~#AS_CLRKEYHIGHD#: RESERVED_21#CSC1_COEF0D#: RESERVED_22#CSC1_COEF1D#: RESERVED_23#CSC1_COEF2D#ں:RESERVED_24M#POWERD#:RESERVED_25|#NEXTD#:;RESERVED_26#PORTER_DUFF_CTRLD#PPXP_Type*ƽ:RESERVED_0#DROMPATCHD#ROMPATCHCNTLD#ROMPATCHENHY#ROMPATCHENLD#DROMPATCHAv#:RESERVED_1#ROMPATCHSRD#PROMC_Type*CSD#CNTD#TOVALD#WIND# PRTWDOG_Type*MCRD#IOCRD#BMCR0D#BMCR1D# DBRX#:RESERVED_0l#4INTEND#8INTRD#<SDRAMCR0D#@SDRAMCR1D#DSDRAMCR2D#HSDRAMCR3D#LNANDCR0D#PNANDCR1D#TNANDCR2D#XNANDCR3D#\NORCR0D#`NORCR1D#dNORCR2D#hNORCR3Y#lSRAMCR0D#pSRAMCR1D#tSRAMCR2D#xSRAMCR3Y#|DBICR0D#DBICR1D#:RESERVED_1#IPCR0D#IPCR1D#IPCR2D#IPCMDD#IPTXDATD#: RESERVED_2#IPRXDATP#: RESERVED_3K#STS0P#STS1Y#STS2P#STS3Y#STS4Y#STS5Y#STS6Y#STS7Y#STS8Y#STS9Y#STS10Y#STS11Y#STS12P#STS13Y#STS14Y#STS15Y#PSEMC_Type!*HPLRD#HPCOMRD#HPCRD#HPSICRD# HPSVCRD#HPSRD#HPSVSRD#HPHACIVRD#HPHACRP# HPRTCMRD#$HPRTCLRD#(HPTAMRD#,HPTALRD#0LPLRD#4LPCRD#8LPMKCRD#<LPSVCRD#@:RESERVED_0\#DLPTDCRD#HLPSRD#LLPSRTCMRD#PLPSRTCLRD#TLPTARD#XLPSMCMRP#\LPSMCLRP#`LPPGDRD#dLPGPR0_LEGACY_ALIASD#hDLPZMKR#l:RESERVED_1 #DLPGPR_ALIAS?#:_RESERVED_2]#DLPGPR|#:RESERVED_3#HPVIDR1P#HPVIDR2P#PSNVS_TypenSSICDSISP*TSCRD#SRCDD#SRPCD#SIED# #SRLP#SRRP#SRCSHP#SRCSLP# SRUP#$SRQP#(STLD#,STRD#0STCSCHD#4STCSCLD#8:RESERVED_0#<SRFMP#D:RESERVED_1#HSTCD#PPSPDIF_Type*HSCRD#SBMR1P#SRSRD#:RESERVED_0B# SBMR2P#D GPRm# PSRC_Type*:RESERVED_0#TEMPSENSE0D#TEMPSENSE0_SETD#TEMPSENSE0_CLRD#TEMPSENSE0_TOGD#TEMPSENSE1D#TEMPSENSE1_SETD#TEMPSENSE1_CLRD#TEMPSENSE1_TOGD#:RESERVED_1j#TEMPSENSE2D#TEMPSENSE2_SETD#TEMPSENSE2_CLRD#TEMPSENSE2_TOGD#PTEMPMON_Type* COMP1p#COMP2p#CAPTp#LOADp#HOLDp#CNTRp# CTRLp# SCTRLp#CMPLD1p#CMPLD2p#CSCTRLp#FILTp#DMAp#:RESERVED_0#ENBLp#*CHANNEL#PTMR_TypeSPKRMAXDPKRSQPSSBLIMDTOTSAMPSFRQCNTPFRQMAXDSSCMCPSCMLDSSCR1CPSCR1LDSSCR2CPSCR2LDSSCR3CPSCR3LDSSCR4CPSCR4LDSSCR5CPSCR5LDSSCR6PCPSCR6PLD*MCTLD#SCMISCD#PKRRNGD## SDCTLD##FRQMIND#5#Q# i#$#(#,#0#4#8STATUSP#<PENT#@PKRCNT10P#PKRCNT32P#PKRCNT54P#PKRCNT76P#PKRCNT98P#PKRCNTBAP#PKRCNTDCP#PKRCNTFEP#SEC_CFGD#INT_CTRLD#INT_MASKD#INT_STATUSP#:?RESERVED_0#VID1P#VID2P#PTRNG_Typeŧ*BASIC_SETTINGD#: RESERVED_0#PS_INPUT_BUFFER_ADDRD#: RESERVED_12#FLOW_CONTROLD# : RESERVED_2d#$MEASEURE_VALUEP#0: RESERVED_3#4INT_END#@: RESERVED_4#DINT_SIG_END#P: RESERVED_5#TINT_STATUSD#`: RESERVED_6$#dDEBUG_MODED#p: RESERVED_7T#tDEBUG_MODE2D#PTSC_TypeSDEVICEADDRDPERIODICLISTBASEDSASYNCLISTADDRDENDPTLISTADDRD*IDP#HWGENERALP#HWHOSTP#HWDEVICEP# HWTXBUFP#HWRXBUFP#:gRESERVED_0J#GPTIMER0LDD#GPTIMER0CTRLD#GPTIMER1LDD#GPTIMER1CTRLD#SBUSCFGD#:kRESERVED_1#CAPLENGTH#:RESERVED_2#HCIVERSION֣#HCSPARAMSP#HCCPARAMSP#:RESERVED_3O#DCIVERSION֣#:RESERVED_4#DCCPARAMSP#:RESERVED_5#USBCMDD#USBSTSD#USBINTRD#FRINDEXD#:RESERVED_6###:RESERVED_7@#BURSTSIZED#TXFILLTUNINGD#:RESERVED_8#ENDPTNAKD#ENDPTNAKEND#CONFIGFLAGP#PORTSC1D#:RESERVED_9#OTGSCD#USBMODED#ENDPTSETUPSTATD#ENDPTPRIMED#ENDPTFLUSHD#ENDPTSTATP#ENDPTCOMPLETED#ENDPTCTRL0D#DENDPTCTRL#:tPUSB_Type*:RESERVED_0#USB_OTGn_CTRLD#:RESERVED_1#USB_OTGn_PHY_CTRL_0D#PUSBNC_Type*PWDD#PWD_SETD#PWD_CLRD#PWD_TOGD# TXD#TX_SETD#TX_CLRD#TX_TOGD#RXD# RX_SETD#$RX_CLRD#(RX_TOGD#,CTRLD#0CTRL_SETD#4CTRL_CLRD#8CTRL_TOGD#<STATUSD#@: RESERVED_0U#DDEBUGrD#PDEBUG_SETD#TDEBUG_CLRD#XDEBUG_TOGD#\DEBUG0_STATUSP#`: RESERVED_1#dDEBUG1D#pDEBUG1_SETD#tDEBUG1_CLRD#xDEBUG1_TOGD#|VERSIONP#PUSBPHY_Typee*`VBUS_DETECTD#VBUS_DETECT_SETD#VBUS_DETECT_CLRD#VBUS_DETECT_TOGD# CHRG_DETECTD#CHRG_DETECT_SETD#CHRG_DETECT_CLRD#CHRG_DETECT_TOGD#VBUS_DETECT_STATP# : RESERVED_0#$CHRG_DETECT_STATP#0:RESERVED_1T#4MISCD#PMISC_SETD#TMISC_CLRD#XMISC_TOGD#\*:RESERVED_0#QINSTANCE#DIGPROGP#PUSB_ANALOG_Type*DS_ADDRD#BLK_ATTD#CMD_ARGD#CMD_XFR_TYPD# CMD_RSP0P#CMD_RSP1P#CMD_RSP2P#CMD_RSP3P#DATA_BUFF_ACC_PORTD# PRES_STATEP#$PROT_CTRLD#(SYS_CTRLD#,INT_STATUSD#0INT_STATUS_END#4INT_SIGNAL_END#8AUTOCMD12_ERR_STATUSD#<HOST_CTRL_CAPD#@WTMK_LVLD#DMIX_CTRLD#H:RESERVED_0y#LFORCE_EVENTD#PADMA_ERR_STATUSP#TADMA_SYS_ADDRD#X:RESERVED_1#\DLL_CTRLD#`DLL_STATUSP#dCLK_TUNE_CTRL_STATUSD#h:SRESERVED_22#lVEND_SPECD#MMC_BOOTD#VEND_SPEC2D#TUNING_CTRLD#PUSDHC_Type* WCRp#WSRp#WRSR֣#WICRp#WMCRp#PWDOG_Type*SEL0p#SEL1p#SEL2p#SEL3p#SEL4p#SEL5p# SEL6p# SEL7p#SEL8p#SEL9p#SEL10p#SEL11p#SEL12p#SEL13p#SEL14p#SEL15p#SEL16p# SEL17p#"SEL18p#$SEL19p#&SEL20p#(SEL21p#*SEL22p#,SEL23p#.SEL24p#0SEL25p#2SEL26p#4SEL27p#6SEL28p#8SEL29p#:SEL30p#<SEL31p#>SEL32p#@SEL33p#BSEL34p#DSEL35p#FSEL36p#HSEL37p#JSEL38p#LSEL39p#NSEL40p#PSEL41p#RSEL42p#TSEL43p#VSEL44p#XSEL45p#ZSEL46p#\SEL47p#^SEL48p#`SEL49p#bSEL50p#dSEL51p#fSEL52p#hSEL53p#jSEL54p#lSEL55p#nSEL56p#pSEL57p#rSEL58p#tSEL59p#vSEL60p#xSEL61p#zSEL62p#|SEL63p#~SEL64p#SEL65p#CTRL0p#CTRL1p#PXBARA_Type*SEL0p#SEL1p#SEL2p#SEL3p#SEL4p#SEL5p# SEL6p# SEL7p#PXBARB_Type*:RESERVED_0 #MISC0D#MISC0_SETD#MISC0_CLRD#MISC0_TOGD#:RESERVED_1n#LOWPWR_CTRLD#LOWPWR_CTRL_SETD#LOWPWR_CTRL_CLRD#LOWPWR_CTRL_TOGD#:RESERVED_2#OSC_CONFIG0D#OSC_CONFIG0_SETD#OSC_CONFIG0_CLRD#OSC_CONFIG0_TOGD#OSC_CONFIG1D#OSC_CONFIG1_SETD#OSC_CONFIG1_CLRD#OSC_CONFIG1_TOGD#OSC_CONFIG2D#OSC_CONFIG2_SETD#OSC_CONFIG2_CLRD#OSC_CONFIG2_TOGD#PXTALOSC24M_Type| .\middleware\flexspi/fsl_flexspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash)L>_Bool"YPflexspi_serial_clk_freq_tuPflexspi_read_sample_clk_tPflexspi_ipcmd_error_tPflexspi_lut_seq_tPflexspi_dll_time_t Pflexspi_mem_config_t$ Pflexspi_operation_t)Pflexspi_xfer_tkFlexSpiClock_CoreClock kFlexSpiClock_AhbClock kFlexSpiClock_SerialRootClock kFlexSpiClock_IpgClock Pflexspi_clock_type_t_FlexSpiSerialClockFreqkFlexSpiSerialClk_30MHz kFlexSpiSerialClk_50MHz kFlexSpiSerialClk_60MHz kFlexSpiSerialClk_75MHz kFlexSpiSerialClk_80MHz kFlexSpiSerialClk_100MHz kFlexSpiSerialClk_133MHz kFlexSpiSerialClk_166MHz kFlexSpiSerialClk_200MHz kFlexSpiClk_SDR kFlexSpiClk_DDR  _FlashReadSampleClkSourcekFlexSPIReadSampleClk_LoopbackInternally kFlexSPIReadSampleClk_LoopbackFromDqsPad kFlexSPIReadSampleClk_LoopbackFromSckPad kFlexSPIReadSampleClk_ExternalInputFromDqsPad  _FlexSpiIpCmdErrorkFlexSpiIpCmdError_NoError kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode kFlexSpiIpCmdError_JumpOnCsInIpCmd kFlexSpiIpCmdError_UnknownOpCode kFlexSpiIpCmdError_SdrDummyInDdrSequence kFlexSpiIpCmdError_DDRDummyInSdrSequence kFlexSpiIpCmdError_InvalidAddress kFlexSpiIpCmdError_SequenceExecutionTimeout kFlexSpiIpCmdError_FlashBoundaryAcrosss  _flexspi_statuskStatus_FLEXSPI_SequenceExecutionTimeoutXkStatus_FLEXSPI_InvalidSequenceYkStatus_FLEXSPI_DeviceTimeoutZkFlexSpiMiscOffset_DiffClkEnable kFlexSpiMiscOffset_Ck2Enable kFlexSpiMiscOffset_ParallelEnable kFlexSpiMiscOffset_WordAddressableEnable kFlexSpiMiscOffset_SafeConfigFreqEnable kFlexSpiMiscOffset_PadSettingOverrideEnable kFlexSpiMiscOffset_DdrModeEnable kFlexSpiMiscOffset_UseValidTimeForAllFreq kFlexSpiDeviceType_SerialNOR kFlexSpiDeviceType_SerialNAND kFlexSpiDeviceType_SerialRAM kFlexSpiDeviceType_MCP_NOR_NAND kFlexSpiDeviceType_MCP_NOR_RAM kSerialFlash_1Pad kSerialFlash_2Pads kSerialFlash_4Pads kSerialFlash_8Pads )_lut_sequenceseqNum:#seqId:#reservedI#kDeviceConfigCmdType_Generic kDeviceConfigCmdType_QuadEnable kDeviceConfigCmdType_Spi2Xpi kDeviceConfigCmdType_Xpi2Spi kDeviceConfigCmdType_Spi2NoCmd kDeviceConfigCmdType_Reset *time_100ps:#delay_cells:#)_FlexSPIConfigtagY#versionY#reserved0Y#readSampleClkSrc:# dataHoldTime:# dataSetupTime:#columnAddressWidth:#deviceModeCfgEnable:#deviceModeType:#waitTimeCfgCommandsI#deviceModeSeq^#deviceModeArgY#configCmdEnable:#:configModeTypec #^configCmdSeqs # reserved1Y#,YconfigCmdArgs #0reserved2Y#<controllerMiscOptionY#@deviceType:#DsflashPadType:#EserialClkFreq:#FlutCustomSeqEnable:#GYreserved3d #HsflashA1SizeY#PsflashA2SizeY#TsflashB1SizeY#XsflashB2SizeY#\csPadSettingOverrideY#`sclkPadSettingOverrideY#ddataPadSettingOverrideY#hdqsPadSettingOverrideY#ltimeoutInMsY#pcommandIntervalY#txdataValidTime #xbusyOffsetI#|busyBitPolarityI#~Y?lookupTable #^ lutCustomSeq #Yreserved4 #_FlexSPIOperationTypekFlexSpiOperation_Command kFlexSpiOperation_Config kFlexSpiOperation_Write kFlexSpiOperation_Read kFlexSpiOperation_End )_FlexSpiXfer$operation#baseAddressY#seqIdY#seqNumY# isParallelModeEnable#txBuffer#txSizeY#rxBuffer#rxSizeY# 4 devices\MIMXRT1052\MIMXRT1052.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashIRQnNotAvail_IRQnNonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnDMA0_DMA16_IRQnDMA1_DMA17_IRQnDMA2_DMA18_IRQnDMA3_DMA19_IRQnDMA4_DMA20_IRQnDMA5_DMA21_IRQnDMA6_DMA22_IRQnDMA7_DMA23_IRQnDMA8_DMA24_IRQnDMA9_DMA25_IRQn DMA10_DMA26_IRQn DMA11_DMA27_IRQn DMA12_DMA28_IRQn DMA13_DMA29_IRQn DMA14_DMA30_IRQnDMA15_DMA31_IRQnDMA_ERROR_IRQnCTI0_ERROR_IRQnCTI1_ERROR_IRQnCORE_IRQnLPUART1_IRQnLPUART2_IRQnLPUART3_IRQnLPUART4_IRQnLPUART5_IRQnLPUART6_IRQnLPUART7_IRQnLPUART8_IRQnLPI2C1_IRQnLPI2C2_IRQnLPI2C3_IRQnLPI2C4_IRQnLPSPI1_IRQn LPSPI2_IRQn!LPSPI3_IRQn"LPSPI4_IRQn#CAN1_IRQn$CAN2_IRQn%FLEXRAM_IRQn&KPP_IRQn'TSC_DIG_IRQn(GPR_IRQ_IRQn)LCDIF_IRQn*CSI_IRQn+PXP_IRQn,WDOG2_IRQn-SNVS_HP_WRAPPER_IRQn.SNVS_HP_WRAPPER_TZ_IRQn/SNVS_LP_WRAPPER_IRQn0CSU_IRQn1DCP_IRQn2DCP_VMI_IRQn3Reserved68_IRQn4TRNG_IRQn5SJC_IRQn6BEE_IRQn7SAI1_IRQn8SAI2_IRQn9SAI3_RX_IRQn:SAI3_TX_IRQn;SPDIF_IRQn<ANATOP_EVENT0_IRQn=ANATOP_EVENT1_IRQn>ANATOP_TAMP_LOW_HIGH_IRQn?ANATOP_TEMP_PANIC_IRQnUSB_PHY1_IRQnUSB_PHY2_IRQnADC1_IRQnADC2_IRQnDCDC_IRQnReserved86_IRQnReserved87_IRQnGPIO1_INT0_IRQnGPIO1_INT1_IRQnGPIO1_INT2_IRQnGPIO1_INT3_IRQnGPIO1_INT4_IRQnGPIO1_INT5_IRQnGPIO1_INT6_IRQnGPIO1_INT7_IRQnGPIO1_Combined_0_15_IRQnGPIO1_Combined_16_31_IRQnGPIO2_Combined_0_15_IRQnGPIO2_Combined_16_31_IRQnGPIO3_Combined_0_15_IRQnGPIO3_Combined_16_31_IRQnGPIO4_Combined_0_15_IRQnGPIO4_Combined_16_31_IRQnGPIO5_Combined_0_15_IRQnGPIO5_Combined_16_31_IRQnFLEXIO1_IRQnFLEXIO2_IRQnWDOG1_IRQnRTWDOG_IRQnEWM_IRQnCCM_1_IRQnCCM_2_IRQnGPC_IRQnSRC_IRQnReserved115_IRQnGPT1_IRQnGPT2_IRQnPWM1_0_IRQnPWM1_1_IRQnPWM1_2_IRQnPWM1_3_IRQnPWM1_FAULT_IRQnReserved123_IRQnFLEXSPI_IRQnSEMC_IRQnUSDHC1_IRQnUSDHC2_IRQnUSB_OTG2_IRQnUSB_OTG1_IRQnENET_IRQnENET_1588_Timer_IRQnXBAR1_IRQ_0_1_IRQnXBAR1_IRQ_2_3_IRQnADC_ETC_IRQ0_IRQnADC_ETC_IRQ1_IRQnADC_ETC_IRQ2_IRQnADC_ETC_ERROR_IRQ_IRQnPIT_IRQnACMP1_IRQnACMP2_IRQnACMP3_IRQnACMP4_IRQnReserved143_IRQnReserved144_IRQnENC1_IRQnENC2_IRQnENC3_IRQnENC4_IRQnTMR1_IRQnTMR2_IRQnTMR3_IRQnTMR4_IRQnPWM2_0_IRQnPWM2_1_IRQnPWM2_2_IRQnPWM2_3_IRQnPWM2_FAULT_IRQnPWM3_0_IRQnPWM3_1_IRQnPWM3_2_IRQnPWM3_3_IRQnPWM3_FAULT_IRQnPWM4_0_IRQnPWM4_1_IRQnPWM4_2_IRQnPWM4_3_IRQnPWM4_FAULT_IRQnReserved168_IRQnReserved169_IRQnReserved170_IRQnReserved171_IRQnReserved172_IRQnReserved173_IRQnSJC_ARM_DEBUG_IRQnNMI_WAKEUP_IRQnPIRQn_Type7_dma_request_sourcekDmaRequestMuxFlexIO1Request0Request1kDmaRequestMuxFlexIO2Request0Request1kDmaRequestMuxLPUART1TxkDmaRequestMuxLPUART1RxkDmaRequestMuxLPUART3TxkDmaRequestMuxLPUART3RxkDmaRequestMuxLPUART5TxkDmaRequestMuxLPUART5RxkDmaRequestMuxLPUART7TxkDmaRequestMuxLPUART7Rx kDmaRequestMuxCSI kDmaRequestMuxLPSPI1Rx kDmaRequestMuxLPSPI1TxkDmaRequestMuxLPSPI3RxkDmaRequestMuxLPSPI3TxkDmaRequestMuxLPI2C1kDmaRequestMuxLPI2C3kDmaRequestMuxSai1RxkDmaRequestMuxSai1TxkDmaRequestMuxSai2RxkDmaRequestMuxSai2TxkDmaRequestMuxADC_ETCkDmaRequestMuxADC1kDmaRequestMuxACMP1kDmaRequestMuxACMP2kDmaRequestMuxFlexSPIRxkDmaRequestMuxFlexSPITxkDmaRequestMuxXBAR1Request0kDmaRequestMuxXBAR1Request1kDmaRequestMuxFlexPWM1CaptureSub0 kDmaRequestMuxFlexPWM1CaptureSub1!kDmaRequestMuxFlexPWM1CaptureSub2"kDmaRequestMuxFlexPWM1CaptureSub3#kDmaRequestMuxFlexPWM1ValueSub0$kDmaRequestMuxFlexPWM1ValueSub1%kDmaRequestMuxFlexPWM1ValueSub2&kDmaRequestMuxFlexPWM1ValueSub3'kDmaRequestMuxFlexPWM3CaptureSub0(kDmaRequestMuxFlexPWM3CaptureSub1)kDmaRequestMuxFlexPWM3CaptureSub2*kDmaRequestMuxFlexPWM3CaptureSub3+kDmaRequestMuxFlexPWM3ValueSub0,kDmaRequestMuxFlexPWM3ValueSub1-kDmaRequestMuxFlexPWM3ValueSub2.kDmaRequestMuxFlexPWM3ValueSub3/kDmaRequestMuxQTIMER1CaptTimer00kDmaRequestMuxQTIMER1CaptTimer11kDmaRequestMuxQTIMER1CaptTimer22kDmaRequestMuxQTIMER1CaptTimer33kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer14kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer05kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer36kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer27kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer18kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer19kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1:kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1;kDmaRequestMuxFlexIO1Request2Request3@kDmaRequestMuxFlexIO2Request2Request3AkDmaRequestMuxLPUART2TxBkDmaRequestMuxLPUART2RxCkDmaRequestMuxLPUART4TxDkDmaRequestMuxLPUART4RxEkDmaRequestMuxLPUART6TxFkDmaRequestMuxLPUART6RxGkDmaRequestMuxLPUART8TxHkDmaRequestMuxLPUART8RxIkDmaRequestMuxPxpKkDmaRequestMuxLCDIFLkDmaRequestMuxLPSPI2RxMkDmaRequestMuxLPSPI2TxNkDmaRequestMuxLPSPI4RxOkDmaRequestMuxLPSPI4TxPkDmaRequestMuxLPI2C2QkDmaRequestMuxLPI2C4RkDmaRequestMuxSai3RxSkDmaRequestMuxSai3TxTkDmaRequestMuxSpdifRxUkDmaRequestMuxSpdifTxVkDmaRequestMuxADC2XkDmaRequestMuxACMP3YkDmaRequestMuxACMP4ZkDmaRequestMuxEnetTimer0\kDmaRequestMuxEnetTimer1]kDmaRequestMuxXBAR1Request2^kDmaRequestMuxXBAR1Request3_kDmaRequestMuxFlexPWM2CaptureSub0`kDmaRequestMuxFlexPWM2CaptureSub1akDmaRequestMuxFlexPWM2CaptureSub2bkDmaRequestMuxFlexPWM2CaptureSub3ckDmaRequestMuxFlexPWM2ValueSub0dkDmaRequestMuxFlexPWM2ValueSub1ekDmaRequestMuxFlexPWM2ValueSub2fkDmaRequestMuxFlexPWM2ValueSub3gkDmaRequestMuxFlexPWM4CaptureSub0hkDmaRequestMuxFlexPWM4CaptureSub1ikDmaRequestMuxFlexPWM4CaptureSub2jkDmaRequestMuxFlexPWM4CaptureSub3kkDmaRequestMuxFlexPWM4ValueSub0lkDmaRequestMuxFlexPWM4ValueSub1mkDmaRequestMuxFlexPWM4ValueSub2nkDmaRequestMuxFlexPWM4ValueSub3okDmaRequestMuxQTIMER2CaptTimer0pkDmaRequestMuxQTIMER2CaptTimer1qkDmaRequestMuxQTIMER2CaptTimer2rkDmaRequestMuxQTIMER2CaptTimer3skDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1tkDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0ukDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3vkDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2wkDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1xkDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1ykDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1zkDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1{Pdma_request_source_te ]_iomuxc_sw_mux_ctl_padkIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 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5kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 6kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 7kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 8kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 9kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 :kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 ;kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 <kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 =kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 >kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 ?kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 @kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 AkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 BkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 CkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 DkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 EkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 FkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 GkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 HkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 IkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 JkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 KkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 LkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 MkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 NkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 OkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 PkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 QkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 RkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 SkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 TkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 UkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 VkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 WkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 XkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 YkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 ZkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 [kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 \kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 ]kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 ^kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 _kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 `kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 akIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 bkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 ckIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 dkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 ekIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 fkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 gkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 hkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 ikIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 jkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 kkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 lkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 mkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 nkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 okIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 pkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 qkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 rkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 skIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 tkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 ukIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 vkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 wkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 xkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 ykIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 zkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 {Piomuxc_sw_mux_ctl_pad_tȃ_iomuxc_sw_pad_ctl_padkIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 !kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 "kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 #kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 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>kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 ?kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 @kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 AkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 BkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 CkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 DkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 EkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 FkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 GkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 HkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 IkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 JkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 KkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 LkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 MkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 NkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 OkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 PkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 QkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 RkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 SkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 TkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 UkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 VkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 WkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 XkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 YkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 ZkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 [kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 \kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 ]kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 ^kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 _kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 `kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 akIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 bkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 ckIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 dkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 ekIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 fkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 gkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 hkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 ikIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 jkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 kkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 lkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 mkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 nkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 okIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 pkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 qkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 rkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 skIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 tkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 ukIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 vkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 wkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 xkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 ykIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 zkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 {Piomuxc_sw_pad_ctl_pad_t._iomuxc_select_inputkIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT kIOMUXC_CCM_PMIC_READY_SELECT_INPUT kIOMUXC_CSI_DATA02_SELECT_INPUT kIOMUXC_CSI_DATA03_SELECT_INPUT kIOMUXC_CSI_DATA04_SELECT_INPUT kIOMUXC_CSI_DATA05_SELECT_INPUT kIOMUXC_CSI_DATA06_SELECT_INPUT kIOMUXC_CSI_DATA07_SELECT_INPUT kIOMUXC_CSI_DATA08_SELECT_INPUT kIOMUXC_CSI_DATA09_SELECT_INPUT kIOMUXC_CSI_HSYNC_SELECT_INPUT kIOMUXC_CSI_PIXCLK_SELECT_INPUT kIOMUXC_CSI_VSYNC_SELECT_INPUT kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT kIOMUXC_ENET_MDIO_SELECT_INPUT kIOMUXC_ENET0_RXDATA_SELECT_INPUT kIOMUXC_ENET1_RXDATA_SELECT_INPUT kIOMUXC_ENET_RXEN_SELECT_INPUT kIOMUXC_ENET_RXERR_SELECT_INPUT kIOMUXC_ENET0_TIMER_SELECT_INPUT kIOMUXC_ENET_TXCLK_SELECT_INPUT kIOMUXC_FLEXCAN1_RX_SELECT_INPUT kIOMUXC_FLEXCAN2_RX_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT !kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT "kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT #kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT $kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT %kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT &kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT 'kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT (kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT )kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT *kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT +kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT ,kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT -kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT .kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT /kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT 0kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT 1kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT 2kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT 3kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT 4kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT 5kIOMUXC_LPI2C1_SCL_SELECT_INPUT 6kIOMUXC_LPI2C1_SDA_SELECT_INPUT 7kIOMUXC_LPI2C2_SCL_SELECT_INPUT 8kIOMUXC_LPI2C2_SDA_SELECT_INPUT 9kIOMUXC_LPI2C3_SCL_SELECT_INPUT :kIOMUXC_LPI2C3_SDA_SELECT_INPUT ;kIOMUXC_LPI2C4_SCL_SELECT_INPUT <kIOMUXC_LPI2C4_SDA_SELECT_INPUT =kIOMUXC_LPSPI1_PCS0_SELECT_INPUT >kIOMUXC_LPSPI1_SCK_SELECT_INPUT ?kIOMUXC_LPSPI1_SDI_SELECT_INPUT @kIOMUXC_LPSPI1_SDO_SELECT_INPUT AkIOMUXC_LPSPI2_PCS0_SELECT_INPUT BkIOMUXC_LPSPI2_SCK_SELECT_INPUT CkIOMUXC_LPSPI2_SDI_SELECT_INPUT DkIOMUXC_LPSPI2_SDO_SELECT_INPUT EkIOMUXC_LPSPI3_PCS0_SELECT_INPUT FkIOMUXC_LPSPI3_SCK_SELECT_INPUT GkIOMUXC_LPSPI3_SDI_SELECT_INPUT HkIOMUXC_LPSPI3_SDO_SELECT_INPUT IkIOMUXC_LPSPI4_PCS0_SELECT_INPUT JkIOMUXC_LPSPI4_SCK_SELECT_INPUT KkIOMUXC_LPSPI4_SDI_SELECT_INPUT LkIOMUXC_LPSPI4_SDO_SELECT_INPUT MkIOMUXC_LPUART2_RX_SELECT_INPUT NkIOMUXC_LPUART2_TX_SELECT_INPUT OkIOMUXC_LPUART3_CTS_B_SELECT_INPUT PkIOMUXC_LPUART3_RX_SELECT_INPUT QkIOMUXC_LPUART3_TX_SELECT_INPUT RkIOMUXC_LPUART4_RX_SELECT_INPUT SkIOMUXC_LPUART4_TX_SELECT_INPUT TkIOMUXC_LPUART5_RX_SELECT_INPUT UkIOMUXC_LPUART5_TX_SELECT_INPUT VkIOMUXC_LPUART6_RX_SELECT_INPUT WkIOMUXC_LPUART6_TX_SELECT_INPUT XkIOMUXC_LPUART7_RX_SELECT_INPUT YkIOMUXC_LPUART7_TX_SELECT_INPUT ZkIOMUXC_LPUART8_RX_SELECT_INPUT [kIOMUXC_LPUART8_TX_SELECT_INPUT \kIOMUXC_NMI_SELECT_INPUT ]kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT ^kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT _kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT `kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT akIOMUXC_QTIMER3_TIMER0_SELECT_INPUT bkIOMUXC_QTIMER3_TIMER1_SELECT_INPUT ckIOMUXC_QTIMER3_TIMER2_SELECT_INPUT dkIOMUXC_QTIMER3_TIMER3_SELECT_INPUT ekIOMUXC_SAI1_MCLK2_SELECT_INPUT fkIOMUXC_SAI1_RX_BCLK_SELECT_INPUT gkIOMUXC_SAI1_RX_DATA0_SELECT_INPUT hkIOMUXC_SAI1_RX_DATA1_SELECT_INPUT ikIOMUXC_SAI1_RX_DATA2_SELECT_INPUT jkIOMUXC_SAI1_RX_DATA3_SELECT_INPUT kkIOMUXC_SAI1_RX_SYNC_SELECT_INPUT lkIOMUXC_SAI1_TX_BCLK_SELECT_INPUT mkIOMUXC_SAI1_TX_SYNC_SELECT_INPUT nkIOMUXC_SAI2_MCLK2_SELECT_INPUT okIOMUXC_SAI2_RX_BCLK_SELECT_INPUT pkIOMUXC_SAI2_RX_DATA0_SELECT_INPUT qkIOMUXC_SAI2_RX_SYNC_SELECT_INPUT rkIOMUXC_SAI2_TX_BCLK_SELECT_INPUT skIOMUXC_SAI2_TX_SYNC_SELECT_INPUT tkIOMUXC_SPDIF_IN_SELECT_INPUT ukIOMUXC_USB_OTG2_OC_SELECT_INPUT vkIOMUXC_USB_OTG1_OC_SELECT_INPUT wkIOMUXC_USDHC1_CD_B_SELECT_INPUT xkIOMUXC_USDHC1_WP_SELECT_INPUT ykIOMUXC_USDHC2_CLK_SELECT_INPUT zkIOMUXC_USDHC2_CD_B_SELECT_INPUT {kIOMUXC_USDHC2_CMD_SELECT_INPUT |kIOMUXC_USDHC2_DATA0_SELECT_INPUT }kIOMUXC_USDHC2_DATA1_SELECT_INPUT ~kIOMUXC_USDHC2_DATA2_SELECT_INPUT kIOMUXC_USDHC2_DATA3_SELECT_INPUT kIOMUXC_USDHC2_DATA4_SELECT_INPUT kIOMUXC_USDHC2_DATA5_SELECT_INPUT kIOMUXC_USDHC2_DATA6_SELECT_INPUT kIOMUXC_USDHC2_DATA7_SELECT_INPUT kIOMUXC_USDHC2_WP_SELECT_INPUT kIOMUXC_XBAR1_IN02_SELECT_INPUT kIOMUXC_XBAR1_IN03_SELECT_INPUT kIOMUXC_XBAR1_IN04_SELECT_INPUT kIOMUXC_XBAR1_IN05_SELECT_INPUT kIOMUXC_XBAR1_IN06_SELECT_INPUT kIOMUXC_XBAR1_IN07_SELECT_INPUT kIOMUXC_XBAR1_IN08_SELECT_INPUT kIOMUXC_XBAR1_IN09_SELECT_INPUT kIOMUXC_XBAR1_IN17_SELECT_INPUT kIOMUXC_XBAR1_IN18_SELECT_INPUT kIOMUXC_XBAR1_IN20_SELECT_INPUT kIOMUXC_XBAR1_IN22_SELECT_INPUT kIOMUXC_XBAR1_IN23_SELECT_INPUT kIOMUXC_XBAR1_IN24_SELECT_INPUT kIOMUXC_XBAR1_IN14_SELECT_INPUT kIOMUXC_XBAR1_IN15_SELECT_INPUT kIOMUXC_XBAR1_IN16_SELECT_INPUT kIOMUXC_XBAR1_IN25_SELECT_INPUT kIOMUXC_XBAR1_IN19_SELECT_INPUT kIOMUXC_XBAR1_IN21_SELECT_INPUT Piomuxc_select_input_tA_xbar_input_signalkXBARA1_InputLogicLowkXBARA1_InputLogicHighkXBARA1_InputIomuxXbarIn02kXBARA1_InputIomuxXbarIn03kXBARA1_InputIomuxXbarInout04kXBARA1_InputIomuxXbarInout05kXBARA1_InputIomuxXbarInout06kXBARA1_InputIomuxXbarInout07kXBARA1_InputIomuxXbarInout08kXBARA1_InputIomuxXbarInout09 kXBARA1_InputIomuxXbarInout10 kXBARA1_InputIomuxXbarInout11 kXBARA1_InputIomuxXbarInout12 kXBARA1_InputIomuxXbarInout13 kXBARA1_InputIomuxXbarInout14kXBARA1_InputIomuxXbarInout15kXBARA1_InputIomuxXbarInout16kXBARA1_InputIomuxXbarInout17kXBARA1_InputIomuxXbarInout18kXBARA1_InputIomuxXbarInout19kXBARA1_InputIomuxXbarIn20kXBARA1_InputIomuxXbarIn21kXBARA1_InputIomuxXbarIn22kXBARA1_InputIomuxXbarIn23kXBARA1_InputIomuxXbarIn24kXBARA1_InputIomuxXbarIn25kXBARA1_InputAcmp1OutkXBARA1_InputAcmp2OutkXBARA1_InputAcmp3OutkXBARA1_InputAcmp4OutkXBARA1_InputRESERVED30kXBARA1_InputRESERVED31kXBARA1_InputQtimer3Tmr0Output kXBARA1_InputQtimer3Tmr1Output!kXBARA1_InputQtimer3Tmr2Output"kXBARA1_InputQtimer3Tmr3Output#kXBARA1_InputQtimer4Tmr0Output$kXBARA1_InputQtimer4Tmr1Output%kXBARA1_InputQtimer4Tmr2Output&kXBARA1_InputQtimer4Tmr3Output'kXBARA1_InputFlexpwm1Pwm1OutTrig01(kXBARA1_InputFlexpwm1Pwm2OutTrig01)kXBARA1_InputFlexpwm1Pwm3OutTrig01*kXBARA1_InputFlexpwm1Pwm4OutTrig01+kXBARA1_InputFlexpwm2Pwm1OutTrig01,kXBARA1_InputFlexpwm2Pwm2OutTrig01-kXBARA1_InputFlexpwm2Pwm3OutTrig01.kXBARA1_InputFlexpwm2Pwm4OutTrig01/kXBARA1_InputFlexpwm3Pwm1OutTrig010kXBARA1_InputFlexpwm3Pwm2OutTrig011kXBARA1_InputFlexpwm3Pwm3OutTrig012kXBARA1_InputFlexpwm3Pwm4OutTrig013kXBARA1_InputFlexpwm4Pwm1OutTrig014kXBARA1_InputFlexpwm4Pwm2OutTrig015kXBARA1_InputFlexpwm4Pwm3OutTrig016kXBARA1_InputFlexpwm4Pwm4OutTrig017kXBARA1_InputPitTrigger08kXBARA1_InputPitTrigger19kXBARA1_InputPitTrigger2:kXBARA1_InputPitTrigger3;kXBARA1_InputEnc1PosMatch<kXBARA1_InputEnc2PosMatch=kXBARA1_InputEnc3PosMatch>kXBARA1_InputEnc4PosMatch?kXBARA1_InputDmaDone0@kXBARA1_InputDmaDone1AkXBARA1_InputDmaDone2BkXBARA1_InputDmaDone3CkXBARA1_InputDmaDone4DkXBARA1_InputDmaDone5EkXBARA1_InputDmaDone6FkXBARA1_InputDmaDone7GkXBARA1_InputAoi1Out0HkXBARA1_InputAoi1Out1IkXBARA1_InputAoi1Out2JkXBARA1_InputAoi1Out3KkXBARA1_InputAoi2Out0LkXBARA1_InputAoi2Out1MkXBARA1_InputAoi2Out2NkXBARA1_InputAoi2Out3OkXBARA1_InputAdcEtcXbar0Coco0PkXBARA1_InputAdcEtcXbar0Coco1QkXBARA1_InputAdcEtcXbar0Coco2RkXBARA1_InputAdcEtcXbar0Coco3SkXBARA1_InputAdcEtcXbar1Coco0TkXBARA1_InputAdcEtcXbar1Coco1UkXBARA1_InputAdcEtcXbar1Coco2VkXBARA1_InputAdcEtcXbar1Coco3WkXBARB2_InputLogicLowkXBARB2_InputLogicHighkXBARB2_InputRESERVED2kXBARB2_InputRESERVED3kXBARB2_InputRESERVED4kXBARB2_InputRESERVED5kXBARB2_InputAcmp1OutkXBARB2_InputAcmp2OutkXBARB2_InputAcmp3OutkXBARB2_InputAcmp4Out kXBARB2_InputRESERVED10 kXBARB2_InputRESERVED11 kXBARB2_InputQtimer3Tmr0Output kXBARB2_InputQtimer3Tmr1Output kXBARB2_InputQtimer3Tmr2OutputkXBARB2_InputQtimer3Tmr3OutputkXBARB2_InputQtimer4Tmr0OutputkXBARB2_InputQtimer4Tmr1OutputkXBARB2_InputQtimer4Tmr2OutputkXBARB2_InputQtimer4Tmr3OutputkXBARB2_InputFlexpwm1Pwm1OutTrig01kXBARB2_InputFlexpwm1Pwm2OutTrig01kXBARB2_InputFlexpwm1Pwm3OutTrig01kXBARB2_InputFlexpwm1Pwm4OutTrig01kXBARB2_InputFlexpwm2Pwm1OutTrig01kXBARB2_InputFlexpwm2Pwm2OutTrig01kXBARB2_InputFlexpwm2Pwm3OutTrig01kXBARB2_InputFlexpwm2Pwm4OutTrig01kXBARB2_InputFlexpwm3Pwm1OutTrig01kXBARB2_InputFlexpwm3Pwm2OutTrig01kXBARB2_InputFlexpwm3Pwm3OutTrig01kXBARB2_InputFlexpwm3Pwm4OutTrig01kXBARB2_InputFlexpwm4Pwm1OutTrig01 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kXBARB3_InputFlexpwm4Pwm2OutTrig01!kXBARB3_InputFlexpwm4Pwm3OutTrig01"kXBARB3_InputFlexpwm4Pwm4OutTrig01#kXBARB3_InputPitTrigger0$kXBARB3_InputPitTrigger1%kXBARB3_InputAdcEtcXbar0Coco0&kXBARB3_InputAdcEtcXbar0Coco1'kXBARB3_InputAdcEtcXbar0Coco2(kXBARB3_InputAdcEtcXbar0Coco3)kXBARB3_InputAdcEtcXbar1Coco0*kXBARB3_InputAdcEtcXbar1Coco1+kXBARB3_InputAdcEtcXbar1Coco2,kXBARB3_InputAdcEtcXbar1Coco3-kXBARB3_InputEnc1PosMatch.kXBARB3_InputEnc2PosMatch/kXBARB3_InputEnc3PosMatch0kXBARB3_InputEnc4PosMatch1kXBARB3_InputDmaDone02kXBARB3_InputDmaDone13kXBARB3_InputDmaDone24kXBARB3_InputDmaDone35kXBARB3_InputDmaDone46kXBARB3_InputDmaDone57kXBARB3_InputDmaDone68kXBARB3_InputDmaDone79Pxbar_input_signal_tX_xbar_output_signalkXBARA1_OutputDmaChMuxReq30kXBARA1_OutputDmaChMuxReq31kXBARA1_OutputDmaChMuxReq94kXBARA1_OutputDmaChMuxReq95kXBARA1_OutputIomuxXbarInout04kXBARA1_OutputIomuxXbarInout05kXBARA1_OutputIomuxXbarInout06kXBARA1_OutputIomuxXbarInout07kXBARA1_OutputIomuxXbarInout08kXBARA1_OutputIomuxXbarInout09 kXBARA1_OutputIomuxXbarInout10 kXBARA1_OutputIomuxXbarInout11 kXBARA1_OutputIomuxXbarInout12 kXBARA1_OutputIomuxXbarInout13 kXBARA1_OutputIomuxXbarInout14kXBARA1_OutputIomuxXbarInout15kXBARA1_OutputIomuxXbarInout16kXBARA1_OutputIomuxXbarInout17kXBARA1_OutputIomuxXbarInout18kXBARA1_OutputIomuxXbarInout19kXBARA1_OutputAcmp1SamplekXBARA1_OutputAcmp2SamplekXBARA1_OutputAcmp3SamplekXBARA1_OutputAcmp4SamplekXBARA1_OutputRESERVED24kXBARA1_OutputRESERVED25kXBARA1_OutputFlexpwm1Exta0kXBARA1_OutputFlexpwm1Exta1kXBARA1_OutputFlexpwm1Exta2kXBARA1_OutputFlexpwm1Exta3kXBARA1_OutputFlexpwm1ExtSync0kXBARA1_OutputFlexpwm1ExtSync1kXBARA1_OutputFlexpwm1ExtSync2 kXBARA1_OutputFlexpwm1ExtSync3!kXBARA1_OutputFlexpwm1ExtClk"kXBARA1_OutputFlexpwm1Fault0#kXBARA1_OutputFlexpwm1Fault1$kXBARA1_OutputFlexpwm1234Fault2%kXBARA1_OutputFlexpwm1234Fault3&kXBARA1_OutputFlexpwm1ExtForce'kXBARA1_OutputFlexpwm234Exta0(kXBARA1_OutputFlexpwm234Exta1)kXBARA1_OutputFlexpwm234Exta2*kXBARA1_OutputFlexpwm234Exta3+kXBARA1_OutputFlexpwm2ExtSync0,kXBARA1_OutputFlexpwm2ExtSync1-kXBARA1_OutputFlexpwm2ExtSync2.kXBARA1_OutputFlexpwm2ExtSync3/kXBARA1_OutputFlexpwm234ExtClk0kXBARA1_OutputFlexpwm2Fault01kXBARA1_OutputFlexpwm2Fault12kXBARA1_OutputFlexpwm2ExtForce3kXBARA1_OutputFlexpwm3ExtSync04kXBARA1_OutputFlexpwm3ExtSync15kXBARA1_OutputFlexpwm3ExtSync26kXBARA1_OutputFlexpwm3ExtSync37kXBARA1_OutputFlexpwm3Fault08kXBARA1_OutputFlexpwm3Fault19kXBARA1_OutputFlexpwm3ExtForce:kXBARA1_OutputFlexpwm4ExtSync0;kXBARA1_OutputFlexpwm4ExtSync1<kXBARA1_OutputFlexpwm4ExtSync2=kXBARA1_OutputFlexpwm4ExtSync3>kXBARA1_OutputFlexpwm4Fault0?kXBARA1_OutputFlexpwm4Fault1@kXBARA1_OutputFlexpwm4ExtForceAkXBARA1_OutputEnc1PhaseAInputBkXBARA1_OutputEnc1PhaseBInputCkXBARA1_OutputEnc1IndexDkXBARA1_OutputEnc1HomeEkXBARA1_OutputEnc1TriggerFkXBARA1_OutputEnc2PhaseAInputGkXBARA1_OutputEnc2PhaseBInputHkXBARA1_OutputEnc2IndexIkXBARA1_OutputEnc2HomeJkXBARA1_OutputEnc2TriggerKkXBARA1_OutputEnc3PhaseAInputLkXBARA1_OutputEnc3PhaseBInputMkXBARA1_OutputEnc3IndexNkXBARA1_OutputEnc3HomeOkXBARA1_OutputEnc3TriggerPkXBARA1_OutputEnc4PhaseAInputQkXBARA1_OutputEnc4PhaseBInputRkXBARA1_OutputEnc4IndexSkXBARA1_OutputEnc4HomeTkXBARA1_OutputEnc4TriggerUkXBARA1_OutputQtimer1Tmr0InputVkXBARA1_OutputQtimer1Tmr1InputWkXBARA1_OutputQtimer1Tmr2InputXkXBARA1_OutputQtimer1Tmr3InputYkXBARA1_OutputQtimer2Tmr0InputZkXBARA1_OutputQtimer2Tmr1Input[kXBARA1_OutputQtimer2Tmr2Input\kXBARA1_OutputQtimer2Tmr3Input]kXBARA1_OutputQtimer3Tmr0Input^kXBARA1_OutputQtimer3Tmr1Input_kXBARA1_OutputQtimer3Tmr2Input`kXBARA1_OutputQtimer3Tmr3InputakXBARA1_OutputQtimer4Tmr0InputbkXBARA1_OutputQtimer4Tmr1InputckXBARA1_OutputQtimer4Tmr2InputdkXBARA1_OutputQtimer4Tmr3InputekXBARA1_OutputEwmEwmInfkXBARA1_OutputAdcEtcXbar0Trig0gkXBARA1_OutputAdcEtcXbar0Trig1hkXBARA1_OutputAdcEtcXbar0Trig2ikXBARA1_OutputAdcEtcXbar0Trig3jkXBARA1_OutputAdcEtcXbar1Trig0kkXBARA1_OutputAdcEtcXbar1Trig1lkXBARA1_OutputAdcEtcXbar1Trig2mkXBARA1_OutputAdcEtcXbar1Trig3nkXBARA1_OutputLpi2c1TrgInputokXBARA1_OutputLpi2c2TrgInputpkXBARA1_OutputLpi2c3TrgInputqkXBARA1_OutputLpi2c4TrgInputrkXBARA1_OutputLpspi1TrgInputskXBARA1_OutputLpspi2TrgInputtkXBARA1_OutputLpspi3TrgInputukXBARA1_OutputLpspi4TrgInputvkXBARA1_OutputLpuart1TrgInputwkXBARA1_OutputLpuart2TrgInputxkXBARA1_OutputLpuart3TrgInputykXBARA1_OutputLpuart4TrgInputzkXBARA1_OutputLpuart5TrgInput{kXBARA1_OutputLpuart6TrgInput|kXBARA1_OutputLpuart7TrgInput}kXBARA1_OutputLpuart8TrgInput~kXBARA1_OutputFlexio1TriggerIn0kXBARA1_OutputFlexio1TriggerIn1kXBARA1_OutputFlexio2TriggerIn0kXBARA1_OutputFlexio2TriggerIn1kXBARB2_OutputAoi1In00kXBARB2_OutputAoi1In01kXBARB2_OutputAoi1In02kXBARB2_OutputAoi1In03kXBARB2_OutputAoi1In04kXBARB2_OutputAoi1In05kXBARB2_OutputAoi1In06kXBARB2_OutputAoi1In07kXBARB2_OutputAoi1In08kXBARB2_OutputAoi1In09 kXBARB2_OutputAoi1In10 kXBARB2_OutputAoi1In11 kXBARB2_OutputAoi1In12 kXBARB2_OutputAoi1In13 kXBARB2_OutputAoi1In14kXBARB2_OutputAoi1In15kXBARB3_OutputAoi2In00kXBARB3_OutputAoi2In01kXBARB3_OutputAoi2In02kXBARB3_OutputAoi2In03kXBARB3_OutputAoi2In04kXBARB3_OutputAoi2In05kXBARB3_OutputAoi2In06kXBARB3_OutputAoi2In07kXBARB3_OutputAoi2In08kXBARB3_OutputAoi2In09 kXBARB3_OutputAoi2In10 kXBARB3_OutputAoi2In11 kXBARB3_OutputAoi2In12 kXBARB3_OutputAoi2In13 kXBARB3_OutputAoi2In14kXBARB3_OutputAoi2In15Pxbar_output_signal_t r *Ž\ۍBHCц#HSN# NR#$CFGB#DGCB#HGSB#LCVB#POFSB#TCALB#XtYYtHPADC_Typĕ *̐(TRIGn_CTRLB#TRIGn_COUNTERB#TRIGn_CHAIN_1_0B#TRIGn_CHAIN_3_2B# TRIGn_CHAIN_5_4B#TRIGn_CHAIN_7_6B#TRIGn_RESULT_1_0N#TRIGn_RESULT_3_2N#TRIGn_RESULT_5_4N# TRIGn_RESULT_7_6N#$*CTRLB#DONE0_1_IRQB#DONE2_ERR_IRQB#DMA_CTRLB# cTRIG#PADC_ETC_TypeL *TMPRB#ޑ:;RESERVED_0҈#OPACRB#@OPACR1B#DOPACR2B#HOPACR3B#LOPACR4B#PPAIPSTZ_Typeˆ*BFCRT01n#BFCRT23n#tI*JBFCRTy#PAOI_Typet*HCTRLB#ADDR_OFFSET0B#ADDR_OFFSET1B#AES_KEY0_W0B# AES_KEY0_W1B#AES_KEY0_W2B#AES_KEY0_W3B#STATUSB#CTR_NONCE0_W0B# CTR_NONCE0_W1B#$CTR_NONCE0_W2B#(CTR_NONCE0_W3B#,CTR_NONCE1_W0B#0CTR_NONCE1_W1B#4CTR_NONCE1_W2B#8CTR_NONCE1_W3B#<REGION1_TOPB#@REGION1_BOTB#DPBEE_Type*ɖCSB#IDB#WORD0B#WORD1B# *MCRB#CTRL1B#TIMERB#:RESERVED_0t# RXMGMASKB#RX14MASKB#RX15MASKB#ECRB#ESR1B# IMASK2B#$IMASK1B#(IFLAG2B#,IFLAG1B#0CTRL2B#4ESR2N#8:RESERVED_1*#<CRCRN#DRXFGMASKB#HRXFIRN#L:/RESERVED_2q#P?MB#:RESERVED_3# ΙB?RXIMRČ#:_RESERVED_4܌#GFWRB#PCAN_TypeI*CCRB#:RESERVED_0+#CSRN#CCSRB# CACRRB#CBCDRB#CBCMRB#CSCMR1B#CSCMR2B# CSCDR1B#$CS1CDRB#(CS2CDRB#,CDCDRB#0:RESERVED_1ڍ#4CSCDR2B#8CSCDR3B#<:RESERVED_2#@CDHIPRN#H̜:RESERVED_3@#LCLPCRB#TCISRB#XCIMRB#\CCOSRB#`CGPRB#dCCGR0B#hCCGR1B#lCCGR2B#pCCGR3B#tCCGR4B#xCCGR5B#|CCGR6B#:RESERVED_4#CMEORB#PCCM_Type*ɨPLL_ARMB#PLL_ARM_SETB#PLL_ARM_CLRB#PLL_ARM_TOGB# PLL_USB1B#PLL_USB1_SETB#PLL_USB1_CLRB#PLL_USB1_TOGB#PLL_USB2B# PLL_USB2_SETB#$PLL_USB2_CLRB#(PLL_USB2_TOGB#,PLL_SYSB#0PLL_SYS_SETB#4PLL_SYS_CLRB#8PLL_SYS_TOGB#<PLL_SYS_SSB#@: RESERVED_0w#DPLL_SYS_NUMB#P: RESERVED_1#TPLL_SYS_DENOMB#`: RESERVED_2ې#dPLL_AUDIOB#pPLL_AUDIO_SETB#tPLL_AUDIO_CLRB#xPLL_AUDIO_TOGB#|PLL_AUDIO_NUMB#: RESERVED_3_#PLL_AUDIO_DENOMB#: RESERVED_4#PLL_VIDEOB#PLL_VIDEO_SETB#PLL_VIDEO_CLRB#PLL_VIDEO_TOGB#PLL_VIDEO_NUMB#: RESERVED_5#PLL_VIDEO_DENOMB#:RESERVED_6V#PLL_ENETB#PLL_ENET_SETB#PLL_ENET_CLRB#PLL_ENET_TOGB#PFD_480B#PFD_480_SETB#PFD_480_CLRB#PFD_480_TOGB#PFD_528B#PFD_528_SETB#PFD_528_CLRB#PFD_528_TOGB#:?RESERVED_7]#MISC0B#MISC0_SETB#MISC0_CLRB#MISC0_TOGB#MISC1B#MISC1_SETB#MISC1_CLRB#MISC1_TOGB#MISC2B#MISC2_SETB#MISC2_CLRB#MISC2_TOGB#PCCM_ANALOG_Type7*CR0#CR1#FPR#SCR#DACCR#MUXCR#t:PCMP_Typea**PCSICR1B#CSICR2B#CSICR3B#CSISTATFIFON# CSIRFIFON#CSIRXCNTB#CSISRB#:RESERVED_03#CSIDMASA_STATFIFOB# CSIDMATS_STATFIFOB#$CSIDMASA_FB1B#(CSIDMASA_FB2B#,CSIFBUF_PARAB#0CSIIMAG_PARAB#4߫:RESERVED_1ӕ#8CSICR18B#HCSICR19B#LPCSI_TypeĔ+*ƭBCSL'#ɬ:RESERVED_0<#HP0B#:RESERVED_1h#SAB#:RESERVED_2#HPCONTROL0B#PCSU_Type!.*REG0B#REG1B#REG2B#REG3B# PDCDC_Typeז0*CTRLB#: RESERVED_01#STATB#: RESERVED_1[#CHANNELCTRLB# : RESERVED_2#$CAPABILITY0B#0ɯ: RESERVED_3#4CAPABILITY1N#@: RESERVED_4#DCONTEXTB#P: RESERVED_5#TKEYB#`а: RESERVED_6D#dKEYDATAB#p: RESERVED_7q#tPACKET0N#: RESERVED_8#PACKET1N#ڱ: RESERVED_9Θ#PACKET2N#: RESERVED_10#PACKET3N#: RESERVED_11-#PACKET4N#: RESERVED_12]#PACKET5N#: RESERVED_13#PACKET6N#ɳ:RESERVED_14#CH0CMDPTRB#: RESERVED_15#CH0SEMAB#: RESERVED_16#CH0STATB#۴: RESERVED_17O#CH0OPTSB#: RESERVED_18#CH1CMDPTRB#: RESERVED_19#CH1SEMAB#: RESERVED_20#CH1STATB#: RESERVED_21#CH1OPTSB#Ͷ: RESERVED_22A#CH2CMDPTRB#: RESERVED_23s#CH2SEMAB#: RESERVED_24#CH2STATB#߷: RESERVED_25ӛ#CH2OPTSB#: RESERVED_26#CH3CMDPTRB#: RESERVED_275#CH3SEMAB#: RESERVED_28e#CH3STATB#: RESERVED_29#CH3OPTSB#ҹ:RESERVED_30Ŝ#DBGSELECTB#: RESERVED_31#DBGDATAN#: RESERVED_32(#PAGETABLEB#: RESERVED_33Z#VERSIONN#PDCP_Type2SٻNBYTES_MLNOBNBYTES_MLOFFNOBNBYTES_MLOFFYESBSCITER_ELINKNOnCITER_ELINKYESnSBITER_ELINKNOnBITER_ELINKYESn* SADDRB#SOFFn#ATTRn##SLASTB# DADDRB#DOFFn#ٝ#DLAST_SGAB#CSRn##*(CRB#ESN#ڽ:RESERVED_0Ξ#ERQB# :RESERVED_1#EEIB#CEEI#SEEI#CERQ#SERQ#CDNE#SSRT#CERR#CINT#:RESERVED_2# INTB#$:RESERVED_3#(ERRB#,޿:RESERVED_4ҟ#0HRSN#4: RESERVED_5#8EARSB#D:RESERVED_6%#HDCHPRI3#DCHPRI2#DCHPRI1#DCHPRI0#DCHPRI7#DCHPRI6#DCHPRI5#DCHPRI4#DCHPRI11#DCHPRI10#DCHPRI9#DCHPRI8#DCHPRI15#DCHPRI14#DCHPRI13#DCHPRI12#DCHPRI19#DCHPRI18#DCHPRI17#DCHPRI16#DCHPRI23#DCHPRI22#DCHPRI21#DCHPRI20#DCHPRI27#DCHPRI26#DCHPRI25#DCHPRI24#DCHPRI31#DCHPRI30#DCHPRI29#DCHPRI28#:RESERVED_7Z#/TCDz# PDMA_Type7*BCHCFG#PDMAMUX_TypeB*(CTRLn#FILTn#WTRn#POSDn#POSDHԣ#REVn# REVHԣ# UPOSn#LPOSn#UPOSHԣ#LPOSHԣ#UINITn#LINITn#IMRԣ#TSTn#CTRL2n#UMODn# LMODn#"UCOMPn#$LCOMPn#&ItΣPENC_TypeԢB*TCSRB#TCCRB#* :RESERVED_0 #EIRB#EIMRB#:RESERVED_1B# RDARB#TDARB#: RESERVED_2x#ECRB#$:RESERVED_3#(MMFRB#@MSCRB#D:RESERVED_4פ#HMIBCB#d:RESERVED_5#hRCRB#:;RESERVED_6+#TCRB#:RESERVED_7V#PALRB#PAURB#OPDB#TXICB#: RESERVED_8#RXICB#:RESERVED_9ԥ#IAURB#IALRB#GAURB#GALRB#:RESERVED_10'#TFWRB#:7RESERVED_11T#RDSRB#TDSRB#MRBRB#:RESERVED_12#RSFLB#RSEMB#RAEMB#RAFLB#TSEMB#TAEMB#TAFLB#TIPGB#FTRLB#: RESERVED_130#TACCB#RACCB#:7RESERVED_14j#RMON_T_DROPY#RMON_T_PACKETSN#RMON_T_BC_PKTN#RMON_T_MC_PKTN#RMON_T_CRC_ALIGNN#RMON_T_UNDERSIZEN#RMON_T_OVERSIZEN#RMON_T_FRAGN#RMON_T_JABN#RMON_T_COLN#RMON_T_P64N#RMON_T_P65TO127N#RMON_T_P128TO255N#RMON_T_P256TO511N#RMON_T_P512TO1023N#RMON_T_P1024TO2047N#RMON_T_P_GTE2048N#RMON_T_OCTETSN#IEEE_T_DROPY#IEEE_T_FRAME_OKN#IEEE_T_1COLN#IEEE_T_MCOLN#IEEE_T_DEFN#IEEE_T_LCOLN#IEEE_T_EXCOLN#IEEE_T_MACERRN#IEEE_T_CSERRN#IEEE_T_SQEN#IEEE_T_FDXFCN#IEEE_T_OCTETS_OKN#: RESERVED_15&#RMON_R_PACKETSN#RMON_R_BC_PKTN#RMON_R_MC_PKTN#RMON_R_CRC_ALIGNN#RMON_R_UNDERSIZEN#RMON_R_OVERSIZEN#RMON_R_FRAGN#RMON_R_JABN#RMON_R_RESVD_0Y#RMON_R_P64N#RMON_R_P65TO127N#RMON_R_P128TO255N#RMON_R_P256TO511N#RMON_R_P512TO1023N#RMON_R_P1024TO2047N#RMON_R_P_GTE2048N#RMON_R_OCTETSN#IEEE_R_DROPN#IEEE_R_FRAME_OKN#IEEE_R_CRCN#IEEE_R_ALIGNN#IEEE_R_MACERRN#IEEE_R_FDXFCN#IEEE_R_OCTETS_OKN#:RESERVED_16l#ATCRB#ATVRB#ATOFFB#ATPERB#ATCORB#ATINCB#ATSTMPN#:RESERVED_17#TGSRB# CHANNEL# PENET_TypeF*CTRL#SERV#CMPL#CMPH#CLKCTRL#CLKPRESCALER#PEWM_TypeIL*VERIDN#PARAMN#CTRLB#PINN# SHIFTSTATB#SHIFTERRB#TIMSTATB#:RESERVED_0#SHIFTSIENB# SHIFTEIENB#$TIMIENB#(:RESERVED_1h#,SHIFTSDENB#0: RESERVED_2#4SHIFTSTATEB#@:;RESERVED_3Ǯ#DBSHIFTCTL#:oRESERVED_4#BSHIFTCFG#:RESERVED_5:#BSHIFTBUFZ#:oRESERVED_6u#BSHIFTBUFBIS#:oRESERVED_7#BSHIFTBUFBYSѯ#:oRESERVED_8#BSHIFTBUFBBS#:oRESERVED_9,#BTIMCTLK#:oRESERVED_10d#BTIMCFG# :oRESERVED_11# BTIMCMP# :RESERVED_12ְ# BSHIFTBUFNBS# :oRESERVED_13# BSHIFTBUFHWS5#:oRESERVED_14S#BSHIFTBUFNISs#PFLEXIO_TypeM*TCM_CTRLB#OCRAM_MAGIC_ADDRB#DTCM_MAGIC_ADDRB#ITCM_MAGIC_ADDRB# INT_STATUSB#INT_STAT_ENB#INT_SIG_ENB#PFLEXRAM_TypeO*MCR0B#MCR1B#MCR2B#AHBCRB# INTENB#INTRB#LUTKEYB#LUTCRB#BAHBRXBUFCR0# :/RESERVED_0ֲ#0BFLSHCR0#`BFLSHCR1 #pBFLSHCR2&#:RESERVED_1@#FLSHCR4B#:RESERVED_2o#IPCR0B#IPCR1B#:RESERVED_3#IPCMDB#:RESERVED_4׳#IPRXFCRB#IPTXFCRB#BDLLCR#:RESERVED_5.#STS0N#STS1N#STS2N#AHBSPNDSTSN#IPRXFSTSN#IPTXFSTSN#:RESERVED_6#NRFDRȴ#BTFDRߴ#B?LUT#PFLEXSPI_TypeNQ*<CNTRB#:RESERVED_03#BIMRQ#NISRf#: RESERVED_1{#(IMR5B#4ISR5N#8PGPC_Type"U* DRB#GDIRB#PSRN#ICR1B# ICR2B#IMRB#ISRB#EDGE_SELB#PGPIO_TypeõU*(CRB#PRB#SRB#IRB# BOCRg#NICR|#CNTN#$PGPT_Type:W*VERIDN#PARAMN#TCSRB#TCR1B# TCR2B#TCR3B#TCR4B#TCR5B#BTDR# :RESERVED_0+#0NTFRI#@:RESERVED_1^#PTMRB#`:#RESERVED_2#dRCSRB#RCR1B#RCR2B#RCR3B#RCR4B#RCR5B#NRDR#:RESERVED_3 #NRFR(#:RESERVED_4>#RMRB#PI2S_TypeY* :RESERVED_0#B{SW_MUX_CTL_PAD#B{SW_PAD_CTL_PAD#BSELECT_INPUT#PIOMUXC_Type{\*hGPR0Y#GPR1B#GPR2B#GPR3B# GPR4B#GPR5B#GPR6B#GPR7B#GPR8B# GPR9Y#$GPR10B#(GPR11B#,GPR12B#0GPR13B#4GPR14B#8GPR15Y#<GPR16B#@GPR17B#DGPR18B#HGPR19B#LGPR20B#PGPR21B#TGPR22B#XGPR23B#\GPR24B#`GPR25B#dPIOMUXC_GPR_Type]*$SW_MUX_CTL_PAD_WAKEUPB#SW_MUX_CTL_PAD_PMIC_ON_REQB#SW_MUX_CTL_PAD_PMIC_STBY_REQB#SW_PAD_CTL_PAD_TEST_MODEB# SW_PAD_CTL_PAD_POR_BB#SW_PAD_CTL_PAD_ONOFFB#SW_PAD_CTL_PAD_WAKEUPB#SW_PAD_CTL_PAD_PMIC_ON_REQB#SW_PAD_CTL_PAD_PMIC_STBY_REQB# PIOMUXC_SNVS_Typec*GPR0Y#GPR1Y#GPR2Y#GPR3B# PIOMUXC_SNVS_GPR_Typed*KPCRn#KPSRn#KDDRn#KPDRn#PKPP_Typee*@PIGEON_0B#: RESERVED_0s#PIGEON_1B#: RESERVED_1#PIGEON_2B# :RESERVED_2ϼ#$*CTRLB#CTRL_SETB#CTRL_CLRB#CTRL_TOGB# CTRL1B#CTRL1_SETB#CTRL1_CLRB#CTRL1_TOGB#CTRL2B# CTRL2_SETB#$CTRL2_CLRB#(CTRL2_TOGB#,TRANSFER_COUNTB#0: RESERVED_0ƽ#4CUR_BUFB#@: RESERVED_1#DNEXT_BUFB#P:RESERVED_2!#TVDCTRL0B#pVDCTRL0_SETB#tVDCTRL0_CLRB#xVDCTRL0_TOGB#|VDCTRL1B#: RESERVED_3#VDCTRL2B#: RESERVED_4ƾ#VDCTRL3B#: RESERVED_5#VDCTRL4B#:RESERVED_6$#BM_ERROR_STATB#: RESERVED_7Z#CRC_STATB#: RESERVED_8#STATN#:KRESERVED_9#THRESB#:RESERVED_10#PIGEONCTRL0B#PIGEONCTRL0_SETB#PIGEONCTRL0_CLRB#PIGEONCTRL0_TOGB#PIGEONCTRL1B#PIGEONCTRL1_SETB#PIGEONCTRL1_CLRB#PIGEONCTRL1_TOGB#PIGEONCTRL2B#PIGEONCTRL2_SETB#PIGEONCTRL2_CLRB#PIGEONCTRL2_TOGB#:RESERVED_11#Â^ PIGEON9#LUT_CTRLB#: RESERVED_12c#LUT0_ADDRB#: RESERVED_13#LUT0_DATAB#Ӄ: RESERVED_14#LUT1_ADDRB#: RESERVED_15#LUT1_DATAB#PLCDIF_Typef*VERIDN#PARAMN#:RESERVED_0_#MCRB#MSRB#MIERB#MDERB#MCFGR0B# MCFGR1B#$MCFGR2B#(MCFGR3B#,:RESERVED_1#0MDMRB#@:RESERVED_2 #DMCCR0B#HĆ:RESERVED_38#LMCCR1B#P:RESERVED_4c#TMFCRB#XMFSRN#\MTDRB#`: RESERVED_5#dMRDRN#p܇:RESERVED_6#tSCRB#SSRB#SIERB#SDERB#:RESERVED_7 #SCFGR1B#SCFGR2B#:RESERVED_8]#SAMRB#: RESERVED_9#SASRN#STARB#Ή:RESERVED_10#STDRB#: RESERVED_11#SRDRN#PLPI2C_Type?o*xVERIDN#PARAMN#ۊ:RESERVED_0O#CRB#SRB#IERB#DERB#CFGR0B# CFGR1B#$:RESERVED_1#(DMR0B#0DMR1B#4:RESERVED_2#8CCRB#@:RESERVED_3#DFCRB#XFSRN#\TCRB#`TDRB#d:RESERVED_4Z#hRSRN#pRDRN#tPLPSPI_Type0s*0VERIDN#PARAMN#GLOBALB#PINCFGB# BAUDB#STATB#CTRLB#DATAB#MATCHB# MODIRB#$FIFOB#(WATERB#,PLPUART_Typeu* CTRLB#CTRL_SETB#CTRL_CLRB#CTRL_TOGB# TIMINGB#: RESERVED_0#DATAB# ۏ: RESERVED_1#$READ_CTRLB#0: RESERVED_2#4READ_FUSE_DATAB#@: RESERVED_32#DSW_STICKYB#P: RESERVED_4a#TSCSB#`SCS_SETB#dSCS_CLRB#hSCS_TOGB#lÑ:RESERVED_5#pVERSIONN#:kRESERVED_6#TIMING2B#:RESERVED_7#LOCKB#͒: RESERVED_8A#CFG0B#: RESERVED_9m#CFG1B#: RESERVED_10#CFG2B#ғ: RESERVED_11#CFG3B#: RESERVED_12#CFG4B#: RESERVED_13 #CFG5B#ٔ: RESERVED_14M#CFG6B#: RESERVED_15z#MEM0B# : RESERVED_16# MEM1B# : RESERVED_17# MEM2B# : RESERVED_18# MEM3B# : RESERVED_19.# MEM4B# : RESERVED_20[# ANA0B# : RESERVED_21# ANA1B# : RESERVED_22# ANA2B# :RESERVED_23# SRK0B# : RESERVED_24# SRK1B# ɘ: RESERVED_25=# SRK2B# : RESERVED_26j# SRK3B# : RESERVED_27# SRK4B# Й: RESERVED_28# SRK5B# : RESERVED_29# SRK6B# : RESERVED_30# SRK7B# ך: RESERVED_31K# SJC_RESP0B# : RESERVED_32}# SJC_RESP1B# : RESERVED_33# MAC0B# : RESERVED_34# MAC1B# : RESERVED_35 # GP3B# :RESERVED_365# GP1B# : RESERVED_37a# GP2B# : RESERVED_38# SW_GP1B# ȝ: RESERVED_39# SW_GP20B# : RESERVED_40# SW_GP21B# : RESERVED_41# SW_GP22B# ؞: RESERVED_42L# SW_GP23B# : RESERVED_43|# MISC_CONF0B# : RESERVED_44# MISC_CONF1B# : RESERVED_45# SRK_REVOKEB# POCOTP_TypeUy*:RESERVED_0/#MEGA_CTRLB#MEGA_PUPSCRB#MEGA_PDNSCRB#MEGA_SRB#:oRESERVED_1#CPU_CTRLB#CPU_PUPSCRB#CPU_PDNSCRB#CPU_SRB#PPGC_Type)}*ǢLDVALB#CVALN#TCTRLB#TFLGB# *ѣMCRB#:RESERVED_0X#LTMR64HN#LTMR64LN#:RESERVED_1#CHANNEL#PPIT_TypeG~*:RESERVED_0#REG_1P1B#REG_1P1_SETB#REG_1P1_CLRB#REG_1P1_TOGB#REG_3P0B#REG_3P0_SETB#REG_3P0_CLRB#REG_3P0_TOGB#REG_2P5B#REG_2P5_SETB#REG_2P5_CLRB#REG_2P5_TOGB#REG_COREB#REG_CORE_SETB#REG_CORE_CLRB#REG_CORE_TOGB#MISC0B#MISC0_SETB#MISC0_CLRB#MISC0_TOGB#MISC1B#MISC1_SETB#MISC1_CLRB#MISC1_TOGB#MISC2B#MISC2_SETB#MISC2_CLRB#MISC2_TOGB#PPMU_Type*`CNTԣ#INITn#CTRL2n#CTRLn#ڨ:RESERVED_0N#VAL0n# FRACVAL1n# VAL1n#FRACVAL2n#VAL2n#FRACVAL3n#VAL3n#FRACVAL4n#VAL4n#FRACVAL5n#VAL5n#FRCTRLn# OCTRLn#"STSn#$INTENn#&DMAENn#(TCTRLn#*۪nDISMAPQ#,DTCNT0n#0DTCNT1n#2CAPTCTRLAn#4CAPTCOMPAn#6CAPTCTRLBn#8CAPTCOMPBn#:CAPTCTRLXn#<CAPTCOMPXn#>CVAL0ԣ#@CVAL0CYCԣ#BCVAL1ԣ#DCVAL1CYCԣ#FCVAL2ԣ#HCVAL2CYCԣ#JCVAL3ԣ#LCVAL3CYCԣ#NCVAL4ԣ#PCVAL4CYCԣ#RCVAL5ԣ#TCVAL5CYCԣ#V:RESERVED_1#X*ȭSM#OUTENn#MASKn#SWCOUTn#DTSRCSELn#MCTRLn#MCTRL2n#FCTRLn#FSTSn#FFILTn#FTSTn#FCTRL2n#PPWM_Type*CTRLB#CTRL_SETB#CTRL_CLRB#CTRL_TOGB# STATB#STAT_SETB#STAT_CLRB#STAT_TOGB#OUT_CTRLB# OUT_CTRL_SETB#$OUT_CTRL_CLRB#(OUT_CTRL_TOGB#,OUT_BUFB#0: RESERVED_0[#4OUT_BUF2B#@: RESERVED_1#DOUT_PITCHB#Pı: RESERVED_2#TOUT_LRCB#`: RESERVED_3#dOUT_PS_ULCB#p: RESERVED_4#tOUT_PS_LRCB#Ҳ: RESERVED_5F#OUT_AS_ULCB#: RESERVED_6x#OUT_AS_LRCB#: RESERVED_7#PS_CTRLB#PS_CTRL_SETB#PS_CTRL_CLRB#PS_CTRL_TOGB#PS_BUFB#: RESERVED_8$#PS_UBUFB#ߴ: RESERVED_9S#PS_VBUFB#: RESERVED_10#PS_PITCHB#: RESERVED_11#PS_BACKGROUNDB#: RESERVED_12#PS_SCALEB#: RESERVED_13#PS_OFFSETB#ض: RESERVED_14L#PS_CLRKEYLOWB#: RESERVED_15#PS_CLRKEYHIGHB#÷: RESERVED_16#AS_CTRLB#: RESERVED_17#AS_BUFB#: RESERVED_18#AS_PITCHB#Ӹ: RESERVED_19G#AS_CLRKEYLOWB#: RESERVED_20|#AS_CLRKEYHIGHB#: RESERVED_21#CSC1_COEF0B#: RESERVED_22#CSC1_COEF1B#: RESERVED_23#CSC1_COEF2B#غ:RESERVED_24K#POWERB#:RESERVED_25z#NEXTB#:;RESERVED_26#PORTER_DUFF_CTRLB#PPXP_Type*Ľ:RESERVED_0#BROMPATCHD#ROMPATCHCNTLB#ROMPATCHENHY#ROMPATCHENLB#BROMPATCHAt#:RESERVED_1#ROMPATCHSRB#PROMC_Type*CSB#CNTB#TOVALB#WINB# PRTWDOG_Type*MCRB#IOCRB#BMCR0B#BMCR1B# BBRV#:RESERVED_0j#4INTENB#8INTRB#<SDRAMCR0B#@SDRAMCR1B#DSDRAMCR2B#HSDRAMCR3B#LNANDCR0B#PNANDCR1B#TNANDCR2B#XNANDCR3B#\NORCR0B#`NORCR1B#dNORCR2B#hNORCR3Y#lSRAMCR0B#pSRAMCR1B#tSRAMCR2B#xSRAMCR3Y#|DBICR0B#DBICR1B#:RESERVED_1#IPCR0B#IPCR1B#IPCR2B#IPCMDB#IPTXDATB#: RESERVED_2#IPRXDATN#: RESERVED_3I#STS0N#STS1Y#STS2N#STS3Y#STS4Y#STS5Y#STS6Y#STS7Y#STS8Y#STS9Y#STS10Y#STS11Y#STS12N#STS13Y#STS14Y#STS15Y#PSEMC_Type*HPLRB#HPCOMRB#HPCRB#HPSICRB# HPSVCRB#HPSRB#HPSVSRB#HPHACIVRB#HPHACRN# HPRTCMRB#$HPRTCLRB#(HPTAMRB#,HPTALRB#0LPLRB#4LPCRB#8LPMKCRB#<LPSVCRB#@:RESERVED_0Z#DLPTDCRB#HLPSRB#LLPSRTCMRB#PLPSRTCLRB#TLPTARB#XLPSMCMRN#\LPSMCLRN#`LPPGDRB#dLPGPR0_LEGACY_ALIASB#hBLPZMKR#l:RESERVED_1#BLPGPR_ALIAS=#:_RESERVED_2[#BLPGPRz#:RESERVED_3#HPVIDR1N#HPVIDR2N#PSNVS_TypelSSICBSISN*TSCRB#SRCDB#SRPCB#SIEB# #SRLN#SRRN#SRCSHN#SRCSLN# SRUN#$SRQN#(STLB#,STRB#0STCSCHB#4STCSCLB#8:RESERVED_0#<SRFMN#D:RESERVED_1#HSTCB#PPSPDIF_Type*HSCRB#SBMR1N#SRSRB#:RESERVED_0@# SBMR2N#B GPRk# PSRC_Type*:RESERVED_0#TEMPSENSE0B#TEMPSENSE0_SETB#TEMPSENSE0_CLRB#TEMPSENSE0_TOGB#TEMPSENSE1B#TEMPSENSE1_SETB#TEMPSENSE1_CLRB#TEMPSENSE1_TOGB#:RESERVED_1h#TEMPSENSE2B#TEMPSENSE2_SETB#TEMPSENSE2_CLRB#TEMPSENSE2_TOGB#PTEMPMON_Type* COMP1n#COMP2n#CAPTn#LOADn#HOLDn#CNTRn# CTRLn# SCTRLn#CMPLD1n#CMPLD2n#CSCTRLn#FILTn#DMAn#:RESERVED_0#ENBLn#*CHANNEL#PTMR_TypeSPKRMAXBPKRSQNSSBLIMBTOTSAMNSFRQCNTNFRQMAXBSSCMCNSCMLBSSCR1CNSCR1LBSSCR2CNSCR2LBSSCR3CNSCR3LBSSCR4CNSCR4LBSSCR5CNSCR5LBSSCR6PCNSCR6PLB*MCTLB#SCMISCB#PKRRNGB## SDCTLB##FRQMINB#3#O# g#$#(#,#0#4#8STATUSN#<NENT#@PKRCNT10N#PKRCNT32N#PKRCNT54N#PKRCNT76N#PKRCNT98N#PKRCNTBAN#PKRCNTDCN#PKRCNTFEN#SEC_CFGB#INT_CTRLB#INT_MASKB#INT_STATUSN#:?RESERVED_0#VID1N#VID2N#PTRNG_Typeŧ*BASIC_SETTINGB#: RESERVED_0#PS_INPUT_BUFFER_ADDRB#: RESERVED_10#FLOW_CONTROLB# : RESERVED_2b#$MEASEURE_VALUEN#0: RESERVED_3#4INT_ENB#@: RESERVED_4#DINT_SIG_ENB#P: RESERVED_5#TINT_STATUSB#`: RESERVED_6"#dDEBUG_MODEB#p: RESERVED_7R#tDEBUG_MODE2B#PTSC_TypeSDEVICEADDRBPERIODICLISTBASEBSASYNCLISTADDRBENDPTLISTADDRB*IDN#HWGENERALN#HWHOSTN#HWDEVICEN# HWTXBUFN#HWRXBUFN#:gRESERVED_0H#GPTIMER0LDB#GPTIMER0CTRLB#GPTIMER1LDB#GPTIMER1CTRLB#SBUSCFGB#:kRESERVED_1#CAPLENGTH#:RESERVED_2#HCIVERSIONԣ#HCSPARAMSN#HCCPARAMSN#:RESERVED_3M#DCIVERSIONԣ#:RESERVED_4#DCCPARAMSN#:RESERVED_5#USBCMDB#USBSTSB#USBINTRB#FRINDEXB#:RESERVED_6 ###:RESERVED_7>#BURSTSIZEB#TXFILLTUNINGB#:RESERVED_8#ENDPTNAKB#ENDPTNAKENB#CONFIGFLAGN#PORTSC1B#:RESERVED_9#OTGSCB#USBMODEB#ENDPTSETUPSTATB#ENDPTPRIMEB#ENDPTFLUSHB#ENDPTSTATN#ENDPTCOMPLETEB#ENDPTCTRL0B#BENDPTCTRL#:tPUSB_Type*:RESERVED_0#USB_OTGn_CTRLB#:RESERVED_1#USB_OTGn_PHY_CTRL_0B#PUSBNC_Type*PWDB#PWD_SETB#PWD_CLRB#PWD_TOGB# TXB#TX_SETB#TX_CLRB#TX_TOGB#RXB# RX_SETB#$RX_CLRB#(RX_TOGB#,CTRLB#0CTRL_SETB#4CTRL_CLRB#8CTRL_TOGB#<STATUSB#@: RESERVED_0S#DDEBUGrB#PDEBUG_SETB#TDEBUG_CLRB#XDEBUG_TOGB#\DEBUG0_STATUSN#`: RESERVED_1#dDEBUG1B#pDEBUG1_SETB#tDEBUG1_CLRB#xDEBUG1_TOGB#|VERSIONN#PUSBPHY_Typec*`VBUS_DETECTB#VBUS_DETECT_SETB#VBUS_DETECT_CLRB#VBUS_DETECT_TOGB# CHRG_DETECTB#CHRG_DETECT_SETB#CHRG_DETECT_CLRB#CHRG_DETECT_TOGB#VBUS_DETECT_STATN# : RESERVED_0#$CHRG_DETECT_STATN#0:RESERVED_1R#4MISCB#PMISC_SETB#TMISC_CLRB#XMISC_TOGB#\*:RESERVED_0#OINSTANCE#DIGPROGN#PUSB_ANALOG_Type*DS_ADDRB#BLK_ATTB#CMD_ARGB#CMD_XFR_TYPB# CMD_RSP0N#CMD_RSP1N#CMD_RSP2N#CMD_RSP3N#DATA_BUFF_ACC_PORTB# PRES_STATEN#$PROT_CTRLB#(SYS_CTRLB#,INT_STATUSB#0INT_STATUS_ENB#4INT_SIGNAL_ENB#8AUTOCMD12_ERR_STATUSB#<HOST_CTRL_CAPB#@WTMK_LVLB#DMIX_CTRLB#H:RESERVED_0w#LFORCE_EVENTB#PADMA_ERR_STATUSN#TADMA_SYS_ADDRB#X:RESERVED_1#\DLL_CTRLB#`DLL_STATUSN#dCLK_TUNE_CTRL_STATUSB#h:SRESERVED_20#lVEND_SPECB#MMC_BOOTB#VEND_SPEC2B#TUNING_CTRLB#PUSDHC_Type* WCRn#WSRn#WRSRԣ#WICRn#WMCRn#PWDOG_Type*SEL0n#SEL1n#SEL2n#SEL3n#SEL4n#SEL5n# SEL6n# SEL7n#SEL8n#SEL9n#SEL10n#SEL11n#SEL12n#SEL13n#SEL14n#SEL15n#SEL16n# SEL17n#"SEL18n#$SEL19n#&SEL20n#(SEL21n#*SEL22n#,SEL23n#.SEL24n#0SEL25n#2SEL26n#4SEL27n#6SEL28n#8SEL29n#:SEL30n#<SEL31n#>SEL32n#@SEL33n#BSEL34n#DSEL35n#FSEL36n#HSEL37n#JSEL38n#LSEL39n#NSEL40n#PSEL41n#RSEL42n#TSEL43n#VSEL44n#XSEL45n#ZSEL46n#\SEL47n#^SEL48n#`SEL49n#bSEL50n#dSEL51n#fSEL52n#hSEL53n#jSEL54n#lSEL55n#nSEL56n#pSEL57n#rSEL58n#tSEL59n#vSEL60n#xSEL61n#zSEL62n#|SEL63n#~SEL64n#SEL65n#CTRL0n#CTRL1n#PXBARA_Type*SEL0n#SEL1n#SEL2n#SEL3n#SEL4n#SEL5n# SEL6n# SEL7n#PXBARB_Type*:RESERVED_0 #MISC0B#MISC0_SETB#MISC0_CLRB#MISC0_TOGB#:RESERVED_1l#LOWPWR_CTRLB#LOWPWR_CTRL_SETB#LOWPWR_CTRL_CLRB#LOWPWR_CTRL_TOGB#:RESERVED_2#OSC_CONFIG0B#OSC_CONFIG0_SETB#OSC_CONFIG0_CLRB#OSC_CONFIG0_TOGB#OSC_CONFIG1B#OSC_CONFIG1_SETB#OSC_CONFIG1_CLRB#OSC_CONFIG1_TOGB#OSC_CONFIG2B#OSC_CONFIG2_SETB#OSC_CONFIG2_CLRB#OSC_CONFIG2_TOGB#PXTALOSC24M_Type .\devices\MIMXRT1052\drivers\fsl_common.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash/>_status_groupskStatusGroup_Generic kStatusGroup_FLASH kStatusGroup_LPSPI kStatusGroup_FLEXIO_SPI kStatusGroup_DSPI kStatusGroup_FLEXIO_UART kStatusGroup_FLEXIO_I2C kStatusGroup_LPI2C kStatusGroup_UART kStatusGroup_I2C kStatusGroup_LPSCI kStatusGroup_LPUART kStatusGroup_SPI kStatusGroup_XRDC kStatusGroup_SEMA42 kStatusGroup_SDHC kStatusGroup_SDMMC kStatusGroup_SAI kStatusGroup_MCG kStatusGroup_SCG kStatusGroup_SDSPI kStatusGroup_FLEXIO_I2S kStatusGroup_FLEXIO_MCULCD kStatusGroup_FLASHIAP kStatusGroup_FLEXCOMM_I2C kStatusGroup_I2S kStatusGroup_IUART kStatusGroup_CSI kStatusGroup_MIPI_DSI kStatusGroup_SDRAMC #kStatusGroup_POWER 'kStatusGroup_ENET (kStatusGroup_PHY )kStatusGroup_TRGMUX *kStatusGroup_SMARTCARD +kStatusGroup_LMEM ,kStatusGroup_QSPI -kStatusGroup_DMA 2kStatusGroup_EDMA 3kStatusGroup_DMAMGR 4kStatusGroup_FLEXCAN 5kStatusGroup_LTC 6kStatusGroup_FLEXIO_CAMERA 7kStatusGroup_LPC_SPI 8kStatusGroup_LPC_USART 9kStatusGroup_DMIC :kStatusGroup_SDIF ;kStatusGroup_SPIFI <kStatusGroup_OTP =kStatusGroup_MCAN >kStatusGroup_CAAM ?kStatusGroup_ECSPI @kStatusGroup_USDHC AkStatusGroup_LPC_I2C BkStatusGroup_DCP CkStatusGroup_MSCAN DkStatusGroup_ESAI EkStatusGroup_FLEXSPI FkStatusGroup_MMDC GkStatusGroup_MICFIL HkStatusGroup_SDMA IkStatusGroup_ICS JkStatusGroup_SPDIF KkStatusGroup_NOTIFIER bkStatusGroup_DebugConsole ckStatusGroup_SEMC dkStatusGroup_ApplicationRangeStart e_generic_statuskStatus_Success kStatus_Fail kStatus_ReadOnly kStatus_OutOfRange kStatus_InvalidArgument kStatus_Timeout kStatus_NoTransferInProgress Pstatus_t ; EnableIRQ$ainterrupta__result; DisableIRQ$ainterrupta__result; DisableGlobalIRQYa__resultY\regPrimaskY< EnableGlobalIRQ$Yprimask| middleware\flexspi\fsl_flexspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash_Bool"YPflexspi_serial_clk_freq_tsPflexspi_read_sample_clk_tPflexspi_ipcmd_error_tPflexspi_lut_seq_tPflexspi_dll_time_t Pflexspi_mem_config_t" Pflexspi_operation_t'Pflexspi_xfer_tkFlexSpiClock_CoreClock kFlexSpiClock_AhbClock kFlexSpiClock_SerialRootClock kFlexSpiClock_IpgClock Pflexspi_clock_type_t_FlexSpiSerialClockFreqkFlexSpiSerialClk_30MHz kFlexSpiSerialClk_50MHz kFlexSpiSerialClk_60MHz kFlexSpiSerialClk_75MHz kFlexSpiSerialClk_80MHz kFlexSpiSerialClk_100MHz kFlexSpiSerialClk_133MHz kFlexSpiSerialClk_166MHz kFlexSpiSerialClk_200MHz kFlexSpiClk_SDR kFlexSpiClk_DDR  _FlashReadSampleClkSourcekFlexSPIReadSampleClk_LoopbackInternally kFlexSPIReadSampleClk_LoopbackFromDqsPad kFlexSPIReadSampleClk_LoopbackFromSckPad kFlexSPIReadSampleClk_ExternalInputFromDqsPad  _FlexSpiIpCmdErrorkFlexSpiIpCmdError_NoError kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode kFlexSpiIpCmdError_JumpOnCsInIpCmd kFlexSpiIpCmdError_UnknownOpCode kFlexSpiIpCmdError_SdrDummyInDdrSequence kFlexSpiIpCmdError_DDRDummyInSdrSequence kFlexSpiIpCmdError_InvalidAddress kFlexSpiIpCmdError_SequenceExecutionTimeout kFlexSpiIpCmdError_FlashBoundaryAcrosss  _flexspi_statuskStatus_FLEXSPI_SequenceExecutionTimeoutXkStatus_FLEXSPI_InvalidSequenceYkStatus_FLEXSPI_DeviceTimeoutZkFlexSpiMiscOffset_DiffClkEnable kFlexSpiMiscOffset_Ck2Enable kFlexSpiMiscOffset_ParallelEnable kFlexSpiMiscOffset_WordAddressableEnable kFlexSpiMiscOffset_SafeConfigFreqEnable kFlexSpiMiscOffset_PadSettingOverrideEnable kFlexSpiMiscOffset_DdrModeEnable kFlexSpiMiscOffset_UseValidTimeForAllFreq kFlexSpiDeviceType_SerialNOR kFlexSpiDeviceType_SerialNAND kFlexSpiDeviceType_SerialRAM kFlexSpiDeviceType_MCP_NOR_NAND kFlexSpiDeviceType_MCP_NOR_RAM kSerialFlash_1Pad kSerialFlash_2Pads kSerialFlash_4Pads kSerialFlash_8Pads )_lut_sequenceseqNum:#seqId:#reservedI#kDeviceConfigCmdType_Generic kDeviceConfigCmdType_QuadEnable kDeviceConfigCmdType_Spi2Xpi kDeviceConfigCmdType_Xpi2Spi kDeviceConfigCmdType_Spi2NoCmd kDeviceConfigCmdType_Reset *time_100ps:#delay_cells:#)_FlexSPIConfigtagY#versionY#reserved0Y#readSampleClkSrc:# dataHoldTime:# dataSetupTime:#columnAddressWidth:#deviceModeCfgEnable:#deviceModeType:#waitTimeCfgCommandsI#deviceModeSeq\#deviceModeArgY#configCmdEnable:#:configModeTypea #\configCmdSeqs # reserved1Y#,YconfigCmdArgs #0reserved2Y#<controllerMiscOptionY#@deviceType:#DsflashPadType:#EserialClkFreq:#FlutCustomSeqEnable:#GYreserved3b #HsflashA1SizeY#PsflashA2SizeY#TsflashB1SizeY#XsflashB2SizeY#\csPadSettingOverrideY#`sclkPadSettingOverrideY#ddataPadSettingOverrideY#hdqsPadSettingOverrideY#ltimeoutInMsY#pcommandIntervalY#tvdataValidTime #xbusyOffsetI#|busyBitPolarityI#~Y?lookupTable #\ lutCustomSeq #Yreserved4 #_FlexSPIOperationTypekFlexSpiOperation_Command kFlexSpiOperation_Config kFlexSpiOperation_Write kFlexSpiOperation_Read kFlexSpiOperation_End )_FlexSpiXfer$operation#baseAddressY#seqIdY#seqNumY# isParallelModeEnable#txBuffer#txSizeY#rxBuffer#rxSizeY#  middleware\flexspi_nor\flexspi_nor_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash_flexspi_nor_statuskStatusGroup_FLEXSPINOR kStatus_FLEXSPINOR_ProgramFail NkStatus_FLEXSPINOR_EraseSectorFail!NkStatus_FLEXSPINOR_EraseAllFail"NkStatus_FLEXSPINOR_WaitTimeout#NkStatus_FlexSPINOR_NotSupported$NkStatus_FlexSPINOR_WriteAlignmentError%NkStatus_FlexSPINOR_CommandFailure&NkStatus_FlexSPINOR_SFDP_NotFound'NkStatus_FLEXSPINOR_Unsupported_SFDP_Version(NkStatus_FLEXSPINOR_Flash_NotFound)NkStatus_FLEXSPINOR_DTRRead_DummyProbeFailed*N kSerialNorCfgOption_Tag kSerialNorCfgOption_DeviceType_ReadSFDP_SDR kSerialNorCfgOption_DeviceType_ReadSFDP_DDR kSerialNorCfgOption_DeviceType_HyperFLASH1V8 kSerialNorCfgOption_DeviceType_HyperFLASH3V0 kSerialNorCfgOption_DeviceType_MacronixOctalDDR kSerialNorCfgOption_DeviceType_MacronixOctalSDR kSerialNorCfgOption_DeviceType_MicronOctalDDR kSerialNorCfgOption_DeviceType_MicronOctalSDR kSerialNorCfgOption_DeviceType_AdestoOctalDDR kSerialNorCfgOption_DeviceType_AdestoOctalSDR  kSerialNorQuadMode_NotConfig kSerialNorQuadMode_StatusReg1_Bit6 kSerialNorQuadMode_StatusReg2_Bit1 kSerialNorQuadMode_StatusReg2_Bit7 kSerialNorQuadMode_StatusReg2_Bit1_0x31  kSerialNorEnhanceMode_Disabled kSerialNorEnhanceMode_0_4_4_Mode kSerialNorEnhanceMode_0_8_8_Mode kSerialNorEnhanceMode_DataOrderSwapped kSerialNorEnhanceMode_2ndPinMux *!max_freqY#!misc_modeY#!quad_mode_settingY#!cmd_padsY#!query_padsY# !device_typeY#!option_sizeY#!tagY#SB`UY*!dummy_cyclesY#!status_overrideY#!reservedY#SB-UY)_serial_nor_config_optionoption0#option1|#Pserial_nor_config_option_t*por_mode:#current_mode:#exit_no_cmd_sequence:#restore_sequence:#SBUYPflash_run_context_tTkRestoreSequence_None kRestoreSequence_HW_Reset kRestoreSequence_4QPI_FF kRestoreSequence_5QPI_FF kRestoreSequence_8QPI_FF kRestoreSequence_Send_F0 kRestoreSequence_Send_66_99 kRestoreSequence_Send_6699_9966 kRestoreSequence_Send_06_FF kFlashInstMode_ExtendedSpi kFlashInstMode_0_4_4_SDR kFlashInstMode_0_4_4_DDR kFlashInstMode_QPI_SDR AkFlashInstMode_QPI_DDR BkFlashInstMode_OPI_SDR kFlashInstMode_OPI_DDR )_flexspi_nor_configmemConfig#pageSizeY#sectorSizeY#ipcmdSerialClkFreq:#isUniformBlockSize:#isDataOrderSwapped:#:reserved0 #serialNorType:#needExitNoCmdMode:#halfClkForNonReadCmd:#needRestoreNoCmdMode:#blockSizeY#Y reserve2 #Pflexspi_nor_config_tR h devices\MIMXRT1052\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashP+_BoolPclock_name_tPclock_ip_name_tPclock_osc_tPclock_gate_value_tPclock_mode_t!Pclock_mux_tlPclock_div_tPclock_arm_pll_config_tCPclock_usb_pll_config_tsPclock_sys_pll_config_tPclock_audio_pll_config_tPclock_video_pll_config_tjPclock_enet_pll_config_t_clock_pllkCLOCK_PllArm kCLOCK_PllSys kCLOCK_PllUsb1 kCLOCK_PllAudio kCLOCK_PllVideo kCLOCK_PllEnet0 kCLOCK_PllEnet1 kCLOCK_PllEnet2 kCLOCK_PllUsb2 Pclock_pll_tR_clock_pfdkCLOCK_Pfd0 kCLOCK_Pfd1 kCLOCK_Pfd2 kCLOCK_Pfd3 Pclock_pfd_t_clock_usb_srckCLOCK_Usb480M kCLOCK_UsbSrcUnusedPclock_usb_src_t{_clock_usb_phy_srckCLOCK_Usbphy480M Pclock_usb_phy_src_t<CLOCK_SetMux$kmux$Yvalue\busyShiftY; CLOCK_GetMuxY$kmuxa__resultY< CLOCK_SetDiv$divider$Yvalue\busyShiftY; CLOCK_GetDivY$dividera__resultY\valueY< CLOCK_ControlGate$name$;value\indexY\shiftY\reg^tY"X< CLOCK_EnableClock$name< CLOCK_DisableClock$name< CLOCK_SetMode$Vmode; CLOCK_GetCpuClkFreqYa__resultY< CLOCK_SetXtalFreq$Yfreq< CLOCK_SetRtcXtalFreq$Yfreq8 CLOCK_GetOscFreqYa__resultY8 CLOCK_GetRtcFreqYa__resultY_clock_namekCLOCK_CpuClk kCLOCK_AhbClk kCLOCK_SemcClk kCLOCK_IpgClk kCLOCK_OscClk kCLOCK_RtcClk kCLOCK_ArmPllClk kCLOCK_Usb1PllClk kCLOCK_Usb1PllPfd0Clk kCLOCK_Usb1PllPfd1Clk kCLOCK_Usb1PllPfd2Clk kCLOCK_Usb1PllPfd3Clk kCLOCK_Usb2PllClk kCLOCK_SysPllClk kCLOCK_SysPllPfd0Clk kCLOCK_SysPllPfd1Clk kCLOCK_SysPllPfd2Clk kCLOCK_SysPllPfd3Clk kCLOCK_EnetPll0Clk kCLOCK_EnetPll1Clk kCLOCK_EnetPll2Clk kCLOCK_AudioPllClk kCLOCK_VideoPllClk _clock_ip_namekCLOCK_IpInvalidkCLOCK_Aips_tz1kCLOCK_Aips_tz2kCLOCK_Dcp kCLOCK_Lpuart3 kCLOCK_Can1kCLOCK_Can1SkCLOCK_Can2kCLOCK_Can2SkCLOCK_TracekCLOCK_Gpt2kCLOCK_Gpt2SkCLOCK_Lpuart2kCLOCK_Gpio2kCLOCK_Lpspi1kCLOCK_Lpspi2kCLOCK_Lpspi3kCLOCK_Lpspi4kCLOCK_Adc_5hckCLOCK_EnetkCLOCK_PitkCLOCK_Aoi2kCLOCK_Adc1kCLOCK_Gpt1kCLOCK_Gpt1SkCLOCK_Lpuart4kCLOCK_Gpio1kCLOCK_CsukCLOCK_Gpio5kCLOCK_CsikCLOCK_IomuxcSnvskCLOCK_Lpi2c1kCLOCK_Lpi2c2kCLOCK_Lpi2c3kCLOCK_OcotpkCLOCK_Xbar3kCLOCK_Ipmux1kCLOCK_Ipmux2kCLOCK_Ipmux3kCLOCK_Xbar1kCLOCK_Xbar2kCLOCK_Gpio3kCLOCK_LcdkCLOCK_PxpkCLOCK_Flexio2kCLOCK_Lpuart5kCLOCK_SemckCLOCK_Lpuart6kCLOCK_Aoi1kCLOCK_LcdPixelkCLOCK_Gpio4kCLOCK_Ewm0kCLOCK_Wdog1kCLOCK_FlexRamkCLOCK_Acmp1kCLOCK_Acmp2kCLOCK_Acmp3kCLOCK_Acmp4kCLOCK_OcramkCLOCK_IomuxcSnvsGprkCLOCK_IomuxckCLOCK_IomuxcGprkCLOCK_BeekCLOCK_SimM7kCLOCK_TsckCLOCK_SimMkCLOCK_SimEmskCLOCK_Pwm1kCLOCK_Pwm2kCLOCK_Pwm3kCLOCK_Pwm4kCLOCK_Enc1kCLOCK_Enc2kCLOCK_Enc3kCLOCK_Enc4kCLOCK_Rom kCLOCK_Flexio1 kCLOCK_Wdog3 kCLOCK_Dma kCLOCK_Kpp kCLOCK_Wdog2 kCLOCK_Aips_tz4 kCLOCK_Spdif kCLOCK_SimMain kCLOCK_Sai1 kCLOCK_Sai2 kCLOCK_Sai3 kCLOCK_Lpuart1 kCLOCK_Lpuart7 kCLOCK_SnvsHp kCLOCK_SnvsLp kCLOCK_UsbOh3 kCLOCK_Usdhc1 kCLOCK_Usdhc2 kCLOCK_Dcdc kCLOCK_Ipmux4 kCLOCK_FlexSpi kCLOCK_Trng kCLOCK_Lpuart8 kCLOCK_Timer4 kCLOCK_Aips_tz3 kCLOCK_SimPer kCLOCK_Anadig kCLOCK_Lpi2c4 kCLOCK_Timer1 kCLOCK_Timer2 kCLOCK_Timer3 _clock_osckCLOCK_RcOsc kCLOCK_XtalOsc  _clock_gate_valuekCLOCK_ClockNotNeeded kCLOCK_ClockNeededRun kCLOCK_ClockNeededRunWait  _clock_mode_tkCLOCK_ModeRun kCLOCK_ModeWait kCLOCK_ModeStop %_clock_muxkCLOCK_Pll3SwMux kCLOCK_PeriphMux9kCLOCK_SemcAltMux'kCLOCK_SemcMux&kCLOCK_PrePeriphMuxrkCLOCK_TraceMuxnkCLOCK_PeriphClk2MuxlkCLOCK_LpspiMuxdkCLOCK_FlexspiMux}kCLOCK_Usdhc2Mux1kCLOCK_Usdhc1Mux0kCLOCK_Sai3MuxnkCLOCK_Sai2MuxlkCLOCK_Sai1MuxjkCLOCK_PerclkMux&kCLOCK_Flexio2Mux skCLOCK_CanMux hkCLOCK_UartMux$&kCLOCK_SpdifMux0tkCLOCK_Flexio1Mux0gkCLOCK_Lpi2cMux82kCLOCK_Lcdif1PreMux8kCLOCK_Lcdif1Mux8kCLOCK_CsiMuxkSerialNorCmd_PageProgram_1_1_4_4B 4kSerialNorCmd_Read_SDR_1_4_4_3B kSerialNorCmd_Read_DDR_1_4_4_3B kSerialNorCmd_Read_SDR_1_4_4_4B kSerialNorCmd_Read_SDR_1_1_4_4B lkSerialNorCmd_Read_DDR_1_4_4_4B kSerialNorCmd_ChipErase `kSerialNorCmd_WriteEnable kSerialNorCmd_WriteStatusReg1 kSerialNorCmd_ReadStatusReg1 kSerialNorCmd_WriteStatusReg2 >kSerialNorCmd_ReadStatusReg2 ?kSerialNorCmd_ReadFlagReg pkSerialNorCmd_SE4K_3B kSerialNorCmd_SE4K_4B !kSerialNorCmd_SE64K_3B kSerialNorCmd_SE64K_4B kSerialNorQpiMode_NotConfig kSerialNorQpiMode_Cmd_0x38 kSerialNorQpiMode_Cmd_0x38_QE kSerialNorQpiMode_Cmd_0x35 kSerialNorQpiMode_Cmd_0x71 kSerialNorQpiMode_Cmd_0x61 kSerialNorType_StandardSPI kSerialNorType_HyperBus kSerialNorType_XPI kSerialNorType_NoCmd )_lut_seqYlut#kSerialNOR_IndividualMode kSerialNOR_ParallelMode kFlexSpiSerialClk_Update kFlexSpiSerialClk_Restore kSerialFlash_ReadSFDP ZkSerialFlash_ReadManufacturerId kSfdp_Version_Major_1_0 kSfdp_Version_Minor_0 kSfdp_Version_Minor_A kSfdp_Version_Minor_B kSfdp_Version_Minor_C kSfdp_BasicProtocolTableSize_Rev0 $kSfdp_BasicProtocolTableSize_RevA @kSfdp_BasicProtocolTableSize_RevB @kSfdp_BasicProtocolTableSize_RevC P)_sfdp_headersignatureY#minor_rev:#major_rev:#param_hdr_num:#sfdp_access_protocol:#kParameterID_BasicSpiProtocolkParameterID_SectorMapkParameterID_4ByteAddressInstructionTablekParameterID_xSpiProfile1_0kParameterID_xSpiOrofile2_0kParameterID_StaCtrlCfgRegMapkParameterID_OpiEnableSeq )_sfdp_parameter_headerparameter_id_lsb:#minor_rev:#major_rev:#table_length_in_32bit:#:parameter_table_pointer #parameter_id_msb:#*!erase_sizeY#!write_granularityY#!reserved0Y#!unused0Y#!erase4k_instY#!support_1_1_2_fast_readY#!address_bitsY# !support_ddr_clockingY# !support_1_2_2_fast_readY# !supports_1_4_4_fast_readY# !support_1_1_4_fast_readY# !unused1Y# *!dummy_clocks_1_4_4_readY#!mode_clocks_1_4_4_readY#!inst_1_4_4_readY#!dummy_clocks_1_1_4_readY# !mode_clocks_1_1_4_readY#!inst_1_1_4_readY#*!dummy_clocks_1_2_2_readY#!mode_clocks_1_2_2_readY#!inst_1_2_2_readY#!dummy_clocks_1_1_2_readY# !mode_clocks_1_1_2_readY#!inst_1_1_2_readY#* !support_2_2_2_fast_readY#!reserved0Y#!support_4_4_4_fast_readY#!reserved1Y#*!!reserved0Y#!dummy_clocks_2_2_2_readY# !mode_clocks_2_2_2_readY#!inst_2_2_2_readY#*"!reserved0Y#!dummy_clocks_4_4_4_readY# !mode_clocks_4_4_4_readY#!inst_4_4_4_readY#*"size:#inst:#*#!reserved0Y#!page_sizeY#!reserved1Y#*#suspend_resume_specY#suspend_resume_instY#*$!reserved0Y#!busy_status_pollingY#!reserved1Y#*&!mode_4_4_4_disable_seqY#!mode_4_4_4_enable_seqY#!support_mode_0_4_4Y#!mode_0_4_4_exit_methodY#!mode_0_4_4_entry_methodY# !quad_enable_requirementY# !hold_reset_disableY#!reserved0Y#*'!status_reg_write_enableY#!reserved0Y#!soft_reset_rescue_supportY#!exit_4_byte_addressingY# !enter_4_byte_addrssingY#*)!dummy_clocks_1_8_8_readY#!mode_clocks_1_8_8_readY#!inst_1_8_8_readY#!dummy_clocks_1_1_8_readY# !mode_clocks_1_1_8_readY#!inst_1_1_8_readY#*+!reservedY#!output_driver_strengthY# !jedec_spi_protocol_resetY#!dqs_waveform_type_sdrY#!dqs_support_in_qpi_sdrY#!dqs_support_in_qpi_ddrY#!dqs_support_in_opi_strY#!cmd_and_extension_in_opi_ddrY#!byte_order_in_opi_ddrY#*-!opi_sdr_disable_seqY#!opi_sdr_enable_deqY#!support_mode_0_8_8Y#!mode_0_8_8_exit_methodY#!mode_0_8_8_entry_methodY# !octal_enable_requirementY# !reservedY# */!qpi_sdr_no_dqsY#!qpi_sdr_with_dqsY#!qpi_ddr_no_dqsY#!qpi_ddr_with_dqsY#!opi_sdr_no_dqsY# !opi_sdr_with_dqsY#!opi_ddr_no_dqsY#!opi_ddr_with_dqsY#)2_jedec_flash_param_tablePmisc #flash_densityY#read_1_4_info*#read_1_2_info# read_22_44_check#read_2_2_info9#read_4_4_info#05erase_infoY#erase_timingY#$chip_erase_progrm_infoV#(suspend_resume_info#,busy_status_info#4mode_4_4_info-#8mode_config_info6#<read_1_8_info#@xpi_misc_info#Dmode_octal_info#Hmax_speed_info_xpi#L*9!support_1_1_1_readY#!support_1_1_1_fast_readY#!support_1_1_2_fast_readY#!support_1_2_2_fast_readY#!support_1_1_4_fast_readY#!support_1_4_4_fast_readY#!support_1_1_1_page_programY#!support_1_1_4_page_programY#!support_1_4_4_page_programY#!support_erase_type1_sizeY#!support_erase_type2_sizeY#!support_erase_type3_sizeY#!support_erase_type4_sizeY#!support_1_1_1_dtr_readY#!support_1_2_2_dtr_readY#!support_1_4_4_dtr_readY#!support_volatile_sector_lock_read_cmdY#!support_volatile_sector_lock_write_cmdY#!support_nonvolatile_sector_lock_read_cmdY# !support_nonvolatile_sector_lock_write_cmdY# !reservedY# *99:erase_inst#):_jedec_4byte_addressing_inst_tablecmd_4byte_support_infod#erase_inst_info#);_jdec_query_tabledstandard_versionY#flash_param_tbl_sizeY#flash_param_tblE#has_4b_addressing_inst_table#Xflash_4b_inst_tblg#\ devices\MIMXRT1052\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash@(+_Bool6"6"6"6" 7""*7",YtY9CLOCK_InitUsb1Pll$config9CLOCK_DeinitUsb1Pll9CLOCK_InitUsb2Pll$config9CLOCK_DeinitUsb2Pll .\devices\MIMXRT1052\drivers\fsl_common.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash8_status_groupskStatusGroup_Generic kStatusGroup_FLASH kStatusGroup_LPSPI kStatusGroup_FLEXIO_SPI kStatusGroup_DSPI kStatusGroup_FLEXIO_UART kStatusGroup_FLEXIO_I2C kStatusGroup_LPI2C kStatusGroup_UART kStatusGroup_I2C kStatusGroup_LPSCI kStatusGroup_LPUART kStatusGroup_SPI kStatusGroup_XRDC kStatusGroup_SEMA42 kStatusGroup_SDHC kStatusGroup_SDMMC kStatusGroup_SAI kStatusGroup_MCG kStatusGroup_SCG kStatusGroup_SDSPI kStatusGroup_FLEXIO_I2S kStatusGroup_FLEXIO_MCULCD kStatusGroup_FLASHIAP kStatusGroup_FLEXCOMM_I2C kStatusGroup_I2S kStatusGroup_IUART kStatusGroup_CSI kStatusGroup_MIPI_DSI kStatusGroup_SDRAMC #kStatusGroup_POWER 'kStatusGroup_ENET (kStatusGroup_PHY )kStatusGroup_TRGMUX *kStatusGroup_SMARTCARD +kStatusGroup_LMEM ,kStatusGroup_QSPI -kStatusGroup_DMA 2kStatusGroup_EDMA 3kStatusGroup_DMAMGR 4kStatusGroup_FLEXCAN 5kStatusGroup_LTC 6kStatusGroup_FLEXIO_CAMERA 7kStatusGroup_LPC_SPI 8kStatusGroup_LPC_USART 9kStatusGroup_DMIC :kStatusGroup_SDIF ;kStatusGroup_SPIFI <kStatusGroup_OTP =kStatusGroup_MCAN >kStatusGroup_CAAM ?kStatusGroup_ECSPI @kStatusGroup_USDHC AkStatusGroup_LPC_I2C BkStatusGroup_DCP CkStatusGroup_MSCAN DkStatusGroup_ESAI EkStatusGroup_FLEXSPI FkStatusGroup_MMDC GkStatusGroup_MICFIL HkStatusGroup_SDMA IkStatusGroup_ICS JkStatusGroup_SPDIF KkStatusGroup_NOTIFIER bkStatusGroup_DebugConsole ckStatusGroup_SEMC dkStatusGroup_ApplicationRangeStart e_generic_statuskStatus_Success kStatus_Fail kStatus_ReadOnly kStatus_OutOfRange kStatus_InvalidArgument kStatus_Timeout kStatus_NoTransferInProgress Pstatus_t;EnableIRQ$ainterrupta__result;DisableIRQ$ainterrupta__result;DisableGlobalIRQYa__resultY\regPrimaskY<EnableGlobalIRQ$Yprimask bsp\src\hardware_init_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash44"Y"Y bsp\src\clock_config_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash P7kMaxAHBClockD"YtY9flexspi_clock_gate_enable$Yinstance9flexspi_clock_gate_disable$Yinstance8 get_core_clockYa__resultY .\devices\MIMXRT1052\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash 9_BoolPclock_name_tPclock_ip_name_tPclock_osc_tPclock_gate_value_tPclock_mode_tKPclock_mux_tPclock_div_tPclock_arm_pll_config_tmPclock_usb_pll_config_tPclock_sys_pll_config_tPclock_audio_pll_config_t%Pclock_video_pll_config_tPclock_enet_pll_config_t_clock_pllkCLOCK_PllArm kCLOCK_PllSys kCLOCK_PllUsb1 kCLOCK_PllAudio kCLOCK_PllVideo kCLOCK_PllEnet0 kCLOCK_PllEnet1 kCLOCK_PllEnet2 kCLOCK_PllUsb2 Pclock_pll_tT_clock_pfdkCLOCK_Pfd0 kCLOCK_Pfd1 kCLOCK_Pfd2 kCLOCK_Pfd3 Pclock_pfd_t_clock_usb_srckCLOCK_Usb480M kCLOCK_UsbSrcUnusedPclock_usb_src_t}_clock_usb_phy_srckCLOCK_Usbphy480M Pclock_usb_phy_src_tqg_xtalFreqYqg_rtcXtalFreqY< CLOCK_SetMux$mmux$Yvalue\busyShiftY; CLOCK_GetMuxY$mmuxa__resultY< CLOCK_SetDiv$divider$Yvalue\busyShiftY; CLOCK_GetDivY$dividera__resultY\valueY< CLOCK_ControlGate$name$=value\indexY\shiftY\regtY"< CLOCK_EnableClock$name< CLOCK_DisableClock$name< CLOCK_SetMode$Xmode; CLOCK_GetCpuClkFreqYa__resultY; CLOCK_GetOscFreqYa__resultY; CLOCK_GetRtcFreqYa__resultY< CLOCK_SetRtcXtalFreq$Yfreq9 CLOCK_SetXtalFreq$Yfreq_clock_namekCLOCK_CpuClk kCLOCK_AhbClk kCLOCK_SemcClk kCLOCK_IpgClk kCLOCK_OscClk kCLOCK_RtcClk kCLOCK_ArmPllClk kCLOCK_Usb1PllClk kCLOCK_Usb1PllPfd0Clk kCLOCK_Usb1PllPfd1Clk kCLOCK_Usb1PllPfd2Clk kCLOCK_Usb1PllPfd3Clk kCLOCK_Usb2PllClk kCLOCK_SysPllClk kCLOCK_SysPllPfd0Clk kCLOCK_SysPllPfd1Clk kCLOCK_SysPllPfd2Clk kCLOCK_SysPllPfd3Clk kCLOCK_EnetPll0Clk kCLOCK_EnetPll1Clk kCLOCK_EnetPll2Clk kCLOCK_AudioPllClk kCLOCK_VideoPllClk _clock_ip_namekCLOCK_IpInvalidkCLOCK_Aips_tz1kCLOCK_Aips_tz2kCLOCK_Dcp kCLOCK_Lpuart3 kCLOCK_Can1kCLOCK_Can1SkCLOCK_Can2kCLOCK_Can2SkCLOCK_TracekCLOCK_Gpt2kCLOCK_Gpt2SkCLOCK_Lpuart2kCLOCK_Gpio2kCLOCK_Lpspi1kCLOCK_Lpspi2kCLOCK_Lpspi3kCLOCK_Lpspi4kCLOCK_Adc_5hckCLOCK_EnetkCLOCK_PitkCLOCK_Aoi2kCLOCK_Adc1kCLOCK_Gpt1kCLOCK_Gpt1SkCLOCK_Lpuart4kCLOCK_Gpio1kCLOCK_CsukCLOCK_Gpio5kCLOCK_CsikCLOCK_IomuxcSnvskCLOCK_Lpi2c1kCLOCK_Lpi2c2kCLOCK_Lpi2c3kCLOCK_OcotpkCLOCK_Xbar3kCLOCK_Ipmux1kCLOCK_Ipmux2kCLOCK_Ipmux3kCLOCK_Xbar1kCLOCK_Xbar2kCLOCK_Gpio3kCLOCK_LcdkCLOCK_PxpkCLOCK_Flexio2kCLOCK_Lpuart5kCLOCK_SemckCLOCK_Lpuart6kCLOCK_Aoi1kCLOCK_LcdPixelkCLOCK_Gpio4kCLOCK_Ewm0kCLOCK_Wdog1kCLOCK_FlexRamkCLOCK_Acmp1kCLOCK_Acmp2kCLOCK_Acmp3kCLOCK_Acmp4kCLOCK_OcramkCLOCK_IomuxcSnvsGprkCLOCK_IomuxckCLOCK_IomuxcGprkCLOCK_BeekCLOCK_SimM7kCLOCK_TsckCLOCK_SimMkCLOCK_SimEmskCLOCK_Pwm1kCLOCK_Pwm2kCLOCK_Pwm3kCLOCK_Pwm4kCLOCK_Enc1kCLOCK_Enc2kCLOCK_Enc3kCLOCK_Enc4kCLOCK_Rom kCLOCK_Flexio1 kCLOCK_Wdog3 kCLOCK_Dma kCLOCK_Kpp kCLOCK_Wdog2 kCLOCK_Aips_tz4 kCLOCK_Spdif kCLOCK_SimMain kCLOCK_Sai1 kCLOCK_Sai2 kCLOCK_Sai3 kCLOCK_Lpuart1 kCLOCK_Lpuart7 kCLOCK_SnvsHp kCLOCK_SnvsLp kCLOCK_UsbOh3 kCLOCK_Usdhc1 kCLOCK_Usdhc2 kCLOCK_Dcdc kCLOCK_Ipmux4 kCLOCK_FlexSpi kCLOCK_Trng kCLOCK_Lpuart8 kCLOCK_Timer4 kCLOCK_Aips_tz3 kCLOCK_SimPer kCLOCK_Anadig kCLOCK_Lpi2c4 kCLOCK_Timer1 kCLOCK_Timer2 kCLOCK_Timer3 _clock_osckCLOCK_RcOsc kCLOCK_XtalOsc  _clock_gate_valuekCLOCK_ClockNotNeeded kCLOCK_ClockNeededRun kCLOCK_ClockNeededRunWait !_clock_mode_tkCLOCK_ModeRun kCLOCK_ModeWait kCLOCK_ModeStop %_clock_muxkCLOCK_Pll3SwMux kCLOCK_PeriphMux9kCLOCK_SemcAltMux'kCLOCK_SemcMux&kCLOCK_PrePeriphMuxrkCLOCK_TraceMuxnkCLOCK_PeriphClk2MuxlkCLOCK_LpspiMuxdkCLOCK_FlexspiMux}kCLOCK_Usdhc2Mux1kCLOCK_Usdhc1Mux0kCLOCK_Sai3MuxnkCLOCK_Sai2MuxlkCLOCK_Sai1MuxjkCLOCK_PerclkMux&kCLOCK_Flexio2Mux skCLOCK_CanMux hkCLOCK_UartMux$&kCLOCK_SpdifMux0tkCLOCK_Flexio1Mux0gkCLOCK_Lpi2cMux82kCLOCK_Lcdif1PreMux8kCLOCK_Lcdif1Mux8kCLOCK_CsiMuxf44tcXfcefcpf?}SystemCoreClockUpdate45ZfreqYZPLL1MainClockYlZPLL2MainClockYCdevices\MIMXRT1052\system_MIMXRT1052.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashpSystemCoreClockY y"0devices\\MIMXRT1052\\system_MIMXRT1052.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flashlp__asm___19_system_MIMXRT1052_c_5d646a67____REVSHlp0devices\\MIMXRT1052\\system_MIMXRT1052.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashPTT__asm___19_system_MIMXRT1052_c_5d646a67____REV16PTmiddleware\flexspi\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashT)4_BoolI hT)b)Ro.h!c9h>flexspi_is_padsetting_override_enableb)p)>iconfigtg___resultIHhp)z)*oyhbhPIhz))ohchIh))oh{ci]Ii))o9iJcDi,> flexspi_configure_dll)*iinstanceYiconfigtg^__resultPZstatusZmdisConfigRequired)*Zbasemn\isUnifiedConfigYflexspiRootClkY\YYflexspiDllPZdllValueYZtempY)*\useDLL)*ZiYP**ZdataValidTimeHY=\dataValidTimeLY**YmaxFreqYXZis_ddr_enabled>  flexspi_get_ticks*+itickszgiintervalNsYifreqYviunitYM^__resultP<Zstatus: *+XcalculatedTicksP(ZcycleNsY>  flexspi_config_mcr1+z+RiinstanceYiconfigtg___resultYseqWaitTicksYXYahbBusWaitTicksY\YserialRootClockFreqY`YahbBusClockFreqYdZbasem>  flexspi_config_flash_control_registersz+B,iinstanceYbiconfigtg.^__resultPZstatus +>,ZindexYYflashSizeYZtempYYserialClockFrequencyYXYcsIntervalTicksYHZbasemZflashSizeStartzg> flexspi_config_ahb_buffersB,,ibasemaiconfigtgN^__resultPNZtempY(ZindexYZstatus;ITj,,o|jcj,,jbjP> flexspi_command_xfer,.iinstanceYixferg___result0 Zstatus[Zbasem,.ZtempY ZisParallelMode,-ZxferRemainingSizeYZxferBufferPtrzg\rx_fifo_sizeY\watermarkYZburst_rx_sizeY,-Zrx_fifo_regg}Z--Zburst_rx_roundY_,-YbufYdZsrcgAZdstg.,-XindexYS-.ZxferRemainingSizeZxferBufferPtrzg \tx_fifo_sizeY\watermarkYZburst_tx_sizeY Zis_transfer_started .^.Ztx_fifo_regga .^.Zburst_tx_roundYC F&j,, fJjFi:-H- fiFi-. fi> flexspi_update_lut..iinstanceY iseqIndexY ilutBaseg iseqNumberY ^__resultP^Zstatus ..Zbasem Zstart_indexY} Zend_indexYj ZflexspiLutPtrgW Fg.. fgFg.. fh> flexspi_device_write_enable.R/biinstanceY9 iconfigtg& iisParallelMode ibaseAddrY ^__resultPVZstatus /N/YflashXferfH> flexspi_device_wait_busyR/b0iinstanceY iconfigtg iisParallelModeI ibaseAddrY6 ___resultL Zstatus Z/b0YYstatusDataBuffer HZbusyMaskY ZbusyPolarityY ZisBusy_ Ystatus0Y@Ystatus1YDYflashXferfZenableTimeoutCheckW ZremainingMsi# Fj/0 oj oj oj oj ejdk /0kck c%k c2k} > flexspi_device_cmd_configb0$1iinstanceY! iconfigtgibaseAddrY^__resultPZstatusj0 1ZbasemeYflashXferfZindexYG01Yread_cmd_padsY>! flexspi_init$12iinstanceYiconfigtg^__resultPZmcr0YZstatus,12ZbasemQZneed_safe_freq F k 2`2 olo+le6lcFl 2`2SlcVlcelxbqlLcleF!ll22 olQol3elcl !p22mc m cmb$mLc;m?! flexspi_wait_idle2 3iinstanceY!23Zbasem?" flexspi_clear_cache 33wiinstanceY" 33XbasemP?# flexspi_half_clock_control3>3WiinstanceYioptionY|#3<3ZbasemiI#g>3N3CogVI$SiN3^3/owi8biPci%I$i^3n3ojI%@kn34omko|kokbkPcky%z34kckfbkbkH middleware\flexspi\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashYg_flexSpiInstancesm y"$middleware\\flexspi\\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flashhl__asm___13_fsl_flexspi_c_c729c902____REVSHhl$middleware\\flexspi\\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashLPT__asm___13_fsl_flexspi_c_c729c902____REV16LPmiddleware\flexspi_nor\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash R)T_BoolIo oo9ood9boP(boU> flexspi_nor_exit_no_cmd_mode  iinstanceYQ9iconfigRo>9iisParallelMode+9ibaseAddrY9^__resultP2YflashXferH> flexspi_nor_write_enable t iinstanceY8iconfigRo8iisParallelMode8ibaseAddrY8^__resultP`Zstatusk8YZlut_tmp~8>flexspi_nor_restore_no_cmd_modet giinstanceYL8iconfigRo.8iisParallelMode8ibaseAddrY7^__resultP>Zstatus7~ YflashXfer> flexspi_nor_wait_busy ;iinstanceY7iconfigRo7iisParallMode7ibaseAddrYq7^__resultPNZstatus)7YZlut_tmpG7? flexspi_change_serial_clockiinstanceY6iconfigRo6ioperationY6 YisClockChangeRequiredZisDdrModeEnabled6Yserial_clockYXYcore_clockY\\dummy_cntY>  flexspi_nor_flash_page_programviinstanceYn6iconfigRoE6idstAddrY6isrc^o5^__resultPZstatus5YflashXferYmemCfgboZisParallelMode5>  flexspi_nor_flash_erase_allvfiinstanceY5iconfigRov5^__resultPZflashSizeStartho4YcurrentFlashSizeY\YbaseAddrY\ZindexY5ZstatusM5YflashXferZmemCfgbo:5> flexspi_nor_flash_erase_sectorf|iinstanceY4iconfigRo4iaddressYk4^__resultPZstatus:4YflashXferZisParallelModeM4YmemCfgbo> flexspi_nor_flash_erase_blockOiinstanceY4iconfigRo3iaddressY3^__resultPZstatus3YflashXferZisParallelMode3YmemCfgbo> flexspi_nor_read_sfdpiinstanceYn3iaddrYP3ibufferho23ibytesY3^__resultP2YflashXferHZstatus3> prepare_quad_mode_enable_sequence.iinstanceY2iconfigRoi2itblnoK2ioptionro2___result1Ystatus,Zenter_quad_mode_optionY1YYlut_seq HT,YxferYstatus_valY> probe_dtr_quad_read_dummy_cycles.iinstanceY1iconfigRoO1idummy_cyclesho1___result`0Zstatuss0Zdummy_cycle_detected0YflashXferYYlut_seq DBXoYprobe_pattern, YYbufferM \need_program_patternZmax_probe_tryY0Zprobe_cntY0Zprobe_dummy_cyclesY0> get_page_sector_block_size_from_sfdpGiconfigRo50itblno 0isector_erase_cmdho/iblock_erase_cmdho/___resultr.Zparam_tblxo#/Zflash_4b_tbl|o.Yflash_sizeYZflash_densityY.Zpage_sizeY.Zsector_sizeY.Zblock_sizeY.Zblock_erase_typeYu/Zsector_erase_typeYL/ZindexY.Zcurrent_erase_sizeY.> parse_sfdpFiinstanceY-iconfigRog-itblno,ioptionroQ,___resultt(Zstatus+FZparam_tblxo#+Zflash_4b_tbl|o*Zsupport_ddr_modeH*Yread_cmd:Ydummy_cyclesYZmode_cycles:)Ysector_erase_cmdYPYblock_erase_cmdYTZaddress_bitsY(Zaddress_padsYk)Ycmd_padsYZenhance_modeY(*Zentry_methodY(Zexit_methodY(FZmode_instYV(>" flexspi_nor_read_sfdp_infoF.iinstanceY(itblno'iaddress_shift_enable'^__resultPZstatus'"F,Ysfdp_headernZaddressY7'Yparameter_header_numberY n Ysfdp_param_hdrsiZmax_hdr_countYv'"F*XiYVh""Zparameter_idY'""Xtable_sizeYW"Zindex'>$ flexspi_nor_generate_config_block_hyperflash.diinstanceY&iconfigRo&iis_1v8&___resultL&Zstatusj&$4b#YYlut_seq@YdataYX#YYbufferP>& flexspi_nor_restore_spi_protocoldUiinstanceY&iconfigRo%irun_ctxo%^__resultPZstatus%Yxfer&dZpadY|%Zcmd_instY^%%YYlut_seq&dYwait_cnto\>* flexspi_nor_generate_config_block_mxic_octalflash&!iinstanceY'%iconfigRo$ioptionrom$^__resultPZstatus#Yxfer~'YYmfg_idZis_sdr_mode#$(oYk_rdid_lut*"!Zcmd_padsY#Zquery_padsYv#ZindexY#\mfg_id_bufferoZenableDTR")PYrun_ctx1~) Yrun_ctx1~* !Zcmd_instY"Zaddr_instY"Zdummy_instY"Zread_instY"Ywrite_instY~>- flexspi_nor_generate_config_block_micron_octalflash&!"iinstanceYa"iconfigRo8"ioptionro"^__resultPZstatus!+oYk_sdfp_lutZis_sdr_mode!-F!"Yjedec_info_tbl7o~Ysector_erase_cmdY~Yblock_erase_cmdY~\opi_mode_enable-P!"Yrun_ctx1~-!"Zaddress_bitsYv!Ypage_program_cmdY-""Yrun_ctx1~>3 flexspi_nor_generate_config_block_adesto_octalflash" &iinstanceYK!iconfigRo ioptionro ___result0kSfdp_LutIndex_Sdr_1_1 kSfdp_LutIndex_Sdr_4_4 kSfdp_LutIndex_Sdr_8_8 kSfdp_LutIndex_Ddr_4_4 kSfdp_LutIndex_Ddr_8_8 Zstatus] Zis_sdr_mode 0oYk_sdfp_lut,3#&Zaddress_shift_enableZquery_padsYZcmd_padsYsZlutIndexYUYjedec_info_tbl7o~Ysector_erase_cmdYXYblock_erase_cmdY\Zaddr_padsYB\dummy_padsY\write_padsY\read_padsYZaddr_instY/Zdummy_instYZread_instYYwrite_instY~Yrun_ctx1~30#&Yrun_ctx1~>4 flexspi_nor_get_config &&}iinstanceYiconfigRoioptionro^__resultPZstatuso>6 flexspi_nor_flash_erase&\'9iinstanceYPiconfigRo2istartYilengthY ___resultZaligned_startYZaligned_endYZstatus6'V'Zis_addr_block_alignedvZremaining_sizeYc>8 flexspi_nor_flash_read\''iinstanceY8iconfigRo%idsthoistartYibytesY^__resultPVZstatus8f''YflashXferYisParallelModeYmemCfgbo8''XreadLengthYUI9o'&(o$po3pfo>p@oFpSbQpPlbapbyp`9'"(pbp6bp6I:p&()op"opopbqPcqb,q :H();qb>q~NI;Sq).)bo{qoqoqoq|bqP$bqPbqI;q.)R)4oqio rVorCo#r0b/rP"b?rPbJr4middleware\\flexspi_nor\\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flashdh*__asm___19_flexspi_nor_flash_c_93f2e184____REVSHdh4middleware\\flexspi_nor\\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashHL*__asm___19_flexspi_nor_flash_c_93f2e184____REV16HL devices\MIMXRT1052\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash| ,_Bool> CLOCK_GetPllFreqY<ipll7A___resultY@AZfreqYAZdivSelectY"AZfreqTmpiAYenetRefClkFreqX> CLOCK_GetSysPfdFreqY><ipfd_8A___resultY@ZfreqY@>5CLOCK_GetPeriphClkFreqY><___resultY@ZfreqY@?sCLOCK_InitExternalClk<ibypassXtalOscn@?CLOCK_DeinitExternalClkp<?CLOCK_SwitchOsc\<iosc6[@?CLOCK_InitRcOsc24MH<?CLOCK_DeinitRcOsc24M 4<> CLOCK_GetUsb1PfdFreqY P<ipfd_8=@___resultY @ZfreqY@> CLOCK_GetFreqYP& ;iname5?___resultY?ZfreqY?Ft; e;?CLOCK_InitArmPll& > ;iconfig\s??CLOCK_DeinitArmPll> H ;? CLOCK_InitSysPllH ` ;iconfigf`?? CLOCK_DeinitSysPll` j ;I j ;oM?I Ō |;I  h;o:?I  T;? CLOCK_InitAudioPll 2 4;iconfigz'?ZpllAudioY ?Zmisc2Y>? CLOCK_DeinitAudioPll2 > ;? CLOCK_InitVideoPll> ;iconfig>ZpllVideoY>Zmisc2Y>? CLOCK_DeinitVideoPll :? CLOCK_InitEnetPll :iconfig>Zenet_pllYv>? CLOCK_DeinitEnetPll :?CLOCK_InitSysPfd $ :ipfd_8c>ipfdFrac:P>ZpfdIndexY=>Xpfd528YR?CLOCK_DeinitSysPfd$ 6 :ipfd_8*>?CLOCK_InitUsb1Pfd6 Z p:ipfd_8>ipfdFrac:>ZpfdIndexY=Xpfd480YR?CLOCK_DeinitUsb1PfdZ l \:ipfd_8=>CLOCK_EnableUsbhs0Clockl <:isrc8=ifreqY=^__resultP<l Yix>CLOCK_EnableUsbhs1Clock :isrc8=ifreqY=^__resultP< Yix>CLOCK_EnableUsbhs0PhyPllClock  9isrc8=ifreqYl=^__resultP,Yg_ccmConfigUsbPlljx>CLOCK_EnableUsbhs1PhyPllClock D 9isrc8Y=ifreqYF=^__resultP,Yg_ccmConfigUsbPlljx?CLOCK_DisableUsbhs0PhyPllClockD V 9FŌD J ?CLOCK_DisableUsbhs1PhyPllClockV h 9F V \ ID;h | 9cc;(= devices\MIMXRT1052\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flashpg_xtalFreqY y"pg_rtcXtalFreqY y"(devices\\MIMXRT1052\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash`d3__asm___11_fsl_clock_c_07a918fd____REVSH`d(devices\\MIMXRT1052\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashDH3__asm___11_fsl_clock_c_07a918fd____REV16DHbsp\src\hardware_init_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash04?qflexspi_iomux_config0^LBiinstanceYeCiconfig flexspi_set_failsafe_setting^8BiconfigB^__resultP(ZstatusB> flexspi_nor_write_persistent$BidataB^__resultP> flexspi_nor_read_persistentBidatalB^__resultP4bsp\\src\\hardware_init_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash\`6__asm___26_hardware_init_MIMXRT1051_c_753bbbb7____REVSH\`4bsp\\src\\hardware_init_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash@D6__asm___26_hardware_init_MIMXRT1051_c_753bbbb7____REV16@Dbsp\src\clock_config_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashL9?>clock_initLRoDXahb_dividerYU|F#PV@f>IܗRb[DoFIbrGDo3F?flexspi_clock_configrDiinstanceYFifreqD^FisampleClkModeY@F)_flexspi_clock_paramfrac:#podf:#Pflexspi_clock_param_tZpfd480YFZcscmr1YEZfracYEZpodfYEm Yk_sdr_clock_configqm Yk_ddr_clock_configLZflexspi_config_arrayE"m> flexspi_get_clockhCiinstanceYEitypeEifreqЗfE___resultEZclockFrequencyYSEZstatus@EYahbBusDividerYYseralRootClkDividerYZarm_clockY"E.`YpfdFracYXpfdClkYP,\flexspi_clk_srcY>  flexspi_get_max_supported_freqh|CiinstanceYDifreqЗDiclkModeYD^__resultPZstatusDI C|Cb`P>  get_bus_clockYC^__resultYPYahbBusDividerY? flexspi_sw_delay_usxCiusiDXticksPerUsYV YticksCount֗hF Ce`0bsp\\src\\clock_config_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashX\<__asm___25_clock_config_MIMXRT1051_c_efd8dd31____REVSHX\0bsp\\src\\clock_config_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash<@$=__asm___25_clock_config_MIMXRT1051_c_efd8dd31____REV16<@FlashDev.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashpFlashDevice y"FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flashp.@intunsigned longunsigned char">InitpCGiadrGiclkGifncG^__resultPj\statusYoptionp>IUnInit/GifncG^__resultP>UEraseChipG^__resultPYstatus>iEraseSectorF$adr^__resultPYstatus>ProgramPage.F$adriszGibufcG^__resultPYstatusFlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flashpconfig y"FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_FlashTXA__asm___10_FlashPrg_c_Init____REVSHTXFlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_HYPER_flashloader\_Template_Flash8<$B__asm___10_FlashPrg_c_Init____REV168<xm devices\MIMXRT1052\.\CMSIS\Include\MIMXRT1052.hcore_cm7.hsystem_MIMXRT1052.h .\CMSIS\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm7.hstdint.hcmsis_version.hcmsis_compiler.hmpu_armv7.h] devices\MIMXRT1052\.\CMSIS\Include\system_MIMXRT1052.ccore_cm7.h4 ~x   / &1 ~ 0 'o#u#y  = qfl  * V.ek F} + w1;~-klP8 .\\CMSIS\\Include\\cmsis_armcc.hlP8 .\\CMSIS\\Include\\cmsis_armcc.hP middleware\flexspi\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\MIMXRT1052\middleware\flexspi\fsl_flexspi.cfsl_flexspi.hassert.hstdbool.hfsl_device_registers.hfsl_flexspi.cpf middleware\flexspi\.\devices\MIMXRT1052\drivers\fsl_flexspi.hfsl_common.h 8 middleware\flexspi\fsl_flexspi.cT)  ~  ~   ~  ~  ~   7 %*m! -   %&Q7 4  !1U ! %w! y -I{ %  %  (   |!/ -  !&&,-  - k-" u     !"d/"d/ j4~K' &- /%'/ !] & y   "'   $~ ~+   ~1|~ ) 2  y "{ ! }{ L $ $ {   96~# ~(0~&-2~7X />% $ z- & 99~6 ~!# w  #X .  "  n} z~ ! 6 <y & ~y | |  +% - ?* { ,'-H + - !?,   }+   )w  $!& vz     (4&88?& 3U+1$ !  ?!: 9 %   x " G   !  " %' *"""""~ "~  !~{ &v%   ~  ~{ 2 &v%   !A!       z u  ~ o &  % 0 -?, n 0 ;)P8 .\\CMSIS\\Include\\cmsis_armcc.hhP8 .\\CMSIS\\Include\\cmsis_armcc.hL C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\middleware\middleware\flexspi_nor\middleware\flexspi_nor\flexspi_nor_flash.cstring.hstdlib.hstdbool.hflexspi/fsl_flexspi.hflexspi_nor_flash.hflexspi_nor_flash.c middleware\flexspi_nor\.\devices\MIMXRT1052\drivers\.\middleware\flexspi_nor_flash.hfsl_common.hflexspi/fsl_flexspi.h(B middleware\flexspi_nor\flexspi_nor_flash.c  . /&) {   /&   ~[. 1 * @)4 z   ! ~  Z % x%"($ 2  . ! &  %( 8 Y! ! !~$ *2+ + ! F,2 '6'ws'  -/  2E& i H v2'2 k'$# )2+ - @,2 ' 1'$# )2+ - @,2 ' 1'~ *{   *  w   o r 8 ! G}  - 2!  z *1  v&fczv  s) ':&,J  7, 4&,      %} & - &3 &   |qg7 ,` .+i7~7*{*y  }x  0 znj h &8> )'  7!sZ;%  -  )" z. @  {& +.{.; v+     | v% 3 '   ,!&  H>Bp z$\n|!  A).1 (~T0'   &  ! h 8I+!!| !##!^ 0 B= C= C=B % }8',&& ! x 9 ]~6+ 1O 3P 9w"  2 y   ! * "A   3! # 4 $)}%",,V5   |u    ) ~|.  1 ,,~+ ' ~,   , u %! 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FlashDev.cFlashOS.H .\middleware\.\devices\MIMXRT1052\drivers\flexspi_nor/flexspi_nor_flash.hfsl_common.hflexspi/fsl_flexspi.hth .\middleware\.\devices\MIMXRT1052\drivers\flexspi/fsl_flexspi.hfsl_common.h .\devices\MIMXRT1052\drivers\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\MIMXRT1052\fsl_common.hassert.hstdbool.hstdint.hstring.hstdlib.hfsl_device_registers.hfsl_clock.hdrivers\fsl_common.hxo .\devices\MIMXRT1052\.\CMSIS\Include\MIMXRT1052.hcore_cm7.hsystem_MIMXRT1052.hPD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h,  FlashOS.H! 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(((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) ADC_HC_AIEN_MASK (0x80U) ADC_HC_AIEN_SHIFT (7U) ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) ADC_HC_COUNT (8U) ADC_HS_COCO0_MASK (0x1U) ADC_HS_COCO0_SHIFT (0U) ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) ADC_R_CDATA_MASK (0xFFFU) ADC_R_CDATA_SHIFT (0U) ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) ADC_R_COUNT (8U) ADC_CFG_ADICLK_MASK (0x3U) ADC_CFG_ADICLK_SHIFT (0U) ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) ADC_CFG_MODE_MASK (0xCU) ADC_CFG_MODE_SHIFT (2U) ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) ADC_CFG_ADLSMP_MASK (0x10U) ADC_CFG_ADLSMP_SHIFT (4U) ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) ADC_CFG_ADIV_MASK (0x60U) ADC_CFG_ADIV_SHIFT (5U) ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) ADC_CFG_ADLPC_MASK (0x80U) ADC_CFG_ADLPC_SHIFT (7U) ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) ADC_CFG_ADSTS_MASK (0x300U) ADC_CFG_ADSTS_SHIFT (8U) ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) ADC_CFG_ADHSC_MASK (0x400U) ADC_CFG_ADHSC_SHIFT (10U) ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) ADC_CFG_REFSEL_MASK (0x1800U) ADC_CFG_REFSEL_SHIFT (11U) ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) ADC_CFG_ADTRG_MASK (0x2000U) ADC_CFG_ADTRG_SHIFT (13U) ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) ADC_CFG_AVGS_MASK (0xC000U) ADC_CFG_AVGS_SHIFT (14U) ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) ADC_CFG_OVWREN_MASK (0x10000U) ADC_CFG_OVWREN_SHIFT (16U) ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) ADC_GC_ADACKEN_MASK (0x1U) ADC_GC_ADACKEN_SHIFT (0U) ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) ADC_GC_DMAEN_MASK (0x2U) ADC_GC_DMAEN_SHIFT (1U) ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) ADC_GC_ACREN_MASK (0x4U) ADC_GC_ACREN_SHIFT (2U) ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) ADC_GC_ACFGT_MASK (0x8U) ADC_GC_ACFGT_SHIFT (3U) ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) ADC_GC_ACFE_MASK (0x10U) ADC_GC_ACFE_SHIFT (4U) ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) ADC_GC_AVGE_MASK (0x20U) ADC_GC_AVGE_SHIFT (5U) ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) ADC_GC_ADCO_MASK (0x40U) ADC_GC_ADCO_SHIFT (6U) ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) ADC_GC_CAL_MASK (0x80U) ADC_GC_CAL_SHIFT (7U) ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) ADC_GS_ADACT_MASK (0x1U) ADC_GS_ADACT_SHIFT (0U) ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) ADC_GS_CALF_MASK (0x2U) ADC_GS_CALF_SHIFT (1U) ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) ADC_GS_AWKST_MASK (0x4U) ADC_GS_AWKST_SHIFT (2U) ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) ADC_CV_CV1_MASK (0xFFFU) ADC_CV_CV1_SHIFT (0U) ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) ADC_CV_CV2_MASK (0xFFF0000U) ADC_CV_CV2_SHIFT (16U) ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) ADC_OFS_OFS_MASK (0xFFFU) ADC_OFS_OFS_SHIFT (0U) ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) ADC_OFS_SIGN_MASK (0x1000U) ADC_OFS_SIGN_SHIFT (12U) ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) ADC_CAL_CAL_CODE_MASK (0xFU) ADC_CAL_CAL_CODE_SHIFT (0U) ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) ADC1_BASE (0x400C4000u) ADC1 ((ADC_Type *)ADC1_BASE) ADC2_BASE (0x400C8000u) ADC2 ((ADC_Type *)ADC2_BASE) ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) ADC_ETC_CTRL_SOFTRST_SHIFT (31U) ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) ADC_ETC_TRIGn_CTRL_COUNT (8U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) ADC_ETC_TRIGn_COUNTER_COUNT (8U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)ADC_ETC_BASE (0x403B0000u)ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }ADC_ETC_BASE_PTRS { ADC_ETC }ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }AIPSTZ_MPR_MPROT5_MASK (0xF00U)AIPSTZ_MPR_MPROT5_SHIFT (8U)AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)AIPSTZ_MPR_MPROT3_MASK (0xF0000U)AIPSTZ_MPR_MPROT3_SHIFT (16U)AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)AIPSTZ_MPR_MPROT2_MASK (0xF00000U)AIPSTZ_MPR_MPROT2_SHIFT (20U)AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)AIPSTZ_MPR_MPROT1_MASK (0xF000000U)AIPSTZ_MPR_MPROT1_SHIFT (24U)AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)AIPSTZ_MPR_MPROT0_SHIFT (28U)AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)AIPSTZ_OPACR_OPAC7_MASK (0xFU)AIPSTZ_OPACR_OPAC7_SHIFT (0U)AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)AIPSTZ_OPACR_OPAC6_MASK (0xF0U)AIPSTZ_OPACR_OPAC6_SHIFT (4U)AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)AIPSTZ_OPACR_OPAC5_MASK (0xF00U)AIPSTZ_OPACR_OPAC5_SHIFT (8U)AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)AIPSTZ_OPACR_OPAC4_MASK (0xF000U)AIPSTZ_OPACR_OPAC4_SHIFT (12U)AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)AIPSTZ_OPACR_OPAC3_SHIFT (16U)AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)AIPSTZ_OPACR_OPAC2_SHIFT (20U)AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)AIPSTZ_OPACR_OPAC1_SHIFT (24U)AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)AIPSTZ_OPACR_OPAC0_SHIFT (28U)AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)AIPSTZ_OPACR1_OPAC15_MASK (0xFU)AIPSTZ_OPACR1_OPAC15_SHIFT (0U)AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)AIPSTZ_OPACR1_OPAC14_SHIFT (4U)AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)AIPSTZ_OPACR1_OPAC13_SHIFT (8U)AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)AIPSTZ_OPACR1_OPAC12_SHIFT (12U)AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)AIPSTZ_OPACR1_OPAC11_SHIFT (16U)AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)AIPSTZ_OPACR1_OPAC10_SHIFT (20U)AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)AIPSTZ_OPACR1_OPAC9_SHIFT (24U)AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)AIPSTZ_OPACR1_OPAC8_SHIFT (28U)AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)AIPSTZ_OPACR2_OPAC23_MASK (0xFU)AIPSTZ_OPACR2_OPAC23_SHIFT (0U)AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)AIPSTZ_OPACR2_OPAC22_SHIFT (4U)AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)AIPSTZ_OPACR2_OPAC21_SHIFT (8U)AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)AIPSTZ_OPACR2_OPAC20_SHIFT (12U)AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)AIPSTZ_OPACR2_OPAC19_SHIFT (16U)AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)AIPSTZ_OPACR2_OPAC18_SHIFT (20U)AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)AIPSTZ_OPACR2_OPAC17_SHIFT (24U)AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)AIPSTZ_OPACR2_OPAC16_SHIFT (28U)AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)AIPSTZ_OPACR3_OPAC31_MASK (0xFU)AIPSTZ_OPACR3_OPAC31_SHIFT (0U)AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)AIPSTZ_OPACR3_OPAC30_SHIFT (4U)AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)AIPSTZ_OPACR3_OPAC29_SHIFT (8U)AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)AIPSTZ_OPACR3_OPAC28_SHIFT (12U)AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)AIPSTZ_OPACR3_OPAC27_SHIFT (16U)AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)AIPSTZ_OPACR3_OPAC26_SHIFT (20U)AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)AIPSTZ_OPACR3_OPAC25_SHIFT (24U)AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)AIPSTZ_OPACR3_OPAC24_SHIFT (28U)AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)AIPSTZ_OPACR4_OPAC33_SHIFT (24U)AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)AIPSTZ_OPACR4_OPAC32_SHIFT (28U)AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)AIPSTZ1_BASE (0x4007C000u)AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)AIPSTZ2_BASE (0x4017C000u)AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)AIPSTZ3_BASE (0x4027C000u)AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)AIPSTZ4_BASE (0x4037C000u)AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }AOI_BFCRT01_PT1_DC_MASK (0x3U)AOI_BFCRT01_PT1_DC_SHIFT (0U)AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)AOI_BFCRT01_PT1_CC_MASK (0xCU)AOI_BFCRT01_PT1_CC_SHIFT (2U)AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)AOI_BFCRT01_PT1_BC_MASK (0x30U)AOI_BFCRT01_PT1_BC_SHIFT (4U)AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)AOI_BFCRT01_PT1_AC_MASK (0xC0U)AOI_BFCRT01_PT1_AC_SHIFT (6U)AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)AOI_BFCRT01_PT0_DC_MASK (0x300U)AOI_BFCRT01_PT0_DC_SHIFT (8U)AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)AOI_BFCRT01_PT0_CC_MASK (0xC00U)AOI_BFCRT01_PT0_CC_SHIFT (10U)AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)AOI_BFCRT01_PT0_BC_MASK (0x3000U)AOI_BFCRT01_PT0_BC_SHIFT (12U)AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)AOI_BFCRT01_PT0_AC_MASK (0xC000U)AOI_BFCRT01_PT0_AC_SHIFT (14U)AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)AOI_BFCRT01_COUNT (4U)AOI_BFCRT23_PT3_DC_MASK (0x3U)AOI_BFCRT23_PT3_DC_SHIFT (0U)AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)AOI_BFCRT23_PT3_CC_MASK (0xCU)AOI_BFCRT23_PT3_CC_SHIFT (2U)AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)AOI_BFCRT23_PT3_BC_MASK (0x30U)AOI_BFCRT23_PT3_BC_SHIFT (4U)AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)AOI_BFCRT23_PT3_AC_MASK (0xC0U)AOI_BFCRT23_PT3_AC_SHIFT (6U)AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)AOI_BFCRT23_PT2_DC_MASK (0x300U)AOI_BFCRT23_PT2_DC_SHIFT (8U)AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)AOI_BFCRT23_PT2_CC_MASK (0xC00U)AOI_BFCRT23_PT2_CC_SHIFT (10U)AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)AOI_BFCRT23_PT2_BC_MASK (0x3000U)AOI_BFCRT23_PT2_BC_SHIFT (12U)AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)AOI_BFCRT23_PT2_AC_MASK (0xC000U)AOI_BFCRT23_PT2_AC_SHIFT (14U)AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)AOI_BFCRT23_COUNT (4U)AOI1_BASE (0x403B4000u)AOI1 ((AOI_Type *)AOI1_BASE)AOI2_BASE (0x403B8000u)AOI2 ((AOI_Type *)AOI2_BASE)AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }BEE_CTRL_BEE_ENABLE_MASK (0x1U)BEE_CTRL_BEE_ENABLE_SHIFT (0U)BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)BEE_CTRL_KEY_VALID_MASK (0x10U)BEE_CTRL_KEY_VALID_SHIFT (4U)BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)BEE_CTRL_AC_PROT_EN_MASK (0x40U)BEE_CTRL_AC_PROT_EN_SHIFT (6U)BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU)BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U)BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK)BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W0_KEY0_SHIFT (0U)BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W1_KEY1_SHIFT (0U)BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W2_KEY2_SHIFT (0U)BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W3_KEY3_SHIFT (0U)BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)BEE_STATUS_IRQ_VEC_MASK (0xFFU)BEE_STATUS_IRQ_VEC_SHIFT (0U)BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)BEE_STATUS_BEE_IDLE_MASK (0x100U)BEE_STATUS_BEE_IDLE_SHIFT (8U)BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)BEE_BASE (0x403EC000u)BEE ((BEE_Type *)BEE_BASE)BEE_BASE_ADDRS { BEE_BASE }BEE_BASE_PTRS { BEE }CAN_MCR_MAXMB_MASK (0x7FU)CAN_MCR_MAXMB_SHIFT (0U)CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)CAN_MCR_IDAM_MASK (0x300U)CAN_MCR_IDAM_SHIFT (8U)CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)CAN_MCR_AEN_MASK (0x1000U)CAN_MCR_AEN_SHIFT (12U)CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)CAN_MCR_LPRIOEN_MASK (0x2000U)CAN_MCR_LPRIOEN_SHIFT (13U)CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)CAN_MCR_IRMQ_MASK (0x10000U)CAN_MCR_IRMQ_SHIFT (16U)CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)CAN_MCR_SRXDIS_MASK (0x20000U)CAN_MCR_SRXDIS_SHIFT (17U)CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)CAN_MCR_WAKSRC_MASK (0x80000U)CAN_MCR_WAKSRC_SHIFT (19U)CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)CAN_MCR_LPMACK_MASK (0x100000U)CAN_MCR_LPMACK_SHIFT (20U)CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)CAN_MCR_WRNEN_MASK (0x200000U)CAN_MCR_WRNEN_SHIFT (21U)CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)CAN_MCR_SLFWAK_MASK (0x400000U)CAN_MCR_SLFWAK_SHIFT (22U)CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)CAN_MCR_SUPV_MASK (0x800000U)CAN_MCR_SUPV_SHIFT (23U)CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)CAN_MCR_FRZACK_MASK (0x1000000U)CAN_MCR_FRZACK_SHIFT (24U)CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)CAN_MCR_SOFTRST_MASK (0x2000000U)CAN_MCR_SOFTRST_SHIFT (25U)CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)CAN_MCR_WAKMSK_MASK (0x4000000U)CAN_MCR_WAKMSK_SHIFT (26U)CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)CAN_MCR_NOTRDY_MASK (0x8000000U)CAN_MCR_NOTRDY_SHIFT (27U)CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)CAN_MCR_HALT_MASK (0x10000000U)CAN_MCR_HALT_SHIFT (28U)CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)CAN_MCR_RFEN_MASK (0x20000000U)CAN_MCR_RFEN_SHIFT (29U)CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)CAN_MCR_FRZ_MASK (0x40000000U)CAN_MCR_FRZ_SHIFT (30U)CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)CAN_MCR_MDIS_MASK (0x80000000U)CAN_MCR_MDIS_SHIFT (31U)CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)CAN_CTRL1_PROPSEG_MASK (0x7U)CAN_CTRL1_PROPSEG_SHIFT (0U)CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)CAN_CTRL1_LOM_MASK (0x8U)CAN_CTRL1_LOM_SHIFT (3U)CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)CAN_CTRL1_LBUF_MASK (0x10U)CAN_CTRL1_LBUF_SHIFT (4U)CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)CAN_CTRL1_TSYN_MASK (0x20U)CAN_CTRL1_TSYN_SHIFT (5U)CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)CAN_CTRL1_BOFFREC_MASK (0x40U)CAN_CTRL1_BOFFREC_SHIFT (6U)CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)CAN_CTRL1_SMP_MASK (0x80U)CAN_CTRL1_SMP_SHIFT (7U)CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)CAN_CTRL1_RWRNMSK_MASK (0x400U)CAN_CTRL1_RWRNMSK_SHIFT (10U)CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)CAN_CTRL1_TWRNMSK_MASK (0x800U)CAN_CTRL1_TWRNMSK_SHIFT (11U)CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)CAN_CTRL1_LPB_MASK (0x1000U)CAN_CTRL1_LPB_SHIFT (12U)CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)CAN_CTRL1_ERRMSK_MASK (0x4000U)CAN_CTRL1_ERRMSK_SHIFT (14U)CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)CAN_CTRL1_BOFFMSK_MASK (0x8000U)CAN_CTRL1_BOFFMSK_SHIFT (15U)CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)CAN_CTRL1_PSEG2_MASK (0x70000U)CAN_CTRL1_PSEG2_SHIFT (16U)CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)CAN_CTRL1_PSEG1_MASK (0x380000U)CAN_CTRL1_PSEG1_SHIFT (19U)CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)CAN_CTRL1_RJW_MASK (0xC00000U)CAN_CTRL1_RJW_SHIFT (22U)CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)CAN_CTRL1_PRESDIV_MASK (0xFF000000U)CAN_CTRL1_PRESDIV_SHIFT (24U)CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)CAN_TIMER_TIMER_MASK (0xFFFFU)CAN_TIMER_TIMER_SHIFT (0U)CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)CAN_RXMGMASK_MG_SHIFT (0U)CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)CAN_RX14MASK_RX14M_SHIFT (0U)CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)CAN_RX15MASK_RX15M_SHIFT (0U)CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)CAN_ESR1_WAKINT_MASK (0x1U)CAN_ESR1_WAKINT_SHIFT (0U)CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)CAN_ESR1_ERRINT_MASK (0x2U)CAN_ESR1_ERRINT_SHIFT (1U)CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)CAN_ESR1_BOFFINT_MASK (0x4U)CAN_ESR1_BOFFINT_SHIFT (2U)CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)CAN_ESR1_RX_MASK (0x8U)CAN_ESR1_RX_SHIFT (3U)CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)CAN_ESR1_FLTCONF_MASK (0x30U)CAN_ESR1_FLTCONF_SHIFT (4U)CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)CAN_ESR1_TX_MASK (0x40U)CAN_ESR1_TX_SHIFT (6U)CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)CAN_ESR1_IDLE_MASK (0x80U)CAN_ESR1_IDLE_SHIFT (7U)CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)CAN_ESR1_RXWRN_MASK (0x100U)CAN_ESR1_RXWRN_SHIFT (8U)CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)CAN_ESR1_TXWRN_MASK (0x200U)CAN_ESR1_TXWRN_SHIFT (9U)CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)CAN_ESR1_STFERR_MASK (0x400U)CAN_ESR1_STFERR_SHIFT (10U)CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)CAN_ESR1_FRMERR_MASK (0x800U)CAN_ESR1_FRMERR_SHIFT (11U)CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)CAN_ESR1_CRCERR_MASK (0x1000U)CAN_ESR1_CRCERR_SHIFT (12U)CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)CAN_ESR1_ACKERR_MASK (0x2000U)CAN_ESR1_ACKERR_SHIFT (13U)CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)CAN_ESR1_BIT0ERR_MASK (0x4000U)CAN_ESR1_BIT0ERR_SHIFT (14U)CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)CAN_ESR1_BIT1ERR_MASK (0x8000U)CAN_ESR1_BIT1ERR_SHIFT (15U)CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)CAN_ESR1_RWRNINT_MASK (0x10000U)CAN_ESR1_RWRNINT_SHIFT (16U)CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)CAN_ESR1_TWRNINT_MASK (0x20000U)CAN_ESR1_TWRNINT_SHIFT (17U)CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)CAN_ESR1_SYNCH_MASK (0x40000U)CAN_ESR1_SYNCH_SHIFT (18U)CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)CAN_IMASK2_BUFHM_SHIFT (0U)CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)CAN_IMASK1_BUFLM_SHIFT (0U)CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)CAN_IFLAG2_BUFHI_SHIFT (0U)CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)CAN_IFLAG1_BUF4TO0I_SHIFT (0U)CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)CAN_IFLAG1_BUF5I_MASK (0x20U)CAN_IFLAG1_BUF5I_SHIFT (5U)CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)CAN_IFLAG1_BUF6I_MASK (0x40U)CAN_IFLAG1_BUF6I_SHIFT (6U)CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)CAN_IFLAG1_BUF7I_MASK (0x80U)CAN_IFLAG1_BUF7I_SHIFT (7U)CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)CAN_IFLAG1_BUF31TO8I_SHIFT (8U)CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)CAN_CTRL2_EACEN_MASK (0x10000U)CAN_CTRL2_EACEN_SHIFT (16U)CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)CAN_CTRL2_RRS_MASK (0x20000U)CAN_CTRL2_RRS_SHIFT (17U)CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)CAN_CTRL2_MRP_MASK (0x40000U)CAN_CTRL2_MRP_SHIFT (18U)CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)CAN_CTRL2_TASD_MASK (0xF80000U)CAN_CTRL2_TASD_SHIFT (19U)CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)CAN_CTRL2_RFFN_MASK (0xF000000U)CAN_CTRL2_RFFN_SHIFT (24U)CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)CAN_CTRL2_WRMFRZ_MASK (0x10000000U)CAN_CTRL2_WRMFRZ_SHIFT (28U)CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)CAN_ESR2_IMB_MASK (0x2000U)CAN_ESR2_IMB_SHIFT (13U)CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)CAN_ESR2_VPS_MASK (0x4000U)CAN_ESR2_VPS_SHIFT (14U)CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)CAN_ESR2_LPTM_MASK (0x7F0000U)CAN_ESR2_LPTM_SHIFT (16U)CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)CAN_CRCR_TXCRC_MASK (0x7FFFU)CAN_CRCR_TXCRC_SHIFT (0U)CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)CAN_CRCR_MBCRC_MASK (0x7F0000U)CAN_CRCR_MBCRC_SHIFT (16U)CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)CAN_RXFGMASK_FGM_SHIFT (0U)CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)CAN_RXFIR_IDHIT_MASK (0x1FFU)CAN_RXFIR_IDHIT_SHIFT (0U)CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)CAN_CS_TIME_STAMP_MASK (0xFFFFU)CAN_CS_TIME_STAMP_SHIFT (0U)CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)CAN_CS_DLC_MASK (0xF0000U)CAN_CS_DLC_SHIFT (16U)CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)CAN_CS_RTR_MASK (0x100000U)CAN_CS_RTR_SHIFT (20U)CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)CAN_CS_IDE_MASK (0x200000U)CAN_CS_IDE_SHIFT (21U)CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)CAN_CS_SRR_MASK (0x400000U)CAN_CS_SRR_SHIFT (22U)CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)CAN_CS_CODE_MASK (0xF000000U)CAN_CS_CODE_SHIFT (24U)CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)CAN_CS_COUNT (64U)CAN_ID_EXT_MASK (0x3FFFFU)CAN_ID_EXT_SHIFT (0U)CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)CAN_ID_STD_MASK (0x1FFC0000U)CAN_ID_STD_SHIFT (18U)CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)CAN_ID_PRIO_MASK (0xE0000000U)CAN_ID_PRIO_SHIFT (29U)CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)CAN_ID_COUNT (64U)CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)CAN_WORD0_DATA_BYTE_3_SHIFT (0U)CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)CAN_WORD0_DATA_BYTE_2_SHIFT (8U)CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)CAN_WORD0_DATA_BYTE_1_SHIFT (16U)CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)CAN_WORD0_DATA_BYTE_0_SHIFT (24U)CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)CAN_WORD0_COUNT (64U)CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)CAN_WORD1_DATA_BYTE_7_SHIFT (0U)CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)CAN_WORD1_DATA_BYTE_6_SHIFT (8U)CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)CAN_WORD1_DATA_BYTE_5_SHIFT (16U)CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)CAN_WORD1_DATA_BYTE_4_SHIFT (24U)CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)CAN_WORD1_COUNT (64U)CAN_RXIMR_MI_MASK (0xFFFFFFFFU)CAN_RXIMR_MI_SHIFT (0U)CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)CAN_RXIMR_COUNT (64U)CAN_GFWR_GFWR_MASK (0xFFU)CAN_GFWR_GFWR_SHIFT (0U)CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)CAN1_BASE (0x401D0000u)CAN1 ((CAN_Type *)CAN1_BASE)CAN2_BASE (0x401D4000u)CAN2 ((CAN_Type *)CAN2_BASE)CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASKCAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFTCAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASKCAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFTCAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)CCM_CCR_OSCNT_MASK (0xFFU)CCM_CCR_OSCNT_SHIFT (0U)CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)CCM_CCR_COSC_EN_MASK (0x1000U)CCM_CCR_COSC_EN_SHIFT (12U)CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)CCM_CCR_RBC_EN_MASK (0x8000000U)CCM_CCR_RBC_EN_SHIFT (27U)CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)CCM_CSR_REF_EN_B_MASK (0x1U)CCM_CSR_REF_EN_B_SHIFT (0U)CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)CCM_CSR_CAMP2_READY_MASK (0x8U)CCM_CSR_CAMP2_READY_SHIFT (3U)CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)CCM_CSR_COSC_READY_MASK (0x20U)CCM_CSR_COSC_READY_SHIFT (5U)CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)CCM_CACRR_ARM_PODF_MASK (0x7U)CCM_CACRR_ARM_PODF_SHIFT (0U)CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)CCM_CBCDR_IPG_PODF_MASK (0x300U)CCM_CBCDR_IPG_PODF_SHIFT (8U)CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)CCM_CBCDR_AHB_PODF_MASK (0x1C00U)CCM_CBCDR_AHB_PODF_SHIFT (10U)CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)CCM_CBCDR_SEMC_PODF_MASK (0x70000U)CCM_CBCDR_SEMC_PODF_SHIFT (16U)CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)CCM_CBCMR_LCDIF_PODF_SHIFT (23U)CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)CCM_CBCMR_LPSPI_PODF_SHIFT (26U)CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)CCM_CSCDR1_TRACE_PODF_MASK (0xE000000U)CCM_CSCDR1_TRACE_PODF_SHIFT (25U)CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0xE00U)CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9U)CCM_CSCDR2_LCDIF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_CLK_SEL_MASK)CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)CCM_CSCDR3_CSI_PODF_MASK (0x3800U)CCM_CSCDR3_CSI_PODF_SHIFT (11U)CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)CCM_CLPCR_LPM_MASK (0x3U)CCM_CLPCR_LPM_SHIFT (0U)CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)CCM_CLPCR_SBYOS_MASK (0x40U)CCM_CLPCR_SBYOS_SHIFT (6U)CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)CCM_CLPCR_VSTBY_MASK (0x100U)CCM_CLPCR_VSTBY_SHIFT (8U)CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)CCM_CLPCR_STBY_COUNT_MASK (0x600U)CCM_CLPCR_STBY_COUNT_SHIFT (9U)CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)CCM_CISR_LRF_PLL_MASK (0x1U)CCM_CISR_LRF_PLL_SHIFT (0U)CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)CCM_CISR_COSC_READY_MASK (0x40U)CCM_CISR_COSC_READY_SHIFT (6U)CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)CCM_CIMR_MASK_COSC_READY_MASK (0x40U)CCM_CIMR_MASK_COSC_READY_SHIFT (6U)CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)CCM_CCOSR_CLKO1_SEL_MASK (0xFU)CCM_CCOSR_CLKO1_SEL_SHIFT (0U)CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)CCM_CCOSR_CLKO1_DIV_MASK (0x70U)CCM_CCOSR_CLKO1_DIV_SHIFT (4U)CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)CCM_CCOSR_CLKO1_EN_MASK (0x80U)CCM_CCOSR_CLKO1_EN_SHIFT (7U)CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)CCM_CCOSR_CLKO2_SEL_SHIFT (16U)CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)CCM_CCOSR_CLKO2_DIV_SHIFT (21U)CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)CCM_CCOSR_CLKO2_EN_SHIFT (24U)CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)CCM_CGPR_FPL_MASK (0x10000U)CCM_CGPR_FPL_SHIFT (16U)CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)CCM_CCGR0_CG0_MASK (0x3U)CCM_CCGR0_CG0_SHIFT (0U)CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)CCM_CCGR0_CG1_MASK (0xCU)CCM_CCGR0_CG1_SHIFT (2U)CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)CCM_CCGR0_CG2_MASK (0x30U)CCM_CCGR0_CG2_SHIFT (4U)CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)CCM_CCGR0_CG3_MASK (0xC0U)CCM_CCGR0_CG3_SHIFT (6U)CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)CCM_CCGR0_CG4_MASK (0x300U)CCM_CCGR0_CG4_SHIFT (8U)CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)CCM_CCGR0_CG5_MASK (0xC00U)CCM_CCGR0_CG5_SHIFT (10U)CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)CCM_CCGR0_CG6_MASK (0x3000U)CCM_CCGR0_CG6_SHIFT (12U)CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)CCM_CCGR0_CG7_MASK (0xC000U)CCM_CCGR0_CG7_SHIFT (14U)CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)CCM_CCGR0_CG8_MASK (0x30000U)CCM_CCGR0_CG8_SHIFT (16U)CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)CCM_CCGR0_CG9_MASK (0xC0000U)CCM_CCGR0_CG9_SHIFT (18U)CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)CCM_CCGR0_CG10_MASK (0x300000U)CCM_CCGR0_CG10_SHIFT (20U)CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)CCM_CCGR0_CG11_MASK (0xC00000U)CCM_CCGR0_CG11_SHIFT (22U)CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)CCM_CCGR0_CG12_MASK (0x3000000U)CCM_CCGR0_CG12_SHIFT (24U)CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)CCM_CCGR0_CG13_MASK (0xC000000U)CCM_CCGR0_CG13_SHIFT (26U)CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)CCM_CCGR0_CG14_MASK (0x30000000U)CCM_CCGR0_CG14_SHIFT (28U)CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)CCM_CCGR0_CG15_MASK (0xC0000000U)CCM_CCGR0_CG15_SHIFT (30U)CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)CCM_CCGR1_CG0_MASK (0x3U)CCM_CCGR1_CG0_SHIFT (0U)CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)CCM_CCGR1_CG1_MASK (0xCU)CCM_CCGR1_CG1_SHIFT (2U)CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)CCM_CCGR1_CG2_MASK (0x30U)CCM_CCGR1_CG2_SHIFT (4U)CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)CCM_CCGR1_CG3_MASK (0xC0U)CCM_CCGR1_CG3_SHIFT (6U)CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)CCM_CCGR1_CG4_MASK (0x300U)CCM_CCGR1_CG4_SHIFT (8U)CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)CCM_CCGR1_CG5_MASK (0xC00U)CCM_CCGR1_CG5_SHIFT (10U)CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)CCM_CCGR1_CG6_MASK (0x3000U)CCM_CCGR1_CG6_SHIFT (12U)CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)CCM_CCGR1_CG7_MASK (0xC000U)CCM_CCGR1_CG7_SHIFT (14U)CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)CCM_CCGR1_CG8_MASK (0x30000U)CCM_CCGR1_CG8_SHIFT (16U)CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)CCM_CCGR1_CG9_MASK (0xC0000U)CCM_CCGR1_CG9_SHIFT (18U)CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)CCM_CCGR1_CG10_MASK (0x300000U)CCM_CCGR1_CG10_SHIFT (20U)CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)CCM_CCGR1_CG11_MASK (0xC00000U)CCM_CCGR1_CG11_SHIFT (22U)CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)CCM_CCGR1_CG12_MASK (0x3000000U)CCM_CCGR1_CG12_SHIFT (24U)CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)CCM_CCGR1_CG13_MASK (0xC000000U)CCM_CCGR1_CG13_SHIFT (26U)CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)CCM_CCGR1_CG14_MASK (0x30000000U)CCM_CCGR1_CG14_SHIFT (28U)CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)CCM_CCGR1_CG15_MASK (0xC0000000U)CCM_CCGR1_CG15_SHIFT (30U)CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)CCM_CCGR2_CG0_MASK (0x3U)CCM_CCGR2_CG0_SHIFT (0U)CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)CCM_CCGR2_CG1_MASK (0xCU)CCM_CCGR2_CG1_SHIFT (2U)CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)CCM_CCGR2_CG2_MASK (0x30U)CCM_CCGR2_CG2_SHIFT (4U)CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)CCM_CCGR2_CG3_MASK (0xC0U)CCM_CCGR2_CG3_SHIFT (6U)CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)CCM_CCGR2_CG4_MASK (0x300U)CCM_CCGR2_CG4_SHIFT (8U)CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)CCM_CCGR2_CG5_MASK (0xC00U)CCM_CCGR2_CG5_SHIFT (10U)CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)CCM_CCGR2_CG6_MASK (0x3000U)CCM_CCGR2_CG6_SHIFT (12U)CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)CCM_CCGR2_CG7_MASK (0xC000U)CCM_CCGR2_CG7_SHIFT (14U)CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)CCM_CCGR2_CG8_MASK (0x30000U)CCM_CCGR2_CG8_SHIFT (16U)CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)CCM_CCGR2_CG9_MASK (0xC0000U)CCM_CCGR2_CG9_SHIFT (18U)CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)CCM_CCGR2_CG10_MASK (0x300000U)CCM_CCGR2_CG10_SHIFT (20U)CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)CCM_CCGR2_CG11_MASK (0xC00000U)CCM_CCGR2_CG11_SHIFT (22U)CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)CCM_CCGR2_CG12_MASK (0x3000000U)CCM_CCGR2_CG12_SHIFT (24U)CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)CCM_CCGR2_CG13_MASK (0xC000000U)CCM_CCGR2_CG13_SHIFT (26U)CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)CCM_CCGR2_CG14_MASK (0x30000000U)CCM_CCGR2_CG14_SHIFT (28U)CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)CCM_CCGR2_CG15_MASK (0xC0000000U)CCM_CCGR2_CG15_SHIFT (30U)CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)CCM_CCGR3_CG0_MASK (0x3U)CCM_CCGR3_CG0_SHIFT (0U)CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)CCM_CCGR3_CG1_MASK (0xCU)CCM_CCGR3_CG1_SHIFT (2U)CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)CCM_CCGR3_CG2_MASK (0x30U)CCM_CCGR3_CG2_SHIFT (4U)CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)CCM_CCGR3_CG3_MASK (0xC0U)CCM_CCGR3_CG3_SHIFT (6U)CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)CCM_CCGR3_CG4_MASK (0x300U)CCM_CCGR3_CG4_SHIFT (8U)CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)CCM_CCGR3_CG5_MASK (0xC00U)CCM_CCGR3_CG5_SHIFT (10U)CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)CCM_CCGR3_CG6_MASK (0x3000U)CCM_CCGR3_CG6_SHIFT (12U)CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)CCM_CCGR3_CG7_MASK (0xC000U)CCM_CCGR3_CG7_SHIFT (14U)CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)CCM_CCGR3_CG8_MASK (0x30000U)CCM_CCGR3_CG8_SHIFT (16U)CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)CCM_CCGR3_CG9_MASK (0xC0000U)CCM_CCGR3_CG9_SHIFT (18U)CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)CCM_CCGR3_CG10_MASK (0x300000U)CCM_CCGR3_CG10_SHIFT (20U)CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)CCM_CCGR3_CG11_MASK (0xC00000U)CCM_CCGR3_CG11_SHIFT (22U)CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)CCM_CCGR3_CG12_MASK (0x3000000U)CCM_CCGR3_CG12_SHIFT (24U)CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)CCM_CCGR3_CG13_MASK (0xC000000U)CCM_CCGR3_CG13_SHIFT (26U)CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)CCM_CCGR3_CG14_MASK (0x30000000U)CCM_CCGR3_CG14_SHIFT (28U)CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)CCM_CCGR3_CG15_MASK (0xC0000000U)CCM_CCGR3_CG15_SHIFT (30U)CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)CCM_CCGR4_CG0_MASK (0x3U)CCM_CCGR4_CG0_SHIFT (0U)CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)CCM_CCGR4_CG1_MASK (0xCU)CCM_CCGR4_CG1_SHIFT (2U)CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)CCM_CCGR4_CG2_MASK (0x30U)CCM_CCGR4_CG2_SHIFT (4U)CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)CCM_CCGR4_CG3_MASK (0xC0U)CCM_CCGR4_CG3_SHIFT (6U)CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)CCM_CCGR4_CG4_MASK (0x300U)CCM_CCGR4_CG4_SHIFT (8U)CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)CCM_CCGR4_CG5_MASK (0xC00U)CCM_CCGR4_CG5_SHIFT (10U)CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)CCM_CCGR4_CG6_MASK (0x3000U)CCM_CCGR4_CG6_SHIFT (12U)CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)CCM_CCGR4_CG7_MASK (0xC000U)CCM_CCGR4_CG7_SHIFT (14U)CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)CCM_CCGR4_CG8_MASK (0x30000U)CCM_CCGR4_CG8_SHIFT (16U)CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)CCM_CCGR4_CG9_MASK (0xC0000U)CCM_CCGR4_CG9_SHIFT (18U)CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)CCM_CCGR4_CG10_MASK (0x300000U)CCM_CCGR4_CG10_SHIFT (20U)CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)CCM_CCGR4_CG11_MASK (0xC00000U)CCM_CCGR4_CG11_SHIFT (22U)CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)CCM_CCGR4_CG12_MASK (0x3000000U)CCM_CCGR4_CG12_SHIFT (24U)CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)CCM_CCGR4_CG13_MASK (0xC000000U)CCM_CCGR4_CG13_SHIFT (26U)CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)CCM_CCGR4_CG14_MASK (0x30000000U)CCM_CCGR4_CG14_SHIFT (28U)CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)CCM_CCGR4_CG15_MASK (0xC0000000U)CCM_CCGR4_CG15_SHIFT (30U)CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)CCM_CCGR5_CG0_MASK (0x3U)CCM_CCGR5_CG0_SHIFT (0U)CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)CCM_CCGR5_CG1_MASK (0xCU)CCM_CCGR5_CG1_SHIFT (2U)CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)CCM_CCGR5_CG2_MASK (0x30U)CCM_CCGR5_CG2_SHIFT (4U)CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)CCM_CCGR5_CG3_MASK (0xC0U)CCM_CCGR5_CG3_SHIFT (6U)CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)CCM_CCGR5_CG4_MASK (0x300U)CCM_CCGR5_CG4_SHIFT (8U)CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)CCM_CCGR5_CG5_MASK (0xC00U)CCM_CCGR5_CG5_SHIFT (10U)CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)CCM_CCGR5_CG6_MASK (0x3000U)CCM_CCGR5_CG6_SHIFT (12U)CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)CCM_CCGR5_CG7_MASK (0xC000U)CCM_CCGR5_CG7_SHIFT (14U)CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)CCM_CCGR5_CG8_MASK (0x30000U)CCM_CCGR5_CG8_SHIFT (16U)CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)CCM_CCGR5_CG9_MASK (0xC0000U)CCM_CCGR5_CG9_SHIFT (18U)CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)CCM_CCGR5_CG10_MASK (0x300000U)CCM_CCGR5_CG10_SHIFT (20U)CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)CCM_CCGR5_CG11_MASK (0xC00000U)CCM_CCGR5_CG11_SHIFT (22U)CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)CCM_CCGR5_CG12_MASK (0x3000000U)CCM_CCGR5_CG12_SHIFT (24U)CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)CCM_CCGR5_CG13_MASK (0xC000000U)CCM_CCGR5_CG13_SHIFT (26U)CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)CCM_CCGR5_CG14_MASK (0x30000000U)CCM_CCGR5_CG14_SHIFT (28U)CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)CCM_CCGR5_CG15_MASK (0xC0000000U)CCM_CCGR5_CG15_SHIFT (30U)CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)CCM_CCGR6_CG0_MASK (0x3U)CCM_CCGR6_CG0_SHIFT (0U)CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)CCM_CCGR6_CG1_MASK (0xCU)CCM_CCGR6_CG1_SHIFT (2U)CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)CCM_CCGR6_CG2_MASK (0x30U)CCM_CCGR6_CG2_SHIFT (4U)CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)CCM_CCGR6_CG3_MASK (0xC0U)CCM_CCGR6_CG3_SHIFT (6U)CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)CCM_CCGR6_CG4_MASK (0x300U)CCM_CCGR6_CG4_SHIFT (8U)CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)CCM_CCGR6_CG5_MASK (0xC00U)CCM_CCGR6_CG5_SHIFT (10U)CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)CCM_CCGR6_CG6_MASK (0x3000U)CCM_CCGR6_CG6_SHIFT (12U)CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)CCM_CCGR6_CG7_MASK (0xC000U)CCM_CCGR6_CG7_SHIFT (14U)CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)CCM_CCGR6_CG8_MASK (0x30000U)CCM_CCGR6_CG8_SHIFT (16U)CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)CCM_CCGR6_CG9_MASK (0xC0000U)CCM_CCGR6_CG9_SHIFT (18U)CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)CCM_CCGR6_CG10_MASK (0x300000U)CCM_CCGR6_CG10_SHIFT (20U)CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)CCM_CCGR6_CG11_MASK (0xC00000U)CCM_CCGR6_CG11_SHIFT (22U)CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)CCM_CCGR6_CG12_MASK (0x3000000U)CCM_CCGR6_CG12_SHIFT (24U)CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)CCM_CCGR6_CG13_MASK (0xC000000U)CCM_CCGR6_CG13_SHIFT (26U)CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)CCM_CCGR6_CG14_MASK (0x30000000U)CCM_CCGR6_CG14_SHIFT (28U)CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)CCM_CCGR6_CG15_MASK (0xC0000000U)CCM_CCGR6_CG15_SHIFT (30U)CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)CCM_BASE (0x400FC000u)CCM ((CCM_Type *)CCM_BASE)CCM_BASE_ADDRS { CCM_BASE }CCM_BASE_PTRS { CCM }CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)!CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)!CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)!CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)!CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)!CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)!CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)!CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)!CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)!CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)!CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)!CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)!CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)!CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)!CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)!CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)!CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)!CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)!CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)!CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)!CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)!CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)!CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)!CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)!CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)!CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)!CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)!CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)!CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)!CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)!CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)!CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)!CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)!CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)!CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)!CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)!CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)!CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)!CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)!CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)!CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)!CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)"CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)"CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)"CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)"CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)"CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)"CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)"CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U)"CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U)"CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)"CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)"CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)"CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)"CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)"CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)"CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)"CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)"CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)"CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)"CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)"CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U)"CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U)"CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU)"CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U)"CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)"CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)"CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)"CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U)"CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U)"CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)"CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)"CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)"CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)"CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)"CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)"CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U)"CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U)"CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK)"CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U)"CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U)"CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK)"CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U)"CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U)"CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)"CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)"CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)"CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)"CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)"CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U)"CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U)"CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU)"CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U)"CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)"CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)"CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U)"CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U)"CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)"CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)"CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)"CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)"CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)"CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)"CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U)"CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U)"CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK)"CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U)"CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U)"CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U)"CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U)"CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)"CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)"CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)"CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)"CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)"CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)"CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U)"CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U)"CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU)"CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U)"CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)"CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)"CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)"CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U)"CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U)"CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)"CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)"CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U)#CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U)#CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK)#CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U)#CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U)#CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK)#CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U)#CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U)#CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK)#CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)#CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)#CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)#CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)#CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)#CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U)#CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U)#CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU)#CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U)#CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK)#CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)#CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)#CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U)#CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U)#CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)#CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)#CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U)#CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U)#CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U)#CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U)#CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U)#CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U)#CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)#CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)#CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)#CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)#CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)#CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)#CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)#CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)#CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)#CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)#CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)#CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)#CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)#CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)#CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)#CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)#CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)#CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)#CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)#CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)#CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)#CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)#CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)#CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)#CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)#CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)#CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)#CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)#CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)#CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)#CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)#CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)#CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)#CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)#CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)#CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)#CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)#CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)#CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)#CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)#CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)#CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)#CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)#CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)#CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)#CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)#CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)#CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)#CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)#CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)#CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)#CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)#CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)#CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)#CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)#CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)#CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)#CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)#CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)#CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)#CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)#CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)#CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)#CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)#CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)#CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)#CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)#CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)#CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)#CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)#CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)#CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)#CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)#CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)#CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)#CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)#CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)#CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)#CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)$CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)$CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)$CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)$CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)$CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)$CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)$CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)$CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)$CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)$CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)$CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)$CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)$CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)$CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)$CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)$CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)$CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)$CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)$CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)$CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)$CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)$CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)$CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)$CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)$CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)$CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)$CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)$CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)$CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)$CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)$CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)$CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)$CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)$CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)$CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)$CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)$CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)$CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)$CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)$CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)$CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)$CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)$CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)$CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)$CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)$CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)$CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)$CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)$CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)$CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)$CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)$CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)$CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)$CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)$CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)$CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)$CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)$CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)$CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)$CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)$CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)$CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)$CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)$CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)$CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)$CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)$CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)$CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)$CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)$CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)$CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)$CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)$CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)$CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)$CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)$CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)$CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)$CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)$CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)$CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)$CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)$CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)$CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)$CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)$CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)$CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)$CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)$CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)$CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)$CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)$CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)$CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)$CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)$CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)$CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)$CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)$CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)$CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)$CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)$CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)$CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)$CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)$CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)$CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)$CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)$CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)$CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)%CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)%CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)%CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)%CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)%CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)%CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)%CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)%CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)%CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)%CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)%CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)%CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)%CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)%CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)%CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)%CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)%CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)%CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)%CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)%CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)%CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)%CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)%CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)%CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)%CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)%CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)%CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)%CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)%CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)%CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)%CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)%CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)%CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)%CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)%CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)%CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)%CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)%CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)%CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)%CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)%CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)%CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)%CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)%CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)%CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)%CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)%CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)%CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)%CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)%CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)%CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)%CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)%CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)%CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)%CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)%CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)%CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)%CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)%CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)%CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)%CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)%CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)%CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)%CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)%CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)%CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)%CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)%CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)%CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)%CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)%CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)%CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)%CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)%CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)%CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)%CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)%CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)%CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)%CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)%CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)%CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)%CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)%CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)%CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)%CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)%CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)%CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)%CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)%CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)%CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)%CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)%CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)%CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)%CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)%CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)%CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)%CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)%CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)%CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)%CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)%CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)%CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)%CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)%CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)%CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)%CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)&CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)&CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)&CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)&CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)&CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)&CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)&CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)&CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)&CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)&CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)&CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)&CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U)&CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK)&CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)&CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)&CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)&CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)&CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)&CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)&CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)&CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)&CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)&CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)&CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)&CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)&CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)&CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)&CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)&CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)&CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)&CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)&CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)&CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)&CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)&CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)&CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)&CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)&CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)&CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)&CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)&CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)&CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)&CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)&CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)&CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)&CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)&CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)&CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)&CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)&CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK)&CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)&CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)&CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)&CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)&CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)&CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)&CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)&CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)&CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)&CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)&CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)&CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)&CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)&CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)&CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)&CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)&CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)&CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)&CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)&CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)&CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)&CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)&CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)&CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)&CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)&CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)&CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)&CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)&CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)&CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK)&CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)&CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)&CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)&CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)&CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)&CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)&CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)&CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)&CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)&CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)&CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)&CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)&CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)&CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)&CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)&CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)&CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)&CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)&CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)'CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)'CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)'CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)'CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)'CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)'CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)'CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)'CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)'CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)'CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)'CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)'CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)'CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)'CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)'CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)'CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)'CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK)'CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)'CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)'CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)'CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)'CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)'CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)'CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)'CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)'CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)'CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)'CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)'CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)'CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)'CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)'CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)'CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)'CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)'CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)'CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)'CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)'CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)'CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)'CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)'CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)'CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)'CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)'CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)'CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)'CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)'CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)'CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)'CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)'CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)'CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)'CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)'CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)'CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)'CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)'CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)'CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)'CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)'CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)'CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)'CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)'CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)'CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)'CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)'CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)'CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)'CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)'CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)'CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)'CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)'CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)'CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)'CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)'CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)'CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)'CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)'CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)'CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)'CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)'CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)'CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)'CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)'CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)'CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)'CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)(CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)(CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)(CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)(CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)(CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)(CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)(CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)(CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)(CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)(CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)(CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)(CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)(CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)(CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)(CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)(CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)(CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U)(CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U)(CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)(CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)(CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)(CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)(CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)(CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)(CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)(CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)(CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)(CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)(CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)(CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)(CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)(CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)(CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)(CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)(CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)(CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)(CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)(CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)(CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)(CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)(CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)(CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)(CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)(CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)(CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)(CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)(CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)(CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)(CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)(CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)(CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)(CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)(CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)(CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)(CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)(CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)(CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)(CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)(CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)(CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)(CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)(CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)(CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)(CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)(CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)(CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U)(CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U)(CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)(CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)(CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)(CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)(CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)(CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)(CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)(CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)(CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)(CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)(CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)(CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)(CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)(CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)(CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)(CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)(CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)(CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)(CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)(CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)(CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)(CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)(CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)(CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)(CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)(CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U))CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK))CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U))CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U))CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK))CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U))CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U))CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK))CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U))CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U))CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK))CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U))CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U))CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK))CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U))CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U))CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK))CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U))CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U))CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK))CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U))CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U))CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK))CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U))CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U))CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK))CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U))CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U))CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK))CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U))CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U))CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK))CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U))CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U))CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK))CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U))CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U))CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK))CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U))CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U))CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK))CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U))CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U))CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK))CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U))CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U))CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK))CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U))CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U))CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK))CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U))CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U))CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK))CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U))CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U))CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK))CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U))CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U))CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK))CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U))CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U))CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK))CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U))CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U))CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK))CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U))CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U))CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK))CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U))CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U))CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK))CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U))CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U))CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK))CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U))CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U))CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK))CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U))CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U))CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK))CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U))CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U))CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK))CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U))CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U))CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK))CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U))CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U))CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK))CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U))CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U))CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK))CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U))CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U))CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK))CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U))CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U))CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK))CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U))CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U))CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK))CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U))CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U))CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK))CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U))CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U))CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK))CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U))CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U))CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)*CCM_ANALOG_BASE (0x400D8000u)*CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)*CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }*CCM_ANALOG_BASE_PTRS { CCM_ANALOG }*CMP_CR0_HYSTCTR_MASK (0x3U)*CMP_CR0_HYSTCTR_SHIFT (0U)*CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)*CMP_CR0_FILTER_CNT_MASK (0x70U)*CMP_CR0_FILTER_CNT_SHIFT (4U)*CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)*CMP_CR1_EN_MASK (0x1U)*CMP_CR1_EN_SHIFT (0U)*CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)*CMP_CR1_OPE_MASK (0x2U)*CMP_CR1_OPE_SHIFT (1U)*CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)*CMP_CR1_COS_MASK (0x4U)*CMP_CR1_COS_SHIFT (2U)*CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)*CMP_CR1_INV_MASK (0x8U)*CMP_CR1_INV_SHIFT (3U)*CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)*CMP_CR1_PMODE_MASK (0x10U)*CMP_CR1_PMODE_SHIFT (4U)*CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)*CMP_CR1_WE_MASK (0x40U)*CMP_CR1_WE_SHIFT (6U)*CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)*CMP_CR1_SE_MASK (0x80U)*CMP_CR1_SE_SHIFT (7U)*CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)*CMP_FPR_FILT_PER_MASK (0xFFU)*CMP_FPR_FILT_PER_SHIFT (0U)*CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)*CMP_SCR_COUT_MASK (0x1U)*CMP_SCR_COUT_SHIFT (0U)*CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)*CMP_SCR_CFF_MASK (0x2U)*CMP_SCR_CFF_SHIFT (1U)*CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)*CMP_SCR_CFR_MASK (0x4U)*CMP_SCR_CFR_SHIFT (2U)*CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)*CMP_SCR_IEF_MASK (0x8U)*CMP_SCR_IEF_SHIFT (3U)*CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)*CMP_SCR_IER_MASK (0x10U)*CMP_SCR_IER_SHIFT (4U)*CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)*CMP_SCR_DMAEN_MASK (0x40U)*CMP_SCR_DMAEN_SHIFT (6U)*CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)*CMP_DACCR_VOSEL_MASK (0x3FU)*CMP_DACCR_VOSEL_SHIFT (0U)*CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)*CMP_DACCR_VRSEL_MASK (0x40U)*CMP_DACCR_VRSEL_SHIFT (6U)*CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)*CMP_DACCR_DACEN_MASK (0x80U)*CMP_DACCR_DACEN_SHIFT (7U)*CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)*CMP_MUXCR_MSEL_MASK (0x7U)*CMP_MUXCR_MSEL_SHIFT (0U)*CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)*CMP_MUXCR_PSEL_MASK (0x38U)*CMP_MUXCR_PSEL_SHIFT (3U)*CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)+CMP1_BASE (0x40094000u)+CMP1 ((CMP_Type *)CMP1_BASE)+CMP2_BASE (0x40094008u)+CMP2 ((CMP_Type *)CMP2_BASE)+CMP3_BASE (0x40094010u)+CMP3 ((CMP_Type *)CMP3_BASE)+CMP4_BASE (0x40094018u)+CMP4 ((CMP_Type *)CMP4_BASE)+CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }+CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }+CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }+CSI_CSICR1_PIXEL_BIT_MASK (0x1U)+CSI_CSICR1_PIXEL_BIT_SHIFT (0U)+CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)+CSI_CSICR1_REDGE_MASK (0x2U)+CSI_CSICR1_REDGE_SHIFT (1U)+CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)+CSI_CSICR1_INV_PCLK_MASK (0x4U)+CSI_CSICR1_INV_PCLK_SHIFT (2U)+CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)+CSI_CSICR1_INV_DATA_MASK (0x8U)+CSI_CSICR1_INV_DATA_SHIFT (3U)+CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)+CSI_CSICR1_GCLK_MODE_MASK (0x10U)+CSI_CSICR1_GCLK_MODE_SHIFT (4U)+CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)+CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)+CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)+CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)+CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)+CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)+CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)+CSI_CSICR1_PACK_DIR_MASK (0x80U)+CSI_CSICR1_PACK_DIR_SHIFT (7U)+CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)+CSI_CSICR1_FCC_MASK (0x100U)+CSI_CSICR1_FCC_SHIFT (8U)+CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)+CSI_CSICR1_CCIR_EN_MASK (0x400U)+CSI_CSICR1_CCIR_EN_SHIFT (10U)+CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)+CSI_CSICR1_HSYNC_POL_MASK (0x800U)+CSI_CSICR1_HSYNC_POL_SHIFT (11U)+CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)+CSI_CSICR1_SOF_INTEN_MASK (0x10000U)+CSI_CSICR1_SOF_INTEN_SHIFT (16U)+CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)+CSI_CSICR1_SOF_POL_MASK (0x20000U)+CSI_CSICR1_SOF_POL_SHIFT (17U)+CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)+CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)+CSI_CSICR1_RXFF_INTEN_SHIFT (18U)+CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)+CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)+CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)+CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)+CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)+CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)+CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)+CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)+CSI_CSICR1_STATFF_INTEN_SHIFT (21U)+CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)+CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)+CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)+CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)+CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)+CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)+CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)+CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)+CSI_CSICR1_SF_OR_INTEN_SHIFT (25U),CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK),CSI_CSICR1_COF_INT_EN_MASK (0x4000000U),CSI_CSICR1_COF_INT_EN_SHIFT (26U),CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK),CSI_CSICR1_CCIR_MODE_MASK (0x8000000U),CSI_CSICR1_CCIR_MODE_SHIFT (27U),CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK),CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U),CSI_CSICR1_PrP_IF_EN_SHIFT (28U),CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK),CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U),CSI_CSICR1_EOF_INT_EN_SHIFT (29U),CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK),CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U),CSI_CSICR1_EXT_VSYNC_SHIFT (30U),CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK),CSI_CSICR1_SWAP16_EN_MASK (0x80000000U),CSI_CSICR1_SWAP16_EN_SHIFT (31U),CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK),CSI_CSICR2_HSC_MASK (0xFFU),CSI_CSICR2_HSC_SHIFT (0U),CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK),CSI_CSICR2_VSC_MASK (0xFF00U),CSI_CSICR2_VSC_SHIFT (8U),CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK),CSI_CSICR2_LVRM_MASK (0x70000U),CSI_CSICR2_LVRM_SHIFT (16U),CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK),CSI_CSICR2_BTS_MASK (0x180000U),CSI_CSICR2_BTS_SHIFT (19U),CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK),CSI_CSICR2_SCE_MASK (0x800000U),CSI_CSICR2_SCE_SHIFT (23U),CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK),CSI_CSICR2_AFS_MASK (0x3000000U),CSI_CSICR2_AFS_SHIFT (24U),CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK),CSI_CSICR2_DRM_MASK (0x4000000U),CSI_CSICR2_DRM_SHIFT (26U),CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK),CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U),CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U),CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK),CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U),CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U),CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK),CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U),CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U),CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK),CSI_CSICR3_ECC_INT_EN_MASK (0x2U),CSI_CSICR3_ECC_INT_EN_SHIFT (1U),CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK),CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U),CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U),CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK),CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U),CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U),CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK),CSI_CSICR3_RxFF_LEVEL_MASK (0x70U),CSI_CSICR3_RxFF_LEVEL_SHIFT (4U),CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK),CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U),CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U),CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK),CSI_CSICR3_STATFF_LEVEL_MASK (0x700U),CSI_CSICR3_STATFF_LEVEL_SHIFT (8U),CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK),CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U),CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U),CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK),CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U),CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U),CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK),CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U),CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U),CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK),CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U),CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U),CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK),CSI_CSICR3_FRMCNT_RST_MASK (0x8000U),CSI_CSICR3_FRMCNT_RST_SHIFT (15U),CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK),CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U),CSI_CSICR3_FRMCNT_SHIFT (16U),CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK),CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU),CSI_CSISTATFIFO_STAT_SHIFT (0U),CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK),CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU),CSI_CSIRFIFO_IMAGE_SHIFT (0U),CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK),CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU),CSI_CSIRXCNT_RXCNT_SHIFT (0U),CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK),CSI_CSISR_DRDY_MASK (0x1U),CSI_CSISR_DRDY_SHIFT (0U),CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK),CSI_CSISR_ECC_INT_MASK (0x2U),CSI_CSISR_ECC_INT_SHIFT (1U),CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK),CSI_CSISR_HRESP_ERR_INT_MASK (0x80U),CSI_CSISR_HRESP_ERR_INT_SHIFT (7U),CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK),CSI_CSISR_COF_INT_MASK (0x2000U),CSI_CSISR_COF_INT_SHIFT (13U),CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK),CSI_CSISR_F1_INT_MASK (0x4000U),CSI_CSISR_F1_INT_SHIFT (14U),CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK),CSI_CSISR_F2_INT_MASK (0x8000U),CSI_CSISR_F2_INT_SHIFT (15U),CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK),CSI_CSISR_SOF_INT_MASK (0x10000U),CSI_CSISR_SOF_INT_SHIFT (16U),CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK),CSI_CSISR_EOF_INT_MASK (0x20000U)-CSI_CSISR_EOF_INT_SHIFT (17U)-CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)-CSI_CSISR_RxFF_INT_MASK (0x40000U)-CSI_CSISR_RxFF_INT_SHIFT (18U)-CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)-CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)-CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)-CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)-CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)-CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)-CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)-CSI_CSISR_STATFF_INT_MASK (0x200000U)-CSI_CSISR_STATFF_INT_SHIFT (21U)-CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)-CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)-CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)-CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)-CSI_CSISR_RF_OR_INT_MASK (0x1000000U)-CSI_CSISR_RF_OR_INT_SHIFT (24U)-CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)-CSI_CSISR_SF_OR_INT_MASK (0x2000000U)-CSI_CSISR_SF_OR_INT_SHIFT (25U)-CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)-CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)-CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)-CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)-CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)-CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)-CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)-CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)-CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)-CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)-CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)-CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)-CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)-CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)-CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)-CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)-CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)-CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)-CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)-CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)-CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)-CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)-CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)-CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)-CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)-CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)-CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)-CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)-CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)-CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)-CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)-CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)-CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)-CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)-CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)-CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)-CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)-CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)-CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)-CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)-CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)-CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)-CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)-CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)-CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)-CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)-CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)-CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)-CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)-CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)-CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)-CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)-CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)-CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)-CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)-CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)-CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)-CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)-CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)-CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)-CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)-CSI_CSICR18_AHB_HPROT_MASK (0xF000U)-CSI_CSICR18_AHB_HPROT_SHIFT (12U)-CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)-CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U)-CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U)-CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK)-CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)-CSI_CSICR18_MASK_OPTION_SHIFT (18U)-CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)-CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)-CSI_CSICR18_CSI_ENABLE_SHIFT (31U)-CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)-CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)-CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)-CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)-CSI_BASE (0x402BC000u)-CSI ((CSI_Type *)CSI_BASE)-CSI_BASE_ADDRS { CSI_BASE }.CSI_BASE_PTRS { CSI }.CSI_IRQS { CSI_IRQn }.CSU_CSL_SUR_S2_MASK (0x1U).CSU_CSL_SUR_S2_SHIFT (0U).CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK).CSU_CSL_SSR_S2_MASK (0x2U).CSU_CSL_SSR_S2_SHIFT (1U).CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK).CSU_CSL_NUR_S2_MASK (0x4U).CSU_CSL_NUR_S2_SHIFT (2U).CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK).CSU_CSL_NSR_S2_MASK (0x8U).CSU_CSL_NSR_S2_SHIFT (3U).CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK).CSU_CSL_SUW_S2_MASK (0x10U).CSU_CSL_SUW_S2_SHIFT (4U).CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK).CSU_CSL_SSW_S2_MASK (0x20U).CSU_CSL_SSW_S2_SHIFT (5U).CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK).CSU_CSL_NUW_S2_MASK (0x40U).CSU_CSL_NUW_S2_SHIFT (6U).CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK).CSU_CSL_NSW_S2_MASK (0x80U).CSU_CSL_NSW_S2_SHIFT (7U).CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK).CSU_CSL_LOCK_S2_MASK (0x100U).CSU_CSL_LOCK_S2_SHIFT (8U).CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK).CSU_CSL_SUR_S1_MASK (0x10000U).CSU_CSL_SUR_S1_SHIFT (16U).CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK).CSU_CSL_SSR_S1_MASK (0x20000U).CSU_CSL_SSR_S1_SHIFT (17U).CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK).CSU_CSL_NUR_S1_MASK (0x40000U).CSU_CSL_NUR_S1_SHIFT (18U).CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK).CSU_CSL_NSR_S1_MASK (0x80000U).CSU_CSL_NSR_S1_SHIFT (19U).CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK).CSU_CSL_SUW_S1_MASK (0x100000U).CSU_CSL_SUW_S1_SHIFT (20U).CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK).CSU_CSL_SSW_S1_MASK (0x200000U).CSU_CSL_SSW_S1_SHIFT (21U).CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK).CSU_CSL_NUW_S1_MASK (0x400000U).CSU_CSL_NUW_S1_SHIFT (22U).CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK).CSU_CSL_NSW_S1_MASK (0x800000U).CSU_CSL_NSW_S1_SHIFT (23U).CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK).CSU_CSL_LOCK_S1_MASK (0x1000000U).CSU_CSL_LOCK_S1_SHIFT (24U).CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK).CSU_CSL_COUNT (32U).CSU_HP0_HP_DMA_MASK (0x4U).CSU_HP0_HP_DMA_SHIFT (2U).CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK).CSU_HP0_L_DMA_MASK (0x8U).CSU_HP0_L_DMA_SHIFT (3U).CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK).CSU_HP0_HP_LCDIF_MASK (0x10U).CSU_HP0_HP_LCDIF_SHIFT (4U).CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK).CSU_HP0_L_LCDIF_MASK (0x20U).CSU_HP0_L_LCDIF_SHIFT (5U).CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK).CSU_HP0_HP_CSI_MASK (0x40U).CSU_HP0_HP_CSI_SHIFT (6U).CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK).CSU_HP0_L_CSI_MASK (0x80U).CSU_HP0_L_CSI_SHIFT (7U).CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK).CSU_HP0_HP_PXP_MASK (0x100U).CSU_HP0_HP_PXP_SHIFT (8U).CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK).CSU_HP0_L_PXP_MASK (0x200U).CSU_HP0_L_PXP_SHIFT (9U).CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK).CSU_HP0_HP_DCP_MASK (0x400U).CSU_HP0_HP_DCP_SHIFT (10U).CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK).CSU_HP0_L_DCP_MASK (0x800U).CSU_HP0_L_DCP_SHIFT (11U)/CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)/CSU_HP0_HP_ENET_MASK (0x4000U)/CSU_HP0_HP_ENET_SHIFT (14U)/CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)/CSU_HP0_L_ENET_MASK (0x8000U)/CSU_HP0_L_ENET_SHIFT (15U)/CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)/CSU_HP0_HP_USDHC1_MASK (0x10000U)/CSU_HP0_HP_USDHC1_SHIFT (16U)/CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)/CSU_HP0_L_USDHC1_MASK (0x20000U)/CSU_HP0_L_USDHC1_SHIFT (17U)/CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)/CSU_HP0_HP_USDHC2_MASK (0x40000U)/CSU_HP0_HP_USDHC2_SHIFT (18U)/CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)/CSU_HP0_L_USDHC2_MASK (0x80000U)/CSU_HP0_L_USDHC2_SHIFT (19U)/CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)/CSU_HP0_HP_TPSMP_MASK (0x100000U)/CSU_HP0_HP_TPSMP_SHIFT (20U)/CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)/CSU_HP0_L_TPSMP_MASK (0x200000U)/CSU_HP0_L_TPSMP_SHIFT (21U)/CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)/CSU_HP0_HP_USB_MASK (0x400000U)/CSU_HP0_HP_USB_SHIFT (22U)/CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)/CSU_HP0_L_USB_MASK (0x800000U)/CSU_HP0_L_USB_SHIFT (23U)/CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)/CSU_SA_NSA_DMA_MASK (0x4U)/CSU_SA_NSA_DMA_SHIFT (2U)/CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)/CSU_SA_L_DMA_MASK (0x8U)/CSU_SA_L_DMA_SHIFT (3U)/CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)/CSU_SA_NSA_LCDIF_MASK (0x10U)/CSU_SA_NSA_LCDIF_SHIFT (4U)/CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)/CSU_SA_L_LCDIF_MASK (0x20U)/CSU_SA_L_LCDIF_SHIFT (5U)/CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)/CSU_SA_NSA_CSI_MASK (0x40U)/CSU_SA_NSA_CSI_SHIFT (6U)/CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)/CSU_SA_L_CSI_MASK (0x80U)/CSU_SA_L_CSI_SHIFT (7U)/CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)/CSU_SA_NSA_PXP_MASK (0x100U)/CSU_SA_NSA_PXP_SHIFT (8U)/CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)/CSU_SA_L_PXP_MASK (0x200U)/CSU_SA_L_PXP_SHIFT (9U)/CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)/CSU_SA_NSA_DCP_MASK (0x400U)/CSU_SA_NSA_DCP_SHIFT (10U)/CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)/CSU_SA_L_DCP_MASK (0x800U)/CSU_SA_L_DCP_SHIFT (11U)/CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)/CSU_SA_NSA_ENET_MASK (0x4000U)/CSU_SA_NSA_ENET_SHIFT (14U)/CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)/CSU_SA_L_ENET_MASK (0x8000U)/CSU_SA_L_ENET_SHIFT (15U)/CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)/CSU_SA_NSA_USDHC1_MASK (0x10000U)/CSU_SA_NSA_USDHC1_SHIFT (16U)/CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)/CSU_SA_L_USDHC1_MASK (0x20000U)/CSU_SA_L_USDHC1_SHIFT (17U)/CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)/CSU_SA_NSA_USDHC2_MASK (0x40000U)/CSU_SA_NSA_USDHC2_SHIFT (18U)/CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)/CSU_SA_L_USDHC2_MASK (0x80000U)/CSU_SA_L_USDHC2_SHIFT (19U)/CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)/CSU_SA_NSA_TPSMP_MASK (0x100000U)/CSU_SA_NSA_TPSMP_SHIFT (20U)/CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)/CSU_SA_L_TPSMP_MASK (0x200000U)/CSU_SA_L_TPSMP_SHIFT (21U)/CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)/CSU_SA_NSA_USB_MASK (0x400000U)/CSU_SA_NSA_USB_SHIFT (22U)/CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)/CSU_SA_L_USB_MASK (0x800000U)/CSU_SA_L_USB_SHIFT (23U)/CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)/CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)/CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)/CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)/CSU_HPCONTROL0_L_DMA_MASK (0x8U)/CSU_HPCONTROL0_L_DMA_SHIFT (3U)/CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)/CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)/CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)/CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)/CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)/CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)/CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)/CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)/CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)/CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)/CSU_HPCONTROL0_L_CSI_MASK (0x80U)/CSU_HPCONTROL0_L_CSI_SHIFT (7U)/CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)/CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)/CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)/CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)/CSU_HPCONTROL0_L_PXP_MASK (0x200U)/CSU_HPCONTROL0_L_PXP_SHIFT (9U)/CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)/CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)/CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)/CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)/CSU_HPCONTROL0_L_DCP_MASK (0x800U)/CSU_HPCONTROL0_L_DCP_SHIFT (11U)/CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)/CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)/CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)/CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)0CSU_HPCONTROL0_L_ENET_MASK (0x8000U)0CSU_HPCONTROL0_L_ENET_SHIFT (15U)0CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)0CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)0CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)0CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)0CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)0CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)0CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)0CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)0CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)0CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)0CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)0CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)0CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)0CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)0CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)0CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)0CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)0CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)0CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)0CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)0CSU_HPCONTROL0_HPC_USB_SHIFT (22U)0CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)0CSU_HPCONTROL0_L_USB_MASK (0x800000U)0CSU_HPCONTROL0_L_USB_SHIFT (23U)0CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)0CSU_BASE (0x400DC000u)0CSU ((CSU_Type *)CSU_BASE)0CSU_BASE_ADDRS { CSU_BASE }0CSU_BASE_PTRS { CSU }0DCDC_REG0_PWD_ZCD_MASK (0x1U)0DCDC_REG0_PWD_ZCD_SHIFT (0U)0DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)0DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)0DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)0DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)0DCDC_REG0_SEL_CLK_MASK (0x4U)0DCDC_REG0_SEL_CLK_SHIFT (2U)0DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)0DCDC_REG0_PWD_OSC_INT_MASK (0x8U)0DCDC_REG0_PWD_OSC_INT_SHIFT (3U)0DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)0DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)0DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)0DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)0DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)0DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)0DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)0DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)0DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)0DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)0DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)0DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)0DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)0DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)0DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)0DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)0DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)0DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)0DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)0DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)0DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)0DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)0DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)0DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)0DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)0DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)0DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)0DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)0DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)0DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)0DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)0DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)0DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)0DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)0DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)0DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)0DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)0DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)0DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)0DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)0DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)1DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)1DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)1DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)1DCDC_REG0_XTAL_24M_OK_SHIFT (29U)1DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)1DCDC_REG0_STS_DC_OK_MASK (0x80000000U)1DCDC_REG0_STS_DC_OK_SHIFT (31U)1DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)1DCDC_REG1_REG_FBK_SEL_MASK (0x180U)1DCDC_REG1_REG_FBK_SEL_SHIFT (7U)1DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)1DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)1DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)1DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)1DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)1DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)1DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)1DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)1DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)1DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)1DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)1DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)1DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)1DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)1DCDC_REG1_VBG_TRIM_SHIFT (24U)1DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)1DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)1DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)1DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)1DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)1DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)1DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)1DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)1DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)1DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)1DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)1DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)1DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)1DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)1DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)1DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)1DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)1DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)1DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)1DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)1DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)1DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)1DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)1DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)1DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)1DCDC_REG3_TRG_MASK (0x1FU)1DCDC_REG3_TRG_SHIFT (0U)1DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)1DCDC_REG3_TARGET_LP_MASK (0x700U)1DCDC_REG3_TARGET_LP_SHIFT (8U)1DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)1DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)1DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)1DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)1DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)1DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)1DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)1DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)1DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)1DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)1DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)1DCDC_REG3_DISABLE_STEP_SHIFT (30U)1DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)1DCDC_BASE (0x40080000u)1DCDC ((DCDC_Type *)DCDC_BASE)1DCDC_BASE_ADDRS { DCDC_BASE }1DCDC_BASE_PTRS { DCDC }1DCDC_IRQS { DCDC_IRQn }2DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)2DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)2DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)2DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)2DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)2DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)2DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)2DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)2DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)2DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)2DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)2DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)2DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)2DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)2DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)2DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)2DCP_CTRL_PRESENT_SHA_SHIFT (28U)2DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)2DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)2DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)2DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)2DCP_CTRL_CLKGATE_MASK (0x40000000U)2DCP_CTRL_CLKGATE_SHIFT (30U)2DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)2DCP_CTRL_SFTRST_MASK (0x80000000U)2DCP_CTRL_SFTRST_SHIFT (31U)2DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)2DCP_STAT_IRQ_MASK (0xFU)2DCP_STAT_IRQ_SHIFT (0U)2DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)2DCP_STAT_RSVD_IRQ_MASK (0x100U)2DCP_STAT_RSVD_IRQ_SHIFT (8U)2DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)2DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)2DCP_STAT_READY_CHANNELS_SHIFT (16U)2DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)2DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)2DCP_STAT_CUR_CHANNEL_SHIFT (24U)2DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)2DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)2DCP_STAT_OTP_KEY_READY_SHIFT (28U)2DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)2DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)2DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)2DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)2DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)2DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)2DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)2DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)2DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)2DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)2DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)2DCP_CHANNELCTRL_RSVD_SHIFT (17U)2DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)2DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)2DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)2DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)2DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)2DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)2DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)3DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)3DCP_CAPABILITY0_RSVD_SHIFT (12U)3DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)3DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)3DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)3DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)3DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)3DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)3DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)3DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)3DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)3DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)3DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)3DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)3DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)3DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)3DCP_CONTEXT_ADDR_SHIFT (0U)3DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)3DCP_KEY_SUBWORD_MASK (0x3U)3DCP_KEY_SUBWORD_SHIFT (0U)3DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)3DCP_KEY_RSVD_SUBWORD_MASK (0xCU)3DCP_KEY_RSVD_SUBWORD_SHIFT (2U)3DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)3DCP_KEY_INDEX_MASK (0x30U)3DCP_KEY_INDEX_SHIFT (4U)3DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)3DCP_KEY_RSVD_INDEX_MASK (0xC0U)3DCP_KEY_RSVD_INDEX_SHIFT (6U)3DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)3DCP_KEY_RSVD_MASK (0xFFFFFF00U)3DCP_KEY_RSVD_SHIFT (8U)3DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)3DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)3DCP_KEYDATA_DATA_SHIFT (0U)3DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)3DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)3DCP_PACKET0_ADDR_SHIFT (0U)3DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)3DCP_PACKET1_INTERRUPT_MASK (0x1U)3DCP_PACKET1_INTERRUPT_SHIFT (0U)3DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)3DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)3DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)3DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)3DCP_PACKET1_CHAIN_MASK (0x4U)3DCP_PACKET1_CHAIN_SHIFT (2U)3DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)3DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)3DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)3DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)3DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)3DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)3DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)3DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)3DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)3DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)3DCP_PACKET1_ENABLE_HASH_MASK (0x40U)3DCP_PACKET1_ENABLE_HASH_SHIFT (6U)3DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)3DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)3DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)3DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)3DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)3DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)3DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)3DCP_PACKET1_CIPHER_INIT_MASK (0x200U)3DCP_PACKET1_CIPHER_INIT_SHIFT (9U)3DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)3DCP_PACKET1_OTP_KEY_MASK (0x400U)3DCP_PACKET1_OTP_KEY_SHIFT (10U)3DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)3DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)3DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)3DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)3DCP_PACKET1_HASH_INIT_MASK (0x1000U)3DCP_PACKET1_HASH_INIT_SHIFT (12U)3DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)3DCP_PACKET1_HASH_TERM_MASK (0x2000U)3DCP_PACKET1_HASH_TERM_SHIFT (13U)3DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)3DCP_PACKET1_CHECK_HASH_MASK (0x4000U)3DCP_PACKET1_CHECK_HASH_SHIFT (14U)3DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)3DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)3DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)3DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)3DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)3DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)3DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)3DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)3DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)3DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)3DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)3DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)3DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)3DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)3DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)3DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)3DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)3DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)3DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)3DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)3DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)3DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)3DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)3DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)3DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)3DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)3DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)3DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)3DCP_PACKET1_TAG_MASK (0xFF000000U)3DCP_PACKET1_TAG_SHIFT (24U)3DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)4DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)4DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)4DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)4DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)4DCP_PACKET2_CIPHER_MODE_SHIFT (4U)4DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)4DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)4DCP_PACKET2_KEY_SELECT_SHIFT (8U)4DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)4DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)4DCP_PACKET2_HASH_SELECT_SHIFT (16U)4DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)4DCP_PACKET2_RSVD_MASK (0xF00000U)4DCP_PACKET2_RSVD_SHIFT (20U)4DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)4DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)4DCP_PACKET2_CIPHER_CFG_SHIFT (24U)4DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)4DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)4DCP_PACKET3_ADDR_SHIFT (0U)4DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)4DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)4DCP_PACKET4_ADDR_SHIFT (0U)4DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)4DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)4DCP_PACKET5_COUNT_SHIFT (0U)4DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)4DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)4DCP_PACKET6_ADDR_SHIFT (0U)4DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)4DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)4DCP_CH0CMDPTR_ADDR_SHIFT (0U)4DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)4DCP_CH0SEMA_INCREMENT_MASK (0xFFU)4DCP_CH0SEMA_INCREMENT_SHIFT (0U)4DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)4DCP_CH0SEMA_VALUE_MASK (0xFF0000U)4DCP_CH0SEMA_VALUE_SHIFT (16U)4DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)4DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)4DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)4DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)4DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)4DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)4DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)4DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)4DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)4DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)4DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)4DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)4DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)4DCP_CH0STAT_ERROR_SRC_MASK (0x10U)4DCP_CH0STAT_ERROR_SRC_SHIFT (4U)4DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)4DCP_CH0STAT_ERROR_DST_MASK (0x20U)4DCP_CH0STAT_ERROR_DST_SHIFT (5U)4DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)4DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)4DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)4DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)4DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)4DCP_CH0STAT_ERROR_CODE_SHIFT (16U)4DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)4DCP_CH0STAT_TAG_MASK (0xFF000000U)4DCP_CH0STAT_TAG_SHIFT (24U)4DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)4DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)4DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)4DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)4DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)4DCP_CH0OPTS_RSVD_SHIFT (16U)4DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)4DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)4DCP_CH1CMDPTR_ADDR_SHIFT (0U)4DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)4DCP_CH1SEMA_INCREMENT_MASK (0xFFU)4DCP_CH1SEMA_INCREMENT_SHIFT (0U)4DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)4DCP_CH1SEMA_VALUE_MASK (0xFF0000U)4DCP_CH1SEMA_VALUE_SHIFT (16U)4DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)4DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)4DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)4DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)4DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)4DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)4DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)4DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)4DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)4DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)4DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)4DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)4DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)4DCP_CH1STAT_ERROR_SRC_MASK (0x10U)4DCP_CH1STAT_ERROR_SRC_SHIFT (4U)4DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)4DCP_CH1STAT_ERROR_DST_MASK (0x20U)4DCP_CH1STAT_ERROR_DST_SHIFT (5U)4DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)4DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)4DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)4DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)4DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)4DCP_CH1STAT_ERROR_CODE_SHIFT (16U)4DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)4DCP_CH1STAT_TAG_MASK (0xFF000000U)5DCP_CH1STAT_TAG_SHIFT (24U)5DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)5DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)5DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)5DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)5DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)5DCP_CH1OPTS_RSVD_SHIFT (16U)5DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)5DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)5DCP_CH2CMDPTR_ADDR_SHIFT (0U)5DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)5DCP_CH2SEMA_INCREMENT_MASK (0xFFU)5DCP_CH2SEMA_INCREMENT_SHIFT (0U)5DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)5DCP_CH2SEMA_VALUE_MASK (0xFF0000U)5DCP_CH2SEMA_VALUE_SHIFT (16U)5DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)5DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)5DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)5DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)5DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)5DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)5DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)5DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)5DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)5DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)5DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)5DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)5DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)5DCP_CH2STAT_ERROR_SRC_MASK (0x10U)5DCP_CH2STAT_ERROR_SRC_SHIFT (4U)5DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)5DCP_CH2STAT_ERROR_DST_MASK (0x20U)5DCP_CH2STAT_ERROR_DST_SHIFT (5U)5DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)5DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)5DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)5DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)5DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)5DCP_CH2STAT_ERROR_CODE_SHIFT (16U)5DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)5DCP_CH2STAT_TAG_MASK (0xFF000000U)5DCP_CH2STAT_TAG_SHIFT (24U)5DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)5DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)5DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)5DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)5DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)5DCP_CH2OPTS_RSVD_SHIFT (16U)5DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)5DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)5DCP_CH3CMDPTR_ADDR_SHIFT (0U)5DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)5DCP_CH3SEMA_INCREMENT_MASK (0xFFU)5DCP_CH3SEMA_INCREMENT_SHIFT (0U)5DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)5DCP_CH3SEMA_VALUE_MASK (0xFF0000U)5DCP_CH3SEMA_VALUE_SHIFT (16U)5DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)5DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)5DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)5DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)5DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)5DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)5DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)5DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)5DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)5DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)5DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)5DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)5DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)5DCP_CH3STAT_ERROR_SRC_MASK (0x10U)5DCP_CH3STAT_ERROR_SRC_SHIFT (4U)5DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)5DCP_CH3STAT_ERROR_DST_MASK (0x20U)5DCP_CH3STAT_ERROR_DST_SHIFT (5U)5DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)5DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)5DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)5DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)5DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)5DCP_CH3STAT_ERROR_CODE_SHIFT (16U)5DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)5DCP_CH3STAT_TAG_MASK (0xFF000000U)5DCP_CH3STAT_TAG_SHIFT (24U)5DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)5DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)5DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)5DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)5DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)5DCP_CH3OPTS_RSVD_SHIFT (16U)5DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)5DCP_DBGSELECT_INDEX_MASK (0xFFU)5DCP_DBGSELECT_INDEX_SHIFT (0U)5DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)5DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)5DCP_DBGSELECT_RSVD_SHIFT (8U)5DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)5DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)5DCP_DBGDATA_DATA_SHIFT (0U)5DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)5DCP_PAGETABLE_ENABLE_MASK (0x1U)5DCP_PAGETABLE_ENABLE_SHIFT (0U)5DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)6DCP_PAGETABLE_FLUSH_MASK (0x2U)6DCP_PAGETABLE_FLUSH_SHIFT (1U)6DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)6DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)6DCP_PAGETABLE_BASE_SHIFT (2U)6DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)6DCP_VERSION_STEP_MASK (0xFFFFU)6DCP_VERSION_STEP_SHIFT (0U)6DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)6DCP_VERSION_MINOR_MASK (0xFF0000U)6DCP_VERSION_MINOR_SHIFT (16U)6DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)6DCP_VERSION_MAJOR_MASK (0xFF000000U)6DCP_VERSION_MAJOR_SHIFT (24U)6DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)6DCP_BASE (0x402FC000u)6DCP ((DCP_Type *)DCP_BASE)6DCP_BASE_ADDRS { DCP_BASE }6DCP_BASE_PTRS { DCP }6DCP_IRQS { DCP_IRQn }6DCP_VMI_IRQS { DCP_VMI_IRQn }7DMA_CR_EDBG_MASK (0x2U)7DMA_CR_EDBG_SHIFT (1U)7DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)7DMA_CR_ERCA_MASK (0x4U)7DMA_CR_ERCA_SHIFT (2U)7DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)7DMA_CR_ERGA_MASK (0x8U)7DMA_CR_ERGA_SHIFT (3U)7DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)7DMA_CR_HOE_MASK (0x10U)7DMA_CR_HOE_SHIFT (4U)7DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)7DMA_CR_HALT_MASK (0x20U)7DMA_CR_HALT_SHIFT (5U)7DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)7DMA_CR_CLM_MASK (0x40U)7DMA_CR_CLM_SHIFT (6U)7DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)7DMA_CR_EMLM_MASK (0x80U)7DMA_CR_EMLM_SHIFT (7U)7DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)7DMA_CR_GRP0PRI_MASK (0x100U)7DMA_CR_GRP0PRI_SHIFT (8U)7DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)7DMA_CR_GRP1PRI_MASK (0x400U)7DMA_CR_GRP1PRI_SHIFT (10U)7DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)7DMA_CR_ECX_MASK (0x10000U)7DMA_CR_ECX_SHIFT (16U)7DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)7DMA_CR_CX_MASK (0x20000U)7DMA_CR_CX_SHIFT (17U)7DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)7DMA_CR_ACTIVE_MASK (0x80000000U)7DMA_CR_ACTIVE_SHIFT (31U)7DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)7DMA_ES_DBE_MASK (0x1U)7DMA_ES_DBE_SHIFT (0U)7DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)7DMA_ES_SBE_MASK (0x2U)7DMA_ES_SBE_SHIFT (1U)7DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)7DMA_ES_SGE_MASK (0x4U)7DMA_ES_SGE_SHIFT (2U)7DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)7DMA_ES_NCE_MASK (0x8U)7DMA_ES_NCE_SHIFT (3U)7DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)7DMA_ES_DOE_MASK (0x10U)7DMA_ES_DOE_SHIFT (4U)7DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)7DMA_ES_DAE_MASK (0x20U)7DMA_ES_DAE_SHIFT (5U)7DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)7DMA_ES_SOE_MASK (0x40U)7DMA_ES_SOE_SHIFT (6U)7DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)7DMA_ES_SAE_MASK (0x80U)7DMA_ES_SAE_SHIFT (7U)7DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)7DMA_ES_ERRCHN_MASK (0x1F00U)7DMA_ES_ERRCHN_SHIFT (8U)7DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)7DMA_ES_CPE_MASK (0x4000U)7DMA_ES_CPE_SHIFT (14U)7DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)7DMA_ES_GPE_MASK (0x8000U)7DMA_ES_GPE_SHIFT (15U)7DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)7DMA_ES_ECX_MASK (0x10000U)7DMA_ES_ECX_SHIFT (16U)7DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)7DMA_ES_VLD_MASK (0x80000000U)7DMA_ES_VLD_SHIFT (31U)7DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)7DMA_ERQ_ERQ0_MASK (0x1U)7DMA_ERQ_ERQ0_SHIFT (0U)7DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)7DMA_ERQ_ERQ1_MASK (0x2U)7DMA_ERQ_ERQ1_SHIFT (1U)7DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)7DMA_ERQ_ERQ2_MASK (0x4U)7DMA_ERQ_ERQ2_SHIFT (2U)7DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)7DMA_ERQ_ERQ3_MASK (0x8U)7DMA_ERQ_ERQ3_SHIFT (3U)7DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)7DMA_ERQ_ERQ4_MASK (0x10U)7DMA_ERQ_ERQ4_SHIFT (4U)7DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)7DMA_ERQ_ERQ5_MASK (0x20U)7DMA_ERQ_ERQ5_SHIFT (5U)7DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)7DMA_ERQ_ERQ6_MASK (0x40U)7DMA_ERQ_ERQ6_SHIFT (6U)7DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)7DMA_ERQ_ERQ7_MASK (0x80U)7DMA_ERQ_ERQ7_SHIFT (7U)7DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)7DMA_ERQ_ERQ8_MASK (0x100U)7DMA_ERQ_ERQ8_SHIFT (8U)7DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)7DMA_ERQ_ERQ9_MASK (0x200U)7DMA_ERQ_ERQ9_SHIFT (9U)7DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)7DMA_ERQ_ERQ10_MASK (0x400U)7DMA_ERQ_ERQ10_SHIFT (10U)7DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)8DMA_ERQ_ERQ11_MASK (0x800U)8DMA_ERQ_ERQ11_SHIFT (11U)8DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)8DMA_ERQ_ERQ12_MASK (0x1000U)8DMA_ERQ_ERQ12_SHIFT (12U)8DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)8DMA_ERQ_ERQ13_MASK (0x2000U)8DMA_ERQ_ERQ13_SHIFT (13U)8DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)8DMA_ERQ_ERQ14_MASK (0x4000U)8DMA_ERQ_ERQ14_SHIFT (14U)8DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)8DMA_ERQ_ERQ15_MASK (0x8000U)8DMA_ERQ_ERQ15_SHIFT (15U)8DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)8DMA_ERQ_ERQ16_MASK (0x10000U)8DMA_ERQ_ERQ16_SHIFT (16U)8DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)8DMA_ERQ_ERQ17_MASK (0x20000U)8DMA_ERQ_ERQ17_SHIFT (17U)8DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)8DMA_ERQ_ERQ18_MASK (0x40000U)8DMA_ERQ_ERQ18_SHIFT (18U)8DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)8DMA_ERQ_ERQ19_MASK (0x80000U)8DMA_ERQ_ERQ19_SHIFT (19U)8DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)8DMA_ERQ_ERQ20_MASK (0x100000U)8DMA_ERQ_ERQ20_SHIFT (20U)8DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)8DMA_ERQ_ERQ21_MASK (0x200000U)8DMA_ERQ_ERQ21_SHIFT (21U)8DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)8DMA_ERQ_ERQ22_MASK (0x400000U)8DMA_ERQ_ERQ22_SHIFT (22U)8DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)8DMA_ERQ_ERQ23_MASK (0x800000U)8DMA_ERQ_ERQ23_SHIFT (23U)8DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)8DMA_ERQ_ERQ24_MASK (0x1000000U)8DMA_ERQ_ERQ24_SHIFT (24U)8DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)8DMA_ERQ_ERQ25_MASK (0x2000000U)8DMA_ERQ_ERQ25_SHIFT (25U)8DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)8DMA_ERQ_ERQ26_MASK (0x4000000U)8DMA_ERQ_ERQ26_SHIFT (26U)8DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)8DMA_ERQ_ERQ27_MASK (0x8000000U)8DMA_ERQ_ERQ27_SHIFT (27U)8DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)8DMA_ERQ_ERQ28_MASK (0x10000000U)8DMA_ERQ_ERQ28_SHIFT (28U)8DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)8DMA_ERQ_ERQ29_MASK (0x20000000U)8DMA_ERQ_ERQ29_SHIFT (29U)8DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)8DMA_ERQ_ERQ30_MASK (0x40000000U)8DMA_ERQ_ERQ30_SHIFT (30U)8DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)8DMA_ERQ_ERQ31_MASK (0x80000000U)8DMA_ERQ_ERQ31_SHIFT (31U)8DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)8DMA_EEI_EEI0_MASK (0x1U)8DMA_EEI_EEI0_SHIFT (0U)8DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)8DMA_EEI_EEI1_MASK (0x2U)8DMA_EEI_EEI1_SHIFT (1U)8DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)8DMA_EEI_EEI2_MASK (0x4U)8DMA_EEI_EEI2_SHIFT (2U)8DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)8DMA_EEI_EEI3_MASK (0x8U)8DMA_EEI_EEI3_SHIFT (3U)8DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)8DMA_EEI_EEI4_MASK (0x10U)8DMA_EEI_EEI4_SHIFT (4U)8DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)8DMA_EEI_EEI5_MASK (0x20U)8DMA_EEI_EEI5_SHIFT (5U)8DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)8DMA_EEI_EEI6_MASK (0x40U)8DMA_EEI_EEI6_SHIFT (6U)8DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)8DMA_EEI_EEI7_MASK (0x80U)8DMA_EEI_EEI7_SHIFT (7U)8DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)8DMA_EEI_EEI8_MASK (0x100U)8DMA_EEI_EEI8_SHIFT (8U)8DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)8DMA_EEI_EEI9_MASK (0x200U)8DMA_EEI_EEI9_SHIFT (9U)8DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)8DMA_EEI_EEI10_MASK (0x400U)8DMA_EEI_EEI10_SHIFT (10U)8DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)8DMA_EEI_EEI11_MASK (0x800U)8DMA_EEI_EEI11_SHIFT (11U)8DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)8DMA_EEI_EEI12_MASK (0x1000U)8DMA_EEI_EEI12_SHIFT (12U)8DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)8DMA_EEI_EEI13_MASK (0x2000U)8DMA_EEI_EEI13_SHIFT (13U)8DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)8DMA_EEI_EEI14_MASK (0x4000U)8DMA_EEI_EEI14_SHIFT (14U)8DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)8DMA_EEI_EEI15_MASK (0x8000U)8DMA_EEI_EEI15_SHIFT (15U)8DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)8DMA_EEI_EEI16_MASK (0x10000U)8DMA_EEI_EEI16_SHIFT (16U)8DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)8DMA_EEI_EEI17_MASK (0x20000U)8DMA_EEI_EEI17_SHIFT (17U)8DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)8DMA_EEI_EEI18_MASK (0x40000U)8DMA_EEI_EEI18_SHIFT (18U)8DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)8DMA_EEI_EEI19_MASK (0x80000U)8DMA_EEI_EEI19_SHIFT (19U)8DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)8DMA_EEI_EEI20_MASK (0x100000U)8DMA_EEI_EEI20_SHIFT (20U)8DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)9DMA_EEI_EEI21_MASK (0x200000U)9DMA_EEI_EEI21_SHIFT (21U)9DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)9DMA_EEI_EEI22_MASK (0x400000U)9DMA_EEI_EEI22_SHIFT (22U)9DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)9DMA_EEI_EEI23_MASK (0x800000U)9DMA_EEI_EEI23_SHIFT (23U)9DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)9DMA_EEI_EEI24_MASK (0x1000000U)9DMA_EEI_EEI24_SHIFT (24U)9DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)9DMA_EEI_EEI25_MASK (0x2000000U)9DMA_EEI_EEI25_SHIFT (25U)9DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)9DMA_EEI_EEI26_MASK (0x4000000U)9DMA_EEI_EEI26_SHIFT (26U)9DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)9DMA_EEI_EEI27_MASK (0x8000000U)9DMA_EEI_EEI27_SHIFT (27U)9DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)9DMA_EEI_EEI28_MASK (0x10000000U)9DMA_EEI_EEI28_SHIFT (28U)9DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)9DMA_EEI_EEI29_MASK (0x20000000U)9DMA_EEI_EEI29_SHIFT (29U)9DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)9DMA_EEI_EEI30_MASK (0x40000000U)9DMA_EEI_EEI30_SHIFT (30U)9DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)9DMA_EEI_EEI31_MASK (0x80000000U)9DMA_EEI_EEI31_SHIFT (31U)9DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)9DMA_CEEI_CEEI_MASK (0x1FU)9DMA_CEEI_CEEI_SHIFT (0U)9DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)9DMA_CEEI_CAEE_MASK (0x40U)9DMA_CEEI_CAEE_SHIFT (6U)9DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)9DMA_CEEI_NOP_MASK (0x80U)9DMA_CEEI_NOP_SHIFT (7U)9DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)9DMA_SEEI_SEEI_MASK (0x1FU)9DMA_SEEI_SEEI_SHIFT (0U)9DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)9DMA_SEEI_SAEE_MASK (0x40U)9DMA_SEEI_SAEE_SHIFT (6U)9DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)9DMA_SEEI_NOP_MASK (0x80U)9DMA_SEEI_NOP_SHIFT (7U)9DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)9DMA_CERQ_CERQ_MASK (0x1FU)9DMA_CERQ_CERQ_SHIFT (0U)9DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)9DMA_CERQ_CAER_MASK (0x40U)9DMA_CERQ_CAER_SHIFT (6U)9DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)9DMA_CERQ_NOP_MASK (0x80U)9DMA_CERQ_NOP_SHIFT (7U)9DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)9DMA_SERQ_SERQ_MASK (0x1FU)9DMA_SERQ_SERQ_SHIFT (0U)9DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)9DMA_SERQ_SAER_MASK (0x40U)9DMA_SERQ_SAER_SHIFT (6U)9DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)9DMA_SERQ_NOP_MASK (0x80U)9DMA_SERQ_NOP_SHIFT (7U)9DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)9DMA_CDNE_CDNE_MASK (0x1FU)9DMA_CDNE_CDNE_SHIFT (0U)9DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)9DMA_CDNE_CADN_MASK (0x40U)9DMA_CDNE_CADN_SHIFT (6U)9DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)9DMA_CDNE_NOP_MASK (0x80U)9DMA_CDNE_NOP_SHIFT (7U)9DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)9DMA_SSRT_SSRT_MASK (0x1FU)9DMA_SSRT_SSRT_SHIFT (0U)9DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)9DMA_SSRT_SAST_MASK (0x40U)9DMA_SSRT_SAST_SHIFT (6U)9DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)9DMA_SSRT_NOP_MASK (0x80U)9DMA_SSRT_NOP_SHIFT (7U)9DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)9DMA_CERR_CERR_MASK (0x1FU)9DMA_CERR_CERR_SHIFT (0U)9DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)9DMA_CERR_CAEI_MASK (0x40U)9DMA_CERR_CAEI_SHIFT (6U)9DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)9DMA_CERR_NOP_MASK (0x80U)9DMA_CERR_NOP_SHIFT (7U)9DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)9DMA_CINT_CINT_MASK (0x1FU)9DMA_CINT_CINT_SHIFT (0U)9DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)9DMA_CINT_CAIR_MASK (0x40U)9DMA_CINT_CAIR_SHIFT (6U)9DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)9DMA_CINT_NOP_MASK (0x80U)9DMA_CINT_NOP_SHIFT (7U)9DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)9DMA_INT_INT0_MASK (0x1U)9DMA_INT_INT0_SHIFT (0U)9DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)9DMA_INT_INT1_MASK (0x2U)9DMA_INT_INT1_SHIFT (1U):DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK):DMA_INT_INT2_MASK (0x4U):DMA_INT_INT2_SHIFT (2U):DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK):DMA_INT_INT3_MASK (0x8U):DMA_INT_INT3_SHIFT (3U):DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK):DMA_INT_INT4_MASK (0x10U):DMA_INT_INT4_SHIFT (4U):DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK):DMA_INT_INT5_MASK (0x20U):DMA_INT_INT5_SHIFT (5U):DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK):DMA_INT_INT6_MASK (0x40U):DMA_INT_INT6_SHIFT (6U):DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK):DMA_INT_INT7_MASK (0x80U):DMA_INT_INT7_SHIFT (7U):DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK):DMA_INT_INT8_MASK (0x100U):DMA_INT_INT8_SHIFT (8U):DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK):DMA_INT_INT9_MASK (0x200U):DMA_INT_INT9_SHIFT (9U):DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK):DMA_INT_INT10_MASK (0x400U):DMA_INT_INT10_SHIFT (10U):DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK):DMA_INT_INT11_MASK (0x800U):DMA_INT_INT11_SHIFT (11U):DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK):DMA_INT_INT12_MASK (0x1000U):DMA_INT_INT12_SHIFT (12U):DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK):DMA_INT_INT13_MASK (0x2000U):DMA_INT_INT13_SHIFT (13U):DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK):DMA_INT_INT14_MASK (0x4000U):DMA_INT_INT14_SHIFT (14U):DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK):DMA_INT_INT15_MASK (0x8000U):DMA_INT_INT15_SHIFT (15U):DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK):DMA_INT_INT16_MASK (0x10000U):DMA_INT_INT16_SHIFT (16U):DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK):DMA_INT_INT17_MASK (0x20000U):DMA_INT_INT17_SHIFT (17U):DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK):DMA_INT_INT18_MASK (0x40000U):DMA_INT_INT18_SHIFT (18U):DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK):DMA_INT_INT19_MASK (0x80000U):DMA_INT_INT19_SHIFT (19U):DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK):DMA_INT_INT20_MASK (0x100000U):DMA_INT_INT20_SHIFT (20U):DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK):DMA_INT_INT21_MASK (0x200000U):DMA_INT_INT21_SHIFT (21U):DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK):DMA_INT_INT22_MASK (0x400000U):DMA_INT_INT22_SHIFT (22U):DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK):DMA_INT_INT23_MASK (0x800000U):DMA_INT_INT23_SHIFT (23U):DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK):DMA_INT_INT24_MASK (0x1000000U):DMA_INT_INT24_SHIFT (24U):DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK):DMA_INT_INT25_MASK (0x2000000U):DMA_INT_INT25_SHIFT (25U):DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK):DMA_INT_INT26_MASK (0x4000000U):DMA_INT_INT26_SHIFT (26U):DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK):DMA_INT_INT27_MASK (0x8000000U):DMA_INT_INT27_SHIFT (27U):DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK):DMA_INT_INT28_MASK (0x10000000U):DMA_INT_INT28_SHIFT (28U):DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK):DMA_INT_INT29_MASK (0x20000000U):DMA_INT_INT29_SHIFT (29U):DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK):DMA_INT_INT30_MASK (0x40000000U):DMA_INT_INT30_SHIFT (30U):DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK):DMA_INT_INT31_MASK (0x80000000U):DMA_INT_INT31_SHIFT (31U):DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK):DMA_ERR_ERR0_MASK (0x1U):DMA_ERR_ERR0_SHIFT (0U):DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK):DMA_ERR_ERR1_MASK (0x2U):DMA_ERR_ERR1_SHIFT (1U):DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK):DMA_ERR_ERR2_MASK (0x4U):DMA_ERR_ERR2_SHIFT (2U):DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK):DMA_ERR_ERR3_MASK (0x8U):DMA_ERR_ERR3_SHIFT (3U):DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK):DMA_ERR_ERR4_MASK (0x10U):DMA_ERR_ERR4_SHIFT (4U):DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK):DMA_ERR_ERR5_MASK (0x20U):DMA_ERR_ERR5_SHIFT (5U):DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK):DMA_ERR_ERR6_MASK (0x40U):DMA_ERR_ERR6_SHIFT (6U):DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK):DMA_ERR_ERR7_MASK (0x80U):DMA_ERR_ERR7_SHIFT (7U):DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK):DMA_ERR_ERR8_MASK (0x100U):DMA_ERR_ERR8_SHIFT (8U):DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK):DMA_ERR_ERR9_MASK (0x200U):DMA_ERR_ERR9_SHIFT (9U):DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK):DMA_ERR_ERR10_MASK (0x400U):DMA_ERR_ERR10_SHIFT (10U):DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK):DMA_ERR_ERR11_MASK (0x800U):DMA_ERR_ERR11_SHIFT (11U);DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK);DMA_ERR_ERR12_MASK (0x1000U);DMA_ERR_ERR12_SHIFT (12U);DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK);DMA_ERR_ERR13_MASK (0x2000U);DMA_ERR_ERR13_SHIFT (13U);DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK);DMA_ERR_ERR14_MASK (0x4000U);DMA_ERR_ERR14_SHIFT (14U);DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK);DMA_ERR_ERR15_MASK (0x8000U);DMA_ERR_ERR15_SHIFT (15U);DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK);DMA_ERR_ERR16_MASK (0x10000U);DMA_ERR_ERR16_SHIFT (16U);DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK);DMA_ERR_ERR17_MASK (0x20000U);DMA_ERR_ERR17_SHIFT (17U);DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK);DMA_ERR_ERR18_MASK (0x40000U);DMA_ERR_ERR18_SHIFT (18U);DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK);DMA_ERR_ERR19_MASK (0x80000U);DMA_ERR_ERR19_SHIFT (19U);DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK);DMA_ERR_ERR20_MASK (0x100000U);DMA_ERR_ERR20_SHIFT (20U);DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK);DMA_ERR_ERR21_MASK (0x200000U);DMA_ERR_ERR21_SHIFT (21U);DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK);DMA_ERR_ERR22_MASK (0x400000U);DMA_ERR_ERR22_SHIFT (22U);DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK);DMA_ERR_ERR23_MASK (0x800000U);DMA_ERR_ERR23_SHIFT (23U);DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK);DMA_ERR_ERR24_MASK (0x1000000U);DMA_ERR_ERR24_SHIFT (24U);DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK);DMA_ERR_ERR25_MASK (0x2000000U);DMA_ERR_ERR25_SHIFT (25U);DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK);DMA_ERR_ERR26_MASK (0x4000000U);DMA_ERR_ERR26_SHIFT (26U);DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK);DMA_ERR_ERR27_MASK (0x8000000U);DMA_ERR_ERR27_SHIFT (27U);DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK);DMA_ERR_ERR28_MASK (0x10000000U);DMA_ERR_ERR28_SHIFT (28U);DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK);DMA_ERR_ERR29_MASK (0x20000000U);DMA_ERR_ERR29_SHIFT (29U);DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK);DMA_ERR_ERR30_MASK (0x40000000U);DMA_ERR_ERR30_SHIFT (30U);DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK);DMA_ERR_ERR31_MASK (0x80000000U);DMA_ERR_ERR31_SHIFT (31U);DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK);DMA_HRS_HRS0_MASK (0x1U);DMA_HRS_HRS0_SHIFT (0U);DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK);DMA_HRS_HRS1_MASK (0x2U);DMA_HRS_HRS1_SHIFT (1U);DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK);DMA_HRS_HRS2_MASK (0x4U);DMA_HRS_HRS2_SHIFT (2U);DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK);DMA_HRS_HRS3_MASK (0x8U);DMA_HRS_HRS3_SHIFT (3U);DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK);DMA_HRS_HRS4_MASK (0x10U);DMA_HRS_HRS4_SHIFT (4U);DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK);DMA_HRS_HRS5_MASK (0x20U);DMA_HRS_HRS5_SHIFT (5U);DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK);DMA_HRS_HRS6_MASK (0x40U);DMA_HRS_HRS6_SHIFT (6U);DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK);DMA_HRS_HRS7_MASK (0x80U);DMA_HRS_HRS7_SHIFT (7U);DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK);DMA_HRS_HRS8_MASK (0x100U);DMA_HRS_HRS8_SHIFT (8U);DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK);DMA_HRS_HRS9_MASK (0x200U);DMA_HRS_HRS9_SHIFT (9U);DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK);DMA_HRS_HRS10_MASK (0x400U);DMA_HRS_HRS10_SHIFT (10U);DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK);DMA_HRS_HRS11_MASK (0x800U);DMA_HRS_HRS11_SHIFT (11U);DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK);DMA_HRS_HRS12_MASK (0x1000U);DMA_HRS_HRS12_SHIFT (12U);DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK);DMA_HRS_HRS13_MASK (0x2000U);DMA_HRS_HRS13_SHIFT (13U);DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK);DMA_HRS_HRS14_MASK (0x4000U);DMA_HRS_HRS14_SHIFT (14U);DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK);DMA_HRS_HRS15_MASK (0x8000U);DMA_HRS_HRS15_SHIFT (15U);DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK);DMA_HRS_HRS16_MASK (0x10000U);DMA_HRS_HRS16_SHIFT (16U);DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK);DMA_HRS_HRS17_MASK (0x20000U);DMA_HRS_HRS17_SHIFT (17U);DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK);DMA_HRS_HRS18_MASK (0x40000U);DMA_HRS_HRS18_SHIFT (18U);DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK);DMA_HRS_HRS19_MASK (0x80000U);DMA_HRS_HRS19_SHIFT (19U);DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK);DMA_HRS_HRS20_MASK (0x100000U);DMA_HRS_HRS20_SHIFT (20U);DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK);DMA_HRS_HRS21_MASK (0x200000U);DMA_HRS_HRS21_SHIFT (21U)DMA_DCHPRI10_CHPRI_MASK (0xFU)>DMA_DCHPRI10_CHPRI_SHIFT (0U)>DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)>DMA_DCHPRI10_GRPPRI_MASK (0x30U)>DMA_DCHPRI10_GRPPRI_SHIFT (4U)>DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)>DMA_DCHPRI10_DPA_MASK (0x40U)>DMA_DCHPRI10_DPA_SHIFT (6U)>DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)>DMA_DCHPRI10_ECP_MASK (0x80U)>DMA_DCHPRI10_ECP_SHIFT (7U)>DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)>DMA_DCHPRI9_CHPRI_MASK (0xFU)>DMA_DCHPRI9_CHPRI_SHIFT (0U)>DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)>DMA_DCHPRI9_GRPPRI_MASK (0x30U)>DMA_DCHPRI9_GRPPRI_SHIFT (4U)>DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)>DMA_DCHPRI9_DPA_MASK (0x40U)>DMA_DCHPRI9_DPA_SHIFT (6U)>DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)>DMA_DCHPRI9_ECP_MASK (0x80U)>DMA_DCHPRI9_ECP_SHIFT (7U)>DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)>DMA_DCHPRI8_CHPRI_MASK (0xFU)>DMA_DCHPRI8_CHPRI_SHIFT (0U)>DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)>DMA_DCHPRI8_GRPPRI_MASK (0x30U)>DMA_DCHPRI8_GRPPRI_SHIFT (4U)>DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)>DMA_DCHPRI8_DPA_MASK (0x40U)>DMA_DCHPRI8_DPA_SHIFT (6U)>DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)>DMA_DCHPRI8_ECP_MASK (0x80U)>DMA_DCHPRI8_ECP_SHIFT (7U)>DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)>DMA_DCHPRI15_CHPRI_MASK (0xFU)>DMA_DCHPRI15_CHPRI_SHIFT (0U)>DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)>DMA_DCHPRI15_GRPPRI_MASK (0x30U)>DMA_DCHPRI15_GRPPRI_SHIFT (4U)>DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)>DMA_DCHPRI15_DPA_MASK (0x40U)>DMA_DCHPRI15_DPA_SHIFT (6U)>DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)>DMA_DCHPRI15_ECP_MASK (0x80U)>DMA_DCHPRI15_ECP_SHIFT (7U)>DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)>DMA_DCHPRI14_CHPRI_MASK (0xFU)>DMA_DCHPRI14_CHPRI_SHIFT (0U)>DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)>DMA_DCHPRI14_GRPPRI_MASK (0x30U)>DMA_DCHPRI14_GRPPRI_SHIFT (4U)>DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)>DMA_DCHPRI14_DPA_MASK (0x40U)>DMA_DCHPRI14_DPA_SHIFT (6U)>DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)>DMA_DCHPRI14_ECP_MASK (0x80U)>DMA_DCHPRI14_ECP_SHIFT (7U)>DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)>DMA_DCHPRI13_CHPRI_MASK (0xFU)>DMA_DCHPRI13_CHPRI_SHIFT (0U)>DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)>DMA_DCHPRI13_GRPPRI_MASK (0x30U)>DMA_DCHPRI13_GRPPRI_SHIFT (4U)>DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)>DMA_DCHPRI13_DPA_MASK (0x40U)>DMA_DCHPRI13_DPA_SHIFT (6U)>DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)>DMA_DCHPRI13_ECP_MASK (0x80U)>DMA_DCHPRI13_ECP_SHIFT (7U)>DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)>DMA_DCHPRI12_CHPRI_MASK (0xFU)>DMA_DCHPRI12_CHPRI_SHIFT (0U)>DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)>DMA_DCHPRI12_GRPPRI_MASK (0x30U)>DMA_DCHPRI12_GRPPRI_SHIFT (4U)>DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)>DMA_DCHPRI12_DPA_MASK (0x40U)>DMA_DCHPRI12_DPA_SHIFT (6U)>DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)>DMA_DCHPRI12_ECP_MASK (0x80U)>DMA_DCHPRI12_ECP_SHIFT (7U)>DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)>DMA_DCHPRI19_CHPRI_MASK (0xFU)>DMA_DCHPRI19_CHPRI_SHIFT (0U)>DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)>DMA_DCHPRI19_GRPPRI_MASK (0x30U)>DMA_DCHPRI19_GRPPRI_SHIFT (4U)>DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)>DMA_DCHPRI19_DPA_MASK (0x40U)>DMA_DCHPRI19_DPA_SHIFT (6U)>DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)>DMA_DCHPRI19_ECP_MASK (0x80U)>DMA_DCHPRI19_ECP_SHIFT (7U)>DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)>DMA_DCHPRI18_CHPRI_MASK (0xFU)>DMA_DCHPRI18_CHPRI_SHIFT (0U)>DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)>DMA_DCHPRI18_GRPPRI_MASK (0x30U)>DMA_DCHPRI18_GRPPRI_SHIFT (4U)>DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)>DMA_DCHPRI18_DPA_MASK (0x40U)>DMA_DCHPRI18_DPA_SHIFT (6U)>DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)>DMA_DCHPRI18_ECP_MASK (0x80U)>DMA_DCHPRI18_ECP_SHIFT (7U)>DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)>DMA_DCHPRI17_CHPRI_MASK (0xFU)?DMA_DCHPRI17_CHPRI_SHIFT (0U)?DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)?DMA_DCHPRI17_GRPPRI_MASK (0x30U)?DMA_DCHPRI17_GRPPRI_SHIFT (4U)?DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)?DMA_DCHPRI17_DPA_MASK (0x40U)?DMA_DCHPRI17_DPA_SHIFT (6U)?DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)?DMA_DCHPRI17_ECP_MASK (0x80U)?DMA_DCHPRI17_ECP_SHIFT (7U)?DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)?DMA_DCHPRI16_CHPRI_MASK (0xFU)?DMA_DCHPRI16_CHPRI_SHIFT (0U)?DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)?DMA_DCHPRI16_GRPPRI_MASK (0x30U)?DMA_DCHPRI16_GRPPRI_SHIFT (4U)?DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)?DMA_DCHPRI16_DPA_MASK (0x40U)?DMA_DCHPRI16_DPA_SHIFT (6U)?DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)?DMA_DCHPRI16_ECP_MASK (0x80U)?DMA_DCHPRI16_ECP_SHIFT (7U)?DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)?DMA_DCHPRI23_CHPRI_MASK (0xFU)?DMA_DCHPRI23_CHPRI_SHIFT (0U)?DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)?DMA_DCHPRI23_GRPPRI_MASK (0x30U)?DMA_DCHPRI23_GRPPRI_SHIFT (4U)?DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)?DMA_DCHPRI23_DPA_MASK (0x40U)?DMA_DCHPRI23_DPA_SHIFT (6U)?DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)?DMA_DCHPRI23_ECP_MASK (0x80U)?DMA_DCHPRI23_ECP_SHIFT (7U)?DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)?DMA_DCHPRI22_CHPRI_MASK (0xFU)?DMA_DCHPRI22_CHPRI_SHIFT (0U)?DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)?DMA_DCHPRI22_GRPPRI_MASK (0x30U)?DMA_DCHPRI22_GRPPRI_SHIFT (4U)?DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)?DMA_DCHPRI22_DPA_MASK (0x40U)?DMA_DCHPRI22_DPA_SHIFT (6U)?DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)?DMA_DCHPRI22_ECP_MASK (0x80U)?DMA_DCHPRI22_ECP_SHIFT (7U)?DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)?DMA_DCHPRI21_CHPRI_MASK (0xFU)?DMA_DCHPRI21_CHPRI_SHIFT (0U)?DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)?DMA_DCHPRI21_GRPPRI_MASK (0x30U)?DMA_DCHPRI21_GRPPRI_SHIFT (4U)?DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)?DMA_DCHPRI21_DPA_MASK (0x40U)?DMA_DCHPRI21_DPA_SHIFT (6U)?DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)?DMA_DCHPRI21_ECP_MASK (0x80U)?DMA_DCHPRI21_ECP_SHIFT (7U)?DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)?DMA_DCHPRI20_CHPRI_MASK (0xFU)?DMA_DCHPRI20_CHPRI_SHIFT (0U)?DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)?DMA_DCHPRI20_GRPPRI_MASK (0x30U)?DMA_DCHPRI20_GRPPRI_SHIFT (4U)?DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)?DMA_DCHPRI20_DPA_MASK (0x40U)?DMA_DCHPRI20_DPA_SHIFT (6U)?DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)?DMA_DCHPRI20_ECP_MASK (0x80U)?DMA_DCHPRI20_ECP_SHIFT (7U)?DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)?DMA_DCHPRI27_CHPRI_MASK (0xFU)?DMA_DCHPRI27_CHPRI_SHIFT (0U)?DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)?DMA_DCHPRI27_GRPPRI_MASK (0x30U)?DMA_DCHPRI27_GRPPRI_SHIFT (4U)?DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)?DMA_DCHPRI27_DPA_MASK (0x40U)?DMA_DCHPRI27_DPA_SHIFT (6U)?DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)?DMA_DCHPRI27_ECP_MASK (0x80U)?DMA_DCHPRI27_ECP_SHIFT (7U)?DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)?DMA_DCHPRI26_CHPRI_MASK (0xFU)?DMA_DCHPRI26_CHPRI_SHIFT (0U)?DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)?DMA_DCHPRI26_GRPPRI_MASK (0x30U)?DMA_DCHPRI26_GRPPRI_SHIFT (4U)?DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)?DMA_DCHPRI26_DPA_MASK (0x40U)?DMA_DCHPRI26_DPA_SHIFT (6U)?DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)?DMA_DCHPRI26_ECP_MASK (0x80U)?DMA_DCHPRI26_ECP_SHIFT (7U)?DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)?DMA_DCHPRI25_CHPRI_MASK (0xFU)?DMA_DCHPRI25_CHPRI_SHIFT (0U)?DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)?DMA_DCHPRI25_GRPPRI_MASK (0x30U)?DMA_DCHPRI25_GRPPRI_SHIFT (4U)?DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)?DMA_DCHPRI25_DPA_MASK (0x40U)?DMA_DCHPRI25_DPA_SHIFT (6U)?DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)?DMA_DCHPRI25_ECP_MASK (0x80U)?DMA_DCHPRI25_ECP_SHIFT (7U)?DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)?DMA_DCHPRI24_CHPRI_MASK (0xFU)?DMA_DCHPRI24_CHPRI_SHIFT (0U)?DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)@DMA_DCHPRI24_GRPPRI_MASK (0x30U)@DMA_DCHPRI24_GRPPRI_SHIFT (4U)@DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)@DMA_DCHPRI24_DPA_MASK (0x40U)@DMA_DCHPRI24_DPA_SHIFT (6U)@DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)@DMA_DCHPRI24_ECP_MASK (0x80U)@DMA_DCHPRI24_ECP_SHIFT (7U)@DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)@DMA_DCHPRI31_CHPRI_MASK (0xFU)@DMA_DCHPRI31_CHPRI_SHIFT (0U)@DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)@DMA_DCHPRI31_GRPPRI_MASK (0x30U)@DMA_DCHPRI31_GRPPRI_SHIFT (4U)@DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)@DMA_DCHPRI31_DPA_MASK (0x40U)@DMA_DCHPRI31_DPA_SHIFT (6U)@DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)@DMA_DCHPRI31_ECP_MASK (0x80U)@DMA_DCHPRI31_ECP_SHIFT (7U)@DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)@DMA_DCHPRI30_CHPRI_MASK (0xFU)@DMA_DCHPRI30_CHPRI_SHIFT (0U)@DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)@DMA_DCHPRI30_GRPPRI_MASK (0x30U)@DMA_DCHPRI30_GRPPRI_SHIFT (4U)@DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)@DMA_DCHPRI30_DPA_MASK (0x40U)@DMA_DCHPRI30_DPA_SHIFT (6U)@DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)@DMA_DCHPRI30_ECP_MASK (0x80U)@DMA_DCHPRI30_ECP_SHIFT (7U)@DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)@DMA_DCHPRI29_CHPRI_MASK (0xFU)@DMA_DCHPRI29_CHPRI_SHIFT (0U)@DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)@DMA_DCHPRI29_GRPPRI_MASK (0x30U)@DMA_DCHPRI29_GRPPRI_SHIFT (4U)@DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)@DMA_DCHPRI29_DPA_MASK (0x40U)@DMA_DCHPRI29_DPA_SHIFT (6U)@DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)@DMA_DCHPRI29_ECP_MASK (0x80U)@DMA_DCHPRI29_ECP_SHIFT (7U)@DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)@DMA_DCHPRI28_CHPRI_MASK (0xFU)@DMA_DCHPRI28_CHPRI_SHIFT (0U)@DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)@DMA_DCHPRI28_GRPPRI_MASK (0x30U)@DMA_DCHPRI28_GRPPRI_SHIFT (4U)@DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)@DMA_DCHPRI28_DPA_MASK (0x40U)@DMA_DCHPRI28_DPA_SHIFT (6U)@DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)@DMA_DCHPRI28_ECP_MASK (0x80U)@DMA_DCHPRI28_ECP_SHIFT (7U)@DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)@DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)@DMA_SADDR_SADDR_SHIFT (0U)@DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)@DMA_SADDR_COUNT (32U)@DMA_SOFF_SOFF_MASK (0xFFFFU)@DMA_SOFF_SOFF_SHIFT (0U)@DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)@DMA_SOFF_COUNT (32U)@DMA_ATTR_DSIZE_MASK (0x7U)@DMA_ATTR_DSIZE_SHIFT (0U)@DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)@DMA_ATTR_DMOD_MASK (0xF8U)@DMA_ATTR_DMOD_SHIFT (3U)@DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)@DMA_ATTR_SSIZE_MASK (0x700U)@DMA_ATTR_SSIZE_SHIFT (8U)@DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)@DMA_ATTR_SMOD_MASK (0xF800U)@DMA_ATTR_SMOD_SHIFT (11U)@DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)@DMA_ATTR_COUNT (32U)@DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)@DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)@DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)@DMA_NBYTES_MLNO_COUNT (32U)@DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)@DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)@DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)@DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)@DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)@DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)@DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)@DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)@DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)@DMA_NBYTES_MLOFFNO_COUNT (32U)@DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)@DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)@DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)@DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)@DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)@DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)ADMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)ADMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)ADMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)ADMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)ADMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)ADMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)ADMA_NBYTES_MLOFFYES_COUNT (32U)ADMA_SLAST_SLAST_MASK (0xFFFFFFFFU)ADMA_SLAST_SLAST_SHIFT (0U)ADMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)ADMA_SLAST_COUNT (32U)ADMA_DADDR_DADDR_MASK (0xFFFFFFFFU)ADMA_DADDR_DADDR_SHIFT (0U)ADMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)ADMA_DADDR_COUNT (32U)ADMA_DOFF_DOFF_MASK (0xFFFFU)ADMA_DOFF_DOFF_SHIFT (0U)ADMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)ADMA_DOFF_COUNT (32U)ADMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)ADMA_CITER_ELINKNO_CITER_SHIFT (0U)ADMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)ADMA_CITER_ELINKNO_ELINK_MASK (0x8000U)ADMA_CITER_ELINKNO_ELINK_SHIFT (15U)ADMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)ADMA_CITER_ELINKNO_COUNT (32U)ADMA_CITER_ELINKYES_CITER_MASK (0x1FFU)ADMA_CITER_ELINKYES_CITER_SHIFT (0U)ADMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)ADMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)ADMA_CITER_ELINKYES_LINKCH_SHIFT (9U)ADMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)ADMA_CITER_ELINKYES_ELINK_MASK (0x8000U)ADMA_CITER_ELINKYES_ELINK_SHIFT (15U)ADMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)ADMA_CITER_ELINKYES_COUNT (32U)ADMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)ADMA_DLAST_SGA_DLASTSGA_SHIFT (0U)ADMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)ADMA_DLAST_SGA_COUNT (32U)ADMA_CSR_START_MASK (0x1U)ADMA_CSR_START_SHIFT (0U)ADMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)ADMA_CSR_INTMAJOR_MASK (0x2U)ADMA_CSR_INTMAJOR_SHIFT (1U)ADMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)ADMA_CSR_INTHALF_MASK (0x4U)ADMA_CSR_INTHALF_SHIFT (2U)ADMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)ADMA_CSR_DREQ_MASK (0x8U)ADMA_CSR_DREQ_SHIFT (3U)ADMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)ADMA_CSR_ESG_MASK (0x10U)ADMA_CSR_ESG_SHIFT (4U)ADMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)ADMA_CSR_MAJORELINK_MASK (0x20U)ADMA_CSR_MAJORELINK_SHIFT (5U)ADMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)ADMA_CSR_ACTIVE_MASK (0x40U)ADMA_CSR_ACTIVE_SHIFT (6U)ADMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)ADMA_CSR_DONE_MASK (0x80U)ADMA_CSR_DONE_SHIFT (7U)ADMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)ADMA_CSR_MAJORLINKCH_MASK (0x1F00U)ADMA_CSR_MAJORLINKCH_SHIFT (8U)ADMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)ADMA_CSR_BWC_MASK (0xC000U)ADMA_CSR_BWC_SHIFT (14U)ADMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)ADMA_CSR_COUNT (32U)ADMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)ADMA_BITER_ELINKNO_BITER_SHIFT (0U)ADMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)ADMA_BITER_ELINKNO_ELINK_MASK (0x8000U)ADMA_BITER_ELINKNO_ELINK_SHIFT (15U)ADMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)ADMA_BITER_ELINKNO_COUNT (32U)ADMA_BITER_ELINKYES_BITER_MASK (0x1FFU)ADMA_BITER_ELINKYES_BITER_SHIFT (0U)ADMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)ADMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)ADMA_BITER_ELINKYES_LINKCH_SHIFT (9U)ADMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)ADMA_BITER_ELINKYES_ELINK_MASK (0x8000U)ADMA_BITER_ELINKYES_ELINK_SHIFT (15U)ADMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)ADMA_BITER_ELINKYES_COUNT (32U)BDMA0_BASE (0x400E8000u)BDMA0 ((DMA_Type *)DMA0_BASE)BDMA_BASE_ADDRS { DMA0_BASE }BDMA_BASE_PTRS { DMA0 }BDMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }BDMA_ERROR_IRQS { DMA_ERROR_IRQn }BDMAMUX_CHCFG_SOURCE_MASK (0x7FU)BDMAMUX_CHCFG_SOURCE_SHIFT (0U)BDMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)BDMAMUX_CHCFG_A_ON_MASK (0x20000000U)BDMAMUX_CHCFG_A_ON_SHIFT (29U)BDMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)BDMAMUX_CHCFG_TRIG_MASK (0x40000000U)BDMAMUX_CHCFG_TRIG_SHIFT (30U)BDMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)BDMAMUX_CHCFG_ENBL_MASK (0x80000000U)BDMAMUX_CHCFG_ENBL_SHIFT (31U)BDMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)BDMAMUX_CHCFG_COUNT (32U)BDMAMUX_BASE (0x400EC000u)BDMAMUX ((DMAMUX_Type *)DMAMUX_BASE)BDMAMUX_BASE_ADDRS { DMAMUX_BASE }BDMAMUX_BASE_PTRS { DMAMUX }CENC_CTRL_CMPIE_MASK (0x1U)CENC_CTRL_CMPIE_SHIFT (0U)CENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)CENC_CTRL_CMPIRQ_MASK (0x2U)CENC_CTRL_CMPIRQ_SHIFT (1U)CENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)CENC_CTRL_WDE_MASK (0x4U)CENC_CTRL_WDE_SHIFT (2U)CENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)CENC_CTRL_DIE_MASK (0x8U)CENC_CTRL_DIE_SHIFT (3U)CENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)CENC_CTRL_DIRQ_MASK (0x10U)CENC_CTRL_DIRQ_SHIFT (4U)CENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)CENC_CTRL_XNE_MASK (0x20U)CENC_CTRL_XNE_SHIFT (5U)CENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)CENC_CTRL_XIP_MASK (0x40U)CENC_CTRL_XIP_SHIFT (6U)CENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)CENC_CTRL_XIE_MASK (0x80U)CENC_CTRL_XIE_SHIFT (7U)CENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)CENC_CTRL_XIRQ_MASK (0x100U)CENC_CTRL_XIRQ_SHIFT (8U)CENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)CENC_CTRL_PH1_MASK (0x200U)CENC_CTRL_PH1_SHIFT (9U)CENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)CENC_CTRL_REV_MASK (0x400U)CENC_CTRL_REV_SHIFT (10U)CENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)CENC_CTRL_SWIP_MASK (0x800U)CENC_CTRL_SWIP_SHIFT (11U)CENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)CENC_CTRL_HNE_MASK (0x1000U)CENC_CTRL_HNE_SHIFT (12U)CENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)CENC_CTRL_HIP_MASK (0x2000U)CENC_CTRL_HIP_SHIFT (13U)CENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)CENC_CTRL_HIE_MASK (0x4000U)CENC_CTRL_HIE_SHIFT (14U)CENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)CENC_CTRL_HIRQ_MASK (0x8000U)CENC_CTRL_HIRQ_SHIFT (15U)CENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)CENC_FILT_FILT_PER_MASK (0xFFU)CENC_FILT_FILT_PER_SHIFT (0U)CENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)CENC_FILT_FILT_CNT_MASK (0x700U)CENC_FILT_FILT_CNT_SHIFT (8U)CENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)CENC_WTR_WDOG_MASK (0xFFFFU)CENC_WTR_WDOG_SHIFT (0U)CENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)CENC_POSD_POSD_MASK (0xFFFFU)CENC_POSD_POSD_SHIFT (0U)CENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)CENC_POSDH_POSDH_MASK (0xFFFFU)CENC_POSDH_POSDH_SHIFT (0U)CENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)CENC_REV_REV_MASK (0xFFFFU)CENC_REV_REV_SHIFT (0U)CENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)CENC_REVH_REVH_MASK (0xFFFFU)CENC_REVH_REVH_SHIFT (0U)CENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)CENC_UPOS_POS_MASK (0xFFFFU)CENC_UPOS_POS_SHIFT (0U)CENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)CENC_LPOS_POS_MASK (0xFFFFU)CENC_LPOS_POS_SHIFT (0U)CENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)CENC_UPOSH_POSH_MASK (0xFFFFU)CENC_UPOSH_POSH_SHIFT (0U)CENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)CENC_LPOSH_POSH_MASK (0xFFFFU)CENC_LPOSH_POSH_SHIFT (0U)CENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)CENC_UINIT_INIT_MASK (0xFFFFU)CENC_UINIT_INIT_SHIFT (0U)CENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)CENC_LINIT_INIT_MASK (0xFFFFU)CENC_LINIT_INIT_SHIFT (0U)CENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)CENC_IMR_HOME_MASK (0x1U)CENC_IMR_HOME_SHIFT (0U)CENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)CENC_IMR_INDEX_MASK (0x2U)CENC_IMR_INDEX_SHIFT (1U)CENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)CENC_IMR_PHB_MASK (0x4U)CENC_IMR_PHB_SHIFT (2U)DENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)DENC_IMR_PHA_MASK (0x8U)DENC_IMR_PHA_SHIFT (3U)DENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)DENC_IMR_FHOM_MASK (0x10U)DENC_IMR_FHOM_SHIFT (4U)DENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)DENC_IMR_FIND_MASK (0x20U)DENC_IMR_FIND_SHIFT (5U)DENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)DENC_IMR_FPHB_MASK (0x40U)DENC_IMR_FPHB_SHIFT (6U)DENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)DENC_IMR_FPHA_MASK (0x80U)DENC_IMR_FPHA_SHIFT (7U)DENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)DENC_TST_TEST_COUNT_MASK (0xFFU)DENC_TST_TEST_COUNT_SHIFT (0U)DENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)DENC_TST_TEST_PERIOD_MASK (0x1F00U)DENC_TST_TEST_PERIOD_SHIFT (8U)DENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)DENC_TST_QDN_MASK (0x2000U)DENC_TST_QDN_SHIFT (13U)DENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)DENC_TST_TCE_MASK (0x4000U)DENC_TST_TCE_SHIFT (14U)DENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)DENC_TST_TEN_MASK (0x8000U)DENC_TST_TEN_SHIFT (15U)DENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)DENC_CTRL2_UPDHLD_MASK (0x1U)DENC_CTRL2_UPDHLD_SHIFT (0U)DENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)DENC_CTRL2_UPDPOS_MASK (0x2U)DENC_CTRL2_UPDPOS_SHIFT (1U)DENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)DENC_CTRL2_MOD_MASK (0x4U)DENC_CTRL2_MOD_SHIFT (2U)DENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)DENC_CTRL2_DIR_MASK (0x8U)DENC_CTRL2_DIR_SHIFT (3U)DENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)DENC_CTRL2_RUIE_MASK (0x10U)DENC_CTRL2_RUIE_SHIFT (4U)DENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)DENC_CTRL2_RUIRQ_MASK (0x20U)DENC_CTRL2_RUIRQ_SHIFT (5U)DENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)DENC_CTRL2_ROIE_MASK (0x40U)DENC_CTRL2_ROIE_SHIFT (6U)DENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)DENC_CTRL2_ROIRQ_MASK (0x80U)DENC_CTRL2_ROIRQ_SHIFT (7U)DENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)DENC_CTRL2_REVMOD_MASK (0x100U)DENC_CTRL2_REVMOD_SHIFT (8U)DENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)DENC_CTRL2_OUTCTL_MASK (0x200U)DENC_CTRL2_OUTCTL_SHIFT (9U)DENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)DENC_CTRL2_SABIE_MASK (0x400U)DENC_CTRL2_SABIE_SHIFT (10U)DENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)DENC_CTRL2_SABIRQ_MASK (0x800U)DENC_CTRL2_SABIRQ_SHIFT (11U)DENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)DENC_UMOD_MOD_MASK (0xFFFFU)DENC_UMOD_MOD_SHIFT (0U)DENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)DENC_LMOD_MOD_MASK (0xFFFFU)DENC_LMOD_MOD_SHIFT (0U)DENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)DENC_UCOMP_COMP_MASK (0xFFFFU)DENC_UCOMP_COMP_SHIFT (0U)DENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)DENC_LCOMP_COMP_MASK (0xFFFFU)DENC_LCOMP_COMP_SHIFT (0U)DENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)DENC1_BASE (0x403C8000u)DENC1 ((ENC_Type *)ENC1_BASE)DENC2_BASE (0x403CC000u)DENC2 ((ENC_Type *)ENC2_BASE)DENC3_BASE (0x403D0000u)DENC3 ((ENC_Type *)ENC3_BASE)DENC4_BASE (0x403D4000u)DENC4 ((ENC_Type *)ENC4_BASE)DENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }DENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }DENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }DENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }DENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }DENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }DENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }FENET_EIR_TS_TIMER_MASK (0x8000U)FENET_EIR_TS_TIMER_SHIFT (15U)FENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)FENET_EIR_TS_AVAIL_MASK (0x10000U)FENET_EIR_TS_AVAIL_SHIFT (16U)FENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)FENET_EIR_WAKEUP_MASK (0x20000U)FENET_EIR_WAKEUP_SHIFT (17U)FENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)FENET_EIR_PLR_MASK (0x40000U)FENET_EIR_PLR_SHIFT (18U)FENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)FENET_EIR_UN_MASK (0x80000U)FENET_EIR_UN_SHIFT (19U)FENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)FENET_EIR_RL_MASK (0x100000U)FENET_EIR_RL_SHIFT (20U)FENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)FENET_EIR_LC_MASK (0x200000U)FENET_EIR_LC_SHIFT (21U)FENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)FENET_EIR_EBERR_MASK (0x400000U)FENET_EIR_EBERR_SHIFT (22U)FENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)FENET_EIR_MII_MASK (0x800000U)FENET_EIR_MII_SHIFT (23U)FENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)FENET_EIR_RXB_MASK (0x1000000U)FENET_EIR_RXB_SHIFT (24U)FENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)FENET_EIR_RXF_MASK (0x2000000U)FENET_EIR_RXF_SHIFT (25U)FENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)FENET_EIR_TXB_MASK (0x4000000U)FENET_EIR_TXB_SHIFT (26U)FENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)FENET_EIR_TXF_MASK (0x8000000U)FENET_EIR_TXF_SHIFT (27U)FENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)FENET_EIR_GRA_MASK (0x10000000U)FENET_EIR_GRA_SHIFT (28U)FENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)FENET_EIR_BABT_MASK (0x20000000U)FENET_EIR_BABT_SHIFT (29U)FENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)FENET_EIR_BABR_MASK (0x40000000U)FENET_EIR_BABR_SHIFT (30U)FENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)FENET_EIMR_TS_TIMER_MASK (0x8000U)FENET_EIMR_TS_TIMER_SHIFT (15U)FENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)FENET_EIMR_TS_AVAIL_MASK (0x10000U)FENET_EIMR_TS_AVAIL_SHIFT (16U)FENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)FENET_EIMR_WAKEUP_MASK (0x20000U)FENET_EIMR_WAKEUP_SHIFT (17U)FENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)FENET_EIMR_PLR_MASK (0x40000U)FENET_EIMR_PLR_SHIFT (18U)FENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)FENET_EIMR_UN_MASK (0x80000U)FENET_EIMR_UN_SHIFT (19U)FENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)FENET_EIMR_RL_MASK (0x100000U)FENET_EIMR_RL_SHIFT (20U)FENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)FENET_EIMR_LC_MASK (0x200000U)FENET_EIMR_LC_SHIFT (21U)FENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)FENET_EIMR_EBERR_MASK (0x400000U)FENET_EIMR_EBERR_SHIFT (22U)FENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)FENET_EIMR_MII_MASK (0x800000U)FENET_EIMR_MII_SHIFT (23U)FENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)FENET_EIMR_RXB_MASK (0x1000000U)FENET_EIMR_RXB_SHIFT (24U)FENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)FENET_EIMR_RXF_MASK (0x2000000U)FENET_EIMR_RXF_SHIFT (25U)FENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)FENET_EIMR_TXB_MASK (0x4000000U)FENET_EIMR_TXB_SHIFT (26U)FENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)FENET_EIMR_TXF_MASK (0x8000000U)FENET_EIMR_TXF_SHIFT (27U)FENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)FENET_EIMR_GRA_MASK (0x10000000U)FENET_EIMR_GRA_SHIFT (28U)FENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)FENET_EIMR_BABT_MASK (0x20000000U)FENET_EIMR_BABT_SHIFT (29U)FENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)FENET_EIMR_BABR_MASK (0x40000000U)FENET_EIMR_BABR_SHIFT (30U)FENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)FENET_RDAR_RDAR_MASK (0x1000000U)FENET_RDAR_RDAR_SHIFT (24U)FENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)FENET_TDAR_TDAR_MASK (0x1000000U)FENET_TDAR_TDAR_SHIFT (24U)FENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)FENET_ECR_RESET_MASK (0x1U)FENET_ECR_RESET_SHIFT (0U)GENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)GENET_ECR_ETHEREN_MASK (0x2U)GENET_ECR_ETHEREN_SHIFT (1U)GENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)GENET_ECR_MAGICEN_MASK (0x4U)GENET_ECR_MAGICEN_SHIFT (2U)GENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)GENET_ECR_SLEEP_MASK (0x8U)GENET_ECR_SLEEP_SHIFT (3U)GENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)GENET_ECR_EN1588_MASK (0x10U)GENET_ECR_EN1588_SHIFT (4U)GENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)GENET_ECR_DBGEN_MASK (0x40U)GENET_ECR_DBGEN_SHIFT (6U)GENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)GENET_ECR_DBSWP_MASK (0x100U)GENET_ECR_DBSWP_SHIFT (8U)GENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)GENET_MMFR_DATA_MASK (0xFFFFU)GENET_MMFR_DATA_SHIFT (0U)GENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)GENET_MMFR_TA_MASK (0x30000U)GENET_MMFR_TA_SHIFT (16U)GENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)GENET_MMFR_RA_MASK (0x7C0000U)GENET_MMFR_RA_SHIFT (18U)GENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)GENET_MMFR_PA_MASK (0xF800000U)GENET_MMFR_PA_SHIFT (23U)GENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)GENET_MMFR_OP_MASK (0x30000000U)GENET_MMFR_OP_SHIFT (28U)GENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)GENET_MMFR_ST_MASK (0xC0000000U)GENET_MMFR_ST_SHIFT (30U)GENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)GENET_MSCR_MII_SPEED_MASK (0x7EU)GENET_MSCR_MII_SPEED_SHIFT (1U)GENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)GENET_MSCR_DIS_PRE_MASK (0x80U)GENET_MSCR_DIS_PRE_SHIFT (7U)GENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)GENET_MSCR_HOLDTIME_MASK (0x700U)GENET_MSCR_HOLDTIME_SHIFT (8U)GENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)GENET_MIBC_MIB_CLEAR_MASK (0x20000000U)GENET_MIBC_MIB_CLEAR_SHIFT (29U)GENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)GENET_MIBC_MIB_IDLE_MASK (0x40000000U)GENET_MIBC_MIB_IDLE_SHIFT (30U)GENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)GENET_MIBC_MIB_DIS_MASK (0x80000000U)GENET_MIBC_MIB_DIS_SHIFT (31U)GENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)GENET_RCR_LOOP_MASK (0x1U)GENET_RCR_LOOP_SHIFT (0U)GENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)GENET_RCR_DRT_MASK (0x2U)GENET_RCR_DRT_SHIFT (1U)GENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)GENET_RCR_MII_MODE_MASK (0x4U)GENET_RCR_MII_MODE_SHIFT (2U)GENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)GENET_RCR_PROM_MASK (0x8U)GENET_RCR_PROM_SHIFT (3U)GENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)GENET_RCR_BC_REJ_MASK (0x10U)GENET_RCR_BC_REJ_SHIFT (4U)GENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)GENET_RCR_FCE_MASK (0x20U)GENET_RCR_FCE_SHIFT (5U)GENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)GENET_RCR_RMII_MODE_MASK (0x100U)GENET_RCR_RMII_MODE_SHIFT (8U)GENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)GENET_RCR_RMII_10T_MASK (0x200U)GENET_RCR_RMII_10T_SHIFT (9U)GENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)GENET_RCR_PADEN_MASK (0x1000U)GENET_RCR_PADEN_SHIFT (12U)GENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)GENET_RCR_PAUFWD_MASK (0x2000U)GENET_RCR_PAUFWD_SHIFT (13U)GENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)GENET_RCR_CRCFWD_MASK (0x4000U)GENET_RCR_CRCFWD_SHIFT (14U)GENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)GENET_RCR_CFEN_MASK (0x8000U)GENET_RCR_CFEN_SHIFT (15U)GENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)GENET_RCR_MAX_FL_MASK (0x3FFF0000U)GENET_RCR_MAX_FL_SHIFT (16U)GENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)GENET_RCR_NLC_MASK (0x40000000U)GENET_RCR_NLC_SHIFT (30U)GENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)GENET_RCR_GRS_MASK (0x80000000U)GENET_RCR_GRS_SHIFT (31U)GENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)GENET_TCR_GTS_MASK (0x1U)GENET_TCR_GTS_SHIFT (0U)GENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)GENET_TCR_FDEN_MASK (0x4U)GENET_TCR_FDEN_SHIFT (2U)GENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)GENET_TCR_TFC_PAUSE_MASK (0x8U)GENET_TCR_TFC_PAUSE_SHIFT (3U)GENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)GENET_TCR_RFC_PAUSE_MASK (0x10U)GENET_TCR_RFC_PAUSE_SHIFT (4U)GENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)GENET_TCR_ADDSEL_MASK (0xE0U)GENET_TCR_ADDSEL_SHIFT (5U)GENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)GENET_TCR_ADDINS_MASK (0x100U)GENET_TCR_ADDINS_SHIFT (8U)GENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)HENET_TCR_CRCFWD_MASK (0x200U)HENET_TCR_CRCFWD_SHIFT (9U)HENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)HENET_PALR_PADDR1_MASK (0xFFFFFFFFU)HENET_PALR_PADDR1_SHIFT (0U)HENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)HENET_PAUR_TYPE_MASK (0xFFFFU)HENET_PAUR_TYPE_SHIFT (0U)HENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)HENET_PAUR_PADDR2_MASK (0xFFFF0000U)HENET_PAUR_PADDR2_SHIFT (16U)HENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)HENET_OPD_PAUSE_DUR_MASK (0xFFFFU)HENET_OPD_PAUSE_DUR_SHIFT (0U)HENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)HENET_OPD_OPCODE_MASK (0xFFFF0000U)HENET_OPD_OPCODE_SHIFT (16U)HENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)HENET_TXIC_ICTT_MASK (0xFFFFU)HENET_TXIC_ICTT_SHIFT (0U)HENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)HENET_TXIC_ICFT_MASK (0xFF00000U)HENET_TXIC_ICFT_SHIFT (20U)HENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)HENET_TXIC_ICCS_MASK (0x40000000U)HENET_TXIC_ICCS_SHIFT (30U)HENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)HENET_TXIC_ICEN_MASK (0x80000000U)HENET_TXIC_ICEN_SHIFT (31U)HENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)HENET_RXIC_ICTT_MASK (0xFFFFU)HENET_RXIC_ICTT_SHIFT (0U)HENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)HENET_RXIC_ICFT_MASK (0xFF00000U)HENET_RXIC_ICFT_SHIFT (20U)HENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)HENET_RXIC_ICCS_MASK (0x40000000U)HENET_RXIC_ICCS_SHIFT (30U)HENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)HENET_RXIC_ICEN_MASK (0x80000000U)HENET_RXIC_ICEN_SHIFT (31U)HENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)HENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)HENET_IAUR_IADDR1_SHIFT (0U)HENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)HENET_IALR_IADDR2_MASK (0xFFFFFFFFU)HENET_IALR_IADDR2_SHIFT (0U)HENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)HENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)HENET_GAUR_GADDR1_SHIFT (0U)HENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)HENET_GALR_GADDR2_MASK (0xFFFFFFFFU)HENET_GALR_GADDR2_SHIFT (0U)HENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)HENET_TFWR_TFWR_MASK (0x3FU)HENET_TFWR_TFWR_SHIFT (0U)HENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)HENET_TFWR_STRFWD_MASK (0x100U)HENET_TFWR_STRFWD_SHIFT (8U)HENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)HENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)HENET_RDSR_R_DES_START_SHIFT (3U)HENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)HENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)HENET_TDSR_X_DES_START_SHIFT (3U)HENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)HENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)HENET_MRBR_R_BUF_SIZE_SHIFT (4U)HENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)HENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)HENET_RSFL_RX_SECTION_FULL_SHIFT (0U)HENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)HENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)HENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)HENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)HENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)HENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)HENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)HENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)HENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)HENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)HENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)HENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)HENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)HENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)HENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)HENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)HENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)HENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)HENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)IENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)IENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)IENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)IENET_TIPG_IPG_MASK (0x1FU)IENET_TIPG_IPG_SHIFT (0U)IENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)IENET_FTRL_TRUNC_FL_MASK (0x3FFFU)IENET_FTRL_TRUNC_FL_SHIFT (0U)IENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)IENET_TACC_SHIFT16_MASK (0x1U)IENET_TACC_SHIFT16_SHIFT (0U)IENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)IENET_TACC_IPCHK_MASK (0x8U)IENET_TACC_IPCHK_SHIFT (3U)IENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)IENET_TACC_PROCHK_MASK (0x10U)IENET_TACC_PROCHK_SHIFT (4U)IENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)IENET_RACC_PADREM_MASK (0x1U)IENET_RACC_PADREM_SHIFT (0U)IENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)IENET_RACC_IPDIS_MASK (0x2U)IENET_RACC_IPDIS_SHIFT (1U)IENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)IENET_RACC_PRODIS_MASK (0x4U)IENET_RACC_PRODIS_SHIFT (2U)IENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)IENET_RACC_LINEDIS_MASK (0x40U)IENET_RACC_LINEDIS_SHIFT (6U)IENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)IENET_RACC_SHIFT16_MASK (0x80U)IENET_RACC_SHIFT16_SHIFT (7U)IENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)IENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)IENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)IENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)IENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)IENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)IENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)IENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)IENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)IENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)IENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)IENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)IENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)IENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)IENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)IENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_JAB_TXPKTS_SHIFT (0U)IENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)IENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_COL_TXPKTS_SHIFT (0U)IENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)IENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P64_TXPKTS_SHIFT (0U)IENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)IENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)IENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)IENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)IENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)IENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)IENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)IENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)IENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)IENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)IENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)IENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)IENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)IENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)IENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)IENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)JENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)JENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)JENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)JENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)JENET_IEEE_T_1COL_COUNT_SHIFT (0U)JENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)JENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)JENET_IEEE_T_MCOL_COUNT_SHIFT (0U)JENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)JENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)JENET_IEEE_T_DEF_COUNT_SHIFT (0U)JENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)JENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)JENET_IEEE_T_LCOL_COUNT_SHIFT (0U)JENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)JENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)JENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)JENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)JENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)JENET_IEEE_T_MACERR_COUNT_SHIFT (0U)JENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)JENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)JENET_IEEE_T_CSERR_COUNT_SHIFT (0U)JENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)JENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)JENET_IEEE_T_SQE_COUNT_SHIFT (0U)JENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)JENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)JENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)JENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)JENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)JENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)JENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)JENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)JENET_RMON_R_PACKETS_COUNT_SHIFT (0U)JENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)JENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)JENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)JENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)JENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)JENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)JENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)JENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)JENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)JENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)JENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)JENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)JENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)JENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)JENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)JENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)JENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)JENET_RMON_R_FRAG_COUNT_SHIFT (0U)JENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)JENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)JENET_RMON_R_JAB_COUNT_SHIFT (0U)JENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)JENET_RMON_R_P64_COUNT_MASK (0xFFFFU)JENET_RMON_R_P64_COUNT_SHIFT (0U)JENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)JENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)JENET_RMON_R_P65TO127_COUNT_SHIFT (0U)JENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)JENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)JENET_RMON_R_P128TO255_COUNT_SHIFT (0U)JENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)JENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)JENET_RMON_R_P256TO511_COUNT_SHIFT (0U)JENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)JENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)JENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)JENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)JENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)JENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)JENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)JENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)KENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)KENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)KENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)KENET_RMON_R_OCTETS_COUNT_SHIFT (0U)KENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)KENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)KENET_IEEE_R_DROP_COUNT_SHIFT (0U)KENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)KENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)KENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)KENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)KENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)KENET_IEEE_R_CRC_COUNT_SHIFT (0U)KENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)KENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)KENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)KENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)KENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)KENET_IEEE_R_MACERR_COUNT_SHIFT (0U)KENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)KENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)KENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)KENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)KENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)KENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)KENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)KENET_ATCR_EN_MASK (0x1U)KENET_ATCR_EN_SHIFT (0U)KENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)KENET_ATCR_OFFEN_MASK (0x4U)KENET_ATCR_OFFEN_SHIFT (2U)KENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)KENET_ATCR_OFFRST_MASK (0x8U)KENET_ATCR_OFFRST_SHIFT (3U)KENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)KENET_ATCR_PEREN_MASK (0x10U)KENET_ATCR_PEREN_SHIFT (4U)KENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)KENET_ATCR_PINPER_MASK (0x80U)KENET_ATCR_PINPER_SHIFT (7U)KENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)KENET_ATCR_RESTART_MASK (0x200U)KENET_ATCR_RESTART_SHIFT (9U)KENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)KENET_ATCR_CAPTURE_MASK (0x800U)KENET_ATCR_CAPTURE_SHIFT (11U)KENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)KENET_ATCR_SLAVE_MASK (0x2000U)KENET_ATCR_SLAVE_SHIFT (13U)KENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)KENET_ATVR_ATIME_MASK (0xFFFFFFFFU)KENET_ATVR_ATIME_SHIFT (0U)KENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)KENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)KENET_ATOFF_OFFSET_SHIFT (0U)KENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)KENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)KENET_ATPER_PERIOD_SHIFT (0U)KENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)KENET_ATCOR_COR_MASK (0x7FFFFFFFU)KENET_ATCOR_COR_SHIFT (0U)KENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)KENET_ATINC_INC_MASK (0x7FU)KENET_ATINC_INC_SHIFT (0U)KENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)KENET_ATINC_INC_CORR_MASK (0x7F00U)KENET_ATINC_INC_CORR_SHIFT (8U)KENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)KENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)KENET_ATSTMP_TIMESTAMP_SHIFT (0U)KENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)KENET_TGSR_TF0_MASK (0x1U)KENET_TGSR_TF0_SHIFT (0U)KENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)KENET_TGSR_TF1_MASK (0x2U)KENET_TGSR_TF1_SHIFT (1U)KENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)KENET_TGSR_TF2_MASK (0x4U)KENET_TGSR_TF2_SHIFT (2U)KENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)KENET_TGSR_TF3_MASK (0x8U)KENET_TGSR_TF3_SHIFT (3U)KENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)KENET_TCSR_TDRE_MASK (0x1U)KENET_TCSR_TDRE_SHIFT (0U)KENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)KENET_TCSR_TMODE_MASK (0x3CU)KENET_TCSR_TMODE_SHIFT (2U)KENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)KENET_TCSR_TIE_MASK (0x40U)KENET_TCSR_TIE_SHIFT (6U)KENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)KENET_TCSR_TF_MASK (0x80U)KENET_TCSR_TF_SHIFT (7U)LENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)LENET_TCSR_TPWC_MASK (0xF800U)LENET_TCSR_TPWC_SHIFT (11U)LENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)LENET_TCSR_COUNT (4U)LENET_TCCR_TCC_MASK (0xFFFFFFFFU)LENET_TCCR_TCC_SHIFT (0U)LENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)LENET_TCCR_COUNT (4U)LENET_BASE (0x402D8000u)LENET ((ENET_Type *)ENET_BASE)LENET_BASE_ADDRS { ENET_BASE }LENET_BASE_PTRS { ENET }LENET_Transmit_IRQS { ENET_IRQn }LENET_Receive_IRQS { ENET_IRQn }LENET_Error_IRQS { ENET_IRQn }LENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }LENET_BUFF_ALIGNMENT (64U)LEWM_CTRL_EWMEN_MASK (0x1U)LEWM_CTRL_EWMEN_SHIFT (0U)LEWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)LEWM_CTRL_ASSIN_MASK (0x2U)LEWM_CTRL_ASSIN_SHIFT (1U)LEWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)LEWM_CTRL_INEN_MASK (0x4U)LEWM_CTRL_INEN_SHIFT (2U)LEWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)LEWM_CTRL_INTEN_MASK (0x8U)LEWM_CTRL_INTEN_SHIFT (3U)LEWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)LEWM_SERV_SERVICE_MASK (0xFFU)LEWM_SERV_SERVICE_SHIFT (0U)LEWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)LEWM_CMPL_COMPAREL_MASK (0xFFU)LEWM_CMPL_COMPAREL_SHIFT (0U)LEWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)LEWM_CMPH_COMPAREH_MASK (0xFFU)LEWM_CMPH_COMPAREH_SHIFT (0U)LEWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)LEWM_CLKCTRL_CLKSEL_MASK (0x3U)LEWM_CLKCTRL_CLKSEL_SHIFT (0U)LEWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)LEWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)LEWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)LEWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)LEWM_BASE (0x400B4000u)LEWM ((EWM_Type *)EWM_BASE)LEWM_BASE_ADDRS { EWM_BASE }LEWM_BASE_PTRS { EWM }MEWM_IRQS { EWM_IRQn }MFLEXIO_VERID_FEATURE_MASK (0xFFFFU)MFLEXIO_VERID_FEATURE_SHIFT (0U)MFLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)MFLEXIO_VERID_MINOR_MASK (0xFF0000U)MFLEXIO_VERID_MINOR_SHIFT (16U)MFLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)MFLEXIO_VERID_MAJOR_MASK (0xFF000000U)MFLEXIO_VERID_MAJOR_SHIFT (24U)MFLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)MFLEXIO_PARAM_SHIFTER_MASK (0xFFU)MFLEXIO_PARAM_SHIFTER_SHIFT (0U)MFLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)MFLEXIO_PARAM_TIMER_MASK (0xFF00U)MFLEXIO_PARAM_TIMER_SHIFT (8U)MFLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)MFLEXIO_PARAM_PIN_MASK (0xFF0000U)MFLEXIO_PARAM_PIN_SHIFT (16U)MFLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)MFLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)MFLEXIO_PARAM_TRIGGER_SHIFT (24U)MFLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)MFLEXIO_CTRL_FLEXEN_MASK (0x1U)MFLEXIO_CTRL_FLEXEN_SHIFT (0U)MFLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)MFLEXIO_CTRL_SWRST_MASK (0x2U)MFLEXIO_CTRL_SWRST_SHIFT (1U)MFLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)MFLEXIO_CTRL_FASTACC_MASK (0x4U)MFLEXIO_CTRL_FASTACC_SHIFT (2U)MFLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)MFLEXIO_CTRL_DBGE_MASK (0x40000000U)MFLEXIO_CTRL_DBGE_SHIFT (30U)MFLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)MFLEXIO_CTRL_DOZEN_MASK (0x80000000U)MFLEXIO_CTRL_DOZEN_SHIFT (31U)MFLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)MFLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)MFLEXIO_PIN_PDI_SHIFT (0U)MFLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)MFLEXIO_SHIFTSTAT_SSF_MASK (0xFU)MFLEXIO_SHIFTSTAT_SSF_SHIFT (0U)MFLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)MFLEXIO_SHIFTERR_SEF_MASK (0xFU)MFLEXIO_SHIFTERR_SEF_SHIFT (0U)MFLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)MFLEXIO_TIMSTAT_TSF_MASK (0xFU)MFLEXIO_TIMSTAT_TSF_SHIFT (0U)NFLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)NFLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)NFLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)NFLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)NFLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)NFLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)NFLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)NFLEXIO_TIMIEN_TEIE_MASK (0xFU)NFLEXIO_TIMIEN_TEIE_SHIFT (0U)NFLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)NFLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)NFLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)NFLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)NFLEXIO_SHIFTSTATE_STATE_MASK (0x7U)NFLEXIO_SHIFTSTATE_STATE_SHIFT (0U)NFLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)NFLEXIO_SHIFTCTL_SMOD_MASK (0x7U)NFLEXIO_SHIFTCTL_SMOD_SHIFT (0U)NFLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)NFLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)NFLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)NFLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)NFLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)NFLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)NFLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)NFLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)NFLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)NFLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)NFLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)NFLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)NFLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)NFLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)NFLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)NFLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)NFLEXIO_SHIFTCTL_COUNT (4U)NFLEXIO_SHIFTCFG_SSTART_MASK (0x3U)NFLEXIO_SHIFTCFG_SSTART_SHIFT (0U)NFLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)NFLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)NFLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)NFLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)NFLEXIO_SHIFTCFG_INSRC_MASK (0x100U)NFLEXIO_SHIFTCFG_INSRC_SHIFT (8U)NFLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)NFLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)NFLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)NFLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)NFLEXIO_SHIFTCFG_COUNT (4U)NFLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)NFLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)NFLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)NFLEXIO_SHIFTBUF_COUNT (4U)NFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)NFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)NFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)NFLEXIO_SHIFTBUFBIS_COUNT (4U)NFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)NFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)NFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)NFLEXIO_SHIFTBUFBYS_COUNT (4U)NFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)NFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)NFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)NFLEXIO_SHIFTBUFBBS_COUNT (4U)NFLEXIO_TIMCTL_TIMOD_MASK (0x3U)NFLEXIO_TIMCTL_TIMOD_SHIFT (0U)NFLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)NFLEXIO_TIMCTL_PINPOL_MASK (0x80U)NFLEXIO_TIMCTL_PINPOL_SHIFT (7U)NFLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)NFLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)NFLEXIO_TIMCTL_PINSEL_SHIFT (8U)NFLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)NFLEXIO_TIMCTL_PINCFG_MASK (0x30000U)NFLEXIO_TIMCTL_PINCFG_SHIFT (16U)NFLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)NFLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)NFLEXIO_TIMCTL_TRGSRC_SHIFT (22U)NFLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)NFLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)NFLEXIO_TIMCTL_TRGPOL_SHIFT (23U)NFLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)NFLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)NFLEXIO_TIMCTL_TRGSEL_SHIFT (24U)NFLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)NFLEXIO_TIMCTL_COUNT (4U)NFLEXIO_TIMCFG_TSTART_MASK (0x2U)NFLEXIO_TIMCFG_TSTART_SHIFT (1U)OFLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)OFLEXIO_TIMCFG_TSTOP_MASK (0x30U)OFLEXIO_TIMCFG_TSTOP_SHIFT (4U)OFLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)OFLEXIO_TIMCFG_TIMENA_MASK (0x700U)OFLEXIO_TIMCFG_TIMENA_SHIFT (8U)OFLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)OFLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)OFLEXIO_TIMCFG_TIMDIS_SHIFT (12U)OFLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)OFLEXIO_TIMCFG_TIMRST_MASK (0x70000U)OFLEXIO_TIMCFG_TIMRST_SHIFT (16U)OFLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)OFLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)OFLEXIO_TIMCFG_TIMDEC_SHIFT (20U)OFLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)OFLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)OFLEXIO_TIMCFG_TIMOUT_SHIFT (24U)OFLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)OFLEXIO_TIMCFG_COUNT (4U)OFLEXIO_TIMCMP_CMP_MASK (0xFFFFU)OFLEXIO_TIMCMP_CMP_SHIFT (0U)OFLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)OFLEXIO_TIMCMP_COUNT (4U)OFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)OFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)OFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)OFLEXIO_SHIFTBUFNBS_COUNT (4U)OFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)OFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)OFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)OFLEXIO_SHIFTBUFHWS_COUNT (4U)OFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)OFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)OFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)OFLEXIO_SHIFTBUFNIS_COUNT (4U)OFLEXIO1_BASE (0x401AC000u)OFLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)OFLEXIO2_BASE (0x401B0000u)OFLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)OFLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }OFLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }OFLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }OFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)OFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)OFLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)OFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)OFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)OFLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)OFLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)OFLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)OFLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)OFLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U)OFLEXRAM_TCM_CTRL_Reserved_SHIFT (3U)OFLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)OFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)OFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)PFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)PFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU)PFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)PFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)PFLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)PFLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U)PFLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)PFLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)PFLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U)PFLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)PFLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)PFLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U)PFLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)PFLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U)PFLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)PFLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)PFLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U)PFLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)PFLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)PFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)PFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)PFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)PFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)PFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)PFLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)PFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)PFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)PFLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)PFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)PFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)PFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)PFLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U)PFLEXRAM_INT_STATUS_Reserved_SHIFT (6U)PFLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)PFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)PFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)PFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)PFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)PFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)PFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)PFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)PFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)PFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)PFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)PFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)PFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)PFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U)PFLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U)PFLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)PFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U)PFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)PFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U)PFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)PFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)PFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)PFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)PFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)PFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)PFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)PFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)PFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)PFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U)PFLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U)PFLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)PFLEXRAM_BASE (0x400B0000u)PFLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)PFLEXRAM_BASE_ADDRS { FLEXRAM_BASE }PFLEXRAM_BASE_PTRS { FLEXRAM }PFLEXRAM_IRQS { FLEXRAM_IRQn }QFLEXSPI_MCR0_SWRESET_MASK (0x1U)QFLEXSPI_MCR0_SWRESET_SHIFT (0U)QFLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)QFLEXSPI_MCR0_MDIS_MASK (0x2U)QFLEXSPI_MCR0_MDIS_SHIFT (1U)QFLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)QFLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)QFLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)QFLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)QFLEXSPI_MCR0_ARDFEN_MASK (0x40U)QFLEXSPI_MCR0_ARDFEN_SHIFT (6U)QFLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)QFLEXSPI_MCR0_ATDFEN_MASK (0x80U)QFLEXSPI_MCR0_ATDFEN_SHIFT (7U)QFLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)QFLEXSPI_MCR0_HSEN_MASK (0x800U)QFLEXSPI_MCR0_HSEN_SHIFT (11U)QFLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)QFLEXSPI_MCR0_DOZEEN_MASK (0x1000U)QFLEXSPI_MCR0_DOZEEN_SHIFT (12U)QFLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)QFLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)QFLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)QFLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)QFLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)QFLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)QFLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)QFLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)QFLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)QFLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)QFLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)QFLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)QFLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)QFLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)QFLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)QFLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)QFLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)QFLEXSPI_MCR1_SEQWAIT_SHIFT (16U)QFLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)QFLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)QFLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)QFLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)QFLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)QFLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)QFLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)QFLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)QFLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)QFLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)QFLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)QFLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)QFLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)QFLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)QFLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)QFLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)QFLEXSPI_AHBCR_APAREN_MASK (0x1U)QFLEXSPI_AHBCR_APAREN_SHIFT (0U)QFLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)QFLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)QFLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)QFLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)QFLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)QFLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)QFLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)QFLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)QFLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)QFLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)QFLEXSPI_AHBCR_READADDROPT_MASK (0x40U)QFLEXSPI_AHBCR_READADDROPT_SHIFT (6U)QFLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)RFLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)RFLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)RFLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)RFLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)RFLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)RFLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)RFLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)RFLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)RFLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)RFLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)RFLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)RFLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)RFLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)RFLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)RFLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)RFLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)RFLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)RFLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)RFLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)RFLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)RFLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)RFLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)RFLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)RFLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)RFLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)RFLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)RFLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)RFLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)RFLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)RFLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)RFLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)RFLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)RFLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)RFLEXSPI_INTR_IPCMDDONE_MASK (0x1U)RFLEXSPI_INTR_IPCMDDONE_SHIFT (0U)RFLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)RFLEXSPI_INTR_IPCMDGE_MASK (0x2U)RFLEXSPI_INTR_IPCMDGE_SHIFT (1U)RFLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)RFLEXSPI_INTR_AHBCMDGE_MASK (0x4U)RFLEXSPI_INTR_AHBCMDGE_SHIFT (2U)RFLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)RFLEXSPI_INTR_IPCMDERR_MASK (0x8U)RFLEXSPI_INTR_IPCMDERR_SHIFT (3U)RFLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)RFLEXSPI_INTR_AHBCMDERR_MASK (0x10U)RFLEXSPI_INTR_AHBCMDERR_SHIFT (4U)RFLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)RFLEXSPI_INTR_IPRXWA_MASK (0x20U)RFLEXSPI_INTR_IPRXWA_SHIFT (5U)RFLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)RFLEXSPI_INTR_IPTXWE_MASK (0x40U)RFLEXSPI_INTR_IPTXWE_SHIFT (6U)RFLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)RFLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)RFLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)RFLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)RFLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)RFLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)RFLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)RFLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)RFLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)RFLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)RFLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)RFLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)RFLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)RFLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)RFLEXSPI_LUTKEY_KEY_SHIFT (0U)RFLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)RFLEXSPI_LUTCR_LOCK_MASK (0x1U)RFLEXSPI_LUTCR_LOCK_SHIFT (0U)RFLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)RFLEXSPI_LUTCR_UNLOCK_MASK (0x2U)RFLEXSPI_LUTCR_UNLOCK_SHIFT (1U)RFLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)RFLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)RFLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)RFLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)RFLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)RFLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)RFLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)RFLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)RFLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)RFLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)RFLEXSPI_AHBRXBUFCR0_COUNT (4U)RFLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)RFLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)RFLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)RFLEXSPI_FLSHCR0_COUNT (4U)RFLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)RFLEXSPI_FLSHCR1_TCSS_SHIFT (0U)RFLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)RFLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)RFLEXSPI_FLSHCR1_TCSH_SHIFT (5U)RFLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)RFLEXSPI_FLSHCR1_WA_MASK (0x400U)RFLEXSPI_FLSHCR1_WA_SHIFT (10U)RFLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)RFLEXSPI_FLSHCR1_CAS_MASK (0x7800U)RFLEXSPI_FLSHCR1_CAS_SHIFT (11U)RFLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)RFLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)RFLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)RFLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)RFLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)RFLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)RFLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)RFLEXSPI_FLSHCR1_COUNT (4U)SFLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)SFLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)SFLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)SFLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)SFLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)SFLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)SFLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)SFLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)SFLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)SFLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)SFLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)SFLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)SFLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)SFLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)SFLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)SFLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)SFLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)SFLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)SFLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)SFLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)SFLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)SFLEXSPI_FLSHCR2_COUNT (4U)SFLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)SFLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)SFLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)SFLEXSPI_FLSHCR4_WMENA_MASK (0x4U)SFLEXSPI_FLSHCR4_WMENA_SHIFT (2U)SFLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)SFLEXSPI_FLSHCR4_WMENB_MASK (0x8U)SFLEXSPI_FLSHCR4_WMENB_SHIFT (3U)SFLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)SFLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)SFLEXSPI_IPCR0_SFAR_SHIFT (0U)SFLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)SFLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)SFLEXSPI_IPCR1_IDATSZ_SHIFT (0U)SFLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)SFLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)SFLEXSPI_IPCR1_ISEQID_SHIFT (16U)SFLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)SFLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)SFLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)SFLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)SFLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)SFLEXSPI_IPCR1_IPAREN_SHIFT (31U)SFLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)SFLEXSPI_IPCMD_TRG_MASK (0x1U)SFLEXSPI_IPCMD_TRG_SHIFT (0U)SFLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)SFLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)SFLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)SFLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)SFLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)SFLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)SFLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)SFLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)SFLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)SFLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)SFLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)SFLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)SFLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)SFLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)SFLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)SFLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)SFLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)SFLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)SFLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)SFLEXSPI_DLLCR_DLLEN_MASK (0x1U)SFLEXSPI_DLLCR_DLLEN_SHIFT (0U)SFLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)SFLEXSPI_DLLCR_DLLRESET_MASK (0x2U)SFLEXSPI_DLLCR_DLLRESET_SHIFT (1U)SFLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)SFLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)SFLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)SFLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)SFLEXSPI_DLLCR_OVRDEN_MASK (0x100U)SFLEXSPI_DLLCR_OVRDEN_SHIFT (8U)SFLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)SFLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)SFLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)SFLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)SFLEXSPI_DLLCR_COUNT (2U)SFLEXSPI_STS0_SEQIDLE_MASK (0x1U)SFLEXSPI_STS0_SEQIDLE_SHIFT (0U)SFLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)SFLEXSPI_STS0_ARBIDLE_MASK (0x2U)SFLEXSPI_STS0_ARBIDLE_SHIFT (1U)SFLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)SFLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)SFLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)SFLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)SFLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)SFLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)SFLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)SFLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)SFLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)SFLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)SFLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)SFLEXSPI_STS1_IPCMDERRID_SHIFT (16U)SFLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)SFLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)SFLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)SFLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)TFLEXSPI_STS2_ASLVLOCK_MASK (0x1U)TFLEXSPI_STS2_ASLVLOCK_SHIFT (0U)TFLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)TFLEXSPI_STS2_AREFLOCK_MASK (0x2U)TFLEXSPI_STS2_AREFLOCK_SHIFT (1U)TFLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)TFLEXSPI_STS2_ASLVSEL_MASK (0xFCU)TFLEXSPI_STS2_ASLVSEL_SHIFT (2U)TFLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)TFLEXSPI_STS2_AREFSEL_MASK (0x3F00U)TFLEXSPI_STS2_AREFSEL_SHIFT (8U)TFLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)TFLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)TFLEXSPI_STS2_BSLVLOCK_SHIFT (16U)TFLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)TFLEXSPI_STS2_BREFLOCK_MASK (0x20000U)TFLEXSPI_STS2_BREFLOCK_SHIFT (17U)TFLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)TFLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)TFLEXSPI_STS2_BSLVSEL_SHIFT (18U)TFLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)TFLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)TFLEXSPI_STS2_BREFSEL_SHIFT (24U)TFLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)TFLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)TFLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)TFLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)TFLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)TFLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)TFLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)TFLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)TFLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)TFLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)TFLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)TFLEXSPI_IPRXFSTS_FILL_SHIFT (0U)TFLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)TFLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)TFLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)TFLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)TFLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)TFLEXSPI_IPTXFSTS_FILL_SHIFT (0U)TFLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)TFLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)TFLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)TFLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)TFLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)TFLEXSPI_RFDR_RXDATA_SHIFT (0U)TFLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)TFLEXSPI_RFDR_COUNT (32U)TFLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)TFLEXSPI_TFDR_TXDATA_SHIFT (0U)TFLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)TFLEXSPI_TFDR_COUNT (32U)TFLEXSPI_LUT_OPERAND0_MASK (0xFFU)TFLEXSPI_LUT_OPERAND0_SHIFT (0U)TFLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)TFLEXSPI_LUT_NUM_PADS0_MASK (0x300U)TFLEXSPI_LUT_NUM_PADS0_SHIFT (8U)TFLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)TFLEXSPI_LUT_OPCODE0_MASK (0xFC00U)TFLEXSPI_LUT_OPCODE0_SHIFT (10U)TFLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)TFLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)TFLEXSPI_LUT_OPERAND1_SHIFT (16U)TFLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)TFLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)TFLEXSPI_LUT_NUM_PADS1_SHIFT (24U)TFLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)TFLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)TFLEXSPI_LUT_OPCODE1_SHIFT (26U)TFLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)TFLEXSPI_LUT_COUNT (64U)TFLEXSPI_BASE (0x402A8000u)TFLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)TFLEXSPI_BASE_ADDRS { FLEXSPI_BASE }TFLEXSPI_BASE_PTRS { FLEXSPI }TFLEXSPI_IRQS { FLEXSPI_IRQn }TFlexSPI_AMBA_BASE (0x60000000U)TFlexSPI_ASFM_BASE (0x00000000U)TFlexSPI_ARDF_BASE (0x7FC00000U)TFlexSPI_ATDF_BASE (0x7F800000U)UGPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)UGPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)UGPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)UGPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)UGPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)UGPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)UGPC_CNTR_PDRAM0_PGE_MASK (0x400000U)UGPC_CNTR_PDRAM0_PGE_SHIFT (22U)UGPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)UGPC_IMR_IMR1_MASK (0xFFFFFFFFU)UGPC_IMR_IMR1_SHIFT (0U)UGPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)UGPC_IMR_IMR2_MASK (0xFFFFFFFFU)UGPC_IMR_IMR2_SHIFT (0U)UGPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)UGPC_IMR_IMR3_MASK (0xFFFFFFFFU)UGPC_IMR_IMR3_SHIFT (0U)UGPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)UGPC_IMR_IMR4_MASK (0xFFFFFFFFU)UGPC_IMR_IMR4_SHIFT (0U)UGPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)UGPC_IMR_COUNT (4U)UGPC_ISR_ISR1_MASK (0xFFFFFFFFU)UGPC_ISR_ISR1_SHIFT (0U)UGPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)UGPC_ISR_ISR2_MASK (0xFFFFFFFFU)UGPC_ISR_ISR2_SHIFT (0U)UGPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)UGPC_ISR_ISR3_MASK (0xFFFFFFFFU)UGPC_ISR_ISR3_SHIFT (0U)UGPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)UGPC_ISR_ISR4_MASK (0xFFFFFFFFU)UGPC_ISR_ISR4_SHIFT (0U)UGPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)UGPC_ISR_COUNT (4U)UGPC_IMR5_IMR5_MASK (0xFFFFFFFFU)UGPC_IMR5_IMR5_SHIFT (0U)UGPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)UGPC_ISR5_ISR4_MASK (0xFFFFFFFFU)UGPC_ISR5_ISR4_SHIFT (0U)UGPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)UGPC_BASE (0x400F4000u)UGPC ((GPC_Type *)GPC_BASE)UGPC_BASE_ADDRS { GPC_BASE }UGPC_BASE_PTRS { GPC }UGPC_IRQS { GPC_IRQn }VGPIO_DR_DR_MASK (0xFFFFFFFFU)VGPIO_DR_DR_SHIFT (0U)VGPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)VGPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)VGPIO_GDIR_GDIR_SHIFT (0U)VGPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)VGPIO_PSR_PSR_MASK (0xFFFFFFFFU)VGPIO_PSR_PSR_SHIFT (0U)VGPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)VGPIO_ICR1_ICR0_MASK (0x3U)VGPIO_ICR1_ICR0_SHIFT (0U)VGPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)VGPIO_ICR1_ICR1_MASK (0xCU)VGPIO_ICR1_ICR1_SHIFT (2U)VGPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)VGPIO_ICR1_ICR2_MASK (0x30U)VGPIO_ICR1_ICR2_SHIFT (4U)VGPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)VGPIO_ICR1_ICR3_MASK (0xC0U)VGPIO_ICR1_ICR3_SHIFT (6U)VGPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)VGPIO_ICR1_ICR4_MASK (0x300U)VGPIO_ICR1_ICR4_SHIFT (8U)VGPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)VGPIO_ICR1_ICR5_MASK (0xC00U)VGPIO_ICR1_ICR5_SHIFT (10U)VGPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)VGPIO_ICR1_ICR6_MASK (0x3000U)VGPIO_ICR1_ICR6_SHIFT (12U)VGPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)VGPIO_ICR1_ICR7_MASK (0xC000U)VGPIO_ICR1_ICR7_SHIFT (14U)VGPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)VGPIO_ICR1_ICR8_MASK (0x30000U)VGPIO_ICR1_ICR8_SHIFT (16U)VGPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)VGPIO_ICR1_ICR9_MASK (0xC0000U)VGPIO_ICR1_ICR9_SHIFT (18U)VGPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)VGPIO_ICR1_ICR10_MASK (0x300000U)VGPIO_ICR1_ICR10_SHIFT (20U)VGPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)VGPIO_ICR1_ICR11_MASK (0xC00000U)VGPIO_ICR1_ICR11_SHIFT (22U)VGPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)VGPIO_ICR1_ICR12_MASK (0x3000000U)VGPIO_ICR1_ICR12_SHIFT (24U)VGPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)VGPIO_ICR1_ICR13_MASK (0xC000000U)VGPIO_ICR1_ICR13_SHIFT (26U)VGPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)VGPIO_ICR1_ICR14_MASK (0x30000000U)VGPIO_ICR1_ICR14_SHIFT (28U)VGPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)VGPIO_ICR1_ICR15_MASK (0xC0000000U)VGPIO_ICR1_ICR15_SHIFT (30U)VGPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)VGPIO_ICR2_ICR16_MASK (0x3U)VGPIO_ICR2_ICR16_SHIFT (0U)VGPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)VGPIO_ICR2_ICR17_MASK (0xCU)VGPIO_ICR2_ICR17_SHIFT (2U)VGPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)VGPIO_ICR2_ICR18_MASK (0x30U)VGPIO_ICR2_ICR18_SHIFT (4U)VGPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)VGPIO_ICR2_ICR19_MASK (0xC0U)VGPIO_ICR2_ICR19_SHIFT (6U)VGPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)VGPIO_ICR2_ICR20_MASK (0x300U)VGPIO_ICR2_ICR20_SHIFT (8U)VGPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)VGPIO_ICR2_ICR21_MASK (0xC00U)VGPIO_ICR2_ICR21_SHIFT (10U)VGPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)VGPIO_ICR2_ICR22_MASK (0x3000U)VGPIO_ICR2_ICR22_SHIFT (12U)VGPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)VGPIO_ICR2_ICR23_MASK (0xC000U)VGPIO_ICR2_ICR23_SHIFT (14U)VGPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)VGPIO_ICR2_ICR24_MASK (0x30000U)VGPIO_ICR2_ICR24_SHIFT (16U)VGPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)VGPIO_ICR2_ICR25_MASK (0xC0000U)VGPIO_ICR2_ICR25_SHIFT (18U)VGPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)VGPIO_ICR2_ICR26_MASK (0x300000U)VGPIO_ICR2_ICR26_SHIFT (20U)VGPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)VGPIO_ICR2_ICR27_MASK (0xC00000U)VGPIO_ICR2_ICR27_SHIFT (22U)VGPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)VGPIO_ICR2_ICR28_MASK (0x3000000U)VGPIO_ICR2_ICR28_SHIFT (24U)VGPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)VGPIO_ICR2_ICR29_MASK (0xC000000U)VGPIO_ICR2_ICR29_SHIFT (26U)VGPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)VGPIO_ICR2_ICR30_MASK (0x30000000U)VGPIO_ICR2_ICR30_SHIFT (28U)VGPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)VGPIO_ICR2_ICR31_MASK (0xC0000000U)VGPIO_ICR2_ICR31_SHIFT (30U)VGPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)VGPIO_IMR_IMR_MASK (0xFFFFFFFFU)VGPIO_IMR_IMR_SHIFT (0U)VGPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)VGPIO_ISR_ISR_MASK (0xFFFFFFFFU)VGPIO_ISR_ISR_SHIFT (0U)WGPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)WGPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)WGPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)WGPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)WGPIO1_BASE (0x401B8000u)WGPIO1 ((GPIO_Type *)GPIO1_BASE)WGPIO2_BASE (0x401BC000u)WGPIO2 ((GPIO_Type *)GPIO2_BASE)WGPIO3_BASE (0x401C0000u)WGPIO3 ((GPIO_Type *)GPIO3_BASE)WGPIO4_BASE (0x401C4000u)WGPIO4 ((GPIO_Type *)GPIO4_BASE)WGPIO5_BASE (0x400C0000u)WGPIO5 ((GPIO_Type *)GPIO5_BASE)WGPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }WGPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }WGPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }WGPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn }WGPT_CR_EN_MASK (0x1U)WGPT_CR_EN_SHIFT (0U)WGPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)WGPT_CR_ENMOD_MASK (0x2U)WGPT_CR_ENMOD_SHIFT (1U)WGPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)WGPT_CR_DBGEN_MASK (0x4U)WGPT_CR_DBGEN_SHIFT (2U)WGPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)WGPT_CR_WAITEN_MASK (0x8U)WGPT_CR_WAITEN_SHIFT (3U)WGPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)WGPT_CR_DOZEEN_MASK (0x10U)WGPT_CR_DOZEEN_SHIFT (4U)WGPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)WGPT_CR_STOPEN_MASK (0x20U)WGPT_CR_STOPEN_SHIFT (5U)WGPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)WGPT_CR_CLKSRC_MASK (0x1C0U)WGPT_CR_CLKSRC_SHIFT (6U)WGPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)WGPT_CR_FRR_MASK (0x200U)WGPT_CR_FRR_SHIFT (9U)WGPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)WGPT_CR_EN_24M_MASK (0x400U)WGPT_CR_EN_24M_SHIFT (10U)WGPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)WGPT_CR_SWR_MASK (0x8000U)WGPT_CR_SWR_SHIFT (15U)WGPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)WGPT_CR_IM1_MASK (0x30000U)WGPT_CR_IM1_SHIFT (16U)WGPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)WGPT_CR_IM2_MASK (0xC0000U)WGPT_CR_IM2_SHIFT (18U)WGPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)WGPT_CR_OM1_MASK (0x700000U)WGPT_CR_OM1_SHIFT (20U)WGPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)WGPT_CR_OM2_MASK (0x3800000U)WGPT_CR_OM2_SHIFT (23U)WGPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)WGPT_CR_OM3_MASK (0x1C000000U)WGPT_CR_OM3_SHIFT (26U)WGPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)WGPT_CR_FO1_MASK (0x20000000U)WGPT_CR_FO1_SHIFT (29U)WGPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)WGPT_CR_FO2_MASK (0x40000000U)WGPT_CR_FO2_SHIFT (30U)WGPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)XGPT_CR_FO3_MASK (0x80000000U)XGPT_CR_FO3_SHIFT (31U)XGPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)XGPT_PR_PRESCALER_MASK (0xFFFU)XGPT_PR_PRESCALER_SHIFT (0U)XGPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)XGPT_PR_PRESCALER24M_MASK (0xF000U)XGPT_PR_PRESCALER24M_SHIFT (12U)XGPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)XGPT_SR_OF1_MASK (0x1U)XGPT_SR_OF1_SHIFT (0U)XGPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)XGPT_SR_OF2_MASK (0x2U)XGPT_SR_OF2_SHIFT (1U)XGPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)XGPT_SR_OF3_MASK (0x4U)XGPT_SR_OF3_SHIFT (2U)XGPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)XGPT_SR_IF1_MASK (0x8U)XGPT_SR_IF1_SHIFT (3U)XGPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)XGPT_SR_IF2_MASK (0x10U)XGPT_SR_IF2_SHIFT (4U)XGPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)XGPT_SR_ROV_MASK (0x20U)XGPT_SR_ROV_SHIFT (5U)XGPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)XGPT_IR_OF1IE_MASK (0x1U)XGPT_IR_OF1IE_SHIFT (0U)XGPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)XGPT_IR_OF2IE_MASK (0x2U)XGPT_IR_OF2IE_SHIFT (1U)XGPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)XGPT_IR_OF3IE_MASK (0x4U)XGPT_IR_OF3IE_SHIFT (2U)XGPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)XGPT_IR_IF1IE_MASK (0x8U)XGPT_IR_IF1IE_SHIFT (3U)XGPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)XGPT_IR_IF2IE_MASK (0x10U)XGPT_IR_IF2IE_SHIFT (4U)XGPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)XGPT_IR_ROVIE_MASK (0x20U)XGPT_IR_ROVIE_SHIFT (5U)XGPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)XGPT_OCR_COMP_MASK (0xFFFFFFFFU)XGPT_OCR_COMP_SHIFT (0U)XGPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)XGPT_OCR_COUNT (3U)XGPT_ICR_CAPT_MASK (0xFFFFFFFFU)XGPT_ICR_CAPT_SHIFT (0U)XGPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)XGPT_ICR_COUNT (2U)XGPT_CNT_COUNT_MASK (0xFFFFFFFFU)XGPT_CNT_COUNT_SHIFT (0U)XGPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)XGPT1_BASE (0x401EC000u)XGPT1 ((GPT_Type *)GPT1_BASE)XGPT2_BASE (0x401F0000u)XGPT2 ((GPT_Type *)GPT2_BASE)XGPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }XGPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }XGPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }YI2S_VERID_FEATURE_MASK (0xFFFFU)YI2S_VERID_FEATURE_SHIFT (0U)YI2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)YI2S_VERID_MINOR_MASK (0xFF0000U)YI2S_VERID_MINOR_SHIFT (16U)YI2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)YI2S_VERID_MAJOR_MASK (0xFF000000U)YI2S_VERID_MAJOR_SHIFT (24U)YI2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)YI2S_PARAM_DATALINE_MASK (0xFU)YI2S_PARAM_DATALINE_SHIFT (0U)YI2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)YI2S_PARAM_FIFO_MASK (0xF00U)YI2S_PARAM_FIFO_SHIFT (8U)YI2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)YI2S_PARAM_FRAME_MASK (0xF0000U)YI2S_PARAM_FRAME_SHIFT (16U)YI2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)YI2S_TCSR_FRDE_MASK (0x1U)YI2S_TCSR_FRDE_SHIFT (0U)YI2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)YI2S_TCSR_FWDE_MASK (0x2U)YI2S_TCSR_FWDE_SHIFT (1U)YI2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)YI2S_TCSR_FRIE_MASK (0x100U)YI2S_TCSR_FRIE_SHIFT (8U)YI2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)YI2S_TCSR_FWIE_MASK (0x200U)YI2S_TCSR_FWIE_SHIFT (9U)YI2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)YI2S_TCSR_FEIE_MASK (0x400U)YI2S_TCSR_FEIE_SHIFT (10U)YI2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)YI2S_TCSR_SEIE_MASK (0x800U)YI2S_TCSR_SEIE_SHIFT (11U)YI2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)YI2S_TCSR_WSIE_MASK (0x1000U)YI2S_TCSR_WSIE_SHIFT (12U)YI2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)YI2S_TCSR_FRF_MASK (0x10000U)YI2S_TCSR_FRF_SHIFT (16U)YI2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)YI2S_TCSR_FWF_MASK (0x20000U)YI2S_TCSR_FWF_SHIFT (17U)YI2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)YI2S_TCSR_FEF_MASK (0x40000U)YI2S_TCSR_FEF_SHIFT (18U)YI2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)YI2S_TCSR_SEF_MASK (0x80000U)YI2S_TCSR_SEF_SHIFT (19U)YI2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)YI2S_TCSR_WSF_MASK (0x100000U)YI2S_TCSR_WSF_SHIFT (20U)YI2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)YI2S_TCSR_SR_MASK (0x1000000U)YI2S_TCSR_SR_SHIFT (24U)YI2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)YI2S_TCSR_FR_MASK (0x2000000U)YI2S_TCSR_FR_SHIFT (25U)YI2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)YI2S_TCSR_BCE_MASK (0x10000000U)YI2S_TCSR_BCE_SHIFT (28U)YI2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)YI2S_TCSR_DBGE_MASK (0x20000000U)YI2S_TCSR_DBGE_SHIFT (29U)YI2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)YI2S_TCSR_STOPE_MASK (0x40000000U)YI2S_TCSR_STOPE_SHIFT (30U)YI2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)YI2S_TCSR_TE_MASK (0x80000000U)YI2S_TCSR_TE_SHIFT (31U)YI2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)YI2S_TCR1_TFW_MASK (0x1FU)YI2S_TCR1_TFW_SHIFT (0U)YI2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)YI2S_TCR2_DIV_MASK (0xFFU)YI2S_TCR2_DIV_SHIFT (0U)YI2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)YI2S_TCR2_BCD_MASK (0x1000000U)YI2S_TCR2_BCD_SHIFT (24U)YI2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)YI2S_TCR2_BCP_MASK (0x2000000U)YI2S_TCR2_BCP_SHIFT (25U)YI2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)YI2S_TCR2_MSEL_MASK (0xC000000U)YI2S_TCR2_MSEL_SHIFT (26U)YI2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)YI2S_TCR2_BCI_MASK (0x10000000U)YI2S_TCR2_BCI_SHIFT (28U)YI2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)YI2S_TCR2_BCS_MASK (0x20000000U)YI2S_TCR2_BCS_SHIFT (29U)YI2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)YI2S_TCR2_SYNC_MASK (0xC0000000U)YI2S_TCR2_SYNC_SHIFT (30U)YI2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)YI2S_TCR3_WDFL_MASK (0x1FU)YI2S_TCR3_WDFL_SHIFT (0U)ZI2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)ZI2S_TCR3_TCE_MASK (0xF0000U)ZI2S_TCR3_TCE_SHIFT (16U)ZI2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)ZI2S_TCR3_CFR_MASK (0xF000000U)ZI2S_TCR3_CFR_SHIFT (24U)ZI2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)ZI2S_TCR4_FSD_MASK (0x1U)ZI2S_TCR4_FSD_SHIFT (0U)ZI2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)ZI2S_TCR4_FSP_MASK (0x2U)ZI2S_TCR4_FSP_SHIFT (1U)ZI2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)ZI2S_TCR4_ONDEM_MASK (0x4U)ZI2S_TCR4_ONDEM_SHIFT (2U)ZI2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)ZI2S_TCR4_FSE_MASK (0x8U)ZI2S_TCR4_FSE_SHIFT (3U)ZI2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)ZI2S_TCR4_MF_MASK (0x10U)ZI2S_TCR4_MF_SHIFT (4U)ZI2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)ZI2S_TCR4_CHMOD_MASK (0x20U)ZI2S_TCR4_CHMOD_SHIFT (5U)ZI2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)ZI2S_TCR4_SYWD_MASK (0x1F00U)ZI2S_TCR4_SYWD_SHIFT (8U)ZI2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)ZI2S_TCR4_FRSZ_MASK (0x1F0000U)ZI2S_TCR4_FRSZ_SHIFT (16U)ZI2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)ZI2S_TCR4_FPACK_MASK (0x3000000U)ZI2S_TCR4_FPACK_SHIFT (24U)ZI2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)ZI2S_TCR4_FCOMB_MASK (0xC000000U)ZI2S_TCR4_FCOMB_SHIFT (26U)ZI2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)ZI2S_TCR4_FCONT_MASK (0x10000000U)ZI2S_TCR4_FCONT_SHIFT (28U)ZI2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)ZI2S_TCR5_FBT_MASK (0x1F00U)ZI2S_TCR5_FBT_SHIFT (8U)ZI2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)ZI2S_TCR5_W0W_MASK (0x1F0000U)ZI2S_TCR5_W0W_SHIFT (16U)ZI2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)ZI2S_TCR5_WNW_MASK (0x1F000000U)ZI2S_TCR5_WNW_SHIFT (24U)ZI2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)ZI2S_TDR_TDR_MASK (0xFFFFFFFFU)ZI2S_TDR_TDR_SHIFT (0U)ZI2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)ZI2S_TDR_COUNT (4U)ZI2S_TFR_RFP_MASK (0x3FU)ZI2S_TFR_RFP_SHIFT (0U)ZI2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)ZI2S_TFR_WFP_MASK (0x3F0000U)ZI2S_TFR_WFP_SHIFT (16U)ZI2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)ZI2S_TFR_WCP_MASK (0x80000000U)ZI2S_TFR_WCP_SHIFT (31U)ZI2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)ZI2S_TFR_COUNT (4U)ZI2S_TMR_TWM_MASK (0xFFFFFFFFU)ZI2S_TMR_TWM_SHIFT (0U)ZI2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)ZI2S_RCSR_FRDE_MASK (0x1U)ZI2S_RCSR_FRDE_SHIFT (0U)ZI2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)ZI2S_RCSR_FWDE_MASK (0x2U)ZI2S_RCSR_FWDE_SHIFT (1U)ZI2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)ZI2S_RCSR_FRIE_MASK (0x100U)ZI2S_RCSR_FRIE_SHIFT (8U)ZI2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)ZI2S_RCSR_FWIE_MASK (0x200U)ZI2S_RCSR_FWIE_SHIFT (9U)ZI2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)ZI2S_RCSR_FEIE_MASK (0x400U)ZI2S_RCSR_FEIE_SHIFT (10U)ZI2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)ZI2S_RCSR_SEIE_MASK (0x800U)ZI2S_RCSR_SEIE_SHIFT (11U)ZI2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)ZI2S_RCSR_WSIE_MASK (0x1000U)ZI2S_RCSR_WSIE_SHIFT (12U)ZI2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)ZI2S_RCSR_FRF_MASK (0x10000U)ZI2S_RCSR_FRF_SHIFT (16U)ZI2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)ZI2S_RCSR_FWF_MASK (0x20000U)ZI2S_RCSR_FWF_SHIFT (17U)ZI2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)ZI2S_RCSR_FEF_MASK (0x40000U)ZI2S_RCSR_FEF_SHIFT (18U)ZI2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)ZI2S_RCSR_SEF_MASK (0x80000U)ZI2S_RCSR_SEF_SHIFT (19U)ZI2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)ZI2S_RCSR_WSF_MASK (0x100000U)ZI2S_RCSR_WSF_SHIFT (20U)ZI2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)ZI2S_RCSR_SR_MASK (0x1000000U)ZI2S_RCSR_SR_SHIFT (24U)ZI2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)ZI2S_RCSR_FR_MASK (0x2000000U)ZI2S_RCSR_FR_SHIFT (25U)ZI2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)ZI2S_RCSR_BCE_MASK (0x10000000U)ZI2S_RCSR_BCE_SHIFT (28U)ZI2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)ZI2S_RCSR_DBGE_MASK (0x20000000U)[I2S_RCSR_DBGE_SHIFT (29U)[I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)[I2S_RCSR_STOPE_MASK (0x40000000U)[I2S_RCSR_STOPE_SHIFT (30U)[I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)[I2S_RCSR_RE_MASK (0x80000000U)[I2S_RCSR_RE_SHIFT (31U)[I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)[I2S_RCR1_RFW_MASK (0x1FU)[I2S_RCR1_RFW_SHIFT (0U)[I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)[I2S_RCR2_DIV_MASK (0xFFU)[I2S_RCR2_DIV_SHIFT (0U)[I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)[I2S_RCR2_BCD_MASK (0x1000000U)[I2S_RCR2_BCD_SHIFT (24U)[I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)[I2S_RCR2_BCP_MASK (0x2000000U)[I2S_RCR2_BCP_SHIFT (25U)[I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)[I2S_RCR2_MSEL_MASK (0xC000000U)[I2S_RCR2_MSEL_SHIFT (26U)[I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)[I2S_RCR2_BCI_MASK (0x10000000U)[I2S_RCR2_BCI_SHIFT (28U)[I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)[I2S_RCR2_BCS_MASK (0x20000000U)[I2S_RCR2_BCS_SHIFT (29U)[I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)[I2S_RCR2_SYNC_MASK (0xC0000000U)[I2S_RCR2_SYNC_SHIFT (30U)[I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)[I2S_RCR3_WDFL_MASK (0x1FU)[I2S_RCR3_WDFL_SHIFT (0U)[I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)[I2S_RCR3_RCE_MASK (0xF0000U)[I2S_RCR3_RCE_SHIFT (16U)[I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)[I2S_RCR3_CFR_MASK (0xF000000U)[I2S_RCR3_CFR_SHIFT (24U)[I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)[I2S_RCR4_FSD_MASK (0x1U)[I2S_RCR4_FSD_SHIFT (0U)[I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)[I2S_RCR4_FSP_MASK (0x2U)[I2S_RCR4_FSP_SHIFT (1U)[I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)[I2S_RCR4_ONDEM_MASK (0x4U)[I2S_RCR4_ONDEM_SHIFT (2U)[I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)[I2S_RCR4_FSE_MASK (0x8U)[I2S_RCR4_FSE_SHIFT (3U)[I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)[I2S_RCR4_MF_MASK (0x10U)[I2S_RCR4_MF_SHIFT (4U)[I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)[I2S_RCR4_SYWD_MASK (0x1F00U)[I2S_RCR4_SYWD_SHIFT (8U)[I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)[I2S_RCR4_FRSZ_MASK (0x1F0000U)[I2S_RCR4_FRSZ_SHIFT (16U)[I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)[I2S_RCR4_FPACK_MASK (0x3000000U)[I2S_RCR4_FPACK_SHIFT (24U)[I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)[I2S_RCR4_FCOMB_MASK (0xC000000U)[I2S_RCR4_FCOMB_SHIFT (26U)[I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)[I2S_RCR4_FCONT_MASK (0x10000000U)[I2S_RCR4_FCONT_SHIFT (28U)[I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)[I2S_RCR5_FBT_MASK (0x1F00U)[I2S_RCR5_FBT_SHIFT (8U)[I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)[I2S_RCR5_W0W_MASK (0x1F0000U)[I2S_RCR5_W0W_SHIFT (16U)[I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)[I2S_RCR5_WNW_MASK (0x1F000000U)[I2S_RCR5_WNW_SHIFT (24U)[I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)[I2S_RDR_RDR_MASK (0xFFFFFFFFU)[I2S_RDR_RDR_SHIFT (0U)[I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)[I2S_RDR_COUNT (4U)[I2S_RFR_RFP_MASK (0x3FU)[I2S_RFR_RFP_SHIFT (0U)[I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)[I2S_RFR_RCP_MASK (0x8000U)[I2S_RFR_RCP_SHIFT (15U)[I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)[I2S_RFR_WFP_MASK (0x3F0000U)[I2S_RFR_WFP_SHIFT (16U)[I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)[I2S_RFR_COUNT (4U)[I2S_RMR_RWM_MASK (0xFFFFFFFFU)[I2S_RMR_RWM_SHIFT (0U)[I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)[SAI1_BASE (0x40384000u)\SAI1 ((I2S_Type *)SAI1_BASE)\SAI2_BASE (0x40388000u)\SAI2 ((I2S_Type *)SAI2_BASE)\SAI3_BASE (0x4038C000u)\SAI3 ((I2S_Type *)SAI3_BASE)\I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }\I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }\I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }\I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }\IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)\IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)\IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)\IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)\IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)\IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)\IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)\IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)\IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)\IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)\IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)\IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)\IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)\IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)\IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)\IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)\IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)\IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)\IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)\IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)\IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)\IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)\IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)\IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)\IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)\IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)\IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)\IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)\IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)\IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)\IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)\IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)\IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U)\IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)\IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)\IOMUXC_SELECT_INPUT_COUNT (154U)\IOMUXC_BASE (0x401F8000u)\IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)\IOMUXC_BASE_ADDRS { IOMUXC_BASE }\IOMUXC_BASE_PTRS { IOMUXC }]IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)]IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)]IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)]IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)]IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)]IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)]IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)]IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)]IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)]IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)]IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)]IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)]IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)]IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)]IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)]IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)]IOMUXC_GPR_GPR1_GINT_SHIFT (12U)]IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)]IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)]IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)]IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)]IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)]IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)]IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)]IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)]IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)]IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)]IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)]IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)]IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)]IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)]IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)]IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)]IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)]IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)]IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)]IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)]IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)]IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)]IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)]IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)]IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)]IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)]IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)]IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)]IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)]IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)]IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)]IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)]IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)]IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)]IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)]IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)]IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)]IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)]IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)]IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)]IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)]IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)]IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)]IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)]IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)]IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)]IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)]IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)]IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)]IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)]IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)]IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)]IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)]IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)]IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)]IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)]IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)]IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)]IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)]IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)]IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)]IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)]IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)]IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)]IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)]IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)]IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)^IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)^IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)^IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)^IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)^IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)^IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)^IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)^IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)^IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)^IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)^IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)^IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)^IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)^IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)^IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)^IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)^IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)^IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)^IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)^IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)^IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)^IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)^IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)^IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)^IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)^IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)^IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)^IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)^IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)^IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)^IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)^IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)^IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)^IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)^IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)^IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)^IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)^IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)^IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)^IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)^IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)^IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)^IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)^IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)^IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)^IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)^IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)^IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)^IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)^IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)^IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U)^IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U)^IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK)^IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)^IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)^IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)^IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)^IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)^IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)^IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)^IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)^IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)^IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)^IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)^IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)^IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)^IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)^IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)^IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)^IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)^IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)^IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)^IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)_IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)_IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)_IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)_IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)_IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)_IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)_IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)_IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)_IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)_IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)_IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)_IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)_IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)_IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)_IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)_IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)_IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)_IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)_IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)_IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)_IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)_IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)_IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)_IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)_IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)_IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)_IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)_IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)_IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)_IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)_IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)_IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)_IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)_IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)_IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)_IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)_IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)_IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)_IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)_IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)_IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)_IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)_IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)_IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)_IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)_IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)_IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)_IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)_IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)_IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)_IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)_IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)_IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)_IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)_IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)`IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)`IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)`IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)`IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)`IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)`IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)`IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)`IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)`IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)`IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)`IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)`IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)`IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)`IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)`IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)`IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)`IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)`IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)`IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)`IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)`IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)`IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)`IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)`IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)`IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)`IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)`IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)`IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)`IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)`IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)`IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)`IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)`IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)`IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)`IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)`IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)`IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)`IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)`IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)`IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)`IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)`IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)`IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)`IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)`IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)`IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)`IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)`IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)`IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)`IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)`IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)`IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)`IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)`IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)`IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)`IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)`IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)`IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)`IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)`IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)`IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)`IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)`IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)`IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)`IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)`IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)`IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)`IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)`IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)`IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)`IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)`IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)`IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)`IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)`IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)`IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)`IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)`IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)`IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)`IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)`IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)`IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)`IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)`IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)`IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)aIOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)aIOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)aIOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)aIOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)aIOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)aIOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)aIOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)aIOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)aIOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)aIOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)aIOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)aIOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)aIOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)aIOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)aIOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)aIOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)aIOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)aIOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)aIOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)aIOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)aIOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)aIOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)aIOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)aIOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)aIOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)aIOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)aIOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)aIOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)aIOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)aIOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)aIOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)aIOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)aIOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)aIOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)aIOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)aIOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)aIOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)aIOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)aIOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)aIOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)aIOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)aIOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)aIOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)aIOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)aIOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)aIOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)aIOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)aIOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)aIOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)aIOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)aIOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)aIOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)aIOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)aIOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)aIOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)aIOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)aIOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)aIOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)aIOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)aIOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)aIOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)aIOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)aIOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)aIOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)aIOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)aIOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)aIOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)aIOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)aIOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)aIOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)aIOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)aIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)aIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)aIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)aIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)aIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)aIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)aIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)aIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)aIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)bIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)bIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)bIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)bIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)bIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)bIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)bIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)bIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)bIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)bIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)bIOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)bIOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)bIOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)bIOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)bIOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)bIOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)bIOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)bIOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)bIOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)bIOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)bIOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)bIOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK (0xF0000U)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT (16U)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK (0xF00000U)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT (20U)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK)bIOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)bIOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)bIOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)bIOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)bIOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)bIOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)bIOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)bIOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)bIOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)bIOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U)bIOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U)bIOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)bIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)bIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)bIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)bIOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)bIOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)bIOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)bIOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)bIOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)bIOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)bIOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)bIOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)bIOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)bIOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)bIOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)bIOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)bIOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)bIOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)bIOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)bIOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)bIOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)bIOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)bIOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)bIOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)bIOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)bIOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)bIOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)bIOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)bIOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)bIOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)bIOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)bIOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK)bIOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)bIOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)bIOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)bIOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)bIOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)bIOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U)bIOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK)bIOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)bIOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)bIOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)bIOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)bIOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)bIOMUXC_GPR_BASE (0x400AC000u)bIOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)bIOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }bIOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)dIOMUXC_SNVS_BASE (0x400A8000u)dIOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)dIOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }dIOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }eIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)eIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)eIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)eIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)eIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)eIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)eIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)eIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK (0x10000U)eIOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT (16U)eIOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)eIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)eIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)eIOMUXC_SNVS_GPR_BASE (0x400A4000u)eIOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)eIOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }eIOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }eKPP_KPCR_KRE_MASK (0xFFU)eKPP_KPCR_KRE_SHIFT (0U)eKPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)eKPP_KPCR_KCO_MASK (0xFF00U)eKPP_KPCR_KCO_SHIFT (8U)eKPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)eKPP_KPSR_KPKD_MASK (0x1U)eKPP_KPSR_KPKD_SHIFT (0U)eKPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)eKPP_KPSR_KPKR_MASK (0x2U)eKPP_KPSR_KPKR_SHIFT (1U)eKPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)eKPP_KPSR_KDSC_MASK (0x4U)eKPP_KPSR_KDSC_SHIFT (2U)eKPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)eKPP_KPSR_KRSS_MASK (0x8U)eKPP_KPSR_KRSS_SHIFT (3U)eKPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)eKPP_KPSR_KDIE_MASK (0x100U)eKPP_KPSR_KDIE_SHIFT (8U)eKPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)eKPP_KPSR_KRIE_MASK (0x200U)eKPP_KPSR_KRIE_SHIFT (9U)eKPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)eKPP_KDDR_KRDD_MASK (0xFFU)eKPP_KDDR_KRDD_SHIFT (0U)eKPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)eKPP_KDDR_KCDD_MASK (0xFF00U)eKPP_KDDR_KCDD_SHIFT (8U)eKPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)eKPP_KPDR_KRD_MASK (0xFFU)eKPP_KPDR_KRD_SHIFT (0U)eKPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)eKPP_KPDR_KCD_MASK (0xFF00U)eKPP_KPDR_KCD_SHIFT (8U)eKPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)fKPP_BASE (0x401FC000u)fKPP ((KPP_Type *)KPP_BASE)fKPP_BASE_ADDRS { KPP_BASE }fKPP_BASE_PTRS { KPP }fKPP_IRQS { KPP_IRQn }fLCDIF_CTRL_RUN_MASK (0x1U)fLCDIF_CTRL_RUN_SHIFT (0U)fLCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)fLCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)fLCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)fLCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)fLCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)fLCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)fLCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)fLCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)fLCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)fLCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)fLCDIF_CTRL_RSRVD0_MASK (0x10U)fLCDIF_CTRL_RSRVD0_SHIFT (4U)fLCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)fLCDIF_CTRL_MASTER_MASK (0x20U)fLCDIF_CTRL_MASTER_SHIFT (5U)fLCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)fLCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)fLCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)fLCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)gLCDIF_CTRL_WORD_LENGTH_MASK (0x300U)gLCDIF_CTRL_WORD_LENGTH_SHIFT (8U)gLCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)gLCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)gLCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)gLCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)gLCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)gLCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)gLCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)gLCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)gLCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)gLCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)gLCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)gLCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)gLCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)gLCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)gLCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)gLCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)gLCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)gLCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)gLCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)gLCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)gLCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)gLCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)gLCDIF_CTRL_CLKGATE_MASK (0x40000000U)gLCDIF_CTRL_CLKGATE_SHIFT (30U)gLCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)gLCDIF_CTRL_SFTRST_MASK (0x80000000U)gLCDIF_CTRL_SFTRST_SHIFT (31U)gLCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)gLCDIF_CTRL_SET_RUN_MASK (0x1U)gLCDIF_CTRL_SET_RUN_SHIFT (0U)gLCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)gLCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)gLCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)gLCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)gLCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)gLCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)gLCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)gLCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)gLCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)gLCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)gLCDIF_CTRL_SET_RSRVD0_MASK (0x10U)gLCDIF_CTRL_SET_RSRVD0_SHIFT (4U)gLCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)gLCDIF_CTRL_SET_MASTER_MASK (0x20U)gLCDIF_CTRL_SET_MASTER_SHIFT (5U)gLCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)gLCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)gLCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)gLCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)gLCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)gLCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)gLCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)gLCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)gLCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)gLCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)gLCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)gLCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)gLCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)gLCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)gLCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)gLCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)gLCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)gLCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)gLCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)gLCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)gLCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)gLCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)gLCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)gLCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)gLCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)gLCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)gLCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)gLCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)gLCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)gLCDIF_CTRL_SET_CLKGATE_SHIFT (30U)gLCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)gLCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)gLCDIF_CTRL_SET_SFTRST_SHIFT (31U)gLCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)gLCDIF_CTRL_CLR_RUN_MASK (0x1U)gLCDIF_CTRL_CLR_RUN_SHIFT (0U)gLCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)gLCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)gLCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)gLCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)gLCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)gLCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)gLCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)gLCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)gLCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)gLCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)gLCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)gLCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)gLCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)gLCDIF_CTRL_CLR_MASTER_MASK (0x20U)gLCDIF_CTRL_CLR_MASTER_SHIFT (5U)gLCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)gLCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)gLCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)gLCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)gLCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)gLCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)gLCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)gLCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)gLCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)gLCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)gLCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)gLCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)gLCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)gLCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)gLCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)gLCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)gLCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)gLCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)gLCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)gLCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)gLCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)gLCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)gLCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)gLCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)gLCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)gLCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)hLCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)hLCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)hLCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)hLCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)hLCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)hLCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)hLCDIF_CTRL_CLR_SFTRST_SHIFT (31U)hLCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)hLCDIF_CTRL_TOG_RUN_MASK (0x1U)hLCDIF_CTRL_TOG_RUN_SHIFT (0U)hLCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)hLCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)hLCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)hLCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)hLCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)hLCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)hLCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)hLCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)hLCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)hLCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)hLCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)hLCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)hLCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)hLCDIF_CTRL_TOG_MASTER_MASK (0x20U)hLCDIF_CTRL_TOG_MASTER_SHIFT (5U)hLCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)hLCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)hLCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)hLCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)hLCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)hLCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)hLCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)hLCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)hLCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)hLCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)hLCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)hLCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)hLCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)hLCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)hLCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)hLCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)hLCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)hLCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)hLCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)hLCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)hLCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)hLCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)hLCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)hLCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)hLCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)hLCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)hLCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)hLCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)hLCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)hLCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)hLCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)hLCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)hLCDIF_CTRL_TOG_SFTRST_SHIFT (31U)hLCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)hLCDIF_CTRL1_RSRVD0_MASK (0xF8U)hLCDIF_CTRL1_RSRVD0_SHIFT (3U)hLCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)hLCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)hLCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)hLCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)hLCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)hLCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)hLCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)hLCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)hLCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)hLCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)hLCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)hLCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)hLCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)hLCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)hLCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)hLCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)hLCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)hLCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)hLCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)hLCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)hLCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)hLCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)hLCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)hLCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)hLCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)hLCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)hLCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)hLCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)hLCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)hLCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)hLCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)hLCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)hLCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)hLCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)hLCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)hLCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)hLCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)hLCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)hLCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)hLCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)hLCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)hLCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)hLCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)hLCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)hLCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)hLCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)hLCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)hLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)hLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)hLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)iLCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)iLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)iLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)iLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)iLCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)iLCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)iLCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)iLCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)iLCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)iLCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)iLCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)iLCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)iLCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)iLCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)iLCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)iLCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)iLCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)iLCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)iLCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)iLCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)iLCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)iLCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)iLCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)iLCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)iLCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)iLCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)iLCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)iLCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)iLCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)iLCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)iLCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)iLCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)iLCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)iLCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)iLCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)iLCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)iLCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)iLCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)iLCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)iLCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)iLCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)iLCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)iLCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)iLCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)iLCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)iLCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)iLCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)iLCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)iLCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)iLCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)iLCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)iLCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)iLCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)iLCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)iLCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)iLCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)iLCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)iLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)iLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)iLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)iLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)iLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)iLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)iLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)iLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)iLCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)iLCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)iLCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)iLCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)iLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)jLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)jLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)jLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)jLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)jLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)jLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)jLCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)jLCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)jLCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)jLCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)jLCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)jLCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)jLCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)jLCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)jLCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)jLCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)jLCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)jLCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)jLCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)jLCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)jLCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)jLCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)jLCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)jLCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)jLCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)jLCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)jLCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)jLCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)jLCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)jLCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)jLCDIF_CTRL2_RSRVD0_MASK (0xFFFU)jLCDIF_CTRL2_RSRVD0_SHIFT (0U)jLCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)jLCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)jLCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)jLCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)jLCDIF_CTRL2_RSRVD3_MASK (0x8000U)jLCDIF_CTRL2_RSRVD3_SHIFT (15U)jLCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)jLCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)jLCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)jLCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)jLCDIF_CTRL2_RSRVD4_MASK (0x80000U)jLCDIF_CTRL2_RSRVD4_SHIFT (19U)jLCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)jLCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)jLCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)jLCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)jLCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)jLCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)jLCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)jLCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)jLCDIF_CTRL2_RSRVD5_SHIFT (24U)jLCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)jLCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)jLCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)jLCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)jLCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)jLCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)jLCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)jLCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)jLCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)jLCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)jLCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)jLCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)jLCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)jLCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)jLCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)jLCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)jLCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)jLCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)jLCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)jLCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)jLCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)jLCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)jLCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)jLCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)jLCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)jLCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)jLCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)jLCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)jLCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)jLCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)jLCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)jLCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)jLCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)jLCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)jLCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)jLCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)jLCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)jLCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)jLCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)jLCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)jLCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)jLCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)jLCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)jLCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)jLCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)jLCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)jLCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)jLCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)jLCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)jLCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)jLCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)jLCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)jLCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)jLCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)jLCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)jLCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)kLCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)kLCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)kLCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)kLCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)kLCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)kLCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)kLCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)kLCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)kLCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)kLCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)kLCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)kLCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)kLCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)kLCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)kLCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)kLCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)kLCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)kLCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)kLCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)kLCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)kLCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)kLCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)kLCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)kLCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)kLCDIF_CUR_BUF_ADDR_SHIFT (0U)kLCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)kLCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)kLCDIF_NEXT_BUF_ADDR_SHIFT (0U)kLCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)kLCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)kLCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)kLCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)kLCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)kLCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)kLCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)kLCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)kLCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)kLCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)kLCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)kLCDIF_VDCTRL0_RSRVD1_SHIFT (22U)kLCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)kLCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)kLCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)kLCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)kLCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)kLCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)kLCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)kLCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)kLCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)kLCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)kLCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)kLCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)kLCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)kLCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)kLCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)kLCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)kLCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)kLCDIF_VDCTRL0_RSRVD2_SHIFT (29U)kLCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)kLCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)kLCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)kLCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)kLCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)kLCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)kLCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)kLCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)kLCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)kLCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)kLCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)kLCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)kLCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)kLCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)kLCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)kLCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)kLCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)kLCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)kLCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)kLCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)kLCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)kLCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)kLCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)kLCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)kLCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)kLCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)kLCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)kLCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)kLCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)kLCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)kLCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)kLCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)kLCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)kLCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)kLCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)kLCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)kLCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)kLCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)kLCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)kLCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)lLCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)lLCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)lLCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)lLCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)lLCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)lLCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)lLCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)lLCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)lLCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)lLCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)lLCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)lLCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)lLCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)lLCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)lLCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)lLCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)lLCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)lLCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)lLCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)lLCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)lLCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)lLCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)lLCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)lLCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)lLCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)lLCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)lLCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)lLCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)lLCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)lLCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)lLCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)lLCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)lLCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)lLCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)lLCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)lLCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)lLCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)lLCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)lLCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)lLCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)lLCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)lLCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)lLCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)lLCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)lLCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)lLCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)lLCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)lLCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)lLCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)lLCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)lLCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)lLCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)lLCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)lLCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)lLCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)lLCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)lLCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)lLCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)lLCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)lLCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)lLCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)lLCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)lLCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)lLCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)lLCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)lLCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)lLCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)lLCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)lLCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)lLCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)lLCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)lLCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)lLCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)lLCDIF_VDCTRL3_RSRVD0_SHIFT (30U)lLCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)lLCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)lLCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)lLCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)lLCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)lLCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)lLCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)lLCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)lLCDIF_VDCTRL4_RSRVD0_SHIFT (19U)lLCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)lLCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)lLCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)lLCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)lLCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)lLCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)lLCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)lLCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)lLCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)lLCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)lLCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)lLCDIF_STAT_LFIFO_COUNT_SHIFT (0U)lLCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)lLCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)lLCDIF_STAT_RSRVD0_SHIFT (9U)lLCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)lLCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)lLCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)lLCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)lLCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)lLCDIF_STAT_TXFIFO_FULL_SHIFT (27U)lLCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)lLCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)mLCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)mLCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)mLCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)mLCDIF_STAT_LFIFO_FULL_SHIFT (29U)mLCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)mLCDIF_STAT_DMA_REQ_MASK (0x40000000U)mLCDIF_STAT_DMA_REQ_SHIFT (30U)mLCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)mLCDIF_STAT_PRESENT_MASK (0x80000000U)mLCDIF_STAT_PRESENT_SHIFT (31U)mLCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)mLCDIF_THRES_PANIC_MASK (0x1FFU)mLCDIF_THRES_PANIC_SHIFT (0U)mLCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK)mLCDIF_THRES_RSRVD1_MASK (0xFE00U)mLCDIF_THRES_RSRVD1_SHIFT (9U)mLCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)mLCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)mLCDIF_THRES_FASTCLOCK_SHIFT (16U)mLCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)mLCDIF_THRES_RSRVD2_MASK (0xFE000000U)mLCDIF_THRES_RSRVD2_SHIFT (25U)mLCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)mLCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)mLCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)mLCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)mLCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)mLCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)mLCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)mLCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)mLCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)mLCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)mLCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)mLCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)mLCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)mLCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)mLCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)mLCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)mLCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)mLCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)mLCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)mLCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)mLCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)mLCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)mLCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)mLCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)mLCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)mLCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)mLCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)mLCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)mLCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)mLCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)mLCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)mLCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)mLCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)mLCDIF_PIGEON_0_EN_MASK (0x1U)mLCDIF_PIGEON_0_EN_SHIFT (0U)mLCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)mLCDIF_PIGEON_0_POL_MASK (0x2U)mLCDIF_PIGEON_0_POL_SHIFT (1U)nLCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)nLCDIF_PIGEON_0_INC_SEL_MASK (0xCU)nLCDIF_PIGEON_0_INC_SEL_SHIFT (2U)nLCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)nLCDIF_PIGEON_0_OFFSET_MASK (0xF0U)nLCDIF_PIGEON_0_OFFSET_SHIFT (4U)nLCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)nLCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)nLCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)nLCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)nLCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)nLCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)nLCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)nLCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)nLCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)nLCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)nLCDIF_PIGEON_0_COUNT (12U)nLCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)nLCDIF_PIGEON_1_SET_CNT_SHIFT (0U)nLCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)nLCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)nLCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)nLCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)nLCDIF_PIGEON_1_COUNT (12U)nLCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)nLCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)nLCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)nLCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)nLCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)nLCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)nLCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)nLCDIF_PIGEON_2_RSVD_SHIFT (9U)nLCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)nLCDIF_PIGEON_2_COUNT (12U)nLCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)nLCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)nLCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)nLCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)nLCDIF_LUT0_ADDR_ADDR_SHIFT (0U)nLCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)nLCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)nLCDIF_LUT0_DATA_DATA_SHIFT (0U)nLCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)nLCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)nLCDIF_LUT1_ADDR_ADDR_SHIFT (0U)nLCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)nLCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)nLCDIF_LUT1_DATA_DATA_SHIFT (0U)nLCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)nLCDIF_BASE (0x402B8000u)nLCDIF ((LCDIF_Type *)LCDIF_BASE)nLCDIF_BASE_ADDRS { LCDIF_BASE }nLCDIF_BASE_PTRS { LCDIF }nLCDIF_IRQ0_IRQS { LCDIF_IRQn }oLPI2C_VERID_FEATURE_MASK (0xFFFFU)oLPI2C_VERID_FEATURE_SHIFT (0U)oLPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)oLPI2C_VERID_MINOR_MASK (0xFF0000U)oLPI2C_VERID_MINOR_SHIFT (16U)oLPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)oLPI2C_VERID_MAJOR_MASK (0xFF000000U)oLPI2C_VERID_MAJOR_SHIFT (24U)oLPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)oLPI2C_PARAM_MTXFIFO_MASK (0xFU)oLPI2C_PARAM_MTXFIFO_SHIFT (0U)oLPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)oLPI2C_PARAM_MRXFIFO_MASK (0xF00U)oLPI2C_PARAM_MRXFIFO_SHIFT (8U)oLPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)oLPI2C_MCR_MEN_MASK (0x1U)oLPI2C_MCR_MEN_SHIFT (0U)oLPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)oLPI2C_MCR_RST_MASK (0x2U)oLPI2C_MCR_RST_SHIFT (1U)oLPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)oLPI2C_MCR_DOZEN_MASK (0x4U)oLPI2C_MCR_DOZEN_SHIFT (2U)oLPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)oLPI2C_MCR_DBGEN_MASK (0x8U)oLPI2C_MCR_DBGEN_SHIFT (3U)oLPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)oLPI2C_MCR_RTF_MASK (0x100U)oLPI2C_MCR_RTF_SHIFT (8U)oLPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)oLPI2C_MCR_RRF_MASK (0x200U)oLPI2C_MCR_RRF_SHIFT (9U)oLPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)oLPI2C_MSR_TDF_MASK (0x1U)oLPI2C_MSR_TDF_SHIFT (0U)oLPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)oLPI2C_MSR_RDF_MASK (0x2U)oLPI2C_MSR_RDF_SHIFT (1U)oLPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)oLPI2C_MSR_EPF_MASK (0x100U)oLPI2C_MSR_EPF_SHIFT (8U)oLPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)oLPI2C_MSR_SDF_MASK (0x200U)oLPI2C_MSR_SDF_SHIFT (9U)oLPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)oLPI2C_MSR_NDF_MASK (0x400U)oLPI2C_MSR_NDF_SHIFT (10U)oLPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)oLPI2C_MSR_ALF_MASK (0x800U)oLPI2C_MSR_ALF_SHIFT (11U)oLPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)oLPI2C_MSR_FEF_MASK (0x1000U)oLPI2C_MSR_FEF_SHIFT (12U)oLPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)oLPI2C_MSR_PLTF_MASK (0x2000U)oLPI2C_MSR_PLTF_SHIFT (13U)oLPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)oLPI2C_MSR_DMF_MASK (0x4000U)oLPI2C_MSR_DMF_SHIFT (14U)oLPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)oLPI2C_MSR_MBF_MASK (0x1000000U)oLPI2C_MSR_MBF_SHIFT (24U)oLPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)oLPI2C_MSR_BBF_MASK (0x2000000U)oLPI2C_MSR_BBF_SHIFT (25U)oLPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)oLPI2C_MIER_TDIE_MASK (0x1U)oLPI2C_MIER_TDIE_SHIFT (0U)oLPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)oLPI2C_MIER_RDIE_MASK (0x2U)oLPI2C_MIER_RDIE_SHIFT (1U)oLPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)oLPI2C_MIER_EPIE_MASK (0x100U)oLPI2C_MIER_EPIE_SHIFT (8U)oLPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)oLPI2C_MIER_SDIE_MASK (0x200U)oLPI2C_MIER_SDIE_SHIFT (9U)oLPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)oLPI2C_MIER_NDIE_MASK (0x400U)oLPI2C_MIER_NDIE_SHIFT (10U)oLPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)oLPI2C_MIER_ALIE_MASK (0x800U)oLPI2C_MIER_ALIE_SHIFT (11U)oLPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)oLPI2C_MIER_FEIE_MASK (0x1000U)oLPI2C_MIER_FEIE_SHIFT (12U)oLPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)oLPI2C_MIER_PLTIE_MASK (0x2000U)oLPI2C_MIER_PLTIE_SHIFT (13U)oLPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)oLPI2C_MIER_DMIE_MASK (0x4000U)oLPI2C_MIER_DMIE_SHIFT (14U)pLPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)pLPI2C_MDER_TDDE_MASK (0x1U)pLPI2C_MDER_TDDE_SHIFT (0U)pLPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)pLPI2C_MDER_RDDE_MASK (0x2U)pLPI2C_MDER_RDDE_SHIFT (1U)pLPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)pLPI2C_MCFGR0_HREN_MASK (0x1U)pLPI2C_MCFGR0_HREN_SHIFT (0U)pLPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)pLPI2C_MCFGR0_HRPOL_MASK (0x2U)pLPI2C_MCFGR0_HRPOL_SHIFT (1U)pLPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)pLPI2C_MCFGR0_HRSEL_MASK (0x4U)pLPI2C_MCFGR0_HRSEL_SHIFT (2U)pLPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)pLPI2C_MCFGR0_CIRFIFO_MASK (0x100U)pLPI2C_MCFGR0_CIRFIFO_SHIFT (8U)pLPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)pLPI2C_MCFGR0_RDMO_MASK (0x200U)pLPI2C_MCFGR0_RDMO_SHIFT (9U)pLPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)pLPI2C_MCFGR1_PRESCALE_MASK (0x7U)pLPI2C_MCFGR1_PRESCALE_SHIFT (0U)pLPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)pLPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)pLPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)pLPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)pLPI2C_MCFGR1_IGNACK_MASK (0x200U)pLPI2C_MCFGR1_IGNACK_SHIFT (9U)pLPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)pLPI2C_MCFGR1_TIMECFG_MASK (0x400U)pLPI2C_MCFGR1_TIMECFG_SHIFT (10U)pLPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)pLPI2C_MCFGR1_MATCFG_MASK (0x70000U)pLPI2C_MCFGR1_MATCFG_SHIFT (16U)pLPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)pLPI2C_MCFGR1_PINCFG_MASK (0x7000000U)pLPI2C_MCFGR1_PINCFG_SHIFT (24U)pLPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)pLPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)pLPI2C_MCFGR2_BUSIDLE_SHIFT (0U)pLPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)pLPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)pLPI2C_MCFGR2_FILTSCL_SHIFT (16U)pLPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)pLPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)pLPI2C_MCFGR2_FILTSDA_SHIFT (24U)pLPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)pLPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)pLPI2C_MCFGR3_PINLOW_SHIFT (8U)pLPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)pLPI2C_MDMR_MATCH0_MASK (0xFFU)pLPI2C_MDMR_MATCH0_SHIFT (0U)pLPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)pLPI2C_MDMR_MATCH1_MASK (0xFF0000U)pLPI2C_MDMR_MATCH1_SHIFT (16U)pLPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)pLPI2C_MCCR0_CLKLO_MASK (0x3FU)pLPI2C_MCCR0_CLKLO_SHIFT (0U)pLPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)pLPI2C_MCCR0_CLKHI_MASK (0x3F00U)pLPI2C_MCCR0_CLKHI_SHIFT (8U)pLPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)pLPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)pLPI2C_MCCR0_SETHOLD_SHIFT (16U)pLPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)pLPI2C_MCCR0_DATAVD_MASK (0x3F000000U)pLPI2C_MCCR0_DATAVD_SHIFT (24U)pLPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)pLPI2C_MCCR1_CLKLO_MASK (0x3FU)pLPI2C_MCCR1_CLKLO_SHIFT (0U)pLPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)pLPI2C_MCCR1_CLKHI_MASK (0x3F00U)pLPI2C_MCCR1_CLKHI_SHIFT (8U)pLPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)pLPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)pLPI2C_MCCR1_SETHOLD_SHIFT (16U)pLPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)pLPI2C_MCCR1_DATAVD_MASK (0x3F000000U)pLPI2C_MCCR1_DATAVD_SHIFT (24U)pLPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)pLPI2C_MFCR_TXWATER_MASK (0x3U)pLPI2C_MFCR_TXWATER_SHIFT (0U)pLPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)pLPI2C_MFCR_RXWATER_MASK (0x30000U)pLPI2C_MFCR_RXWATER_SHIFT (16U)pLPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)pLPI2C_MFSR_TXCOUNT_MASK (0x7U)pLPI2C_MFSR_TXCOUNT_SHIFT (0U)pLPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)pLPI2C_MFSR_RXCOUNT_MASK (0x70000U)pLPI2C_MFSR_RXCOUNT_SHIFT (16U)pLPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)pLPI2C_MTDR_DATA_MASK (0xFFU)pLPI2C_MTDR_DATA_SHIFT (0U)pLPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)pLPI2C_MTDR_CMD_MASK (0x700U)pLPI2C_MTDR_CMD_SHIFT (8U)pLPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)pLPI2C_MRDR_DATA_MASK (0xFFU)pLPI2C_MRDR_DATA_SHIFT (0U)pLPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)pLPI2C_MRDR_RXEMPTY_MASK (0x4000U)qLPI2C_MRDR_RXEMPTY_SHIFT (14U)qLPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)qLPI2C_SCR_SEN_MASK (0x1U)qLPI2C_SCR_SEN_SHIFT (0U)qLPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)qLPI2C_SCR_RST_MASK (0x2U)qLPI2C_SCR_RST_SHIFT (1U)qLPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)qLPI2C_SCR_FILTEN_MASK (0x10U)qLPI2C_SCR_FILTEN_SHIFT (4U)qLPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)qLPI2C_SCR_FILTDZ_MASK (0x20U)qLPI2C_SCR_FILTDZ_SHIFT (5U)qLPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)qLPI2C_SCR_RTF_MASK (0x100U)qLPI2C_SCR_RTF_SHIFT (8U)qLPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)qLPI2C_SCR_RRF_MASK (0x200U)qLPI2C_SCR_RRF_SHIFT (9U)qLPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)qLPI2C_SSR_TDF_MASK (0x1U)qLPI2C_SSR_TDF_SHIFT (0U)qLPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)qLPI2C_SSR_RDF_MASK (0x2U)qLPI2C_SSR_RDF_SHIFT (1U)qLPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)qLPI2C_SSR_AVF_MASK (0x4U)qLPI2C_SSR_AVF_SHIFT (2U)qLPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)qLPI2C_SSR_TAF_MASK (0x8U)qLPI2C_SSR_TAF_SHIFT (3U)qLPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)qLPI2C_SSR_RSF_MASK (0x100U)qLPI2C_SSR_RSF_SHIFT (8U)qLPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)qLPI2C_SSR_SDF_MASK (0x200U)qLPI2C_SSR_SDF_SHIFT (9U)qLPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)qLPI2C_SSR_BEF_MASK (0x400U)qLPI2C_SSR_BEF_SHIFT (10U)qLPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)qLPI2C_SSR_FEF_MASK (0x800U)qLPI2C_SSR_FEF_SHIFT (11U)qLPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)qLPI2C_SSR_AM0F_MASK (0x1000U)qLPI2C_SSR_AM0F_SHIFT (12U)qLPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)qLPI2C_SSR_AM1F_MASK (0x2000U)qLPI2C_SSR_AM1F_SHIFT (13U)qLPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)qLPI2C_SSR_GCF_MASK (0x4000U)qLPI2C_SSR_GCF_SHIFT (14U)qLPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)qLPI2C_SSR_SARF_MASK (0x8000U)qLPI2C_SSR_SARF_SHIFT (15U)qLPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)qLPI2C_SSR_SBF_MASK (0x1000000U)qLPI2C_SSR_SBF_SHIFT (24U)qLPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)qLPI2C_SSR_BBF_MASK (0x2000000U)qLPI2C_SSR_BBF_SHIFT (25U)qLPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)qLPI2C_SIER_TDIE_MASK (0x1U)qLPI2C_SIER_TDIE_SHIFT (0U)qLPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)qLPI2C_SIER_RDIE_MASK (0x2U)qLPI2C_SIER_RDIE_SHIFT (1U)qLPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)qLPI2C_SIER_AVIE_MASK (0x4U)qLPI2C_SIER_AVIE_SHIFT (2U)qLPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)qLPI2C_SIER_TAIE_MASK (0x8U)qLPI2C_SIER_TAIE_SHIFT (3U)qLPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)qLPI2C_SIER_RSIE_MASK (0x100U)qLPI2C_SIER_RSIE_SHIFT (8U)qLPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)qLPI2C_SIER_SDIE_MASK (0x200U)qLPI2C_SIER_SDIE_SHIFT (9U)qLPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)qLPI2C_SIER_BEIE_MASK (0x400U)qLPI2C_SIER_BEIE_SHIFT (10U)qLPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)qLPI2C_SIER_FEIE_MASK (0x800U)qLPI2C_SIER_FEIE_SHIFT (11U)qLPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)qLPI2C_SIER_AM0IE_MASK (0x1000U)qLPI2C_SIER_AM0IE_SHIFT (12U)qLPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)qLPI2C_SIER_AM1F_MASK (0x2000U)qLPI2C_SIER_AM1F_SHIFT (13U)qLPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)qLPI2C_SIER_GCIE_MASK (0x4000U)qLPI2C_SIER_GCIE_SHIFT (14U)qLPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)qLPI2C_SIER_SARIE_MASK (0x8000U)qLPI2C_SIER_SARIE_SHIFT (15U)qLPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)qLPI2C_SDER_TDDE_MASK (0x1U)qLPI2C_SDER_TDDE_SHIFT (0U)qLPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)qLPI2C_SDER_RDDE_MASK (0x2U)qLPI2C_SDER_RDDE_SHIFT (1U)qLPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)qLPI2C_SDER_AVDE_MASK (0x4U)qLPI2C_SDER_AVDE_SHIFT (2U)qLPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)qLPI2C_SCFGR1_ADRSTALL_MASK (0x1U)qLPI2C_SCFGR1_ADRSTALL_SHIFT (0U)qLPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)qLPI2C_SCFGR1_RXSTALL_MASK (0x2U)qLPI2C_SCFGR1_RXSTALL_SHIFT (1U)qLPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)qLPI2C_SCFGR1_TXDSTALL_MASK (0x4U)qLPI2C_SCFGR1_TXDSTALL_SHIFT (2U)qLPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)qLPI2C_SCFGR1_ACKSTALL_MASK (0x8U)qLPI2C_SCFGR1_ACKSTALL_SHIFT (3U)rLPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)rLPI2C_SCFGR1_GCEN_MASK (0x100U)rLPI2C_SCFGR1_GCEN_SHIFT (8U)rLPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)rLPI2C_SCFGR1_SAEN_MASK (0x200U)rLPI2C_SCFGR1_SAEN_SHIFT (9U)rLPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)rLPI2C_SCFGR1_TXCFG_MASK (0x400U)rLPI2C_SCFGR1_TXCFG_SHIFT (10U)rLPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)rLPI2C_SCFGR1_RXCFG_MASK (0x800U)rLPI2C_SCFGR1_RXCFG_SHIFT (11U)rLPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)rLPI2C_SCFGR1_IGNACK_MASK (0x1000U)rLPI2C_SCFGR1_IGNACK_SHIFT (12U)rLPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)rLPI2C_SCFGR1_HSMEN_MASK (0x2000U)rLPI2C_SCFGR1_HSMEN_SHIFT (13U)rLPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)rLPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)rLPI2C_SCFGR1_ADDRCFG_SHIFT (16U)rLPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)rLPI2C_SCFGR2_CLKHOLD_MASK (0xFU)rLPI2C_SCFGR2_CLKHOLD_SHIFT (0U)rLPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)rLPI2C_SCFGR2_DATAVD_MASK (0x3F00U)rLPI2C_SCFGR2_DATAVD_SHIFT (8U)rLPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)rLPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)rLPI2C_SCFGR2_FILTSCL_SHIFT (16U)rLPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)rLPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)rLPI2C_SCFGR2_FILTSDA_SHIFT (24U)rLPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)rLPI2C_SAMR_ADDR0_MASK (0x7FEU)rLPI2C_SAMR_ADDR0_SHIFT (1U)rLPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)rLPI2C_SAMR_ADDR1_MASK (0x7FE0000U)rLPI2C_SAMR_ADDR1_SHIFT (17U)rLPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)rLPI2C_SASR_RADDR_MASK (0x7FFU)rLPI2C_SASR_RADDR_SHIFT (0U)rLPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)rLPI2C_SASR_ANV_MASK (0x4000U)rLPI2C_SASR_ANV_SHIFT (14U)rLPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)rLPI2C_STAR_TXNACK_MASK (0x1U)rLPI2C_STAR_TXNACK_SHIFT (0U)rLPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)rLPI2C_STDR_DATA_MASK (0xFFU)rLPI2C_STDR_DATA_SHIFT (0U)rLPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)rLPI2C_SRDR_DATA_MASK (0xFFU)rLPI2C_SRDR_DATA_SHIFT (0U)rLPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)rLPI2C_SRDR_RXEMPTY_MASK (0x4000U)rLPI2C_SRDR_RXEMPTY_SHIFT (14U)rLPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)rLPI2C_SRDR_SOF_MASK (0x8000U)rLPI2C_SRDR_SOF_SHIFT (15U)rLPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)rLPI2C1_BASE (0x403F0000u)rLPI2C1 ((LPI2C_Type *)LPI2C1_BASE)rLPI2C2_BASE (0x403F4000u)rLPI2C2 ((LPI2C_Type *)LPI2C2_BASE)rLPI2C3_BASE (0x403F8000u)rLPI2C3 ((LPI2C_Type *)LPI2C3_BASE)rLPI2C4_BASE (0x403FC000u)rLPI2C4 ((LPI2C_Type *)LPI2C4_BASE)rLPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }rLPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }rLPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }sLPSPI_VERID_FEATURE_MASK (0xFFFFU)sLPSPI_VERID_FEATURE_SHIFT (0U)sLPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)sLPSPI_VERID_MINOR_MASK (0xFF0000U)sLPSPI_VERID_MINOR_SHIFT (16U)sLPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)sLPSPI_VERID_MAJOR_MASK (0xFF000000U)sLPSPI_VERID_MAJOR_SHIFT (24U)sLPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)sLPSPI_PARAM_TXFIFO_MASK (0xFFU)sLPSPI_PARAM_TXFIFO_SHIFT (0U)sLPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)sLPSPI_PARAM_RXFIFO_MASK (0xFF00U)sLPSPI_PARAM_RXFIFO_SHIFT (8U)sLPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)sLPSPI_PARAM_PCSNUM_MASK (0xFF0000U)sLPSPI_PARAM_PCSNUM_SHIFT (16U)sLPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)sLPSPI_CR_MEN_MASK (0x1U)sLPSPI_CR_MEN_SHIFT (0U)sLPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)sLPSPI_CR_RST_MASK (0x2U)sLPSPI_CR_RST_SHIFT (1U)sLPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)sLPSPI_CR_DOZEN_MASK (0x4U)sLPSPI_CR_DOZEN_SHIFT (2U)sLPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)sLPSPI_CR_DBGEN_MASK (0x8U)sLPSPI_CR_DBGEN_SHIFT (3U)sLPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)sLPSPI_CR_RTF_MASK (0x100U)sLPSPI_CR_RTF_SHIFT (8U)sLPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)sLPSPI_CR_RRF_MASK (0x200U)sLPSPI_CR_RRF_SHIFT (9U)sLPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)sLPSPI_SR_TDF_MASK (0x1U)sLPSPI_SR_TDF_SHIFT (0U)sLPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)sLPSPI_SR_RDF_MASK (0x2U)sLPSPI_SR_RDF_SHIFT (1U)sLPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)sLPSPI_SR_WCF_MASK (0x100U)sLPSPI_SR_WCF_SHIFT (8U)sLPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)sLPSPI_SR_FCF_MASK (0x200U)sLPSPI_SR_FCF_SHIFT (9U)sLPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)sLPSPI_SR_TCF_MASK (0x400U)sLPSPI_SR_TCF_SHIFT (10U)sLPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)sLPSPI_SR_TEF_MASK (0x800U)sLPSPI_SR_TEF_SHIFT (11U)sLPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)sLPSPI_SR_REF_MASK (0x1000U)sLPSPI_SR_REF_SHIFT (12U)sLPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)sLPSPI_SR_DMF_MASK (0x2000U)sLPSPI_SR_DMF_SHIFT (13U)sLPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)sLPSPI_SR_MBF_MASK (0x1000000U)sLPSPI_SR_MBF_SHIFT (24U)sLPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)sLPSPI_IER_TDIE_MASK (0x1U)sLPSPI_IER_TDIE_SHIFT (0U)sLPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)sLPSPI_IER_RDIE_MASK (0x2U)sLPSPI_IER_RDIE_SHIFT (1U)sLPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)sLPSPI_IER_WCIE_MASK (0x100U)sLPSPI_IER_WCIE_SHIFT (8U)sLPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)sLPSPI_IER_FCIE_MASK (0x200U)sLPSPI_IER_FCIE_SHIFT (9U)sLPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)sLPSPI_IER_TCIE_MASK (0x400U)sLPSPI_IER_TCIE_SHIFT (10U)sLPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)sLPSPI_IER_TEIE_MASK (0x800U)sLPSPI_IER_TEIE_SHIFT (11U)sLPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)sLPSPI_IER_REIE_MASK (0x1000U)sLPSPI_IER_REIE_SHIFT (12U)sLPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)sLPSPI_IER_DMIE_MASK (0x2000U)sLPSPI_IER_DMIE_SHIFT (13U)sLPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)sLPSPI_DER_TDDE_MASK (0x1U)sLPSPI_DER_TDDE_SHIFT (0U)sLPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)sLPSPI_DER_RDDE_MASK (0x2U)sLPSPI_DER_RDDE_SHIFT (1U)tLPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)tLPSPI_CFGR0_HREN_MASK (0x1U)tLPSPI_CFGR0_HREN_SHIFT (0U)tLPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)tLPSPI_CFGR0_HRPOL_MASK (0x2U)tLPSPI_CFGR0_HRPOL_SHIFT (1U)tLPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)tLPSPI_CFGR0_HRSEL_MASK (0x4U)tLPSPI_CFGR0_HRSEL_SHIFT (2U)tLPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)tLPSPI_CFGR0_CIRFIFO_MASK (0x100U)tLPSPI_CFGR0_CIRFIFO_SHIFT (8U)tLPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)tLPSPI_CFGR0_RDMO_MASK (0x200U)tLPSPI_CFGR0_RDMO_SHIFT (9U)tLPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)tLPSPI_CFGR1_MASTER_MASK (0x1U)tLPSPI_CFGR1_MASTER_SHIFT (0U)tLPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)tLPSPI_CFGR1_SAMPLE_MASK (0x2U)tLPSPI_CFGR1_SAMPLE_SHIFT (1U)tLPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)tLPSPI_CFGR1_AUTOPCS_MASK (0x4U)tLPSPI_CFGR1_AUTOPCS_SHIFT (2U)tLPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)tLPSPI_CFGR1_NOSTALL_MASK (0x8U)tLPSPI_CFGR1_NOSTALL_SHIFT (3U)tLPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)tLPSPI_CFGR1_PCSPOL_MASK (0xF00U)tLPSPI_CFGR1_PCSPOL_SHIFT (8U)tLPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)tLPSPI_CFGR1_MATCFG_MASK (0x70000U)tLPSPI_CFGR1_MATCFG_SHIFT (16U)tLPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)tLPSPI_CFGR1_PINCFG_MASK (0x3000000U)tLPSPI_CFGR1_PINCFG_SHIFT (24U)tLPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)tLPSPI_CFGR1_OUTCFG_MASK (0x4000000U)tLPSPI_CFGR1_OUTCFG_SHIFT (26U)tLPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)tLPSPI_CFGR1_PCSCFG_MASK (0x8000000U)tLPSPI_CFGR1_PCSCFG_SHIFT (27U)tLPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)tLPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)tLPSPI_DMR0_MATCH0_SHIFT (0U)tLPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)tLPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)tLPSPI_DMR1_MATCH1_SHIFT (0U)tLPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)tLPSPI_CCR_SCKDIV_MASK (0xFFU)tLPSPI_CCR_SCKDIV_SHIFT (0U)tLPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)tLPSPI_CCR_DBT_MASK (0xFF00U)tLPSPI_CCR_DBT_SHIFT (8U)tLPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)tLPSPI_CCR_PCSSCK_MASK (0xFF0000U)tLPSPI_CCR_PCSSCK_SHIFT (16U)tLPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)tLPSPI_CCR_SCKPCS_MASK (0xFF000000U)tLPSPI_CCR_SCKPCS_SHIFT (24U)tLPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)tLPSPI_FCR_TXWATER_MASK (0xFU)tLPSPI_FCR_TXWATER_SHIFT (0U)tLPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)tLPSPI_FCR_RXWATER_MASK (0xF0000U)tLPSPI_FCR_RXWATER_SHIFT (16U)tLPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)tLPSPI_FSR_TXCOUNT_MASK (0x1FU)tLPSPI_FSR_TXCOUNT_SHIFT (0U)tLPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)tLPSPI_FSR_RXCOUNT_MASK (0x1F0000U)tLPSPI_FSR_RXCOUNT_SHIFT (16U)tLPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)tLPSPI_TCR_FRAMESZ_MASK (0xFFFU)tLPSPI_TCR_FRAMESZ_SHIFT (0U)tLPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)tLPSPI_TCR_WIDTH_MASK (0x30000U)tLPSPI_TCR_WIDTH_SHIFT (16U)tLPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)tLPSPI_TCR_TXMSK_MASK (0x40000U)tLPSPI_TCR_TXMSK_SHIFT (18U)tLPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)tLPSPI_TCR_RXMSK_MASK (0x80000U)tLPSPI_TCR_RXMSK_SHIFT (19U)tLPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)tLPSPI_TCR_CONTC_MASK (0x100000U)tLPSPI_TCR_CONTC_SHIFT (20U)tLPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)tLPSPI_TCR_CONT_MASK (0x200000U)tLPSPI_TCR_CONT_SHIFT (21U)tLPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)tLPSPI_TCR_BYSW_MASK (0x400000U)tLPSPI_TCR_BYSW_SHIFT (22U)tLPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)tLPSPI_TCR_LSBF_MASK (0x800000U)tLPSPI_TCR_LSBF_SHIFT (23U)tLPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)tLPSPI_TCR_PCS_MASK (0x3000000U)tLPSPI_TCR_PCS_SHIFT (24U)tLPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)tLPSPI_TCR_PRESCALE_MASK (0x38000000U)tLPSPI_TCR_PRESCALE_SHIFT (27U)tLPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)tLPSPI_TCR_CPHA_MASK (0x40000000U)tLPSPI_TCR_CPHA_SHIFT (30U)tLPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)tLPSPI_TCR_CPOL_MASK (0x80000000U)tLPSPI_TCR_CPOL_SHIFT (31U)tLPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)tLPSPI_TDR_DATA_MASK (0xFFFFFFFFU)uLPSPI_TDR_DATA_SHIFT (0U)uLPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)uLPSPI_RSR_SOF_MASK (0x1U)uLPSPI_RSR_SOF_SHIFT (0U)uLPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)uLPSPI_RSR_RXEMPTY_MASK (0x2U)uLPSPI_RSR_RXEMPTY_SHIFT (1U)uLPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)uLPSPI_RDR_DATA_MASK (0xFFFFFFFFU)uLPSPI_RDR_DATA_SHIFT (0U)uLPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)uLPSPI1_BASE (0x40394000u)uLPSPI1 ((LPSPI_Type *)LPSPI1_BASE)uLPSPI2_BASE (0x40398000u)uLPSPI2 ((LPSPI_Type *)LPSPI2_BASE)uLPSPI3_BASE (0x4039C000u)uLPSPI3 ((LPSPI_Type *)LPSPI3_BASE)uLPSPI4_BASE (0x403A0000u)uLPSPI4 ((LPSPI_Type *)LPSPI4_BASE)uLPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }uLPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }uLPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }uLPUART_VERID_FEATURE_MASK (0xFFFFU)uLPUART_VERID_FEATURE_SHIFT (0U)uLPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)uLPUART_VERID_MINOR_MASK (0xFF0000U)uLPUART_VERID_MINOR_SHIFT (16U)uLPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)uLPUART_VERID_MAJOR_MASK (0xFF000000U)uLPUART_VERID_MAJOR_SHIFT (24U)uLPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)uLPUART_PARAM_TXFIFO_MASK (0xFFU)uLPUART_PARAM_TXFIFO_SHIFT (0U)uLPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)uLPUART_PARAM_RXFIFO_MASK (0xFF00U)uLPUART_PARAM_RXFIFO_SHIFT (8U)uLPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)uLPUART_GLOBAL_RST_MASK (0x2U)uLPUART_GLOBAL_RST_SHIFT (1U)uLPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)uLPUART_PINCFG_TRGSEL_MASK (0x3U)uLPUART_PINCFG_TRGSEL_SHIFT (0U)uLPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)uLPUART_BAUD_SBR_MASK (0x1FFFU)uLPUART_BAUD_SBR_SHIFT (0U)uLPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)uLPUART_BAUD_SBNS_MASK (0x2000U)uLPUART_BAUD_SBNS_SHIFT (13U)uLPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)uLPUART_BAUD_RXEDGIE_MASK (0x4000U)uLPUART_BAUD_RXEDGIE_SHIFT (14U)uLPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)uLPUART_BAUD_LBKDIE_MASK (0x8000U)uLPUART_BAUD_LBKDIE_SHIFT (15U)uLPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)uLPUART_BAUD_RESYNCDIS_MASK (0x10000U)vLPUART_BAUD_RESYNCDIS_SHIFT (16U)vLPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)vLPUART_BAUD_BOTHEDGE_MASK (0x20000U)vLPUART_BAUD_BOTHEDGE_SHIFT (17U)vLPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)vLPUART_BAUD_MATCFG_MASK (0xC0000U)vLPUART_BAUD_MATCFG_SHIFT (18U)vLPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)vLPUART_BAUD_RDMAE_MASK (0x200000U)vLPUART_BAUD_RDMAE_SHIFT (21U)vLPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)vLPUART_BAUD_TDMAE_MASK (0x800000U)vLPUART_BAUD_TDMAE_SHIFT (23U)vLPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)vLPUART_BAUD_OSR_MASK (0x1F000000U)vLPUART_BAUD_OSR_SHIFT (24U)vLPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)vLPUART_BAUD_M10_MASK (0x20000000U)vLPUART_BAUD_M10_SHIFT (29U)vLPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)vLPUART_BAUD_MAEN2_MASK (0x40000000U)vLPUART_BAUD_MAEN2_SHIFT (30U)vLPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)vLPUART_BAUD_MAEN1_MASK (0x80000000U)vLPUART_BAUD_MAEN1_SHIFT (31U)vLPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)vLPUART_STAT_MA2F_MASK (0x4000U)vLPUART_STAT_MA2F_SHIFT (14U)vLPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)vLPUART_STAT_MA1F_MASK (0x8000U)vLPUART_STAT_MA1F_SHIFT (15U)vLPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)vLPUART_STAT_PF_MASK (0x10000U)vLPUART_STAT_PF_SHIFT (16U)vLPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)vLPUART_STAT_FE_MASK (0x20000U)vLPUART_STAT_FE_SHIFT (17U)vLPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)vLPUART_STAT_NF_MASK (0x40000U)vLPUART_STAT_NF_SHIFT (18U)vLPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)vLPUART_STAT_OR_MASK (0x80000U)vLPUART_STAT_OR_SHIFT (19U)vLPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)vLPUART_STAT_IDLE_MASK (0x100000U)vLPUART_STAT_IDLE_SHIFT (20U)vLPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)vLPUART_STAT_RDRF_MASK (0x200000U)vLPUART_STAT_RDRF_SHIFT (21U)vLPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)vLPUART_STAT_TC_MASK (0x400000U)vLPUART_STAT_TC_SHIFT (22U)vLPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)vLPUART_STAT_TDRE_MASK (0x800000U)vLPUART_STAT_TDRE_SHIFT (23U)vLPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)vLPUART_STAT_RAF_MASK (0x1000000U)vLPUART_STAT_RAF_SHIFT (24U)vLPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)vLPUART_STAT_LBKDE_MASK (0x2000000U)vLPUART_STAT_LBKDE_SHIFT (25U)vLPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)vLPUART_STAT_BRK13_MASK (0x4000000U)vLPUART_STAT_BRK13_SHIFT (26U)vLPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)vLPUART_STAT_RWUID_MASK (0x8000000U)vLPUART_STAT_RWUID_SHIFT (27U)vLPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)vLPUART_STAT_RXINV_MASK (0x10000000U)vLPUART_STAT_RXINV_SHIFT (28U)vLPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)vLPUART_STAT_MSBF_MASK (0x20000000U)vLPUART_STAT_MSBF_SHIFT (29U)vLPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)vLPUART_STAT_RXEDGIF_MASK (0x40000000U)vLPUART_STAT_RXEDGIF_SHIFT (30U)vLPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)vLPUART_STAT_LBKDIF_MASK (0x80000000U)vLPUART_STAT_LBKDIF_SHIFT (31U)vLPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)vLPUART_CTRL_PT_MASK (0x1U)vLPUART_CTRL_PT_SHIFT (0U)vLPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)vLPUART_CTRL_PE_MASK (0x2U)vLPUART_CTRL_PE_SHIFT (1U)vLPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)vLPUART_CTRL_ILT_MASK (0x4U)vLPUART_CTRL_ILT_SHIFT (2U)vLPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)vLPUART_CTRL_WAKE_MASK (0x8U)vLPUART_CTRL_WAKE_SHIFT (3U)vLPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)vLPUART_CTRL_M_MASK (0x10U)vLPUART_CTRL_M_SHIFT (4U)vLPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)vLPUART_CTRL_RSRC_MASK (0x20U)vLPUART_CTRL_RSRC_SHIFT (5U)vLPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)vLPUART_CTRL_DOZEEN_MASK (0x40U)vLPUART_CTRL_DOZEEN_SHIFT (6U)vLPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)vLPUART_CTRL_LOOPS_MASK (0x80U)vLPUART_CTRL_LOOPS_SHIFT (7U)vLPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)vLPUART_CTRL_IDLECFG_MASK (0x700U)vLPUART_CTRL_IDLECFG_SHIFT (8U)vLPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)vLPUART_CTRL_M7_MASK (0x800U)vLPUART_CTRL_M7_SHIFT (11U)vLPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)vLPUART_CTRL_MA2IE_MASK (0x4000U)vLPUART_CTRL_MA2IE_SHIFT (14U)vLPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)vLPUART_CTRL_MA1IE_MASK (0x8000U)vLPUART_CTRL_MA1IE_SHIFT (15U)vLPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)vLPUART_CTRL_SBK_MASK (0x10000U)vLPUART_CTRL_SBK_SHIFT (16U)vLPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)vLPUART_CTRL_RWU_MASK (0x20000U)vLPUART_CTRL_RWU_SHIFT (17U)vLPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)vLPUART_CTRL_RE_MASK (0x40000U)vLPUART_CTRL_RE_SHIFT (18U)wLPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)wLPUART_CTRL_TE_MASK (0x80000U)wLPUART_CTRL_TE_SHIFT (19U)wLPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)wLPUART_CTRL_ILIE_MASK (0x100000U)wLPUART_CTRL_ILIE_SHIFT (20U)wLPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)wLPUART_CTRL_RIE_MASK (0x200000U)wLPUART_CTRL_RIE_SHIFT (21U)wLPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)wLPUART_CTRL_TCIE_MASK (0x400000U)wLPUART_CTRL_TCIE_SHIFT (22U)wLPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)wLPUART_CTRL_TIE_MASK (0x800000U)wLPUART_CTRL_TIE_SHIFT (23U)wLPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)wLPUART_CTRL_PEIE_MASK (0x1000000U)wLPUART_CTRL_PEIE_SHIFT (24U)wLPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)wLPUART_CTRL_FEIE_MASK (0x2000000U)wLPUART_CTRL_FEIE_SHIFT (25U)wLPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)wLPUART_CTRL_NEIE_MASK (0x4000000U)wLPUART_CTRL_NEIE_SHIFT (26U)wLPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)wLPUART_CTRL_ORIE_MASK (0x8000000U)wLPUART_CTRL_ORIE_SHIFT (27U)wLPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)wLPUART_CTRL_TXINV_MASK (0x10000000U)wLPUART_CTRL_TXINV_SHIFT (28U)wLPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)wLPUART_CTRL_TXDIR_MASK (0x20000000U)wLPUART_CTRL_TXDIR_SHIFT (29U)wLPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)wLPUART_CTRL_R9T8_MASK (0x40000000U)wLPUART_CTRL_R9T8_SHIFT (30U)wLPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)wLPUART_CTRL_R8T9_MASK (0x80000000U)wLPUART_CTRL_R8T9_SHIFT (31U)wLPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)wLPUART_DATA_R0T0_MASK (0x1U)wLPUART_DATA_R0T0_SHIFT (0U)wLPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)wLPUART_DATA_R1T1_MASK (0x2U)wLPUART_DATA_R1T1_SHIFT (1U)wLPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)wLPUART_DATA_R2T2_MASK (0x4U)wLPUART_DATA_R2T2_SHIFT (2U)wLPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)wLPUART_DATA_R3T3_MASK (0x8U)wLPUART_DATA_R3T3_SHIFT (3U)wLPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)wLPUART_DATA_R4T4_MASK (0x10U)wLPUART_DATA_R4T4_SHIFT (4U)wLPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)wLPUART_DATA_R5T5_MASK (0x20U)wLPUART_DATA_R5T5_SHIFT (5U)wLPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)wLPUART_DATA_R6T6_MASK (0x40U)wLPUART_DATA_R6T6_SHIFT (6U)wLPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)wLPUART_DATA_R7T7_MASK (0x80U)wLPUART_DATA_R7T7_SHIFT (7U)wLPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)wLPUART_DATA_R8T8_MASK (0x100U)wLPUART_DATA_R8T8_SHIFT (8U)wLPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)wLPUART_DATA_R9T9_MASK (0x200U)wLPUART_DATA_R9T9_SHIFT (9U)wLPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)wLPUART_DATA_IDLINE_MASK (0x800U)wLPUART_DATA_IDLINE_SHIFT (11U)wLPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)wLPUART_DATA_RXEMPT_MASK (0x1000U)wLPUART_DATA_RXEMPT_SHIFT (12U)wLPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)wLPUART_DATA_FRETSC_MASK (0x2000U)wLPUART_DATA_FRETSC_SHIFT (13U)wLPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)wLPUART_DATA_PARITYE_MASK (0x4000U)wLPUART_DATA_PARITYE_SHIFT (14U)wLPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)wLPUART_DATA_NOISY_MASK (0x8000U)wLPUART_DATA_NOISY_SHIFT (15U)wLPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)wLPUART_MATCH_MA1_MASK (0x3FFU)wLPUART_MATCH_MA1_SHIFT (0U)wLPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)wLPUART_MATCH_MA2_MASK (0x3FF0000U)wLPUART_MATCH_MA2_SHIFT (16U)wLPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)wLPUART_MODIR_TXCTSE_MASK (0x1U)wLPUART_MODIR_TXCTSE_SHIFT (0U)wLPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)wLPUART_MODIR_TXRTSE_MASK (0x2U)wLPUART_MODIR_TXRTSE_SHIFT (1U)wLPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)wLPUART_MODIR_TXRTSPOL_MASK (0x4U)wLPUART_MODIR_TXRTSPOL_SHIFT (2U)wLPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)wLPUART_MODIR_RXRTSE_MASK (0x8U)wLPUART_MODIR_RXRTSE_SHIFT (3U)wLPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)wLPUART_MODIR_TXCTSC_MASK (0x10U)wLPUART_MODIR_TXCTSC_SHIFT (4U)wLPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)wLPUART_MODIR_TXCTSSRC_MASK (0x20U)wLPUART_MODIR_TXCTSSRC_SHIFT (5U)wLPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)wLPUART_MODIR_RTSWATER_MASK (0x300U)wLPUART_MODIR_RTSWATER_SHIFT (8U)wLPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)wLPUART_MODIR_TNP_MASK (0x30000U)wLPUART_MODIR_TNP_SHIFT (16U)wLPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)wLPUART_MODIR_IREN_MASK (0x40000U)wLPUART_MODIR_IREN_SHIFT (18U)wLPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)wLPUART_FIFO_RXFIFOSIZE_MASK (0x7U)wLPUART_FIFO_RXFIFOSIZE_SHIFT (0U)xLPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)xLPUART_FIFO_RXFE_MASK (0x8U)xLPUART_FIFO_RXFE_SHIFT (3U)xLPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)xLPUART_FIFO_TXFIFOSIZE_MASK (0x70U)xLPUART_FIFO_TXFIFOSIZE_SHIFT (4U)xLPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)xLPUART_FIFO_TXFE_MASK (0x80U)xLPUART_FIFO_TXFE_SHIFT (7U)xLPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)xLPUART_FIFO_RXUFE_MASK (0x100U)xLPUART_FIFO_RXUFE_SHIFT (8U)xLPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)xLPUART_FIFO_TXOFE_MASK (0x200U)xLPUART_FIFO_TXOFE_SHIFT (9U)xLPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)xLPUART_FIFO_RXIDEN_MASK (0x1C00U)xLPUART_FIFO_RXIDEN_SHIFT (10U)xLPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)xLPUART_FIFO_RXFLUSH_MASK (0x4000U)xLPUART_FIFO_RXFLUSH_SHIFT (14U)xLPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)xLPUART_FIFO_TXFLUSH_MASK (0x8000U)xLPUART_FIFO_TXFLUSH_SHIFT (15U)xLPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)xLPUART_FIFO_RXUF_MASK (0x10000U)xLPUART_FIFO_RXUF_SHIFT (16U)xLPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)xLPUART_FIFO_TXOF_MASK (0x20000U)xLPUART_FIFO_TXOF_SHIFT (17U)xLPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)xLPUART_FIFO_RXEMPT_MASK (0x400000U)xLPUART_FIFO_RXEMPT_SHIFT (22U)xLPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)xLPUART_FIFO_TXEMPT_MASK (0x800000U)xLPUART_FIFO_TXEMPT_SHIFT (23U)xLPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)xLPUART_WATER_TXWATER_MASK (0x3U)xLPUART_WATER_TXWATER_SHIFT (0U)xLPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)xLPUART_WATER_TXCOUNT_MASK (0x700U)xLPUART_WATER_TXCOUNT_SHIFT (8U)xLPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)xLPUART_WATER_RXWATER_MASK (0x30000U)xLPUART_WATER_RXWATER_SHIFT (16U)xLPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)xLPUART_WATER_RXCOUNT_MASK (0x7000000U)xLPUART_WATER_RXCOUNT_SHIFT (24U)xLPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)xLPUART1_BASE (0x40184000u)xLPUART1 ((LPUART_Type *)LPUART1_BASE)xLPUART2_BASE (0x40188000u)xLPUART2 ((LPUART_Type *)LPUART2_BASE)xLPUART3_BASE (0x4018C000u)xLPUART3 ((LPUART_Type *)LPUART3_BASE)xLPUART4_BASE (0x40190000u)xLPUART4 ((LPUART_Type *)LPUART4_BASE)xLPUART5_BASE (0x40194000u)xLPUART5 ((LPUART_Type *)LPUART5_BASE)xLPUART6_BASE (0x40198000u)xLPUART6 ((LPUART_Type *)LPUART6_BASE)xLPUART7_BASE (0x4019C000u)xLPUART7 ((LPUART_Type *)LPUART7_BASE)xLPUART8_BASE (0x401A0000u)xLPUART8 ((LPUART_Type *)LPUART8_BASE)xLPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }xLPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }xLPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }yOCOTP_CTRL_ADDR_MASK (0x3FU)yOCOTP_CTRL_ADDR_SHIFT (0U)yOCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)yOCOTP_CTRL_BUSY_MASK (0x100U)yOCOTP_CTRL_BUSY_SHIFT (8U)yOCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)yOCOTP_CTRL_ERROR_MASK (0x200U)yOCOTP_CTRL_ERROR_SHIFT (9U)yOCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)yOCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)yOCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)yOCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)yOCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)yOCOTP_CTRL_WR_UNLOCK_SHIFT (16U)yOCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)yOCOTP_CTRL_SET_ADDR_MASK (0x3FU)yOCOTP_CTRL_SET_ADDR_SHIFT (0U)yOCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)yOCOTP_CTRL_SET_BUSY_MASK (0x100U)yOCOTP_CTRL_SET_BUSY_SHIFT (8U)yOCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)yOCOTP_CTRL_SET_ERROR_MASK (0x200U)yOCOTP_CTRL_SET_ERROR_SHIFT (9U)yOCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)yOCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)yOCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)yOCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)yOCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)zOCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)zOCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)zOCOTP_CTRL_CLR_ADDR_MASK (0x3FU)zOCOTP_CTRL_CLR_ADDR_SHIFT (0U)zOCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)zOCOTP_CTRL_CLR_BUSY_MASK (0x100U)zOCOTP_CTRL_CLR_BUSY_SHIFT (8U)zOCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)zOCOTP_CTRL_CLR_ERROR_MASK (0x200U)zOCOTP_CTRL_CLR_ERROR_SHIFT (9U)zOCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)zOCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)zOCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)zOCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)zOCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)zOCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)zOCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)zOCOTP_CTRL_TOG_ADDR_MASK (0x3FU)zOCOTP_CTRL_TOG_ADDR_SHIFT (0U)zOCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)zOCOTP_CTRL_TOG_BUSY_MASK (0x100U)zOCOTP_CTRL_TOG_BUSY_SHIFT (8U)zOCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)zOCOTP_CTRL_TOG_ERROR_MASK (0x200U)zOCOTP_CTRL_TOG_ERROR_SHIFT (9U)zOCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)zOCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)zOCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)zOCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)zOCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)zOCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)zOCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)zOCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)zOCOTP_TIMING_STROBE_PROG_SHIFT (0U)zOCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)zOCOTP_TIMING_RELAX_MASK (0xF000U)zOCOTP_TIMING_RELAX_SHIFT (12U)zOCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)zOCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)zOCOTP_TIMING_STROBE_READ_SHIFT (16U)zOCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)zOCOTP_TIMING_WAIT_MASK (0xFC00000U)zOCOTP_TIMING_WAIT_SHIFT (22U)zOCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)zOCOTP_DATA_DATA_MASK (0xFFFFFFFFU)zOCOTP_DATA_DATA_SHIFT (0U)zOCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)zOCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)zOCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)zOCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)zOCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)zOCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)zOCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)zOCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)zOCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)zOCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)zOCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)zOCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)zOCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)zOCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)zOCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)zOCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)zOCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)zOCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)zOCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)zOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)zOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)zOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)zOCOTP_SCS_HAB_JDE_MASK (0x1U)zOCOTP_SCS_HAB_JDE_SHIFT (0U)zOCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)zOCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)zOCOTP_SCS_SPARE_SHIFT (1U)zOCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)zOCOTP_SCS_LOCK_MASK (0x80000000U)zOCOTP_SCS_LOCK_SHIFT (31U)zOCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)zOCOTP_SCS_SET_HAB_JDE_MASK (0x1U)zOCOTP_SCS_SET_HAB_JDE_SHIFT (0U)zOCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)zOCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)zOCOTP_SCS_SET_SPARE_SHIFT (1U)zOCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)zOCOTP_SCS_SET_LOCK_MASK (0x80000000U)zOCOTP_SCS_SET_LOCK_SHIFT (31U)zOCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)zOCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)zOCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)zOCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)zOCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)zOCOTP_SCS_CLR_SPARE_SHIFT (1U)zOCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)zOCOTP_SCS_CLR_LOCK_MASK (0x80000000U)zOCOTP_SCS_CLR_LOCK_SHIFT (31U)zOCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)zOCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)zOCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)zOCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)zOCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)zOCOTP_SCS_TOG_SPARE_SHIFT (1U)zOCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)zOCOTP_SCS_TOG_LOCK_MASK (0x80000000U)zOCOTP_SCS_TOG_LOCK_SHIFT (31U)zOCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK){OCOTP_VERSION_STEP_MASK (0xFFFFU){OCOTP_VERSION_STEP_SHIFT (0U){OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK){OCOTP_VERSION_MINOR_MASK (0xFF0000U){OCOTP_VERSION_MINOR_SHIFT (16U){OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK){OCOTP_VERSION_MAJOR_MASK (0xFF000000U){OCOTP_VERSION_MAJOR_SHIFT (24U){OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK){OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU){OCOTP_TIMING2_RELAX_PROG_SHIFT (0U){OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK){OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U){OCOTP_TIMING2_RELAX_READ_SHIFT (16U){OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK){OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U){OCOTP_TIMING2_RELAX1_SHIFT (22U){OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK){OCOTP_LOCK_TESTER_MASK (0x3U){OCOTP_LOCK_TESTER_SHIFT (0U){OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK){OCOTP_LOCK_BOOT_CFG_MASK (0xCU){OCOTP_LOCK_BOOT_CFG_SHIFT (2U){OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK){OCOTP_LOCK_MEM_TRIM_MASK (0x30U){OCOTP_LOCK_MEM_TRIM_SHIFT (4U){OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK){OCOTP_LOCK_SJC_RESP_MASK (0x40U){OCOTP_LOCK_SJC_RESP_SHIFT (6U){OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK){OCOTP_LOCK_MAC_ADDR_MASK (0x300U){OCOTP_LOCK_MAC_ADDR_SHIFT (8U){OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK){OCOTP_LOCK_GP1_MASK (0xC00U){OCOTP_LOCK_GP1_SHIFT (10U){OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK){OCOTP_LOCK_GP2_MASK (0x3000U){OCOTP_LOCK_GP2_SHIFT (12U){OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK){OCOTP_LOCK_SRK_MASK (0x4000U){OCOTP_LOCK_SRK_SHIFT (14U){OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK){OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U){OCOTP_LOCK_OTPMK_MSB_SHIFT (15U){OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK){OCOTP_LOCK_SW_GP1_MASK (0x10000U){OCOTP_LOCK_SW_GP1_SHIFT (16U){OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK){OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U){OCOTP_LOCK_OTPMK_LSB_SHIFT (17U){OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK){OCOTP_LOCK_ANALOG_MASK (0xC0000U){OCOTP_LOCK_ANALOG_SHIFT (18U){OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK){OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U){OCOTP_LOCK_OTPMK_CRC_SHIFT (20U){OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK){OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U){OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U){OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK){OCOTP_LOCK_MISC_CONF_MASK (0x400000U){OCOTP_LOCK_MISC_CONF_SHIFT (22U){OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK){OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U){OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U){OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK){OCOTP_LOCK_GP3_MASK (0xC000000U){OCOTP_LOCK_GP3_SHIFT (26U){OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK){OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U){OCOTP_LOCK_FIELD_RETURN_SHIFT (28U){OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK){OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG0_BITS_SHIFT (0U){OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK){OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG1_BITS_SHIFT (0U){OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK){OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG2_BITS_SHIFT (0U){OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK){OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG3_BITS_SHIFT (0U){OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK){OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG4_BITS_SHIFT (0U){OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK){OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG5_BITS_SHIFT (0U){OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK){OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG6_BITS_SHIFT (0U){OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK){OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU){OCOTP_MEM0_BITS_SHIFT (0U){OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK){OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU){OCOTP_MEM1_BITS_SHIFT (0U){OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK){OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU){OCOTP_MEM2_BITS_SHIFT (0U){OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)|OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)|OCOTP_MEM3_BITS_SHIFT (0U)|OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)|OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)|OCOTP_MEM4_BITS_SHIFT (0U)|OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)|OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)|OCOTP_ANA0_BITS_SHIFT (0U)|OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)|OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)|OCOTP_ANA1_BITS_SHIFT (0U)|OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)|OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)|OCOTP_ANA2_BITS_SHIFT (0U)|OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)|OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK0_BITS_SHIFT (0U)|OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)|OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK1_BITS_SHIFT (0U)|OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)|OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK2_BITS_SHIFT (0U)|OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)|OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK3_BITS_SHIFT (0U)|OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)|OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK4_BITS_SHIFT (0U)|OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)|OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK5_BITS_SHIFT (0U)|OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)|OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK6_BITS_SHIFT (0U)|OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)|OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK7_BITS_SHIFT (0U)|OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)|OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)|OCOTP_SJC_RESP0_BITS_SHIFT (0U)|OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)|OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)|OCOTP_SJC_RESP1_BITS_SHIFT (0U)|OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)|OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)|OCOTP_MAC0_BITS_SHIFT (0U)|OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)|OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)|OCOTP_MAC1_BITS_SHIFT (0U)|OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)|OCOTP_GP3_BITS_MASK (0xFFFFFFFFU)|OCOTP_GP3_BITS_SHIFT (0U)|OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)|OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)|OCOTP_GP1_BITS_SHIFT (0U)|OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)|OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)|OCOTP_GP2_BITS_SHIFT (0U)|OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)|OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP1_BITS_SHIFT (0U)|OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)|OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP20_BITS_SHIFT (0U)|OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)|OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP21_BITS_SHIFT (0U)|OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)|OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP22_BITS_SHIFT (0U)|OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)|OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP23_BITS_SHIFT (0U)|OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)|OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)|OCOTP_MISC_CONF0_BITS_SHIFT (0U)|OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)}OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)}OCOTP_MISC_CONF1_BITS_SHIFT (0U)}OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)}OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)}OCOTP_SRK_REVOKE_BITS_SHIFT (0U)}OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)}OCOTP_BASE (0x401F4000u)}OCOTP ((OCOTP_Type *)OCOTP_BASE)}OCOTP_BASE_ADDRS { OCOTP_BASE }}OCOTP_BASE_PTRS { OCOTP }}PGC_MEGA_CTRL_PCR_MASK (0x1U)}PGC_MEGA_CTRL_PCR_SHIFT (0U)}PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)}PGC_MEGA_PUPSCR_SW_MASK (0x3FU)}PGC_MEGA_PUPSCR_SW_SHIFT (0U)}PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)}PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)}PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)}PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)}PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)}PGC_MEGA_PDNSCR_ISO_SHIFT (0U)}PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)}PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)}PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)}PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)}PGC_MEGA_SR_PSR_MASK (0x1U)}PGC_MEGA_SR_PSR_SHIFT (0U)}PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)}PGC_CPU_CTRL_PCR_MASK (0x1U)}PGC_CPU_CTRL_PCR_SHIFT (0U)}PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)}PGC_CPU_PUPSCR_SW_MASK (0x3FU)}PGC_CPU_PUPSCR_SW_SHIFT (0U)}PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)}PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)}PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)}PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)}PGC_CPU_PDNSCR_ISO_MASK (0x3FU)}PGC_CPU_PDNSCR_ISO_SHIFT (0U)}PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)}PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)}PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)}PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)}PGC_CPU_SR_PSR_MASK (0x1U)}PGC_CPU_SR_PSR_SHIFT (0U)}PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)}PGC_BASE (0x400F4000u)}PGC ((PGC_Type *)PGC_BASE)~PGC_BASE_ADDRS { PGC_BASE }~PGC_BASE_PTRS { PGC }~PIT_MCR_FRZ_MASK (0x1U)~PIT_MCR_FRZ_SHIFT (0U)~PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)~PIT_MCR_MDIS_MASK (0x2U)~PIT_MCR_MDIS_SHIFT (1U)~PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)~PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)~PIT_LTMR64H_LTH_SHIFT (0U)~PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)~PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)~PIT_LTMR64L_LTL_SHIFT (0U)~PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)~PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)~PIT_LDVAL_TSV_SHIFT (0U)~PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)~PIT_LDVAL_COUNT (4U)~PIT_CVAL_TVL_MASK (0xFFFFFFFFU)~PIT_CVAL_TVL_SHIFT (0U)~PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)~PIT_CVAL_COUNT (4U)~PIT_TCTRL_TEN_MASK (0x1U)~PIT_TCTRL_TEN_SHIFT (0U)~PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)~PIT_TCTRL_TIE_MASK (0x2U)~PIT_TCTRL_TIE_SHIFT (1U)~PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)~PIT_TCTRL_CHN_MASK (0x4U)~PIT_TCTRL_CHN_SHIFT (2U)~PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)~PIT_TCTRL_COUNT (4U)~PIT_TFLG_TIF_MASK (0x1U)~PIT_TFLG_TIF_SHIFT (0U)~PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)~PIT_TFLG_COUNT (4U)~PIT_BASE (0x40084000u)~PIT ((PIT_Type *)PIT_BASE)~PIT_BASE_ADDRS { PIT_BASE }~PIT_BASE_PTRS { PIT }~PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)PMU_REG_1P1_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)PMU_REG_3P0_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)PMU_REG_3P0_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)PMU_REG_3P0_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)€PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)ÀPMU_REG_3P0_OK_VDD3P0_SHIFT (17U)ĀPMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)ǀPMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)ȀPMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)ɀPMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)ʀPMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)ˀPMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)̀PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)̀PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)΀PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)πPMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)ЀPMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)рPMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)ҀPMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)ӀPMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)ԀPMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)ՀPMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)րPMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)׀PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)؀PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)ـPMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)ڀPMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)ۀPMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)܀PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)݀PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)ހPMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)PMU_REG_2P5_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)ÁPMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)āPMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)ŁPMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)ƁPMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)ǁPMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)ȁPMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)ɁPMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)ʁPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)ˁPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)́PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)ρPMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)ЁPMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)сPMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)ҁPMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)ӁPMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)ԁPMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)ՁPMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)ցPMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)ׁPMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)؁PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)فPMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)ځPMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)ہPMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)܁PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)݁PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)ށPMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)߁PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)PMU_REG_CORE_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_REG0_TARG_SHIFT (0U)PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_REG2_TARG_SHIFT (18U)PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)PMU_MISC0_REFTOP_PWD_MASK (0x1U)‚PMU_MISC0_REFTOP_PWD_SHIFT (0U)ÂPMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)ĂPMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)łPMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)ƂPMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)ǂPMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)ȂPMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)ɂPMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)ʂPMU_MISC0_REFTOP_VBGUP_MASK (0x80U)˂PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)̂PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)͂PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)΂PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)ςPMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)ЂPMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)тPMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)҂PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)ӂPMU_MISC0_OSC_I_MASK (0x6000U)ԂPMU_MISC0_OSC_I_SHIFT (13U)ՂPMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)ւPMU_MISC0_OSC_XTALOK_MASK (0x8000U)ׂPMU_MISC0_OSC_XTALOK_SHIFT (15U)؂PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)قPMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)ڂPMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)ۂPMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)܂PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)݂PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)ނPMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)߂PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)PMU_MISC0_SET_OSC_I_MASK (0x6000U)PMU_MISC0_SET_OSC_I_SHIFT (13U)PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)PMU_MISC0_CLR_OSC_I_MASK (0x6000U)PMU_MISC0_CLR_OSC_I_SHIFT (13U)PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)ƒPMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)ŃPMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)ƃPMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)ǃPMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)ȃPMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)ɃPMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)ʃPMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)˃PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)̃PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)̓PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)΃PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)σPMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)ЃPMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)уPMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)҃PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)ӃPMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)ԃPMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)ՃPMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)փPMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)׃PMU_MISC0_TOG_OSC_I_MASK (0x6000U)؃PMU_MISC0_TOG_OSC_I_SHIFT (13U)كPMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)ڃPMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)ۃPMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)܃PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)݃PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)ރPMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)߃PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)„PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)ÄPMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)ĄPMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)ńPMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)ƄPMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)DŽPMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)ȄPMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)ɄPMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)ʄPMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)˄PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)̄PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)̈́PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)΄PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)фPMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)҄PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)ӄPMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)ԄPMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)ՄPMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)քPMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)ׄPMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)؄PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)لPMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)ڄPMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)ۄPMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)܄PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)݄PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)ބPMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)߄PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)PMU_MISC2_PLL3_disable_MASK (0x80U)PMU_MISC2_PLL3_disable_SHIFT (7U)PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)PMU_MISC2_REG2_OK_MASK (0x400000U)PMU_MISC2_REG2_OK_SHIFT (22U)PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)PMU_MISC2_VIDEO_DIV_SHIFT (30U)PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)PMU_MISC2_SET_PLL3_disable_MASK (0x80U)PMU_MISC2_SET_PLL3_disable_SHIFT (7U)PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)PMU_MISC2_SET_REG2_OK_MASK (0x400000U)PMU_MISC2_SET_REG2_OK_SHIFT (22U)PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)ÅPMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)ąPMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)ŅPMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)ƅPMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)DžPMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)ȅPMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)ɅPMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)ʅPMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)˅PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)̅PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)ͅPMU_MISC2_CLR_PLL3_disable_SHIFT (7U)΅PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)υPMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)ЅPMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)хPMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)҅PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)ӅPMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)ԅPMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)ՅPMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)օPMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)ׅPMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)؅PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)مPMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)څPMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)ۅPMU_MISC2_CLR_REG2_OK_MASK (0x400000U)܅PMU_MISC2_CLR_REG2_OK_SHIFT (22U)݅PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)ޅPMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)߅PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)PMU_MISC2_TOG_REG2_OK_SHIFT (22U)PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)PMU_BASE (0x400D8000u)PMU ((PMU_Type *)PMU_BASE)PMU_BASE_ADDRS { PMU_BASE }PMU_BASE_PTRS { PMU }PWM_CNT_CNT_MASK (0xFFFFU)PWM_CNT_CNT_SHIFT (0U)PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)PWM_CNT_COUNT (4U)PWM_INIT_INIT_MASK (0xFFFFU)PWM_INIT_INIT_SHIFT (0U)PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)PWM_INIT_COUNT (4U)PWM_CTRL2_CLK_SEL_MASK (0x3U)PWM_CTRL2_CLK_SEL_SHIFT (0U)PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)PWM_CTRL2_RELOAD_SEL_MASK (0x4U)PWM_CTRL2_RELOAD_SEL_SHIFT (2U)PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)PWM_CTRL2_FORCE_SEL_MASK (0x38U)PWM_CTRL2_FORCE_SEL_SHIFT (3U)PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)PWM_CTRL2_FORCE_MASK (0x40U)PWM_CTRL2_FORCE_SHIFT (6U)PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)PWM_CTRL2_FRCEN_MASK (0x80U)PWM_CTRL2_FRCEN_SHIFT (7U)PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)PWM_CTRL2_INIT_SEL_MASK (0x300U)PWM_CTRL2_INIT_SEL_SHIFT (8U)PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)PWM_CTRL2_PWMX_INIT_MASK (0x400U)PWM_CTRL2_PWMX_INIT_SHIFT (10U)PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)PWM_CTRL2_PWM45_INIT_MASK (0x800U)PWM_CTRL2_PWM45_INIT_SHIFT (11U)PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)PWM_CTRL2_PWM23_INIT_MASK (0x1000U)PWM_CTRL2_PWM23_INIT_SHIFT (12U)PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)PWM_CTRL2_INDEP_MASK (0x2000U)PWM_CTRL2_INDEP_SHIFT (13U)PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)PWM_CTRL2_WAITEN_MASK (0x4000U)PWM_CTRL2_WAITEN_SHIFT (14U)PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)PWM_CTRL2_DBGEN_MASK (0x8000U)PWM_CTRL2_DBGEN_SHIFT (15U)PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)PWM_CTRL2_COUNT (4U)PWM_CTRL_DBLEN_MASK (0x1U)PWM_CTRL_DBLEN_SHIFT (0U)PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)PWM_CTRL_DBLX_MASK (0x2U)PWM_CTRL_DBLX_SHIFT (1U)PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)PWM_CTRL_LDMOD_MASK (0x4U)PWM_CTRL_LDMOD_SHIFT (2U)PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)PWM_CTRL_SPLIT_MASK (0x8U)PWM_CTRL_SPLIT_SHIFT (3U)PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)PWM_CTRL_PRSC_MASK (0x70U)PWM_CTRL_PRSC_SHIFT (4U)PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)PWM_CTRL_COMPMODE_MASK (0x80U)‡PWM_CTRL_COMPMODE_SHIFT (7U)ÇPWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)ćPWM_CTRL_DT_MASK (0x300U)ŇPWM_CTRL_DT_SHIFT (8U)ƇPWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)LJPWM_CTRL_FULL_MASK (0x400U)ȇPWM_CTRL_FULL_SHIFT (10U)ɇPWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)ʇPWM_CTRL_HALF_MASK (0x800U)ˇPWM_CTRL_HALF_SHIFT (11U)̇PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)͇PWM_CTRL_LDFQ_MASK (0xF000U)·PWM_CTRL_LDFQ_SHIFT (12U)χPWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)҇PWM_CTRL_COUNT (4U)ՇPWM_VAL0_VAL0_MASK (0xFFFFU)ևPWM_VAL0_VAL0_SHIFT (0U)ׇPWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)ڇPWM_VAL0_COUNT (4U)݇PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)އPWM_FRACVAL1_FRACVAL1_SHIFT (11U)߇PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)PWM_FRACVAL1_COUNT (4U)PWM_VAL1_VAL1_MASK (0xFFFFU)PWM_VAL1_VAL1_SHIFT (0U)PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)PWM_VAL1_COUNT (4U)PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)PWM_FRACVAL2_FRACVAL2_SHIFT (11U)PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)PWM_FRACVAL2_COUNT (4U)PWM_VAL2_VAL2_MASK (0xFFFFU)PWM_VAL2_VAL2_SHIFT (0U)PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)PWM_VAL2_COUNT (4U)PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)PWM_FRACVAL3_FRACVAL3_SHIFT (11U)PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)PWM_FRACVAL3_COUNT (4U)PWM_VAL3_VAL3_MASK (0xFFFFU)PWM_VAL3_VAL3_SHIFT (0U)PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)PWM_VAL3_COUNT (4U)PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)PWM_FRACVAL4_FRACVAL4_SHIFT (11U)PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)PWM_FRACVAL4_COUNT (4U)PWM_VAL4_VAL4_MASK (0xFFFFU)PWM_VAL4_VAL4_SHIFT (0U)PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)PWM_VAL4_COUNT (4U)PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)PWM_FRACVAL5_FRACVAL5_SHIFT (11U)PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)PWM_FRACVAL5_COUNT (4U)PWM_VAL5_VAL5_MASK (0xFFFFU)PWM_VAL5_VAL5_SHIFT (0U)PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)PWM_VAL5_COUNT (4U)PWM_FRCTRL_FRAC1_EN_MASK (0x2U)PWM_FRCTRL_FRAC1_EN_SHIFT (1U)PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)PWM_FRCTRL_FRAC23_EN_MASK (0x4U)PWM_FRCTRL_FRAC23_EN_SHIFT (2U)PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)PWM_FRCTRL_FRAC45_EN_MASK (0x10U)PWM_FRCTRL_FRAC45_EN_SHIFT (4U)PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)PWM_FRCTRL_FRAC_PU_MASK (0x100U)PWM_FRCTRL_FRAC_PU_SHIFT (8U)PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)PWM_FRCTRL_TEST_MASK (0x8000U)PWM_FRCTRL_TEST_SHIFT (15U)PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)PWM_FRCTRL_COUNT (4U)PWM_OCTRL_PWMXFS_MASK (0x3U)ˆPWM_OCTRL_PWMXFS_SHIFT (0U)ÈPWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)ĈPWM_OCTRL_PWMBFS_MASK (0xCU)ňPWM_OCTRL_PWMBFS_SHIFT (2U)ƈPWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)LjPWM_OCTRL_PWMAFS_MASK (0x30U)ȈPWM_OCTRL_PWMAFS_SHIFT (4U)ɈPWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)ʈPWM_OCTRL_POLX_MASK (0x100U)ˈPWM_OCTRL_POLX_SHIFT (8U)̈PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)͈PWM_OCTRL_POLB_MASK (0x200U)ΈPWM_OCTRL_POLB_SHIFT (9U)ψPWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)ЈPWM_OCTRL_POLA_MASK (0x400U)шPWM_OCTRL_POLA_SHIFT (10U)҈PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)ӈPWM_OCTRL_PWMX_IN_MASK (0x2000U)ԈPWM_OCTRL_PWMX_IN_SHIFT (13U)ՈPWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)ֈPWM_OCTRL_PWMB_IN_MASK (0x4000U)׈PWM_OCTRL_PWMB_IN_SHIFT (14U)؈PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)وPWM_OCTRL_PWMA_IN_MASK (0x8000U)ڈPWM_OCTRL_PWMA_IN_SHIFT (15U)ۈPWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)ވPWM_OCTRL_COUNT (4U)PWM_STS_CMPF_MASK (0x3FU)PWM_STS_CMPF_SHIFT (0U)PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)PWM_STS_CFX0_MASK (0x40U)PWM_STS_CFX0_SHIFT (6U)PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)PWM_STS_CFX1_MASK (0x80U)PWM_STS_CFX1_SHIFT (7U)PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)PWM_STS_CFB0_MASK (0x100U)PWM_STS_CFB0_SHIFT (8U)PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)PWM_STS_CFB1_MASK (0x200U)PWM_STS_CFB1_SHIFT (9U)PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)PWM_STS_CFA0_MASK (0x400U)PWM_STS_CFA0_SHIFT (10U)PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)PWM_STS_CFA1_MASK (0x800U)PWM_STS_CFA1_SHIFT (11U)PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)PWM_STS_RF_MASK (0x1000U)PWM_STS_RF_SHIFT (12U)PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)PWM_STS_REF_MASK (0x2000U)PWM_STS_REF_SHIFT (13U)PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)PWM_STS_RUF_MASK (0x4000U)PWM_STS_RUF_SHIFT (14U)PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)PWM_STS_COUNT (4U)PWM_INTEN_CMPIE_MASK (0x3FU)PWM_INTEN_CMPIE_SHIFT (0U)PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)PWM_INTEN_CX0IE_MASK (0x40U)PWM_INTEN_CX0IE_SHIFT (6U)PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)PWM_INTEN_CX1IE_MASK (0x80U)PWM_INTEN_CX1IE_SHIFT (7U)PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)PWM_INTEN_CB0IE_MASK (0x100U)PWM_INTEN_CB0IE_SHIFT (8U)PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)PWM_INTEN_CB1IE_MASK (0x200U)PWM_INTEN_CB1IE_SHIFT (9U)PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)PWM_INTEN_CA0IE_MASK (0x400U)PWM_INTEN_CA0IE_SHIFT (10U)PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)PWM_INTEN_CA1IE_MASK (0x800U)PWM_INTEN_CA1IE_SHIFT (11U)PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)PWM_INTEN_RIE_MASK (0x1000U)PWM_INTEN_RIE_SHIFT (12U)PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)PWM_INTEN_REIE_MASK (0x2000U)PWM_INTEN_REIE_SHIFT (13U)PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)PWM_INTEN_COUNT (4U)PWM_DMAEN_CX0DE_MASK (0x1U)PWM_DMAEN_CX0DE_SHIFT (0U)PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)PWM_DMAEN_CX1DE_MASK (0x2U)PWM_DMAEN_CX1DE_SHIFT (1U)PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)PWM_DMAEN_CB0DE_MASK (0x4U)PWM_DMAEN_CB0DE_SHIFT (2U)PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)PWM_DMAEN_CB1DE_MASK (0x8U)PWM_DMAEN_CB1DE_SHIFT (3U)PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)PWM_DMAEN_CA0DE_MASK (0x10U)PWM_DMAEN_CA0DE_SHIFT (4U)PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)PWM_DMAEN_CA1DE_MASK (0x20U)PWM_DMAEN_CA1DE_SHIFT (5U)PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)PWM_DMAEN_CAPTDE_MASK (0xC0U)PWM_DMAEN_CAPTDE_SHIFT (6U)PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)PWM_DMAEN_FAND_MASK (0x100U)PWM_DMAEN_FAND_SHIFT (8U)PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)PWM_DMAEN_VALDE_MASK (0x200U)PWM_DMAEN_VALDE_SHIFT (9U)PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)PWM_DMAEN_COUNT (4U)ĉPWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)ʼnPWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)ƉPWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)ljPWM_TCTRL_TRGFRQ_MASK (0x1000U)ȉPWM_TCTRL_TRGFRQ_SHIFT (12U)ɉPWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)ʉPWM_TCTRL_PWBOT1_MASK (0x4000U)ˉPWM_TCTRL_PWBOT1_SHIFT (14U)̉PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)͉PWM_TCTRL_PWAOT0_MASK (0x8000U)ΉPWM_TCTRL_PWAOT0_SHIFT (15U)ωPWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)҉PWM_TCTRL_COUNT (4U)ՉPWM_DISMAP_DIS0A_MASK (0xFU)։PWM_DISMAP_DIS0A_SHIFT (0U)׉PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)؉PWM_DISMAP_DIS1A_MASK (0xFU)ىPWM_DISMAP_DIS1A_SHIFT (0U)ډPWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)ۉPWM_DISMAP_DIS0B_MASK (0xF0U)܉PWM_DISMAP_DIS0B_SHIFT (4U)݉PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)މPWM_DISMAP_DIS1B_MASK (0xF0U)߉PWM_DISMAP_DIS1B_SHIFT (4U)PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)PWM_DISMAP_DIS1X_MASK (0xF00U)PWM_DISMAP_DIS1X_SHIFT (8U)PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)PWM_DISMAP_DIS0X_MASK (0xF00U)PWM_DISMAP_DIS0X_SHIFT (8U)PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)PWM_DISMAP_COUNT (4U)PWM_DISMAP_COUNT2 (2U)PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)PWM_DTCNT0_DTCNT0_SHIFT (0U)PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)PWM_DTCNT0_COUNT (4U)PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)PWM_DTCNT1_DTCNT1_SHIFT (0U)PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)PWM_DTCNT1_COUNT (4U)PWM_CAPTCTRLA_ARMA_MASK (0x1U)PWM_CAPTCTRLA_ARMA_SHIFT (0U)PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)PWM_CAPTCTRLA_EDGA0_MASK (0xCU)PWM_CAPTCTRLA_EDGA0_SHIFT (2U)PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)PWM_CAPTCTRLA_EDGA1_MASK (0x30U)PWM_CAPTCTRLA_EDGA1_SHIFT (4U)PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)PWM_CAPTCTRLA_CFAWM_MASK (0x300U)PWM_CAPTCTRLA_CFAWM_SHIFT (8U)PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)PWM_CAPTCTRLA_COUNT (4U)PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)PWM_CAPTCOMPA_COUNT (4U)PWM_CAPTCTRLB_ARMB_MASK (0x1U)PWM_CAPTCTRLB_ARMB_SHIFT (0U)PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)PWM_CAPTCTRLB_EDGB0_MASK (0xCU)PWM_CAPTCTRLB_EDGB0_SHIFT (2U)PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)PWM_CAPTCTRLB_EDGB1_MASK (0x30U)PWM_CAPTCTRLB_EDGB1_SHIFT (4U)PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)PWM_CAPTCTRLB_CFBWM_MASK (0x300U)PWM_CAPTCTRLB_CFBWM_SHIFT (8U)PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)ŠPWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)ÊPWM_CAPTCTRLB_CB1CNT_SHIFT (13U)ĊPWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)NJPWM_CAPTCTRLB_COUNT (4U)ʊPWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)ˊPWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)̊PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)͊PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)ΊPWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)ϊPWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)ҊPWM_CAPTCOMPB_COUNT (4U)ՊPWM_CAPTCTRLX_ARMX_MASK (0x1U)֊PWM_CAPTCTRLX_ARMX_SHIFT (0U)׊PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)؊PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)يPWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)ڊPWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)ۊPWM_CAPTCTRLX_EDGX0_MASK (0xCU)܊PWM_CAPTCTRLX_EDGX0_SHIFT (2U)݊PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)ފPWM_CAPTCTRLX_EDGX1_MASK (0x30U)ߊPWM_CAPTCTRLX_EDGX1_SHIFT (4U)PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)PWM_CAPTCTRLX_CFXWM_MASK (0x300U)PWM_CAPTCTRLX_CFXWM_SHIFT (8U)PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)PWM_CAPTCTRLX_COUNT (4U)PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)PWM_CAPTCOMPX_COUNT (4U)PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)PWM_CVAL0_CAPTVAL0_SHIFT (0U)PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)PWM_CVAL0_COUNT (4U)PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)PWM_CVAL0CYC_COUNT (4U)PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)PWM_CVAL1_CAPTVAL1_SHIFT (0U)PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)PWM_CVAL1_COUNT (4U)PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)PWM_CVAL1CYC_COUNT (4U)PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)PWM_CVAL2_CAPTVAL2_SHIFT (0U)PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)PWM_CVAL2_COUNT (4U)PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)PWM_CVAL2CYC_COUNT (4U)PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)PWM_CVAL3_CAPTVAL3_SHIFT (0U)PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)PWM_CVAL3_COUNT (4U)PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)PWM_CVAL3CYC_COUNT (4U)PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)PWM_CVAL4_CAPTVAL4_SHIFT (0U)‹PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)ŋPWM_CVAL4_COUNT (4U)ȋPWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)ɋPWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)ʋPWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)͋PWM_CVAL4CYC_COUNT (4U)ЋPWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)ыPWM_CVAL5_CAPTVAL5_SHIFT (0U)ҋPWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)ՋPWM_CVAL5_COUNT (4U)؋PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)ًPWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)ڋPWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)݋PWM_CVAL5CYC_COUNT (4U)PWM_OUTEN_PWMX_EN_MASK (0xFU)PWM_OUTEN_PWMX_EN_SHIFT (0U)PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)PWM_OUTEN_PWMB_EN_MASK (0xF0U)PWM_OUTEN_PWMB_EN_SHIFT (4U)PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)PWM_OUTEN_PWMA_EN_MASK (0xF00U)PWM_OUTEN_PWMA_EN_SHIFT (8U)PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)PWM_MASK_MASKX_MASK (0xFU)PWM_MASK_MASKX_SHIFT (0U)PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)PWM_MASK_MASKB_MASK (0xF0U)PWM_MASK_MASKB_SHIFT (4U)PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)PWM_MASK_MASKA_MASK (0xF00U)PWM_MASK_MASKA_SHIFT (8U)PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)PWM_MASK_UPDATE_MASK_MASK (0xF000U)PWM_MASK_UPDATE_MASK_SHIFT (12U)PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)PWM_SWCOUT_SM0OUT45_MASK (0x1U)PWM_SWCOUT_SM0OUT45_SHIFT (0U)PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)PWM_SWCOUT_SM0OUT23_MASK (0x2U)PWM_SWCOUT_SM0OUT23_SHIFT (1U)PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)PWM_SWCOUT_SM1OUT45_MASK (0x4U)PWM_SWCOUT_SM1OUT45_SHIFT (2U)PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)PWM_SWCOUT_SM1OUT23_MASK (0x8U)PWM_SWCOUT_SM1OUT23_SHIFT (3U)PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)PWM_SWCOUT_SM2OUT45_MASK (0x10U)PWM_SWCOUT_SM2OUT45_SHIFT (4U)PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)PWM_SWCOUT_SM2OUT23_MASK (0x20U)PWM_SWCOUT_SM2OUT23_SHIFT (5U)PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)PWM_SWCOUT_SM3OUT45_MASK (0x40U)PWM_SWCOUT_SM3OUT45_SHIFT (6U)PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)PWM_SWCOUT_SM3OUT23_MASK (0x80U)PWM_SWCOUT_SM3OUT23_SHIFT (7U)PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)PWM_MCTRL_LDOK_MASK (0xFU)PWM_MCTRL_LDOK_SHIFT (0U)PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)PWM_MCTRL_CLDOK_MASK (0xF0U)PWM_MCTRL_CLDOK_SHIFT (4U)PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)PWM_MCTRL_RUN_MASK (0xF00U)PWM_MCTRL_RUN_SHIFT (8U)PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)PWM_MCTRL_IPOL_MASK (0xF000U)PWM_MCTRL_IPOL_SHIFT (12U)PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)PWM_MCTRL2_MONPLL_MASK (0x3U)PWM_MCTRL2_MONPLL_SHIFT (0U)PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)PWM_FCTRL_FIE_MASK (0xFU)PWM_FCTRL_FIE_SHIFT (0U)ŒPWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)ÌPWM_FCTRL_FSAFE_MASK (0xF0U)ČPWM_FCTRL_FSAFE_SHIFT (4U)ŌPWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)ƌPWM_FCTRL_FAUTO_MASK (0xF00U)njPWM_FCTRL_FAUTO_SHIFT (8U)ȌPWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)ɌPWM_FCTRL_FLVL_MASK (0xF000U)ʌPWM_FCTRL_FLVL_SHIFT (12U)ˌPWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)ΌPWM_FSTS_FFLAG_MASK (0xFU)όPWM_FSTS_FFLAG_SHIFT (0U)ЌPWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)ьPWM_FSTS_FFULL_MASK (0xF0U)ҌPWM_FSTS_FFULL_SHIFT (4U)ӌPWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)ԌPWM_FSTS_FFPIN_MASK (0xF00U)ՌPWM_FSTS_FFPIN_SHIFT (8U)֌PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)׌PWM_FSTS_FHALF_MASK (0xF000U)،PWM_FSTS_FHALF_SHIFT (12U)ٌPWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)܌PWM_FFILT_FILT_PER_MASK (0xFFU)݌PWM_FFILT_FILT_PER_SHIFT (0U)ތPWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)ߌPWM_FFILT_FILT_CNT_MASK (0x700U)PWM_FFILT_FILT_CNT_SHIFT (8U)PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)PWM_FFILT_GSTR_MASK (0x8000U)PWM_FFILT_GSTR_SHIFT (15U)PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)PWM_FTST_FTEST_MASK (0x1U)PWM_FTST_FTEST_SHIFT (0U)PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)PWM_FCTRL2_NOCOMB_MASK (0xFU)PWM_FCTRL2_NOCOMB_SHIFT (0U)PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)PWM1_BASE (0x403DC000u)PWM1 ((PWM_Type *)PWM1_BASE)PWM2_BASE (0x403E0000u)PWM2 ((PWM_Type *)PWM2_BASE)PWM3_BASE (0x403E4000u)PWM3 ((PWM_Type *)PWM3_BASE)PWM4_BASE (0x403E8000u)PWM4 ((PWM_Type *)PWM4_BASE)PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }PXP_CTRL_ENABLE_MASK (0x1U)PXP_CTRL_ENABLE_SHIFT (0U)PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)PXP_CTRL_IRQ_ENABLE_MASK (0x2U)PXP_CTRL_IRQ_ENABLE_SHIFT (1U)PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)PXP_CTRL_RSVD0_MASK (0xE0U)PXP_CTRL_RSVD0_SHIFT (5U)PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)PXP_CTRL_ROTATE_MASK (0x300U)PXP_CTRL_ROTATE_SHIFT (8U)PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)PXP_CTRL_HFLIP_MASK (0x400U)PXP_CTRL_HFLIP_SHIFT (10U)PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)PXP_CTRL_VFLIP_MASK (0x800U)PXP_CTRL_VFLIP_SHIFT (11U)PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)PXP_CTRL_RSVD1_MASK (0x3FF000U)PXP_CTRL_RSVD1_SHIFT (12U)PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK)PXP_CTRL_ROT_POS_MASK (0x400000U)PXP_CTRL_ROT_POS_SHIFT (22U)PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)PXP_CTRL_BLOCK_SIZE_SHIFT (23U)PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)PXP_CTRL_RSVD3_MASK (0xF000000U)PXP_CTRL_RSVD3_SHIFT (24U)PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK)PXP_CTRL_EN_REPEAT_MASK (0x10000000U)PXP_CTRL_EN_REPEAT_SHIFT (28U)PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)PXP_CTRL_RSVD4_MASK (0x20000000U)PXP_CTRL_RSVD4_SHIFT (29U)PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK)PXP_CTRL_CLKGATE_MASK (0x40000000U)PXP_CTRL_CLKGATE_SHIFT (30U)PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)PXP_CTRL_SFTRST_MASK (0x80000000U)PXP_CTRL_SFTRST_SHIFT (31U)PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)PXP_CTRL_SET_ENABLE_MASK (0x1U)PXP_CTRL_SET_ENABLE_SHIFT (0U)PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)PXP_CTRL_SET_RSVD0_MASK (0xE0U)PXP_CTRL_SET_RSVD0_SHIFT (5U)PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)PXP_CTRL_SET_ROTATE_MASK (0x300U)PXP_CTRL_SET_ROTATE_SHIFT (8U)PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)PXP_CTRL_SET_HFLIP_MASK (0x400U)PXP_CTRL_SET_HFLIP_SHIFT (10U)PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)PXP_CTRL_SET_VFLIP_MASK (0x800U)PXP_CTRL_SET_VFLIP_SHIFT (11U)PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)PXP_CTRL_SET_RSVD1_MASK (0x3FF000U)PXP_CTRL_SET_RSVD1_SHIFT (12U)PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK)ŽPXP_CTRL_SET_ROT_POS_MASK (0x400000U)ÎPXP_CTRL_SET_ROT_POS_SHIFT (22U)ĎPXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)ŎPXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)ƎPXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)ǎPXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)ȎPXP_CTRL_SET_RSVD3_MASK (0xF000000U)ɎPXP_CTRL_SET_RSVD3_SHIFT (24U)ʎPXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK)ˎPXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)̎PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)͎PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)ΎPXP_CTRL_SET_RSVD4_MASK (0x20000000U)ώPXP_CTRL_SET_RSVD4_SHIFT (29U)ЎPXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK)юPXP_CTRL_SET_CLKGATE_MASK (0x40000000U)ҎPXP_CTRL_SET_CLKGATE_SHIFT (30U)ӎPXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)ԎPXP_CTRL_SET_SFTRST_MASK (0x80000000U)ՎPXP_CTRL_SET_SFTRST_SHIFT (31U)֎PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)َPXP_CTRL_CLR_ENABLE_MASK (0x1U)ڎPXP_CTRL_CLR_ENABLE_SHIFT (0U)ێPXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)܎PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)ݎPXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)ގPXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)ߎPXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)PXP_CTRL_CLR_RSVD0_MASK (0xE0U)PXP_CTRL_CLR_RSVD0_SHIFT (5U)PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)PXP_CTRL_CLR_ROTATE_MASK (0x300U)PXP_CTRL_CLR_ROTATE_SHIFT (8U)PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)PXP_CTRL_CLR_HFLIP_MASK (0x400U)PXP_CTRL_CLR_HFLIP_SHIFT (10U)PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)PXP_CTRL_CLR_VFLIP_MASK (0x800U)PXP_CTRL_CLR_VFLIP_SHIFT (11U)PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U)PXP_CTRL_CLR_RSVD1_SHIFT (12U)PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK)PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)PXP_CTRL_CLR_ROT_POS_SHIFT (22U)PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)PXP_CTRL_CLR_RSVD3_MASK (0xF000000U)PXP_CTRL_CLR_RSVD3_SHIFT (24U)PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK)PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)PXP_CTRL_CLR_RSVD4_MASK (0x20000000U)PXP_CTRL_CLR_RSVD4_SHIFT (29U)PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK)PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)PXP_CTRL_CLR_CLKGATE_SHIFT (30U)PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)PXP_CTRL_CLR_SFTRST_SHIFT (31U)PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)PXP_CTRL_TOG_ENABLE_MASK (0x1U)PXP_CTRL_TOG_ENABLE_SHIFT (0U)PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)PXP_CTRL_TOG_RSVD0_MASK (0xE0U)PXP_CTRL_TOG_RSVD0_SHIFT (5U)PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)PXP_CTRL_TOG_ROTATE_MASK (0x300U)PXP_CTRL_TOG_ROTATE_SHIFT (8U)PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)PXP_CTRL_TOG_HFLIP_MASK (0x400U)PXP_CTRL_TOG_HFLIP_SHIFT (10U)PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)PXP_CTRL_TOG_VFLIP_MASK (0x800U)PXP_CTRL_TOG_VFLIP_SHIFT (11U)PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U)PXP_CTRL_TOG_RSVD1_SHIFT (12U)PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK)PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)PXP_CTRL_TOG_ROT_POS_SHIFT (22U)PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)PXP_CTRL_TOG_RSVD3_MASK (0xF000000U)PXP_CTRL_TOG_RSVD3_SHIFT (24U)PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK)PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)PXP_CTRL_TOG_RSVD4_MASK (0x20000000U)PXP_CTRL_TOG_RSVD4_SHIFT (29U)PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK)PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)PXP_CTRL_TOG_CLKGATE_SHIFT (30U)PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)PXP_CTRL_TOG_SFTRST_SHIFT (31U)PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)PXP_STAT_IRQ_MASK (0x1U)PXP_STAT_IRQ_SHIFT (0U)PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)ÏPXP_STAT_AXI_READ_ERROR_MASK (0x4U)ďPXP_STAT_AXI_READ_ERROR_SHIFT (2U)ŏPXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)ƏPXP_STAT_NEXT_IRQ_MASK (0x8U)ǏPXP_STAT_NEXT_IRQ_SHIFT (3U)ȏPXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)ɏPXP_STAT_AXI_ERROR_ID_MASK (0xF0U)ʏPXP_STAT_AXI_ERROR_ID_SHIFT (4U)ˏPXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)̏PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)͏PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)ΏPXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)ϏPXP_STAT_RSVD2_MASK (0xFE00U)ЏPXP_STAT_RSVD2_SHIFT (9U)яPXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK)ҏPXP_STAT_BLOCKY_MASK (0xFF0000U)ӏPXP_STAT_BLOCKY_SHIFT (16U)ԏPXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)ՏPXP_STAT_BLOCKX_MASK (0xFF000000U)֏PXP_STAT_BLOCKX_SHIFT (24U)׏PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)ڏPXP_STAT_SET_IRQ_MASK (0x1U)ۏPXP_STAT_SET_IRQ_SHIFT (0U)܏PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)ݏPXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)ޏPXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)ߏPXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)PXP_STAT_SET_RSVD2_MASK (0xFE00U)PXP_STAT_SET_RSVD2_SHIFT (9U)PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK)PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)PXP_STAT_SET_BLOCKY_SHIFT (16U)PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)PXP_STAT_SET_BLOCKX_SHIFT (24U)PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)PXP_STAT_CLR_IRQ_MASK (0x1U)PXP_STAT_CLR_IRQ_SHIFT (0U)PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)PXP_STAT_CLR_RSVD2_MASK (0xFE00U)PXP_STAT_CLR_RSVD2_SHIFT (9U)PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK)PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)PXP_STAT_CLR_BLOCKY_SHIFT (16U)PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)PXP_STAT_CLR_BLOCKX_SHIFT (24U)PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)PXP_STAT_TOG_IRQ_MASK (0x1U)PXP_STAT_TOG_IRQ_SHIFT (0U)PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)PXP_STAT_TOG_RSVD2_MASK (0xFE00U)PXP_STAT_TOG_RSVD2_SHIFT (9U)PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK)PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)PXP_STAT_TOG_BLOCKY_SHIFT (16U)PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)PXP_STAT_TOG_BLOCKX_SHIFT (24U)PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)PXP_OUT_CTRL_FORMAT_MASK (0x1FU)PXP_OUT_CTRL_FORMAT_SHIFT (0U)PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)PXP_OUT_CTRL_RSVD0_MASK (0xE0U)PXP_OUT_CTRL_RSVD0_SHIFT (5U)PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U)PXP_OUT_CTRL_RSVD1_SHIFT (10U)PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK)PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)PXP_OUT_CTRL_ALPHA_SHIFT (24U)PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)ŐPXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)ƐPXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)ǐPXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)ȐPXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U)ɐPXP_OUT_CTRL_SET_RSVD0_SHIFT (5U)ʐPXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)ːPXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)̐PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)͐PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)ΐPXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U)ϐPXP_OUT_CTRL_SET_RSVD1_SHIFT (10U)АPXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK)ѐPXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)ҐPXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)ӐPXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)ԐPXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)ՐPXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)֐PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)ِPXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)ڐPXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)ېPXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)ܐPXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U)ݐPXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U)ސPXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)ߐPXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U)PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U)PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK)PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U)PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U)PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U)PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U)PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK)PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)PXP_OUT_BUF_ADDR_SHIFT (0U)PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)PXP_OUT_BUF2_ADDR_SHIFT (0U)PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)PXP_OUT_PITCH_PITCH_SHIFT (0U)PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U)PXP_OUT_PITCH_RSVD_SHIFT (16U)PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK)PXP_OUT_LRC_Y_MASK (0x3FFFU)PXP_OUT_LRC_Y_SHIFT (0U)PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)PXP_OUT_LRC_RSVD0_MASK (0xC000U)PXP_OUT_LRC_RSVD0_SHIFT (14U)PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK)PXP_OUT_LRC_X_MASK (0x3FFF0000U)PXP_OUT_LRC_X_SHIFT (16U)PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)PXP_OUT_LRC_RSVD1_MASK (0xC0000000U)PXP_OUT_LRC_RSVD1_SHIFT (30U)PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK)PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)PXP_OUT_PS_ULC_Y_SHIFT (0U)PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U)PXP_OUT_PS_ULC_RSVD0_SHIFT (14U)PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK)PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)PXP_OUT_PS_ULC_X_SHIFT (16U)PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U)PXP_OUT_PS_ULC_RSVD1_SHIFT (30U)PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK)PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)PXP_OUT_PS_LRC_Y_SHIFT (0U)PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U)PXP_OUT_PS_LRC_RSVD0_SHIFT (14U)PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK)PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)PXP_OUT_PS_LRC_X_SHIFT (16U)PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U)PXP_OUT_PS_LRC_RSVD1_SHIFT (30U)PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK)PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)PXP_OUT_AS_ULC_Y_SHIFT (0U)PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U)PXP_OUT_AS_ULC_RSVD0_SHIFT (14U)‘PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK)ÑPXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)đPXP_OUT_AS_ULC_X_SHIFT (16U)őPXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)ƑPXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U)ǑPXP_OUT_AS_ULC_RSVD1_SHIFT (30U)ȑPXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK)ˑPXP_OUT_AS_LRC_Y_MASK (0x3FFFU)̑PXP_OUT_AS_LRC_Y_SHIFT (0U)͑PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)ΑPXP_OUT_AS_LRC_RSVD0_MASK (0xC000U)ϑPXP_OUT_AS_LRC_RSVD0_SHIFT (14U)БPXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK)ёPXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)ґPXP_OUT_AS_LRC_X_SHIFT (16U)ӑPXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)ԑPXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U)ՑPXP_OUT_AS_LRC_RSVD1_SHIFT (30U)֑PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK)ّPXP_PS_CTRL_FORMAT_MASK (0x1FU)ڑPXP_PS_CTRL_FORMAT_SHIFT (0U)ۑPXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)ܑPXP_PS_CTRL_WB_SWAP_MASK (0x20U)ݑPXP_PS_CTRL_WB_SWAP_SHIFT (5U)ޑPXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)ߑPXP_PS_CTRL_RSVD0_MASK (0xC0U)PXP_PS_CTRL_RSVD0_SHIFT (6U)PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)PXP_PS_CTRL_DECY_MASK (0x300U)PXP_PS_CTRL_DECY_SHIFT (8U)PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)PXP_PS_CTRL_DECX_MASK (0xC00U)PXP_PS_CTRL_DECX_SHIFT (10U)PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U)PXP_PS_CTRL_RSVD1_SHIFT (12U)PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK)PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU)PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U)PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U)PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U)PXP_PS_CTRL_SET_RSVD0_SHIFT (6U)PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)PXP_PS_CTRL_SET_DECY_MASK (0x300U)PXP_PS_CTRL_SET_DECY_SHIFT (8U)PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)PXP_PS_CTRL_SET_DECX_MASK (0xC00U)PXP_PS_CTRL_SET_DECX_SHIFT (10U)PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U)PXP_PS_CTRL_SET_RSVD1_SHIFT (12U)PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK)PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU)PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U)PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U)PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U)PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U)PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)PXP_PS_CTRL_CLR_DECY_MASK (0x300U)PXP_PS_CTRL_CLR_DECY_SHIFT (8U)PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)PXP_PS_CTRL_CLR_DECX_SHIFT (10U)PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U)PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U)PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK)PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU)PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U)PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U)PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U)PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U)PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)PXP_PS_CTRL_TOG_DECY_MASK (0x300U)PXP_PS_CTRL_TOG_DECY_SHIFT (8U)PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)PXP_PS_CTRL_TOG_DECX_SHIFT (10U)PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U)PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U)PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK)PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)PXP_PS_BUF_ADDR_SHIFT (0U)PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)PXP_PS_UBUF_ADDR_SHIFT (0U)PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)PXP_PS_VBUF_ADDR_SHIFT (0U)PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)PXP_PS_PITCH_PITCH_MASK (0xFFFFU)PXP_PS_PITCH_PITCH_SHIFT (0U)PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U)PXP_PS_PITCH_RSVD_SHIFT (16U)PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK)PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)PXP_PS_BACKGROUND_COLOR_SHIFT (0U)’PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)ÒPXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U)ĒPXP_PS_BACKGROUND_RSVD_SHIFT (24U)ŒPXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK)ȒPXP_PS_SCALE_XSCALE_MASK (0x7FFFU)ɒPXP_PS_SCALE_XSCALE_SHIFT (0U)ʒPXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)˒PXP_PS_SCALE_RSVD1_MASK (0x8000U)̒PXP_PS_SCALE_RSVD1_SHIFT (15U)͒PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK)ΒPXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)ϒPXP_PS_SCALE_YSCALE_SHIFT (16U)ВPXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)ђPXP_PS_SCALE_RSVD2_MASK (0x80000000U)ҒPXP_PS_SCALE_RSVD2_SHIFT (31U)ӒPXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK)֒PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)גPXP_PS_OFFSET_XOFFSET_SHIFT (0U)ؒPXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)ْPXP_PS_OFFSET_RSVD1_MASK (0xF000U)ڒPXP_PS_OFFSET_RSVD1_SHIFT (12U)ےPXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK)ܒPXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)ݒPXP_PS_OFFSET_YOFFSET_SHIFT (16U)ޒPXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)ߒPXP_PS_OFFSET_RSVD2_MASK (0xF0000000U)PXP_PS_OFFSET_RSVD2_SHIFT (28U)PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK)PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U)PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK)PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U)PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK)PXP_AS_CTRL_RSVD0_MASK (0x1U)PXP_AS_CTRL_RSVD0_SHIFT (0U)PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)PXP_AS_CTRL_FORMAT_MASK (0xF0U)PXP_AS_CTRL_FORMAT_SHIFT (4U)PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)PXP_AS_CTRL_ALPHA_MASK (0xFF00U)PXP_AS_CTRL_ALPHA_SHIFT (8U)PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)PXP_AS_CTRL_ROP_MASK (0xF0000U)PXP_AS_CTRL_ROP_SHIFT (16U)PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U)PXP_AS_CTRL_RSVD1_SHIFT (21U)PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK)PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)PXP_AS_BUF_ADDR_SHIFT (0U)PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)PXP_AS_PITCH_PITCH_MASK (0xFFFFU)PXP_AS_PITCH_PITCH_SHIFT (0U)PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U)PXP_AS_PITCH_RSVD_SHIFT (16U)PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK)PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U)PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK)PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK)PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)PXP_CSC1_COEF0_C0_SHIFT (18U)PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U)PXP_CSC1_COEF0_RSVD1_SHIFT (29U)PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK)PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)PXP_CSC1_COEF0_BYPASS_SHIFT (30U)PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)PXP_CSC1_COEF1_C4_MASK (0x7FFU)PXP_CSC1_COEF1_C4_SHIFT (0U)PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)“PXP_CSC1_COEF1_RSVD0_MASK (0xF800U)ÓPXP_CSC1_COEF1_RSVD0_SHIFT (11U)ēPXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK)œPXP_CSC1_COEF1_C1_MASK (0x7FF0000U)ƓPXP_CSC1_COEF1_C1_SHIFT (16U)ǓPXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)ȓPXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U)ɓPXP_CSC1_COEF1_RSVD1_SHIFT (27U)ʓPXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK)͓PXP_CSC1_COEF2_C3_MASK (0x7FFU)ΓPXP_CSC1_COEF2_C3_SHIFT (0U)ϓPXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)ГPXP_CSC1_COEF2_RSVD0_MASK (0xF800U)ѓPXP_CSC1_COEF2_RSVD0_SHIFT (11U)ғPXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK)ӓPXP_CSC1_COEF2_C2_MASK (0x7FF0000U)ԓPXP_CSC1_COEF2_C2_SHIFT (16U)ՓPXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)֓PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U)דPXP_CSC1_COEF2_RSVD1_SHIFT (27U)ؓPXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK)ۓPXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)ܓPXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)ݓPXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)ޓPXP_POWER_CTRL_MASK (0xFFFFF000U)ߓPXP_POWER_CTRL_SHIFT (12U)PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)PXP_NEXT_ENABLED_MASK (0x1U)PXP_NEXT_ENABLED_SHIFT (0U)PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)PXP_NEXT_RSVD_MASK (0x2U)PXP_NEXT_RSVD_SHIFT (1U)PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK)PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)PXP_NEXT_POINTER_SHIFT (2U)PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U)PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U)PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK)PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)PXP_BASE (0x402B4000u)PXP ((PXP_Type *)PXP_BASE)PXP_BASE_ADDRS { PXP_BASE }PXP_BASE_PTRS { PXP }PXP_IRQ0_IRQS { PXP_IRQn }ƔROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)ǔROMC_ROMPATCHD_DATAX_SHIFT (0U)ȔROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)˔ROMC_ROMPATCHD_COUNT (8U)ΔROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)ϔROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)ДROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)єROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)ҔROMC_ROMPATCHCNTL_DIS_SHIFT (29U)ӔROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)֔ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)הROMC_ROMPATCHENL_ENABLE_SHIFT (0U)ؔROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)۔ROMC_ROMPATCHA_THUMBX_MASK (0x1U)ܔROMC_ROMPATCHA_THUMBX_SHIFT (0U)ݔROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)ޔROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)ߔROMC_ROMPATCHA_ADDRX_SHIFT (1U)ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)ROMC_ROMPATCHA_COUNT (16U)ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)ROMC_ROMPATCHSR_SW_MASK (0x20000U)ROMC_ROMPATCHSR_SW_SHIFT (17U)ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)ROMC_BASE (0x40180000u)ROMC ((ROMC_Type *)ROMC_BASE)ROMC_BASE_ADDRS { ROMC_BASE }ROMC_BASE_PTRS { ROMC }RTWDOG_CS_STOP_MASK (0x1U)RTWDOG_CS_STOP_SHIFT (0U)RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)RTWDOG_CS_WAIT_MASK (0x2U)RTWDOG_CS_WAIT_SHIFT (1U)RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)RTWDOG_CS_DBG_MASK (0x4U)RTWDOG_CS_DBG_SHIFT (2U)RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)RTWDOG_CS_TST_MASK (0x18U)RTWDOG_CS_TST_SHIFT (3U)RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)RTWDOG_CS_UPDATE_MASK (0x20U)RTWDOG_CS_UPDATE_SHIFT (5U)RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)RTWDOG_CS_INT_MASK (0x40U)RTWDOG_CS_INT_SHIFT (6U)RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)RTWDOG_CS_EN_MASK (0x80U)RTWDOG_CS_EN_SHIFT (7U)RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)RTWDOG_CS_CLK_MASK (0x300U)RTWDOG_CS_CLK_SHIFT (8U)RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)RTWDOG_CS_RCS_MASK (0x400U)RTWDOG_CS_RCS_SHIFT (10U)RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)RTWDOG_CS_ULK_MASK (0x800U)RTWDOG_CS_ULK_SHIFT (11U)RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)RTWDOG_CS_PRES_MASK (0x1000U)RTWDOG_CS_PRES_SHIFT (12U)RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)RTWDOG_CS_CMD32EN_MASK (0x2000U)RTWDOG_CS_CMD32EN_SHIFT (13U)RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)RTWDOG_CS_FLG_MASK (0x4000U)•RTWDOG_CS_FLG_SHIFT (14U)ÕRTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)ĕRTWDOG_CS_WIN_MASK (0x8000U)ŕRTWDOG_CS_WIN_SHIFT (15U)ƕRTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)ɕRTWDOG_CNT_CNTLOW_MASK (0xFFU)ʕRTWDOG_CNT_CNTLOW_SHIFT (0U)˕RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)̕RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)͕RTWDOG_CNT_CNTHIGH_SHIFT (8U)ΕRTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)ѕRTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)ҕRTWDOG_TOVAL_TOVALLOW_SHIFT (0U)ӕRTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)ԕRTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)ՕRTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)֕RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)ٕRTWDOG_WIN_WINLOW_MASK (0xFFU)ڕRTWDOG_WIN_WINLOW_SHIFT (0U)ەRTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)ܕRTWDOG_WIN_WINHIGH_MASK (0xFF00U)ݕRTWDOG_WIN_WINHIGH_SHIFT (8U)ޕRTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)RTWDOG_BASE (0x400BC000u)RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)RTWDOG_BASE_ADDRS { RTWDOG_BASE }RTWDOG_BASE_PTRS { RTWDOG }RTWDOG_IRQS { RTWDOG_IRQn }RTWDOG_UPDATE_KEY (0xD928C520U)RTWDOG_REFRESH_KEY (0xB480A602U)ŖSEMC_MCR_SWRST_MASK (0x1U)ƖSEMC_MCR_SWRST_SHIFT (0U)ǖSEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)ȖSEMC_MCR_MDIS_MASK (0x2U)ɖSEMC_MCR_MDIS_SHIFT (1U)ʖSEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)˖SEMC_MCR_DQSMD_MASK (0x4U)̖SEMC_MCR_DQSMD_SHIFT (2U)͖SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)ΖSEMC_MCR_WPOL0_MASK (0x40U)ϖSEMC_MCR_WPOL0_SHIFT (6U)ЖSEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)іSEMC_MCR_WPOL1_MASK (0x80U)ҖSEMC_MCR_WPOL1_SHIFT (7U)ӖSEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)ԖSEMC_MCR_CTO_MASK (0xFF0000U)ՖSEMC_MCR_CTO_SHIFT (16U)֖SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)זSEMC_MCR_BTO_MASK (0x1F000000U)ؖSEMC_MCR_BTO_SHIFT (24U)ٖSEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)ܖSEMC_IOCR_MUX_A8_MASK (0x7U)ݖSEMC_IOCR_MUX_A8_SHIFT (0U)ޖSEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)ߖSEMC_IOCR_MUX_CSX0_MASK (0x38U)SEMC_IOCR_MUX_CSX0_SHIFT (3U)SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)SEMC_IOCR_MUX_CSX1_SHIFT (6U)SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)SEMC_IOCR_MUX_CSX2_MASK (0xE00U)SEMC_IOCR_MUX_CSX2_SHIFT (9U)SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)SEMC_IOCR_MUX_CSX3_MASK (0x7000U)SEMC_IOCR_MUX_CSX3_SHIFT (12U)SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)SEMC_IOCR_MUX_RDY_MASK (0x38000U)SEMC_IOCR_MUX_RDY_SHIFT (15U)SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)SEMC_BMCR0_WQOS_MASK (0xFU)SEMC_BMCR0_WQOS_SHIFT (0U)SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)SEMC_BMCR0_WAGE_MASK (0xF0U)SEMC_BMCR0_WAGE_SHIFT (4U)SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)SEMC_BMCR0_WSH_MASK (0xFF00U)SEMC_BMCR0_WSH_SHIFT (8U)SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)SEMC_BMCR0_WRWS_MASK (0xFF0000U)SEMC_BMCR0_WRWS_SHIFT (16U)SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)SEMC_BMCR1_WQOS_MASK (0xFU)SEMC_BMCR1_WQOS_SHIFT (0U)SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)SEMC_BMCR1_WAGE_MASK (0xF0U)SEMC_BMCR1_WAGE_SHIFT (4U)SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)SEMC_BMCR1_WPH_MASK (0xFF00U)SEMC_BMCR1_WPH_SHIFT (8U)SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)SEMC_BMCR1_WRWS_MASK (0xFF0000U)SEMC_BMCR1_WRWS_SHIFT (16U)SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)SEMC_BMCR1_WBR_MASK (0xFF000000U)SEMC_BMCR1_WBR_SHIFT (24U)SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)SEMC_BR_VLD_MASK (0x1U)SEMC_BR_VLD_SHIFT (0U)SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)SEMC_BR_MS_MASK (0x3EU)SEMC_BR_MS_SHIFT (1U)SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)SEMC_BR_BA_MASK (0xFFFFF000U)SEMC_BR_BA_SHIFT (12U)SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)SEMC_BR_COUNT (9U)SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)SEMC_INTEN_IPCMDERREN_MASK (0x2U)SEMC_INTEN_IPCMDERREN_SHIFT (1U)SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)SEMC_INTEN_AXICMDERREN_MASK (0x4U)SEMC_INTEN_AXICMDERREN_SHIFT (2U)SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)SEMC_INTEN_AXIBUSERREN_MASK (0x8U)SEMC_INTEN_AXIBUSERREN_SHIFT (3U)SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)SEMC_INTEN_NDNOPENDEN_MASK (0x20U)SEMC_INTEN_NDNOPENDEN_SHIFT (5U)SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)SEMC_INTR_IPCMDDONE_MASK (0x1U)SEMC_INTR_IPCMDDONE_SHIFT (0U)SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)SEMC_INTR_IPCMDERR_MASK (0x2U)SEMC_INTR_IPCMDERR_SHIFT (1U)SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)SEMC_INTR_AXICMDERR_MASK (0x4U)SEMC_INTR_AXICMDERR_SHIFT (2U)SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)SEMC_INTR_AXIBUSERR_MASK (0x8U)SEMC_INTR_AXIBUSERR_SHIFT (3U)SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)SEMC_INTR_NDPAGEEND_MASK (0x10U)SEMC_INTR_NDPAGEEND_SHIFT (4U)SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)SEMC_INTR_NDNOPEND_MASK (0x20U)SEMC_INTR_NDNOPEND_SHIFT (5U)—SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)ŗSEMC_SDRAMCR0_PS_MASK (0x1U)ƗSEMC_SDRAMCR0_PS_SHIFT (0U)ǗSEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)ȗSEMC_SDRAMCR0_BL_MASK (0x70U)ɗSEMC_SDRAMCR0_BL_SHIFT (4U)ʗSEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)˗SEMC_SDRAMCR0_COL_MASK (0x300U)̗SEMC_SDRAMCR0_COL_SHIFT (8U)͗SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)ΗSEMC_SDRAMCR0_CL_MASK (0xC00U)ϗSEMC_SDRAMCR0_CL_SHIFT (10U)ЗSEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)ӗSEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)ԗSEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)՗SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)֗SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)חSEMC_SDRAMCR1_ACT2RW_SHIFT (4U)ؗSEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)ٗSEMC_SDRAMCR1_RFRC_MASK (0x1F00U)ڗSEMC_SDRAMCR1_RFRC_SHIFT (8U)ۗSEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)ܗSEMC_SDRAMCR1_WRC_MASK (0xE000U)ݗSEMC_SDRAMCR1_WRC_SHIFT (13U)ޗSEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)ߗSEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)SEMC_SDRAMCR2_SRRC_MASK (0xFFU)SEMC_SDRAMCR2_SRRC_SHIFT (0U)SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)SEMC_SDRAMCR2_REF2REF_SHIFT (8U)SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)SEMC_SDRAMCR2_ITO_SHIFT (24U)SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)SEMC_SDRAMCR3_REN_MASK (0x1U)SEMC_SDRAMCR3_REN_SHIFT (0U)SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)SEMC_SDRAMCR3_REBL_MASK (0xEU)SEMC_SDRAMCR3_REBL_SHIFT (1U)SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)SEMC_SDRAMCR3_RT_MASK (0xFF0000U)SEMC_SDRAMCR3_RT_SHIFT (16U)SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)SEMC_SDRAMCR3_UT_MASK (0xFF000000U)SEMC_SDRAMCR3_UT_SHIFT (24U)SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)SEMC_NANDCR0_PS_MASK (0x1U)SEMC_NANDCR0_PS_SHIFT (0U)SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)SEMC_NANDCR0_BL_MASK (0x70U)SEMC_NANDCR0_BL_SHIFT (4U)SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)SEMC_NANDCR0_EDO_MASK (0x80U)SEMC_NANDCR0_EDO_SHIFT (7U)SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)SEMC_NANDCR0_COL_MASK (0x700U)SEMC_NANDCR0_COL_SHIFT (8U)SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)SEMC_NANDCR1_CES_MASK (0xFU)SEMC_NANDCR1_CES_SHIFT (0U)SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)SEMC_NANDCR1_CEH_MASK (0xF0U)SEMC_NANDCR1_CEH_SHIFT (4U)SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)SEMC_NANDCR1_WEL_MASK (0xF00U)SEMC_NANDCR1_WEL_SHIFT (8U)SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)SEMC_NANDCR1_WEH_MASK (0xF000U)SEMC_NANDCR1_WEH_SHIFT (12U)SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)SEMC_NANDCR1_REL_MASK (0xF0000U)SEMC_NANDCR1_REL_SHIFT (16U)SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)SEMC_NANDCR1_REH_MASK (0xF00000U)SEMC_NANDCR1_REH_SHIFT (20U)SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)SEMC_NANDCR1_TA_MASK (0xF000000U)SEMC_NANDCR1_TA_SHIFT (24U)SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)SEMC_NANDCR1_CEITV_MASK (0xF0000000U)SEMC_NANDCR1_CEITV_SHIFT (28U)SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)SEMC_NANDCR2_TWHR_MASK (0x3FU)SEMC_NANDCR2_TWHR_SHIFT (0U)SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)SEMC_NANDCR2_TRHW_MASK (0xFC0U)SEMC_NANDCR2_TRHW_SHIFT (6U)SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)SEMC_NANDCR2_TADL_MASK (0x3F000U)SEMC_NANDCR2_TADL_SHIFT (12U)SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)SEMC_NANDCR2_TRR_MASK (0xFC0000U)SEMC_NANDCR2_TRR_SHIFT (18U)SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)SEMC_NANDCR2_TWB_MASK (0x3F000000U)SEMC_NANDCR2_TWB_SHIFT (24U)SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)SEMC_NANDCR3_NDOPT1_MASK (0x1U)SEMC_NANDCR3_NDOPT1_SHIFT (0U)SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)˜SEMC_NANDCR3_NDOPT2_MASK (0x2U)ØSEMC_NANDCR3_NDOPT2_SHIFT (1U)ĘSEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)ŘSEMC_NANDCR3_NDOPT3_MASK (0x4U)ƘSEMC_NANDCR3_NDOPT3_SHIFT (2U)ǘSEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)ʘSEMC_NORCR0_PS_MASK (0x1U)˘SEMC_NORCR0_PS_SHIFT (0U)̘SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)͘SEMC_NORCR0_BL_MASK (0x70U)ΘSEMC_NORCR0_BL_SHIFT (4U)ϘSEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)ИSEMC_NORCR0_AM_MASK (0x300U)јSEMC_NORCR0_AM_SHIFT (8U)ҘSEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)ӘSEMC_NORCR0_ADVP_MASK (0x400U)ԘSEMC_NORCR0_ADVP_SHIFT (10U)՘SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)֘SEMC_NORCR0_COL_MASK (0xF000U)טSEMC_NORCR0_COL_SHIFT (12U)ؘSEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)ۘSEMC_NORCR1_CES_MASK (0xFU)ܘSEMC_NORCR1_CES_SHIFT (0U)ݘSEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)ޘSEMC_NORCR1_CEH_MASK (0xF0U)ߘSEMC_NORCR1_CEH_SHIFT (4U)SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)SEMC_NORCR1_AS_MASK (0xF00U)SEMC_NORCR1_AS_SHIFT (8U)SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)SEMC_NORCR1_AH_MASK (0xF000U)SEMC_NORCR1_AH_SHIFT (12U)SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)SEMC_NORCR1_WEL_MASK (0xF0000U)SEMC_NORCR1_WEL_SHIFT (16U)SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)SEMC_NORCR1_WEH_MASK (0xF00000U)SEMC_NORCR1_WEH_SHIFT (20U)SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)SEMC_NORCR1_REL_MASK (0xF000000U)SEMC_NORCR1_REL_SHIFT (24U)SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)SEMC_NORCR1_REH_MASK (0xF0000000U)SEMC_NORCR1_REH_SHIFT (28U)SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)SEMC_NORCR2_WDS_MASK (0xFU)SEMC_NORCR2_WDS_SHIFT (0U)SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)SEMC_NORCR2_WDH_MASK (0xF0U)SEMC_NORCR2_WDH_SHIFT (4U)SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)SEMC_NORCR2_TA_MASK (0xF00U)SEMC_NORCR2_TA_SHIFT (8U)SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)SEMC_NORCR2_AWDH_MASK (0xF000U)SEMC_NORCR2_AWDH_SHIFT (12U)SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)SEMC_NORCR2_LC_MASK (0xF0000U)SEMC_NORCR2_LC_SHIFT (16U)SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)SEMC_NORCR2_RD_MASK (0xF00000U)SEMC_NORCR2_RD_SHIFT (20U)SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)SEMC_NORCR2_CEITV_MASK (0xF000000U)SEMC_NORCR2_CEITV_SHIFT (24U)SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)SEMC_SRAMCR0_PS_MASK (0x1U)SEMC_SRAMCR0_PS_SHIFT (0U)SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)SEMC_SRAMCR0_BL_MASK (0x70U)SEMC_SRAMCR0_BL_SHIFT (4U)SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)SEMC_SRAMCR0_AM_MASK (0x300U)SEMC_SRAMCR0_AM_SHIFT (8U)SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)SEMC_SRAMCR0_ADVP_MASK (0x400U)SEMC_SRAMCR0_ADVP_SHIFT (10U)SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)SEMC_SRAMCR0_COL_MASK (0xF000U)SEMC_SRAMCR0_COL_SHIFT (12U)SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)SEMC_SRAMCR1_CES_MASK (0xFU)SEMC_SRAMCR1_CES_SHIFT (0U)SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)SEMC_SRAMCR1_CEH_MASK (0xF0U)SEMC_SRAMCR1_CEH_SHIFT (4U)SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)SEMC_SRAMCR1_AS_MASK (0xF00U)SEMC_SRAMCR1_AS_SHIFT (8U)SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)SEMC_SRAMCR1_AH_MASK (0xF000U)SEMC_SRAMCR1_AH_SHIFT (12U)SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)SEMC_SRAMCR1_WEL_MASK (0xF0000U)SEMC_SRAMCR1_WEL_SHIFT (16U)SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)SEMC_SRAMCR1_WEH_MASK (0xF00000U)SEMC_SRAMCR1_WEH_SHIFT (20U)SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)SEMC_SRAMCR1_REL_MASK (0xF000000U)SEMC_SRAMCR1_REL_SHIFT (24U)SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)SEMC_SRAMCR1_REH_MASK (0xF0000000U)SEMC_SRAMCR1_REH_SHIFT (28U)SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)SEMC_SRAMCR2_WDS_MASK (0xFU)SEMC_SRAMCR2_WDS_SHIFT (0U)SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)SEMC_SRAMCR2_WDH_MASK (0xF0U)SEMC_SRAMCR2_WDH_SHIFT (4U)SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)SEMC_SRAMCR2_TA_MASK (0xF00U)SEMC_SRAMCR2_TA_SHIFT (8U)SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)SEMC_SRAMCR2_AWDH_MASK (0xF000U)SEMC_SRAMCR2_AWDH_SHIFT (12U)™SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)ÙSEMC_SRAMCR2_LC_MASK (0xF0000U)ęSEMC_SRAMCR2_LC_SHIFT (16U)řSEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)ƙSEMC_SRAMCR2_RD_MASK (0xF00000U)ǙSEMC_SRAMCR2_RD_SHIFT (20U)șSEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)əSEMC_SRAMCR2_CEITV_MASK (0xF000000U)ʙSEMC_SRAMCR2_CEITV_SHIFT (24U)˙SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)ΙSEMC_DBICR0_PS_MASK (0x1U)ϙSEMC_DBICR0_PS_SHIFT (0U)ЙSEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)љSEMC_DBICR0_BL_MASK (0x70U)ҙSEMC_DBICR0_BL_SHIFT (4U)әSEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)ԙSEMC_DBICR0_COL_MASK (0xF000U)ՙSEMC_DBICR0_COL_SHIFT (12U)֙SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)ٙSEMC_DBICR1_CES_MASK (0xFU)ڙSEMC_DBICR1_CES_SHIFT (0U)ۙSEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)ܙSEMC_DBICR1_CEH_MASK (0xF0U)ݙSEMC_DBICR1_CEH_SHIFT (4U)ޙSEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)ߙSEMC_DBICR1_WEL_MASK (0xF00U)SEMC_DBICR1_WEL_SHIFT (8U)SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)SEMC_DBICR1_WEH_MASK (0xF000U)SEMC_DBICR1_WEH_SHIFT (12U)SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)SEMC_DBICR1_REL_MASK (0xF0000U)SEMC_DBICR1_REL_SHIFT (16U)SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)SEMC_DBICR1_REH_MASK (0xF00000U)SEMC_DBICR1_REH_SHIFT (20U)SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)SEMC_DBICR1_CEITV_MASK (0xF000000U)SEMC_DBICR1_CEITV_SHIFT (24U)SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)SEMC_IPCR0_SA_SHIFT (0U)SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)SEMC_IPCR1_DATSZ_MASK (0x7U)SEMC_IPCR1_DATSZ_SHIFT (0U)SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)SEMC_IPCR2_BM0_MASK (0x1U)SEMC_IPCR2_BM0_SHIFT (0U)SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)SEMC_IPCR2_BM1_MASK (0x2U)SEMC_IPCR2_BM1_SHIFT (1U)SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)SEMC_IPCR2_BM2_MASK (0x4U)SEMC_IPCR2_BM2_SHIFT (2U)SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)SEMC_IPCR2_BM3_MASK (0x8U)SEMC_IPCR2_BM3_SHIFT (3U)SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)SEMC_IPCMD_CMD_MASK (0xFFFFU)SEMC_IPCMD_CMD_SHIFT (0U)SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)SEMC_IPCMD_KEY_MASK (0xFFFF0000U)SEMC_IPCMD_KEY_SHIFT (16U)SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)SEMC_IPTXDAT_DAT_SHIFT (0U)SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)SEMC_IPRXDAT_DAT_SHIFT (0U)SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)SEMC_STS0_IDLE_MASK (0x1U)SEMC_STS0_IDLE_SHIFT (0U)SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)SEMC_STS0_NARDY_MASK (0x2U)SEMC_STS0_NARDY_SHIFT (1U)SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)SEMC_STS2_NDWRPEND_MASK (0x8U)SEMC_STS2_NDWRPEND_SHIFT (3U)SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)SEMC_STS12_NDADDR_SHIFT (0U)SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)SEMC_BASE (0x402F0000u)SEMC ((SEMC_Type *)SEMC_BASE)SEMC_BASE_ADDRS { SEMC_BASE }SEMC_BASE_PTRS { SEMC }SEMC_IRQS { SEMC_IRQn }SNVS_HPLR_ZMK_WSL_MASK (0x1U)SNVS_HPLR_ZMK_WSL_SHIFT (0U)SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)SNVS_HPLR_ZMK_RSL_MASK (0x2U)SNVS_HPLR_ZMK_RSL_SHIFT (1U)SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)SNVS_HPLR_SRTC_SL_MASK (0x4U)SNVS_HPLR_SRTC_SL_SHIFT (2U)SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)SNVS_HPLR_LPCALB_SL_MASK (0x8U)SNVS_HPLR_LPCALB_SL_SHIFT (3U)SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)SNVS_HPLR_MC_SL_MASK (0x10U)SNVS_HPLR_MC_SL_SHIFT (4U)SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)SNVS_HPLR_GPR_SL_MASK (0x20U)SNVS_HPLR_GPR_SL_SHIFT (5U)SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)SNVS_HPLR_LPSVCR_SL_MASK (0x40U)SNVS_HPLR_LPSVCR_SL_SHIFT (6U)SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)SNVS_HPLR_LPTDCR_SL_MASK (0x100U)SNVS_HPLR_LPTDCR_SL_SHIFT (8U)SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)SNVS_HPLR_MKS_SL_MASK (0x200U)SNVS_HPLR_MKS_SL_SHIFT (9U)SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)SNVS_HPLR_HPSVCR_L_MASK (0x10000U)SNVS_HPLR_HPSVCR_L_SHIFT (16U)SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)SNVS_HPLR_HPSICR_L_MASK (0x20000U)SNVS_HPLR_HPSICR_L_SHIFT (17U)SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)SNVS_HPLR_HAC_L_MASK (0x40000U)SNVS_HPLR_HAC_L_SHIFT (18U)SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)SNVS_HPCOMR_SSM_ST_MASK (0x1U)SNVS_HPCOMR_SSM_ST_SHIFT (0U)SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)SNVS_HPCOMR_LP_SWR_MASK (0x10U)SNVS_HPCOMR_LP_SWR_SHIFT (4U)SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)SNVS_HPCOMR_SW_SV_MASK (0x100U)SNVS_HPCOMR_SW_SV_SHIFT (8U)SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)SNVS_HPCOMR_SW_FSV_MASK (0x200U)SNVS_HPCOMR_SW_FSV_SHIFT (9U)SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)SNVS_HPCOMR_SW_LPSV_MASK (0x400U)SNVS_HPCOMR_SW_LPSV_SHIFT (10U)SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)SNVS_HPCOMR_MKS_EN_MASK (0x2000U)SNVS_HPCOMR_MKS_EN_SHIFT (13U)SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)SNVS_HPCOMR_HAC_EN_MASK (0x10000U)SNVS_HPCOMR_HAC_EN_SHIFT (16U)›SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)ÛSNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)ěSNVS_HPCOMR_HAC_LOAD_SHIFT (17U)śSNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)ƛSNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)ǛSNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)țSNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)ɛSNVS_HPCOMR_HAC_STOP_MASK (0x80000U)ʛSNVS_HPCOMR_HAC_STOP_SHIFT (19U)˛SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)̛SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)͛SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)ΛSNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)ћSNVS_HPCR_RTC_EN_MASK (0x1U)қSNVS_HPCR_RTC_EN_SHIFT (0U)ӛSNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)ԛSNVS_HPCR_HPTA_EN_MASK (0x2U)՛SNVS_HPCR_HPTA_EN_SHIFT (1U)֛SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)כSNVS_HPCR_PI_EN_MASK (0x8U)؛SNVS_HPCR_PI_EN_SHIFT (3U)ٛSNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)ڛSNVS_HPCR_PI_FREQ_MASK (0xF0U)ۛSNVS_HPCR_PI_FREQ_SHIFT (4U)ܛSNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)ݛSNVS_HPCR_HPCALB_EN_MASK (0x100U)ޛSNVS_HPCR_HPCALB_EN_SHIFT (8U)ߛSNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)SNVS_HPCR_HPCALB_VAL_SHIFT (10U)SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)SNVS_HPCR_HP_TS_MASK (0x10000U)SNVS_HPCR_HP_TS_SHIFT (16U)SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)SNVS_HPCR_BTN_CONFIG_SHIFT (24U)SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)SNVS_HPCR_BTN_MASK_MASK (0x8000000U)SNVS_HPCR_BTN_MASK_SHIFT (27U)SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)SNVS_HPSICR_SV0_EN_MASK (0x1U)SNVS_HPSICR_SV0_EN_SHIFT (0U)SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)SNVS_HPSICR_SV1_EN_MASK (0x2U)SNVS_HPSICR_SV1_EN_SHIFT (1U)SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)SNVS_HPSICR_SV2_EN_MASK (0x4U)SNVS_HPSICR_SV2_EN_SHIFT (2U)SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)SNVS_HPSICR_SV3_EN_MASK (0x8U)SNVS_HPSICR_SV3_EN_SHIFT (3U)SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)SNVS_HPSICR_SV4_EN_MASK (0x10U)SNVS_HPSICR_SV4_EN_SHIFT (4U)SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)SNVS_HPSICR_SV5_EN_MASK (0x20U)SNVS_HPSICR_SV5_EN_SHIFT (5U)SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)SNVS_HPSICR_LPSVI_EN_SHIFT (31U)SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)SNVS_HPSVCR_SV0_CFG_MASK (0x1U)SNVS_HPSVCR_SV0_CFG_SHIFT (0U)SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)SNVS_HPSVCR_SV1_CFG_MASK (0x2U)SNVS_HPSVCR_SV1_CFG_SHIFT (1U)SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)SNVS_HPSVCR_SV2_CFG_MASK (0x4U)SNVS_HPSVCR_SV2_CFG_SHIFT (2U)SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)SNVS_HPSVCR_SV3_CFG_MASK (0x8U)SNVS_HPSVCR_SV3_CFG_SHIFT (3U)SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)SNVS_HPSVCR_SV4_CFG_MASK (0x10U)SNVS_HPSVCR_SV4_CFG_SHIFT (4U)SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)SNVS_HPSVCR_SV5_CFG_MASK (0x60U)SNVS_HPSVCR_SV5_CFG_SHIFT (5U)SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)SNVS_HPSR_HPTA_MASK (0x1U)SNVS_HPSR_HPTA_SHIFT (0U)SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)SNVS_HPSR_PI_MASK (0x2U)SNVS_HPSR_PI_SHIFT (1U)SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)SNVS_HPSR_LPDIS_MASK (0x10U)SNVS_HPSR_LPDIS_SHIFT (4U)SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)SNVS_HPSR_BTN_MASK (0x40U)SNVS_HPSR_BTN_SHIFT (6U)SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)SNVS_HPSR_BI_MASK (0x80U)SNVS_HPSR_BI_SHIFT (7U)SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)SNVS_HPSR_SSM_STATE_MASK (0xF00U)SNVS_HPSR_SSM_STATE_SHIFT (8U)SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U)SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U)SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U)SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U)SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)SNVS_HPSR_ZMK_ZERO_SHIFT (31U)SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)SNVS_HPSVSR_SV0_MASK (0x1U)SNVS_HPSVSR_SV0_SHIFT (0U)SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)œSNVS_HPSVSR_SV1_MASK (0x2U)ÜSNVS_HPSVSR_SV1_SHIFT (1U)ĜSNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)ŜSNVS_HPSVSR_SV2_MASK (0x4U)ƜSNVS_HPSVSR_SV2_SHIFT (2U)ǜSNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)ȜSNVS_HPSVSR_SV3_MASK (0x8U)ɜSNVS_HPSVSR_SV3_SHIFT (3U)ʜSNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)˜SNVS_HPSVSR_SV4_MASK (0x10U)̜SNVS_HPSVSR_SV4_SHIFT (4U)͜SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)ΜSNVS_HPSVSR_SV5_MASK (0x20U)ϜSNVS_HPSVSR_SV5_SHIFT (5U)МSNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)ќSNVS_HPSVSR_SW_SV_MASK (0x2000U)ҜSNVS_HPSVSR_SW_SV_SHIFT (13U)ӜSNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)ԜSNVS_HPSVSR_SW_FSV_MASK (0x4000U)՜SNVS_HPSVSR_SW_FSV_SHIFT (14U)֜SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)לSNVS_HPSVSR_SW_LPSV_MASK (0x8000U)؜SNVS_HPSVSR_SW_LPSV_SHIFT (15U)ٜSNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)ڜSNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)ۜSNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)ܜSNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)ݜSNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)ޜSNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)ߜSNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)SNVS_HPRTCMR_RTC_MASK (0x7FFFU)SNVS_HPRTCMR_RTC_SHIFT (0U)SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)SNVS_HPRTCLR_RTC_SHIFT (0U)SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)SNVS_HPTAMR_HPTA_MS_SHIFT (0U)SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)SNVS_HPTALR_HPTA_LS_SHIFT (0U)SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)SNVS_LPLR_ZMK_WHL_MASK (0x1U)SNVS_LPLR_ZMK_WHL_SHIFT (0U)SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)SNVS_LPLR_ZMK_RHL_MASK (0x2U)SNVS_LPLR_ZMK_RHL_SHIFT (1U)SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)SNVS_LPLR_SRTC_HL_MASK (0x4U)SNVS_LPLR_SRTC_HL_SHIFT (2U)SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)SNVS_LPLR_LPCALB_HL_MASK (0x8U)SNVS_LPLR_LPCALB_HL_SHIFT (3U)SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)SNVS_LPLR_MC_HL_MASK (0x10U)SNVS_LPLR_MC_HL_SHIFT (4U)SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)SNVS_LPLR_GPR_HL_MASK (0x20U)SNVS_LPLR_GPR_HL_SHIFT (5U)SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)SNVS_LPLR_LPSVCR_HL_MASK (0x40U)SNVS_LPLR_LPSVCR_HL_SHIFT (6U)SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)SNVS_LPLR_LPTDCR_HL_MASK (0x100U)SNVS_LPLR_LPTDCR_HL_SHIFT (8U)SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)SNVS_LPLR_MKS_HL_MASK (0x200U)SNVS_LPLR_MKS_HL_SHIFT (9U)SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)SNVS_LPCR_SRTC_ENV_MASK (0x1U)SNVS_LPCR_SRTC_ENV_SHIFT (0U)SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)SNVS_LPCR_LPTA_EN_MASK (0x2U)SNVS_LPCR_LPTA_EN_SHIFT (1U)SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)SNVS_LPCR_MC_ENV_MASK (0x4U)SNVS_LPCR_MC_ENV_SHIFT (2U)SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)SNVS_LPCR_LPWUI_EN_MASK (0x8U)SNVS_LPCR_LPWUI_EN_SHIFT (3U)SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)SNVS_LPCR_DP_EN_MASK (0x20U)SNVS_LPCR_DP_EN_SHIFT (5U)SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)SNVS_LPCR_TOP_MASK (0x40U)SNVS_LPCR_TOP_SHIFT (6U)SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)SNVS_LPCR_LPCALB_EN_MASK (0x100U)SNVS_LPCR_LPCALB_EN_SHIFT (8U)SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)SNVS_LPCR_LPCALB_VAL_SHIFT (10U)SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)SNVS_LPCR_DEBOUNCE_SHIFT (18U)ÝSNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)ĝSNVS_LPCR_ON_TIME_MASK (0x300000U)ŝSNVS_LPCR_ON_TIME_SHIFT (20U)ƝSNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)ǝSNVS_LPCR_PK_EN_MASK (0x400000U)ȝSNVS_LPCR_PK_EN_SHIFT (22U)ɝSNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)ʝSNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)˝SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)̝SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)͝SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)ΝSNVS_LPCR_GPR_Z_DIS_SHIFT (24U)ϝSNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)ҝSNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)ӝSNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)ԝSNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)՝SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)֝SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)םSNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)؝SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)ٝSNVS_LPMKCR_ZMK_VAL_SHIFT (3U)ڝSNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)۝SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)ܝSNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)ݝSNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)ޝSNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)ߝSNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)SNVS_LPSVCR_SV0_EN_MASK (0x1U)SNVS_LPSVCR_SV0_EN_SHIFT (0U)SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)SNVS_LPSVCR_SV1_EN_MASK (0x2U)SNVS_LPSVCR_SV1_EN_SHIFT (1U)SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)SNVS_LPSVCR_SV2_EN_MASK (0x4U)SNVS_LPSVCR_SV2_EN_SHIFT (2U)SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)SNVS_LPSVCR_SV3_EN_MASK (0x8U)SNVS_LPSVCR_SV3_EN_SHIFT (3U)SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)SNVS_LPSVCR_SV4_EN_MASK (0x10U)SNVS_LPSVCR_SV4_EN_SHIFT (4U)SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)SNVS_LPSVCR_SV5_EN_MASK (0x20U)SNVS_LPSVCR_SV5_EN_SHIFT (5U)SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)SNVS_LPTDCR_MCR_EN_MASK (0x4U)SNVS_LPTDCR_MCR_EN_SHIFT (2U)SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)SNVS_LPTDCR_ET1_EN_MASK (0x200U)SNVS_LPTDCR_ET1_EN_SHIFT (9U)SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)SNVS_LPTDCR_ET1P_MASK (0x800U)SNVS_LPTDCR_ET1P_SHIFT (11U)SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)SNVS_LPTDCR_OSCB_MASK (0x10000000U)SNVS_LPTDCR_OSCB_SHIFT (28U)SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)SNVS_LPSR_LPTA_MASK (0x1U)SNVS_LPSR_LPTA_SHIFT (0U)SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)SNVS_LPSR_SRTCR_MASK (0x2U)SNVS_LPSR_SRTCR_SHIFT (1U)SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)SNVS_LPSR_MCR_MASK (0x4U)SNVS_LPSR_MCR_SHIFT (2U)SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)SNVS_LPSR_PGD_MASK (0x8U)SNVS_LPSR_PGD_SHIFT (3U)SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)SNVS_LPSR_ET1D_MASK (0x200U)SNVS_LPSR_ET1D_SHIFT (9U)SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)SNVS_LPSR_ESVD_MASK (0x10000U)SNVS_LPSR_ESVD_SHIFT (16U)SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)SNVS_LPSR_EO_MASK (0x20000U)SNVS_LPSR_EO_SHIFT (17U)SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)SNVS_LPSR_SPO_MASK (0x40000U)SNVS_LPSR_SPO_SHIFT (18U)SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)SNVS_LPSR_SED_MASK (0x100000U)SNVS_LPSR_SED_SHIFT (20U)SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)SNVS_LPSR_LPNS_MASK (0x40000000U)SNVS_LPSR_LPNS_SHIFT (30U)SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)SNVS_LPSR_LPS_MASK (0x80000000U)SNVS_LPSR_LPS_SHIFT (31U)SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)SNVS_LPSRTCMR_SRTC_SHIFT (0U)SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)SNVS_LPSRTCLR_SRTC_SHIFT (0U)SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)SNVS_LPTAR_LPTA_SHIFT (0U)SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)žSNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)ÞSNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)ĞSNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)ŞSNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)ȞSNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)ɞSNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)ʞSNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)͞SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)ΞSNVS_LPPGDR_PGD_SHIFT (0U)ϞSNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)ҞSNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)ӞSNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)ԞSNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)מSNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)؞SNVS_LPZMKR_ZMK_SHIFT (0U)ٞSNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)ܞSNVS_LPZMKR_COUNT (8U)ߞSNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)SNVS_LPGPR_ALIAS_COUNT (4U)SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR_GPR_SHIFT (0U)SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)SNVS_LPGPR_COUNT (4U)SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)SNVS_HPVIDR1_IP_ID_SHIFT (16U)SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)SNVS_HPVIDR2_ECO_REV_SHIFT (8U)SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)SNVS_HPVIDR2_IP_ERA_SHIFT (24U)SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)SNVS_BASE (0x400D4000u)SNVS ((SNVS_Type *)SNVS_BASE)SNVS_BASE_ADDRS { SNVS_BASE }SNVS_BASE_PTRS { SNVS }SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }͟SPDIF_SCR_USRC_SEL_MASK (0x3U)ΟSPDIF_SCR_USRC_SEL_SHIFT (0U)ϟSPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)ПSPDIF_SCR_TXSEL_MASK (0x1CU)џSPDIF_SCR_TXSEL_SHIFT (2U)ҟSPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)ӟSPDIF_SCR_VALCTRL_MASK (0x20U)ԟSPDIF_SCR_VALCTRL_SHIFT (5U)՟SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)֟SPDIF_SCR_DMA_TX_EN_MASK (0x100U)ןSPDIF_SCR_DMA_TX_EN_SHIFT (8U)؟SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)ٟSPDIF_SCR_DMA_RX_EN_MASK (0x200U)ڟSPDIF_SCR_DMA_RX_EN_SHIFT (9U)۟SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)ܟSPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)ݟSPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)ޟSPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)ߟSPDIF_SCR_SOFT_RESET_MASK (0x1000U)SPDIF_SCR_SOFT_RESET_SHIFT (12U)SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)SPDIF_SCR_LOW_POWER_MASK (0x2000U)SPDIF_SCR_LOW_POWER_SHIFT (13U)SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)SPDIF_SCR_RXFIFO_RST_SHIFT (21U)SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)SPDIF_SRCD_USYNCMODE_MASK (0x2U)SPDIF_SRCD_USYNCMODE_SHIFT (1U)SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)SPDIF_SRPC_GAINSEL_MASK (0x38U)SPDIF_SRPC_GAINSEL_SHIFT (3U)SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)SPDIF_SRPC_LOCK_MASK (0x40U)SPDIF_SRPC_LOCK_SHIFT (6U)SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)SPDIF_SIE_RXFIFOFUL_MASK (0x1U)SPDIF_SIE_RXFIFOFUL_SHIFT (0U)SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)SPDIF_SIE_TXEM_MASK (0x2U)SPDIF_SIE_TXEM_SHIFT (1U)SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)SPDIF_SIE_LOCKLOSS_MASK (0x4U)SPDIF_SIE_LOCKLOSS_SHIFT (2U)SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)SPDIF_SIE_RXFIFORESYN_MASK (0x8U)SPDIF_SIE_RXFIFORESYN_SHIFT (3U)SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)SPDIF_SIE_UQERR_MASK (0x20U)SPDIF_SIE_UQERR_SHIFT (5U)SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)SPDIF_SIE_UQSYNC_MASK (0x40U)SPDIF_SIE_UQSYNC_SHIFT (6U)SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)SPDIF_SIE_QRXOV_MASK (0x80U)SPDIF_SIE_QRXOV_SHIFT (7U)SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)SPDIF_SIE_QRXFUL_MASK (0x100U)SPDIF_SIE_QRXFUL_SHIFT (8U)SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)SPDIF_SIE_URXOV_MASK (0x200U)SPDIF_SIE_URXOV_SHIFT (9U)SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)SPDIF_SIE_URXFUL_MASK (0x400U)SPDIF_SIE_URXFUL_SHIFT (10U)SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)SPDIF_SIE_BITERR_MASK (0x4000U)SPDIF_SIE_BITERR_SHIFT (14U)SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)SPDIF_SIE_SYMERR_MASK (0x8000U)SPDIF_SIE_SYMERR_SHIFT (15U)SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)SPDIF_SIE_VALNOGOOD_MASK (0x10000U)SPDIF_SIE_VALNOGOOD_SHIFT (16U)SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)SPDIF_SIE_CNEW_MASK (0x20000U)SPDIF_SIE_CNEW_SHIFT (17U)SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)SPDIF_SIE_TXRESYN_MASK (0x40000U)SPDIF_SIE_TXRESYN_SHIFT (18U)SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)SPDIF_SIE_TXUNOV_MASK (0x80000U)SPDIF_SIE_TXUNOV_SHIFT (19U)SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)SPDIF_SIE_LOCK_MASK (0x100000U)SPDIF_SIE_LOCK_SHIFT (20U)SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)ĠSPDIF_SIC_LOCKLOSS_MASK (0x4U)ŠSPDIF_SIC_LOCKLOSS_SHIFT (2U)ƠSPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)ǠSPDIF_SIC_RXFIFORESYN_MASK (0x8U)ȠSPDIF_SIC_RXFIFORESYN_SHIFT (3U)ɠSPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)ʠSPDIF_SIC_RXFIFOUNOV_MASK (0x10U)ˠSPDIF_SIC_RXFIFOUNOV_SHIFT (4U)̠SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)͠SPDIF_SIC_UQERR_MASK (0x20U)ΠSPDIF_SIC_UQERR_SHIFT (5U)ϠSPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)РSPDIF_SIC_UQSYNC_MASK (0x40U)ѠSPDIF_SIC_UQSYNC_SHIFT (6U)ҠSPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)ӠSPDIF_SIC_QRXOV_MASK (0x80U)ԠSPDIF_SIC_QRXOV_SHIFT (7U)ՠSPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)֠SPDIF_SIC_URXOV_MASK (0x200U)נSPDIF_SIC_URXOV_SHIFT (9U)ؠSPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)٠SPDIF_SIC_BITERR_MASK (0x4000U)ڠSPDIF_SIC_BITERR_SHIFT (14U)۠SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)ܠSPDIF_SIC_SYMERR_MASK (0x8000U)ݠSPDIF_SIC_SYMERR_SHIFT (15U)ޠSPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)ߠSPDIF_SIC_VALNOGOOD_MASK (0x10000U)SPDIF_SIC_VALNOGOOD_SHIFT (16U)SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)SPDIF_SIC_CNEW_MASK (0x20000U)SPDIF_SIC_CNEW_SHIFT (17U)SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)SPDIF_SIC_TXRESYN_MASK (0x40000U)SPDIF_SIC_TXRESYN_SHIFT (18U)SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)SPDIF_SIC_TXUNOV_MASK (0x80000U)SPDIF_SIC_TXUNOV_SHIFT (19U)SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)SPDIF_SIC_LOCK_MASK (0x100000U)SPDIF_SIC_LOCK_SHIFT (20U)SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)SPDIF_SIS_RXFIFOFUL_MASK (0x1U)SPDIF_SIS_RXFIFOFUL_SHIFT (0U)SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)SPDIF_SIS_TXEM_MASK (0x2U)SPDIF_SIS_TXEM_SHIFT (1U)SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)SPDIF_SIS_LOCKLOSS_MASK (0x4U)SPDIF_SIS_LOCKLOSS_SHIFT (2U)SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)SPDIF_SIS_RXFIFORESYN_MASK (0x8U)SPDIF_SIS_RXFIFORESYN_SHIFT (3U)SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)SPDIF_SIS_UQERR_MASK (0x20U)SPDIF_SIS_UQERR_SHIFT (5U)SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)SPDIF_SIS_UQSYNC_MASK (0x40U)SPDIF_SIS_UQSYNC_SHIFT (6U)SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)SPDIF_SIS_QRXOV_MASK (0x80U)SPDIF_SIS_QRXOV_SHIFT (7U)SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)SPDIF_SIS_QRXFUL_MASK (0x100U)SPDIF_SIS_QRXFUL_SHIFT (8U)SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)SPDIF_SIS_URXOV_MASK (0x200U)SPDIF_SIS_URXOV_SHIFT (9U)SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)SPDIF_SIS_URXFUL_MASK (0x400U)SPDIF_SIS_URXFUL_SHIFT (10U)SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)SPDIF_SIS_BITERR_MASK (0x4000U)SPDIF_SIS_BITERR_SHIFT (14U)SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)SPDIF_SIS_SYMERR_MASK (0x8000U)SPDIF_SIS_SYMERR_SHIFT (15U)SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)SPDIF_SIS_VALNOGOOD_MASK (0x10000U)SPDIF_SIS_VALNOGOOD_SHIFT (16U)SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)SPDIF_SIS_CNEW_MASK (0x20000U)SPDIF_SIS_CNEW_SHIFT (17U)SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)SPDIF_SIS_TXRESYN_MASK (0x40000U)SPDIF_SIS_TXRESYN_SHIFT (18U)SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)SPDIF_SIS_TXUNOV_MASK (0x80000U)SPDIF_SIS_TXUNOV_SHIFT (19U)SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)SPDIF_SIS_LOCK_MASK (0x100000U)SPDIF_SIS_LOCK_SHIFT (20U)SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)SPDIF_SRL_RXDATALEFT_SHIFT (0U)SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)SPDIF_SRR_RXDATARIGHT_SHIFT (0U)SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)SPDIF_SRU_RXUCHANNEL_SHIFT (0U)SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)¡SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)áSPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)ơSPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)ǡSPDIF_STL_TXDATALEFT_SHIFT (0U)ȡSPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)ˡSPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)̡SPDIF_STR_TXDATARIGHT_SHIFT (0U)͡SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)СSPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)ѡSPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)ҡSPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)աSPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)֡SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)סSPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)ڡSPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)ۡSPDIF_SRFM_FREQMEAS_SHIFT (0U)ܡSPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)ߡSPDIF_STC_TXCLK_DF_MASK (0x7FU)SPDIF_STC_TXCLK_DF_SHIFT (0U)SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)SPDIF_STC_SYSCLK_DF_SHIFT (11U)SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)SPDIF_BASE (0x40380000u)SPDIF ((SPDIF_Type *)SPDIF_BASE)SPDIF_BASE_ADDRS { SPDIF_BASE }SPDIF_BASE_PTRS { SPDIF }SPDIF_IRQS { SPDIF_IRQn }SRC_SCR_LOCKUP_RST_MASK (0x10U)SRC_SCR_LOCKUP_RST_SHIFT (4U)SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK)SRC_SCR_MASK_WDOG_RST_MASK (0x780U)SRC_SCR_MASK_WDOG_RST_SHIFT (7U)SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)SRC_SCR_CORE0_RST_MASK (0x2000U)SRC_SCR_CORE0_RST_SHIFT (13U)SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)SRC_SCR_CORE0_DBG_RST_SHIFT (17U)SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)SRC_SBMR1_BOOT_CFG1_SHIFT (0U)SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)SRC_SBMR1_BOOT_CFG2_SHIFT (8U)SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)SRC_SBMR1_BOOT_CFG3_SHIFT (16U)SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)SRC_SBMR1_BOOT_CFG4_SHIFT (24U)SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)¢SRC_SRSR_IPP_RESET_B_MASK (0x1U)âSRC_SRSR_IPP_RESET_B_SHIFT (0U)ĢSRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)ŢSRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)ƢSRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)ǢSRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)ȢSRC_SRSR_CSU_RESET_B_MASK (0x4U)ɢSRC_SRSR_CSU_RESET_B_SHIFT (2U)ʢSRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)ˢSRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)̢SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)͢SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)΢SRC_SRSR_WDOG_RST_B_MASK (0x10U)ϢSRC_SRSR_WDOG_RST_B_SHIFT (4U)ТSRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)ѢSRC_SRSR_JTAG_RST_B_MASK (0x20U)ҢSRC_SRSR_JTAG_RST_B_SHIFT (5U)ӢSRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)ԢSRC_SRSR_JTAG_SW_RST_MASK (0x40U)բSRC_SRSR_JTAG_SW_RST_SHIFT (6U)֢SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)עSRC_SRSR_WDOG3_RST_B_MASK (0x80U)آSRC_SRSR_WDOG3_RST_B_SHIFT (7U)٢SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)ڢSRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)ۢSRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)ܢSRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)ߢSRC_SBMR2_SEC_CONFIG_MASK (0x3U)SRC_SBMR2_SEC_CONFIG_SHIFT (0U)SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)SRC_SBMR2_BMOD_MASK (0x3000000U)SRC_SBMR2_BMOD_SHIFT (24U)SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)SRC_GPR_COUNT (10U)SRC_BASE (0x400F8000u)SRC ((SRC_Type *)SRC_BASE)SRC_BASE_ADDRS { SRC_BASE }SRC_BASE_PTRS { SRC }SRC_IRQS { SRC_IRQn }SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASKSRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFTSRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASKSRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFTSRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASKSRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFTSRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASKSRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFTSRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASKSRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFTSRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK | SRC_SRSR_JTAG_SW_RST_MASK | SRC_SRSR_JTAG_RST_B_MASK | SRC_SRSR_WDOG_RST_B_MASK | SRC_SRSR_IPP_USER_RESET_B_MASK | SRC_SRSR_CSU_RESET_B_MASK | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK | SRC_SRSR_IPP_RESET_B_MASK)ͣTEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)ΣTEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)ϣTEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)УTEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)ѣTEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)ңTEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)ӣTEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)ԣTEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)գTEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)֣TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)ףTEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)أTEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)٣TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)ڣTEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)ۣTEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)ޣTEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)ߣTEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)¤TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)̤TEMPMON_BASE (0x400D8000u)ΤTEMPMON ((TEMPMON_Type *)TEMPMON_BASE)ФTEMPMON_BASE_ADDRS { TEMPMON_BASE }ҤTEMPMON_BASE_PTRS { TEMPMON }TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)TMR_COMP1_COMPARISON_1_SHIFT (0U)TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)TMR_COMP1_COUNT (4U)TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)TMR_COMP2_COMPARISON_2_SHIFT (0U)TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)TMR_COMP2_COUNT (4U)TMR_CAPT_CAPTURE_MASK (0xFFFFU)TMR_CAPT_CAPTURE_SHIFT (0U)TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)TMR_CAPT_COUNT (4U)TMR_LOAD_LOAD_MASK (0xFFFFU)TMR_LOAD_LOAD_SHIFT (0U)TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)TMR_LOAD_COUNT (4U)TMR_HOLD_HOLD_MASK (0xFFFFU)TMR_HOLD_HOLD_SHIFT (0U)TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)TMR_HOLD_COUNT (4U)TMR_CNTR_COUNTER_MASK (0xFFFFU)TMR_CNTR_COUNTER_SHIFT (0U)TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)TMR_CNTR_COUNT (4U)TMR_CTRL_OUTMODE_MASK (0x7U)TMR_CTRL_OUTMODE_SHIFT (0U)TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)TMR_CTRL_COINIT_MASK (0x8U)TMR_CTRL_COINIT_SHIFT (3U)TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)TMR_CTRL_DIR_MASK (0x10U)TMR_CTRL_DIR_SHIFT (4U)TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)TMR_CTRL_LENGTH_MASK (0x20U)TMR_CTRL_LENGTH_SHIFT (5U)TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)TMR_CTRL_ONCE_MASK (0x40U)TMR_CTRL_ONCE_SHIFT (6U)TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)TMR_CTRL_SCS_MASK (0x180U)TMR_CTRL_SCS_SHIFT (7U)¥TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)åTMR_CTRL_PCS_MASK (0x1E00U)ĥTMR_CTRL_PCS_SHIFT (9U)ťTMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)ƥTMR_CTRL_CM_MASK (0xE000U)ǥTMR_CTRL_CM_SHIFT (13U)ȥTMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)˥TMR_CTRL_COUNT (4U)ΥTMR_SCTRL_OEN_MASK (0x1U)ϥTMR_SCTRL_OEN_SHIFT (0U)ХTMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)ѥTMR_SCTRL_OPS_MASK (0x2U)ҥTMR_SCTRL_OPS_SHIFT (1U)ӥTMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)ԥTMR_SCTRL_FORCE_MASK (0x4U)եTMR_SCTRL_FORCE_SHIFT (2U)֥TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)ץTMR_SCTRL_VAL_MASK (0x8U)إTMR_SCTRL_VAL_SHIFT (3U)٥TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)ڥTMR_SCTRL_EEOF_MASK (0x10U)ۥTMR_SCTRL_EEOF_SHIFT (4U)ܥTMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)ݥTMR_SCTRL_MSTR_MASK (0x20U)ޥTMR_SCTRL_MSTR_SHIFT (5U)ߥTMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)TMR_SCTRL_INPUT_MASK (0x100U)TMR_SCTRL_INPUT_SHIFT (8U)TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)TMR_SCTRL_IPS_MASK (0x200U)TMR_SCTRL_IPS_SHIFT (9U)TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)TMR_SCTRL_IEFIE_MASK (0x400U)TMR_SCTRL_IEFIE_SHIFT (10U)TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)TMR_SCTRL_IEF_MASK (0x800U)TMR_SCTRL_IEF_SHIFT (11U)TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)TMR_SCTRL_TOFIE_MASK (0x1000U)TMR_SCTRL_TOFIE_SHIFT (12U)TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)TMR_SCTRL_TOF_MASK (0x2000U)TMR_SCTRL_TOF_SHIFT (13U)TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)TMR_SCTRL_TCFIE_MASK (0x4000U)TMR_SCTRL_TCFIE_SHIFT (14U)TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)TMR_SCTRL_TCF_MASK (0x8000U)TMR_SCTRL_TCF_SHIFT (15U)TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)TMR_SCTRL_COUNT (4U)TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)TMR_CMPLD1_COUNT (4U)TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)TMR_CMPLD2_COUNT (4U)TMR_CSCTRL_CL1_MASK (0x3U)TMR_CSCTRL_CL1_SHIFT (0U)TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)TMR_CSCTRL_CL2_MASK (0xCU)TMR_CSCTRL_CL2_SHIFT (2U)TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)TMR_CSCTRL_TCF1_MASK (0x10U)TMR_CSCTRL_TCF1_SHIFT (4U)TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)TMR_CSCTRL_TCF2_MASK (0x20U)TMR_CSCTRL_TCF2_SHIFT (5U)TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)TMR_CSCTRL_TCF1EN_MASK (0x40U)TMR_CSCTRL_TCF1EN_SHIFT (6U)TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)TMR_CSCTRL_TCF2EN_MASK (0x80U)TMR_CSCTRL_TCF2EN_SHIFT (7U)TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)TMR_CSCTRL_UP_MASK (0x200U)TMR_CSCTRL_UP_SHIFT (9U)TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)TMR_CSCTRL_TCI_MASK (0x400U)TMR_CSCTRL_TCI_SHIFT (10U)TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)TMR_CSCTRL_ROC_MASK (0x800U)TMR_CSCTRL_ROC_SHIFT (11U)TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)TMR_CSCTRL_ALT_LOAD_SHIFT (12U)TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)TMR_CSCTRL_FAULT_MASK (0x2000U)TMR_CSCTRL_FAULT_SHIFT (13U)TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)TMR_CSCTRL_DBG_EN_MASK (0xC000U)TMR_CSCTRL_DBG_EN_SHIFT (14U)TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)TMR_CSCTRL_COUNT (4U)TMR_FILT_FILT_PER_MASK (0xFFU)TMR_FILT_FILT_PER_SHIFT (0U)TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)TMR_FILT_FILT_CNT_MASK (0x700U)TMR_FILT_FILT_CNT_SHIFT (8U)TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)TMR_FILT_COUNT (4U)ĦTMR_DMA_IEFDE_MASK (0x1U)ŦTMR_DMA_IEFDE_SHIFT (0U)ƦTMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)ǦTMR_DMA_CMPLD1DE_MASK (0x2U)ȦTMR_DMA_CMPLD1DE_SHIFT (1U)ɦTMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)ʦTMR_DMA_CMPLD2DE_MASK (0x4U)˦TMR_DMA_CMPLD2DE_SHIFT (2U)̦TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)ϦTMR_DMA_COUNT (4U)ҦTMR_ENBL_ENBL_MASK (0xFU)ӦTMR_ENBL_ENBL_SHIFT (0U)ԦTMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)צTMR_ENBL_COUNT (4U)TMR1_BASE (0x401DC000u)TMR1 ((TMR_Type *)TMR1_BASE)TMR2_BASE (0x401E0000u)TMR2 ((TMR_Type *)TMR2_BASE)TMR3_BASE (0x401E4000u)TMR3 ((TMR_Type *)TMR3_BASE)TMR4_BASE (0x401E8000u)TMR4 ((TMR_Type *)TMR4_BASE)TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }ѧTRNG_MCTL_SAMP_MODE_MASK (0x3U)ҧTRNG_MCTL_SAMP_MODE_SHIFT (0U)ӧTRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)ԧTRNG_MCTL_OSC_DIV_MASK (0xCU)էTRNG_MCTL_OSC_DIV_SHIFT (2U)֧TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)קTRNG_MCTL_UNUSED4_MASK (0x10U)اTRNG_MCTL_UNUSED4_SHIFT (4U)٧TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)ڧTRNG_MCTL_UNUSED5_MASK (0x20U)ۧTRNG_MCTL_UNUSED5_SHIFT (5U)ܧTRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)ݧTRNG_MCTL_RST_DEF_MASK (0x40U)ާTRNG_MCTL_RST_DEF_SHIFT (6U)ߧTRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)TRNG_MCTL_FOR_SCLK_MASK (0x80U)TRNG_MCTL_FOR_SCLK_SHIFT (7U)TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)TRNG_MCTL_FCT_FAIL_MASK (0x100U)TRNG_MCTL_FCT_FAIL_SHIFT (8U)TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)TRNG_MCTL_FCT_VAL_MASK (0x200U)TRNG_MCTL_FCT_VAL_SHIFT (9U)TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)TRNG_MCTL_ENT_VAL_MASK (0x400U)TRNG_MCTL_ENT_VAL_SHIFT (10U)TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)TRNG_MCTL_TST_OUT_MASK (0x800U)TRNG_MCTL_TST_OUT_SHIFT (11U)TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)TRNG_MCTL_ERR_MASK (0x1000U)TRNG_MCTL_ERR_SHIFT (12U)TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)TRNG_MCTL_TSTOP_OK_MASK (0x2000U)TRNG_MCTL_TSTOP_OK_SHIFT (13U)TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)TRNG_MCTL_LRUN_CONT_MASK (0x4000U)TRNG_MCTL_LRUN_CONT_SHIFT (14U)TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)TRNG_MCTL_PRGM_MASK (0x10000U)TRNG_MCTL_PRGM_SHIFT (16U)TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)TRNG_SCMISC_LRUN_MAX_SHIFT (0U)TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)TRNG_SCMISC_RTY_CT_MASK (0xF0000U)TRNG_SCMISC_RTY_CT_SHIFT (16U)TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)TRNG_PKRRNG_PKR_RNG_SHIFT (0U)TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)TRNG_PKRMAX_PKR_MAX_SHIFT (0U)TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)TRNG_PKRSQ_PKR_SQ_SHIFT (0U)TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)TRNG_SDCTL_ENT_DLY_SHIFT (16U)TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)TRNG_SBLIM_SB_LIM_MASK (0x3FFU)TRNG_SBLIM_SB_LIM_SHIFT (0U)TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)TRNG_TOTSAM_TOT_SAM_SHIFT (0U)TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)TRNG_FRQCNT_FRQ_CT_SHIFT (0U)TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)TRNG_SCMC_MONO_CT_MASK (0xFFFFU)TRNG_SCMC_MONO_CT_SHIFT (0U)TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)TRNG_SCML_MONO_MAX_MASK (0xFFFFU)TRNG_SCML_MONO_MAX_SHIFT (0U)TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)TRNG_SCML_MONO_RNG_SHIFT (16U)TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)¨TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)èTRNG_SCR1C_R1_0_CT_SHIFT (0U)ĨTRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)ŨTRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)ƨTRNG_SCR1C_R1_1_CT_SHIFT (16U)ǨTRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)ʨTRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)˨TRNG_SCR1L_RUN1_MAX_SHIFT (0U)̨TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)ͨTRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)ΨTRNG_SCR1L_RUN1_RNG_SHIFT (16U)ϨTRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)ҨTRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)ӨTRNG_SCR2C_R2_0_CT_SHIFT (0U)ԨTRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)ըTRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)֨TRNG_SCR2C_R2_1_CT_SHIFT (16U)רTRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)ڨTRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)ۨTRNG_SCR2L_RUN2_MAX_SHIFT (0U)ܨTRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)ݨTRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)ިTRNG_SCR2L_RUN2_RNG_SHIFT (16U)ߨTRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)TRNG_SCR3C_R3_0_CT_SHIFT (0U)TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)TRNG_SCR3C_R3_1_CT_SHIFT (16U)TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)TRNG_SCR3L_RUN3_MAX_SHIFT (0U)TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)TRNG_SCR3L_RUN3_RNG_SHIFT (16U)TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)TRNG_SCR4C_R4_0_CT_SHIFT (0U)TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)TRNG_SCR4C_R4_1_CT_SHIFT (16U)TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)TRNG_SCR4L_RUN4_MAX_SHIFT (0U)TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)TRNG_SCR4L_RUN4_RNG_SHIFT (16U)TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)TRNG_SCR5C_R5_0_CT_SHIFT (0U)TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)TRNG_SCR5C_R5_1_CT_SHIFT (16U)TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)TRNG_SCR5L_RUN5_MAX_SHIFT (0U)TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)TRNG_SCR5L_RUN5_RNG_SHIFT (16U)TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)TRNG_STATUS_TF1BR0_MASK (0x1U)TRNG_STATUS_TF1BR0_SHIFT (0U)TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)TRNG_STATUS_TF1BR1_MASK (0x2U)TRNG_STATUS_TF1BR1_SHIFT (1U)TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)TRNG_STATUS_TF2BR0_MASK (0x4U)TRNG_STATUS_TF2BR0_SHIFT (2U)TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)TRNG_STATUS_TF2BR1_MASK (0x8U)TRNG_STATUS_TF2BR1_SHIFT (3U)TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)TRNG_STATUS_TF3BR0_MASK (0x10U)TRNG_STATUS_TF3BR0_SHIFT (4U)TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)TRNG_STATUS_TF3BR1_MASK (0x20U)TRNG_STATUS_TF3BR1_SHIFT (5U)TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)TRNG_STATUS_TF4BR0_MASK (0x40U)TRNG_STATUS_TF4BR0_SHIFT (6U)TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)TRNG_STATUS_TF4BR1_MASK (0x80U)TRNG_STATUS_TF4BR1_SHIFT (7U)TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)TRNG_STATUS_TF5BR0_MASK (0x100U)TRNG_STATUS_TF5BR0_SHIFT (8U)TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)TRNG_STATUS_TF5BR1_MASK (0x200U)TRNG_STATUS_TF5BR1_SHIFT (9U)TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)TRNG_STATUS_TF6PBR0_MASK (0x400U)TRNG_STATUS_TF6PBR0_SHIFT (10U)©TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)éTRNG_STATUS_TF6PBR1_MASK (0x800U)ĩTRNG_STATUS_TF6PBR1_SHIFT (11U)ũTRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)ƩTRNG_STATUS_TFSB_MASK (0x1000U)ǩTRNG_STATUS_TFSB_SHIFT (12U)ȩTRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)ɩTRNG_STATUS_TFLR_MASK (0x2000U)ʩTRNG_STATUS_TFLR_SHIFT (13U)˩TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)̩TRNG_STATUS_TFP_MASK (0x4000U)ͩTRNG_STATUS_TFP_SHIFT (14U)ΩTRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)ϩTRNG_STATUS_TFMB_MASK (0x8000U)ЩTRNG_STATUS_TFMB_SHIFT (15U)ѩTRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)ҩTRNG_STATUS_RETRY_CT_MASK (0xF0000U)өTRNG_STATUS_RETRY_CT_SHIFT (16U)ԩTRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)שTRNG_ENT_ENT_MASK (0xFFFFFFFFU)ةTRNG_ENT_ENT_SHIFT (0U)٩TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)ܩTRNG_ENT_COUNT (16U)ߩTRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)TRNG_SEC_CFG_UNUSED0_MASK (0x1U)TRNG_SEC_CFG_UNUSED0_SHIFT (0U)TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)TRNG_SEC_CFG_UNUSED2_MASK (0x4U)TRNG_SEC_CFG_UNUSED2_SHIFT (2U)TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)TRNG_INT_CTRL_HW_ERR_MASK (0x1U)TRNG_INT_CTRL_HW_ERR_SHIFT (0U)TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)TRNG_INT_CTRL_UNUSED_SHIFT (3U)TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)TRNG_INT_MASK_HW_ERR_MASK (0x1U)TRNG_INT_MASK_HW_ERR_SHIFT (0U)TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)TRNG_INT_MASK_ENT_VAL_MASK (0x2U)TRNG_INT_MASK_ENT_VAL_SHIFT (1U)TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)êTRNG_INT_STATUS_HW_ERR_MASK (0x1U)ĪTRNG_INT_STATUS_HW_ERR_SHIFT (0U)ŪTRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)ƪTRNG_INT_STATUS_ENT_VAL_MASK (0x2U)ǪTRNG_INT_STATUS_ENT_VAL_SHIFT (1U)ȪTRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)ɪTRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)ʪTRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)˪TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)ΪTRNG_VID1_MIN_REV_MASK (0xFFU)ϪTRNG_VID1_MIN_REV_SHIFT (0U)ЪTRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)ѪTRNG_VID1_MAJ_REV_MASK (0xFF00U)ҪTRNG_VID1_MAJ_REV_SHIFT (8U)ӪTRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)ԪTRNG_VID1_IP_ID_MASK (0xFFFF0000U)ժTRNG_VID1_IP_ID_SHIFT (16U)֪TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)٪TRNG_VID2_CONFIG_OPT_MASK (0xFFU)ڪTRNG_VID2_CONFIG_OPT_SHIFT (0U)۪TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)ܪTRNG_VID2_ECO_REV_MASK (0xFF00U)ݪTRNG_VID2_ECO_REV_SHIFT (8U)ުTRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)ߪTRNG_VID2_INTG_OPT_MASK (0xFF0000U)TRNG_VID2_INTG_OPT_SHIFT (16U)TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)TRNG_VID2_ERA_MASK (0xFF000000U)TRNG_VID2_ERA_SHIFT (24U)TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)TRNG_BASE (0x400CC000u)TRNG ((TRNG_Type *)TRNG_BASE)TRNG_BASE_ADDRS { TRNG_BASE }TRNG_BASE_PTRS { TRNG }TRNG_IRQS { TRNG_IRQn }TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U)TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U)TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK)TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U)TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK)TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)«TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)ëTSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)ƫTSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)ǫTSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)ȫTSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)ɫTSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)ʫTSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)˫TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)ΫTSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)ϫTSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)ЫTSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)ѫTSC_INT_EN_DETECT_INT_EN_MASK (0x10U)ҫTSC_INT_EN_DETECT_INT_EN_SHIFT (4U)ӫTSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)ԫTSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)իTSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)֫TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)٫TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)ګTSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)۫TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)ܫTSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)ݫTSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)ޫTSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)߫TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)TSC_INT_STATUS_MEASURE_MASK (0x1U)TSC_INT_STATUS_MEASURE_SHIFT (0U)TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)TSC_INT_STATUS_DETECT_MASK (0x10U)TSC_INT_STATUS_DETECT_SHIFT (4U)TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)TSC_INT_STATUS_VALID_MASK (0x100U)TSC_INT_STATUS_VALID_SHIFT (8U)TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)TSC_INT_STATUS_IDLE_SW_SHIFT (12U)TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)¬TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)ìTSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)ĬTSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)ŬTSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)ƬTSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)ǬTSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)ȬTSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)ɬTSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)ʬTSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)ˬTSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)̬TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)ͬTSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)׬TSC_BASE (0x400E0000u)٬TSC ((TSC_Type *)TSC_BASE)۬TSC_BASE_ADDRS { TSC_BASE }ݬTSC_BASE_PTRS { TSC }߬TSC_IRQS { TSC_DIG_IRQn }TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASKTSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFTTSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x)USB_ID_ID_MASK (0x3FU)USB_ID_ID_SHIFT (0U)USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)USB_ID_NID_MASK (0x3F00U)USB_ID_NID_SHIFT (8U)USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)USB_ID_REVISION_MASK (0xFF0000U)USB_ID_REVISION_SHIFT (16U)USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)íUSB_HWGENERAL_PHYW_MASK (0x30U)ĭUSB_HWGENERAL_PHYW_SHIFT (4U)ŭUSB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)ƭUSB_HWGENERAL_PHYM_MASK (0x1C0U)ǭUSB_HWGENERAL_PHYM_SHIFT (6U)ȭUSB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)ɭUSB_HWGENERAL_SM_MASK (0x600U)ʭUSB_HWGENERAL_SM_SHIFT (9U)˭USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)έUSB_HWHOST_HC_MASK (0x1U)ϭUSB_HWHOST_HC_SHIFT (0U)ЭUSB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)ѭUSB_HWHOST_NPORT_MASK (0xEU)ҭUSB_HWHOST_NPORT_SHIFT (1U)ӭUSB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)֭USB_HWDEVICE_DC_MASK (0x1U)׭USB_HWDEVICE_DC_SHIFT (0U)حUSB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)٭USB_HWDEVICE_DEVEP_MASK (0x3EU)ڭUSB_HWDEVICE_DEVEP_SHIFT (1U)ۭUSB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)ޭUSB_HWTXBUF_TXBURST_MASK (0xFFU)߭USB_HWTXBUF_TXBURST_SHIFT (0U)USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)USB_HWTXBUF_TXCHANADD_SHIFT (16U)USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)USB_HWRXBUF_RXBURST_MASK (0xFFU)USB_HWRXBUF_RXBURST_SHIFT (0U)USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)USB_HWRXBUF_RXADD_MASK (0xFF00U)USB_HWRXBUF_RXADD_SHIFT (8U)USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER0LD_GPTLD_SHIFT (0U)USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER1LD_GPTLD_SHIFT (0U)USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)USB_SBUSCFG_AHBBRST_MASK (0x7U)USB_SBUSCFG_AHBBRST_SHIFT (0U)USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)USB_HCIVERSION_HCIVERSION_SHIFT (0U)USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)USB_HCSPARAMS_N_PORTS_MASK (0xFU)USB_HCSPARAMS_N_PORTS_SHIFT (0U)USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)USB_HCSPARAMS_PPC_MASK (0x10U)USB_HCSPARAMS_PPC_SHIFT (4U)USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)USB_HCSPARAMS_N_PCC_MASK (0xF00U)USB_HCSPARAMS_N_PCC_SHIFT (8U)USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)USB_HCSPARAMS_N_CC_MASK (0xF000U)USB_HCSPARAMS_N_CC_SHIFT (12U)USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)USB_HCSPARAMS_PI_MASK (0x10000U)USB_HCSPARAMS_PI_SHIFT (16U)USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)USB_HCSPARAMS_N_PTT_MASK (0xF00000U)USB_HCSPARAMS_N_PTT_SHIFT (20U)USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)USB_HCSPARAMS_N_TT_MASK (0xF000000U)USB_HCSPARAMS_N_TT_SHIFT (24U)USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)USB_HCCPARAMS_ADC_MASK (0x1U)USB_HCCPARAMS_ADC_SHIFT (0U)USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)USB_HCCPARAMS_PFL_MASK (0x2U)USB_HCCPARAMS_PFL_SHIFT (1U)USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)USB_HCCPARAMS_ASP_MASK (0x4U)USB_HCCPARAMS_ASP_SHIFT (2U)®USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)îUSB_HCCPARAMS_IST_MASK (0xF0U)ĮUSB_HCCPARAMS_IST_SHIFT (4U)ŮUSB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)ƮUSB_HCCPARAMS_EECP_MASK (0xFF00U)ǮUSB_HCCPARAMS_EECP_SHIFT (8U)ȮUSB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)ˮUSB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)̮USB_DCIVERSION_DCIVERSION_SHIFT (0U)ͮUSB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)ЮUSB_DCCPARAMS_DEN_MASK (0x1FU)ѮUSB_DCCPARAMS_DEN_SHIFT (0U)ҮUSB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)ӮUSB_DCCPARAMS_DC_MASK (0x80U)ԮUSB_DCCPARAMS_DC_SHIFT (7U)ծUSB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)֮USB_DCCPARAMS_HC_MASK (0x100U)׮USB_DCCPARAMS_HC_SHIFT (8U)خUSB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)ۮUSB_USBCMD_RS_MASK (0x1U)ܮUSB_USBCMD_RS_SHIFT (0U)ݮUSB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)ޮUSB_USBCMD_RST_MASK (0x2U)߮USB_USBCMD_RST_SHIFT (1U)USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)USB_USBCMD_FS_1_MASK (0xCU)USB_USBCMD_FS_1_SHIFT (2U)USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)USB_USBCMD_PSE_MASK (0x10U)USB_USBCMD_PSE_SHIFT (4U)USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)USB_USBCMD_ASE_MASK (0x20U)USB_USBCMD_ASE_SHIFT (5U)USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)USB_USBCMD_IAA_MASK (0x40U)USB_USBCMD_IAA_SHIFT (6U)USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)USB_USBCMD_ASP_MASK (0x300U)USB_USBCMD_ASP_SHIFT (8U)USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)USB_USBCMD_ASPE_MASK (0x800U)USB_USBCMD_ASPE_SHIFT (11U)USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)USB_USBCMD_ATDTW_MASK (0x1000U)USB_USBCMD_ATDTW_SHIFT (12U)USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)USB_USBCMD_SUTW_MASK (0x2000U)USB_USBCMD_SUTW_SHIFT (13U)USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)USB_USBCMD_FS_2_MASK (0x8000U)USB_USBCMD_FS_2_SHIFT (15U)USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)USB_USBCMD_ITC_MASK (0xFF0000U)USB_USBCMD_ITC_SHIFT (16U)USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)USB_USBSTS_UI_MASK (0x1U)USB_USBSTS_UI_SHIFT (0U)USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)USB_USBSTS_UEI_MASK (0x2U)USB_USBSTS_UEI_SHIFT (1U)USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)USB_USBSTS_PCI_MASK (0x4U)USB_USBSTS_PCI_SHIFT (2U)USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)USB_USBSTS_FRI_MASK (0x8U)USB_USBSTS_FRI_SHIFT (3U)USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)USB_USBSTS_SEI_MASK (0x10U)USB_USBSTS_SEI_SHIFT (4U)USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)USB_USBSTS_AAI_MASK (0x20U)USB_USBSTS_AAI_SHIFT (5U)USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)USB_USBSTS_URI_MASK (0x40U)USB_USBSTS_URI_SHIFT (6U)USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)USB_USBSTS_SRI_MASK (0x80U)USB_USBSTS_SRI_SHIFT (7U)USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)USB_USBSTS_SLI_MASK (0x100U)USB_USBSTS_SLI_SHIFT (8U)USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)USB_USBSTS_ULPII_MASK (0x400U)USB_USBSTS_ULPII_SHIFT (10U)USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)USB_USBSTS_HCH_MASK (0x1000U)USB_USBSTS_HCH_SHIFT (12U)USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)USB_USBSTS_RCL_MASK (0x2000U)USB_USBSTS_RCL_SHIFT (13U)USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)USB_USBSTS_PS_MASK (0x4000U)USB_USBSTS_PS_SHIFT (14U)USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)USB_USBSTS_AS_MASK (0x8000U)USB_USBSTS_AS_SHIFT (15U)USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)USB_USBSTS_NAKI_MASK (0x10000U)USB_USBSTS_NAKI_SHIFT (16U)USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)USB_USBSTS_TI0_MASK (0x1000000U)USB_USBSTS_TI0_SHIFT (24U)USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)USB_USBSTS_TI1_MASK (0x2000000U)USB_USBSTS_TI1_SHIFT (25U)USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)USB_USBINTR_UE_MASK (0x1U)USB_USBINTR_UE_SHIFT (0U)USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)USB_USBINTR_UEE_MASK (0x2U)USB_USBINTR_UEE_SHIFT (1U)USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)USB_USBINTR_PCE_MASK (0x4U)USB_USBINTR_PCE_SHIFT (2U)USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)USB_USBINTR_FRE_MASK (0x8U)USB_USBINTR_FRE_SHIFT (3U)USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)¯USB_USBINTR_SEE_MASK (0x10U)ïUSB_USBINTR_SEE_SHIFT (4U)įUSB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)ůUSB_USBINTR_AAE_MASK (0x20U)ƯUSB_USBINTR_AAE_SHIFT (5U)ǯUSB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)ȯUSB_USBINTR_URE_MASK (0x40U)ɯUSB_USBINTR_URE_SHIFT (6U)ʯUSB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)˯USB_USBINTR_SRE_MASK (0x80U)̯USB_USBINTR_SRE_SHIFT (7U)ͯUSB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)ίUSB_USBINTR_SLE_MASK (0x100U)ϯUSB_USBINTR_SLE_SHIFT (8U)ЯUSB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)ѯUSB_USBINTR_ULPIE_MASK (0x400U)үUSB_USBINTR_ULPIE_SHIFT (10U)ӯUSB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)ԯUSB_USBINTR_NAKE_MASK (0x10000U)կUSB_USBINTR_NAKE_SHIFT (16U)֯USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)ׯUSB_USBINTR_UAIE_MASK (0x40000U)دUSB_USBINTR_UAIE_SHIFT (18U)ٯUSB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)گUSB_USBINTR_UPIE_MASK (0x80000U)ۯUSB_USBINTR_UPIE_SHIFT (19U)ܯUSB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)ݯUSB_USBINTR_TIE0_MASK (0x1000000U)ޯUSB_USBINTR_TIE0_SHIFT (24U)߯USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)USB_USBINTR_TIE1_MASK (0x2000000U)USB_USBINTR_TIE1_SHIFT (25U)USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)USB_FRINDEX_FRINDEX_MASK (0x3FFFU)USB_FRINDEX_FRINDEX_SHIFT (0U)USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)USB_DEVICEADDR_USBADRA_MASK (0x1000000U)USB_DEVICEADDR_USBADRA_SHIFT (24U)USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)USB_DEVICEADDR_USBADR_MASK (0xFE000000U)USB_DEVICEADDR_USBADR_SHIFT (25U)USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)USB_BURSTSIZE_RXPBURST_MASK (0xFFU)USB_BURSTSIZE_RXPBURST_SHIFT (0U)USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)USB_BURSTSIZE_TXPBURST_SHIFT (8U)USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)USB_ENDPTNAK_EPRN_MASK (0xFFU)USB_ENDPTNAK_EPRN_SHIFT (0U)USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)USB_ENDPTNAK_EPTN_MASK (0xFF0000U)USB_ENDPTNAK_EPTN_SHIFT (16U)USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)USB_ENDPTNAKEN_EPRNE_SHIFT (0U)USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)USB_ENDPTNAKEN_EPTNE_SHIFT (16U)USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)USB_CONFIGFLAG_CF_MASK (0x1U)USB_CONFIGFLAG_CF_SHIFT (0U)USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)USB_PORTSC1_CCS_MASK (0x1U)USB_PORTSC1_CCS_SHIFT (0U)USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)USB_PORTSC1_CSC_MASK (0x2U)USB_PORTSC1_CSC_SHIFT (1U)USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)USB_PORTSC1_PE_MASK (0x4U)USB_PORTSC1_PE_SHIFT (2U)USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)USB_PORTSC1_PEC_MASK (0x8U)USB_PORTSC1_PEC_SHIFT (3U)USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)USB_PORTSC1_OCA_MASK (0x10U)USB_PORTSC1_OCA_SHIFT (4U)USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)USB_PORTSC1_OCC_MASK (0x20U)USB_PORTSC1_OCC_SHIFT (5U)USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)USB_PORTSC1_FPR_MASK (0x40U)USB_PORTSC1_FPR_SHIFT (6U)USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)USB_PORTSC1_SUSP_MASK (0x80U)USB_PORTSC1_SUSP_SHIFT (7U)USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)USB_PORTSC1_PR_MASK (0x100U)°USB_PORTSC1_PR_SHIFT (8U)ðUSB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)İUSB_PORTSC1_HSP_MASK (0x200U)ŰUSB_PORTSC1_HSP_SHIFT (9U)ưUSB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)ǰUSB_PORTSC1_LS_MASK (0xC00U)ȰUSB_PORTSC1_LS_SHIFT (10U)ɰUSB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)ʰUSB_PORTSC1_PP_MASK (0x1000U)˰USB_PORTSC1_PP_SHIFT (12U)̰USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)ͰUSB_PORTSC1_PO_MASK (0x2000U)ΰUSB_PORTSC1_PO_SHIFT (13U)ϰUSB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)аUSB_PORTSC1_PIC_MASK (0xC000U)ѰUSB_PORTSC1_PIC_SHIFT (14U)ҰUSB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)ӰUSB_PORTSC1_PTC_MASK (0xF0000U)԰USB_PORTSC1_PTC_SHIFT (16U)հUSB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)ְUSB_PORTSC1_WKCN_MASK (0x100000U)װUSB_PORTSC1_WKCN_SHIFT (20U)ذUSB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)ٰUSB_PORTSC1_WKDC_MASK (0x200000U)ڰUSB_PORTSC1_WKDC_SHIFT (21U)۰USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)ܰUSB_PORTSC1_WKOC_MASK (0x400000U)ݰUSB_PORTSC1_WKOC_SHIFT (22U)ްUSB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)߰USB_PORTSC1_PHCD_MASK (0x800000U)USB_PORTSC1_PHCD_SHIFT (23U)USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)USB_PORTSC1_PFSC_MASK (0x1000000U)USB_PORTSC1_PFSC_SHIFT (24U)USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)USB_PORTSC1_PTS_2_MASK (0x2000000U)USB_PORTSC1_PTS_2_SHIFT (25U)USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)USB_PORTSC1_PSPD_MASK (0xC000000U)USB_PORTSC1_PSPD_SHIFT (26U)USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)USB_PORTSC1_PTW_MASK (0x10000000U)USB_PORTSC1_PTW_SHIFT (28U)USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)USB_PORTSC1_STS_MASK (0x20000000U)USB_PORTSC1_STS_SHIFT (29U)USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)USB_PORTSC1_PTS_1_MASK (0xC0000000U)USB_PORTSC1_PTS_1_SHIFT (30U)USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)USB_OTGSC_VD_MASK (0x1U)USB_OTGSC_VD_SHIFT (0U)USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)USB_OTGSC_VC_MASK (0x2U)USB_OTGSC_VC_SHIFT (1U)USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)USB_OTGSC_OT_MASK (0x8U)USB_OTGSC_OT_SHIFT (3U)USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)USB_OTGSC_DP_MASK (0x10U)USB_OTGSC_DP_SHIFT (4U)USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)USB_OTGSC_IDPU_MASK (0x20U)USB_OTGSC_IDPU_SHIFT (5U)USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)USB_OTGSC_ID_MASK (0x100U)USB_OTGSC_ID_SHIFT (8U)USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)USB_OTGSC_AVV_MASK (0x200U)USB_OTGSC_AVV_SHIFT (9U)USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)USB_OTGSC_ASV_MASK (0x400U)USB_OTGSC_ASV_SHIFT (10U)USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)USB_OTGSC_BSV_MASK (0x800U)USB_OTGSC_BSV_SHIFT (11U)USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)USB_OTGSC_BSE_MASK (0x1000U)USB_OTGSC_BSE_SHIFT (12U)USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)USB_OTGSC_TOG_1MS_MASK (0x2000U)USB_OTGSC_TOG_1MS_SHIFT (13U)USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)USB_OTGSC_DPS_MASK (0x4000U)USB_OTGSC_DPS_SHIFT (14U)USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)USB_OTGSC_IDIS_MASK (0x10000U)USB_OTGSC_IDIS_SHIFT (16U)USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)USB_OTGSC_AVVIS_MASK (0x20000U)USB_OTGSC_AVVIS_SHIFT (17U)USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)USB_OTGSC_ASVIS_MASK (0x40000U)USB_OTGSC_ASVIS_SHIFT (18U)USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)USB_OTGSC_BSVIS_MASK (0x80000U)USB_OTGSC_BSVIS_SHIFT (19U)USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)USB_OTGSC_BSEIS_MASK (0x100000U)USB_OTGSC_BSEIS_SHIFT (20U)USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)USB_OTGSC_STATUS_1MS_MASK (0x200000U)USB_OTGSC_STATUS_1MS_SHIFT (21U)USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)USB_OTGSC_DPIS_MASK (0x400000U)USB_OTGSC_DPIS_SHIFT (22U)USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)USB_OTGSC_IDIE_MASK (0x1000000U)USB_OTGSC_IDIE_SHIFT (24U)USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)USB_OTGSC_AVVIE_MASK (0x2000000U)USB_OTGSC_AVVIE_SHIFT (25U)USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)USB_OTGSC_ASVIE_MASK (0x4000000U)USB_OTGSC_ASVIE_SHIFT (26U)USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)USB_OTGSC_BSVIE_MASK (0x8000000U)USB_OTGSC_BSVIE_SHIFT (27U)USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)USB_OTGSC_BSEIE_MASK (0x10000000U)USB_OTGSC_BSEIE_SHIFT (28U)USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)USB_OTGSC_EN_1MS_MASK (0x20000000U)USB_OTGSC_EN_1MS_SHIFT (29U)USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)USB_OTGSC_DPIE_MASK (0x40000000U)±USB_OTGSC_DPIE_SHIFT (30U)ñUSB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)ƱUSB_USBMODE_CM_MASK (0x3U)DZUSB_USBMODE_CM_SHIFT (0U)ȱUSB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)ɱUSB_USBMODE_ES_MASK (0x4U)ʱUSB_USBMODE_ES_SHIFT (2U)˱USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)̱USB_USBMODE_SLOM_MASK (0x8U)ͱUSB_USBMODE_SLOM_SHIFT (3U)αUSB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)ϱUSB_USBMODE_SDIS_MASK (0x10U)бUSB_USBMODE_SDIS_SHIFT (4U)ѱUSB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)ԱUSB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)ձUSB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)ֱUSB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)ٱUSB_ENDPTPRIME_PERB_MASK (0xFFU)ڱUSB_ENDPTPRIME_PERB_SHIFT (0U)۱USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)ܱUSB_ENDPTPRIME_PETB_MASK (0xFF0000U)ݱUSB_ENDPTPRIME_PETB_SHIFT (16U)ޱUSB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)USB_ENDPTFLUSH_FERB_MASK (0xFFU)USB_ENDPTFLUSH_FERB_SHIFT (0U)USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)USB_ENDPTFLUSH_FETB_SHIFT (16U)USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)USB_ENDPTSTAT_ERBR_MASK (0xFFU)USB_ENDPTSTAT_ERBR_SHIFT (0U)USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)USB_ENDPTSTAT_ETBR_SHIFT (16U)USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)USB_ENDPTCTRL0_RXS_MASK (0x1U)USB_ENDPTCTRL0_RXS_SHIFT (0U)USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)USB_ENDPTCTRL0_RXT_MASK (0xCU)USB_ENDPTCTRL0_RXT_SHIFT (2U)USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)USB_ENDPTCTRL0_RXE_MASK (0x80U)USB_ENDPTCTRL0_RXE_SHIFT (7U)USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)USB_ENDPTCTRL0_TXS_MASK (0x10000U)USB_ENDPTCTRL0_TXS_SHIFT (16U)USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)USB_ENDPTCTRL0_TXT_MASK (0xC0000U)USB_ENDPTCTRL0_TXT_SHIFT (18U)USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)USB_ENDPTCTRL0_TXE_MASK (0x800000U)USB_ENDPTCTRL0_TXE_SHIFT (23U)USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)USB_ENDPTCTRL_RXS_MASK (0x1U)USB_ENDPTCTRL_RXS_SHIFT (0U)USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)USB_ENDPTCTRL_RXD_MASK (0x2U)USB_ENDPTCTRL_RXD_SHIFT (1U)USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)USB_ENDPTCTRL_RXT_MASK (0xCU)USB_ENDPTCTRL_RXT_SHIFT (2U)USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)USB_ENDPTCTRL_RXI_MASK (0x20U)USB_ENDPTCTRL_RXI_SHIFT (5U)USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)USB_ENDPTCTRL_RXR_MASK (0x40U)USB_ENDPTCTRL_RXR_SHIFT (6U)USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)USB_ENDPTCTRL_RXE_MASK (0x80U)USB_ENDPTCTRL_RXE_SHIFT (7U)USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)USB_ENDPTCTRL_TXS_MASK (0x10000U)USB_ENDPTCTRL_TXS_SHIFT (16U)USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)USB_ENDPTCTRL_TXD_MASK (0x20000U)USB_ENDPTCTRL_TXD_SHIFT (17U)USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)USB_ENDPTCTRL_TXT_MASK (0xC0000U)USB_ENDPTCTRL_TXT_SHIFT (18U)USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)USB_ENDPTCTRL_TXI_MASK (0x200000U)USB_ENDPTCTRL_TXI_SHIFT (21U)USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)USB_ENDPTCTRL_TXR_MASK (0x400000U)USB_ENDPTCTRL_TXR_SHIFT (22U)USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)USB_ENDPTCTRL_TXE_MASK (0x800000U)USB_ENDPTCTRL_TXE_SHIFT (23U)USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)USB_ENDPTCTRL_COUNT (7U)USB1_BASE (0x402E0000u)USB1 ((USB_Type *)USB1_BASE)USB2_BASE (0x402E0200u)òUSB2 ((USB_Type *)USB2_BASE)ŲUSB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }DzUSB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }ɲUSB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }˲GPTIMER0CTL GPTIMER0CTRL̲GPTIMER1CTL GPTIMER1CTRLͲUSB_SBUSCFG SBUSCFGβEPLISTADDR ENDPTLISTADDRϲEPSETUPSR ENDPTSETUPSTATвEPPRIME ENDPTPRIMEѲEPFLUSH ENDPTFLUSHҲEPSR ENDPTSTATӲEPCOMPLETE ENDPTCOMPLETEԲEPCR ENDPTCTRLղEPCR0 ENDPTCTRL0ֲUSBHS_ID_ID_MASK USB_ID_ID_MASKײUSBHS_ID_ID_SHIFT USB_ID_ID_SHIFTزUSBHS_ID_ID(x) USB_ID_ID(x)ٲUSBHS_ID_NID_MASK USB_ID_NID_MASKڲUSBHS_ID_NID_SHIFT USB_ID_NID_SHIFT۲USBHS_ID_NID(x) USB_ID_NID(x)ܲUSBHS_ID_REVISION_MASK USB_ID_REVISION_MASKݲUSBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT޲USBHS_ID_REVISION(x) USB_ID_REVISION(x)߲USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASKUSBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFTUSBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASKUSBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFTUSBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASKUSBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFTUSBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASKUSBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFTUSBHS_HWHOST_HC(x) USB_HWHOST_HC(x)USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASKUSBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFTUSBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASKUSBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFTUSBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASKUSBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFTUSBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASKUSBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFTUSBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASKUSBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFTUSBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASKUSBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFTUSBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASKUSBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFTUSBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASKUSBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFTUSBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASKUSBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFTUSBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASKUSBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFTUSBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASKUSBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFTUSBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASKUSBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFTUSBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASKUSBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFTUSBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASKUSBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFTUSBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASKUSBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFTUSBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASKUSBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFTUSBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASKUSBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFTUSBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASKUSBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFTUSBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASKUSBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFTUSBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASKUSBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFTUSBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASKUSBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFTUSBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASKUSBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFTUSBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASKUSBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFTUSBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASKUSBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFTUSBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASKUSBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFTUSBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASKUSBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFTUSBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASKUSBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFTUSBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASKUSBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFTUSBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASKUSBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT³USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)óUSBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASKijUSBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFTųUSBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)ƳUSBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASKdzUSBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFTȳUSBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)ɳUSBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASKʳUSBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT˳USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)̳USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASKͳUSBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFTγUSBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)ϳUSBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASKгUSBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFTѳUSBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)ҳUSBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASKӳUSBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFTԳUSBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)ճUSBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASKֳUSBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT׳USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)سUSBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASKٳUSBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFTڳUSBHS_USBCMD_RST(x) USB_USBCMD_RST(x)۳USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASKܳUSBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFTݳUSBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)޳USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK߳USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFTUSBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASKUSBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFTUSBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASKUSBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFTUSBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASKUSBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFTUSBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASKUSBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFTUSBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASKUSBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFTUSBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASKUSBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFTUSBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASKUSBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFTUSBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASKUSBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFTUSBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASKUSBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFTUSBHS_USBSTS_UI(x) USB_USBSTS_UI(x)USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASKUSBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFTUSBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASKUSBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFTUSBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASKUSBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFTUSBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASKUSBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFTUSBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASKUSBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFTUSBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASKUSBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFTUSBHS_USBSTS_URI(x) USB_USBSTS_URI(x)USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASKUSBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFTUSBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASKUSBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFTUSBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASKUSBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFTUSBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASKUSBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFTUSBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASKUSBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFTUSBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASKUSBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFTUSBHS_USBSTS_PS(x) USB_USBSTS_PS(x)USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASKUSBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFTUSBHS_USBSTS_AS(x) USB_USBSTS_AS(x)USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASKUSBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFTUSBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASKUSBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFTUSBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASKUSBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFTUSBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASKUSBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFTUSBHS_USBINTR_UE(x) USB_USBINTR_UE(x)USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASKUSBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFTUSBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASKUSBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFTUSBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASKUSBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFTUSBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASKUSBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFTUSBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASKUSBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFTUSBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASKUSBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFTUSBHS_USBINTR_URE(x) USB_USBINTR_URE(x)USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK´USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFTôUSBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)ĴUSBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASKŴUSBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFTƴUSBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)ǴUSBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASKȴUSBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFTɴUSBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)ʴUSBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK˴USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT̴USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)ʹUSBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASKδUSBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFTϴUSBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)дUSBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASKѴUSBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFTҴUSBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)ӴUSBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASKԴUSBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFTմUSBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)ִUSBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK״USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFTشUSBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)ٴUSBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASKڴUSBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT۴USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)ܴUSBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASKݴUSBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT޴USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)ߴUSBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASKUSBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFTUSBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASKUSBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFTUSBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASKUSBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFTUSBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASKUSBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFTUSBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASKUSBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFTUSBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASKUSBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFTUSBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASKUSBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFTUSBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASKUSBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFTUSBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASKUSBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFTUSBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASKUSBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFTUSBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASKUSBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFTUSBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASKUSBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFTUSBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASKUSBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFTUSBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASKUSBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFTUSBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASKUSBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFTUSBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASKUSBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFTUSBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASKUSBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFTUSBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASKUSBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFTUSBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASKUSBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFTUSBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASKUSBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFTUSBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASKUSBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFTUSBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASKUSBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFTUSBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASKUSBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFTUSBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASKUSBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFTUSBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASKUSBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFTUSBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASKUSBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFTUSBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASKUSBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFTUSBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASKUSBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFTUSBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASKUSBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFTUSBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASKUSBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFTUSBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASKUSBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFTUSBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASKUSBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFTUSBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASKUSBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFTUSBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)µUSBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASKõUSBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFTĵUSBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)ŵUSBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASKƵUSBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFTǵUSBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)ȵUSBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASKɵUSBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFTʵUSBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)˵USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK̵USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT͵USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)εUSBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASKϵUSBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFTеUSBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)ѵUSBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASKҵUSBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFTӵUSBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)ԵUSBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASKյUSBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFTֵUSBHS_OTGSC_VD(x) USB_OTGSC_VD(x)׵USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASKصUSBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFTٵUSBHS_OTGSC_VC(x) USB_OTGSC_VC(x)ڵUSBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK۵USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFTܵUSBHS_OTGSC_OT(x) USB_OTGSC_OT(x)ݵUSBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK޵USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFTߵUSBHS_OTGSC_DP(x) USB_OTGSC_DP(x)USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASKUSBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFTUSBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASKUSBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFTUSBHS_OTGSC_ID(x) USB_OTGSC_ID(x)USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASKUSBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFTUSBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASKUSBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFTUSBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASKUSBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFTUSBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASKUSBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFTUSBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASKUSBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFTUSBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASKUSBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFTUSBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASKUSBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFTUSBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASKUSBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFTUSBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASKUSBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFTUSBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASKUSBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFTUSBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASKUSBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFTUSBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASKUSBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFTUSBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASKUSBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFTUSBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASKUSBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFTUSBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASKUSBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFTUSBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASKUSBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFTUSBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASKUSBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFTUSBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASKUSBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFTUSBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASKUSBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFTUSBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASKUSBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFTUSBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASKUSBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFTUSBHS_USBMODE_CM(x) USB_USBMODE_CM(x)USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASKUSBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFTUSBHS_USBMODE_ES(x) USB_USBMODE_ES(x)USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASKUSBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFTUSBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASKUSBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFTUSBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASKUSBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFTUSBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASKUSBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFTUSBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASKUSBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFTUSBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASKUSBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFTUSBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASKUSBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFTUSBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASKUSBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFTUSBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASKUSBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT¶USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)öUSBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASKĶUSBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFTŶUSBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)ƶUSBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASKǶUSBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFTȶUSBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)ɶUSBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASKʶUSBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT˶USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)̶USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASKͶUSBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFTζUSBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)϶USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASKжUSBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFTѶUSBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)ҶUSBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASKӶUSBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFTԶUSBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)նUSBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASKֶUSBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT׶USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)ضUSBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASKٶUSBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFTڶUSBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)۶USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASKܶUSBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFTݶUSBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)޶USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK߶USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFTUSBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASKUSBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFTUSBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASKUSBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFTUSBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASKUSBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFTUSBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASKUSBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFTUSBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASKUSBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFTUSBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASKUSBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFTUSBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASKUSBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFTUSBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASKUSBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFTUSBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASKUSBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFTUSBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASKUSBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFTUSBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNTUSBHS_Type USB_TypeUSBHS_BASE_ADDRS { USB1_BASE, USB2_BASE }USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }USBHS_IRQHandler USB_OTG1_IRQHandlerUSBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)·USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)÷USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)ƷUSBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)ǷUSBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)ȷUSBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)ҷUSBNC1_BASE (0x402E0000u)ԷUSBNC1 ((USBNC_Type *)USBNC1_BASE)ַUSBNC2_BASE (0x402E0004u)طUSBNC2 ((USBNC_Type *)USBNC2_BASE)ڷUSBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }ܷUSBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }USBPHY_PWD_RSVD0_MASK (0x3FFU)USBPHY_PWD_RSVD0_SHIFT (0U)USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)USBPHY_PWD_TXPWDFS_MASK (0x400U)USBPHY_PWD_TXPWDFS_SHIFT (10U)USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)USBPHY_PWD_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)USBPHY_PWD_RSVD1_MASK (0x1E000U)USBPHY_PWD_RSVD1_SHIFT (13U)USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)USBPHY_PWD_RXPWDENV_MASK (0x20000U)USBPHY_PWD_RXPWDENV_SHIFT (17U)USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)USBPHY_PWD_RXPWDRX_MASK (0x100000U)USBPHY_PWD_RXPWDRX_SHIFT (20U)USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)USBPHY_PWD_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_RSVD2_SHIFT (21U)USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)USBPHY_PWD_SET_RSVD0_SHIFT (0U)USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)¸USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)øUSBPHY_PWD_SET_RSVD1_MASK (0x1E000U)ĸUSBPHY_PWD_SET_RSVD1_SHIFT (13U)ŸUSBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)ƸUSBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)ǸUSBPHY_PWD_SET_RXPWDENV_SHIFT (17U)ȸUSBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)ɸUSBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)ʸUSBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)˸USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)̸USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)͸USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)θUSBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)ϸUSBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)иUSBPHY_PWD_SET_RXPWDRX_SHIFT (20U)ѸUSBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)ҸUSBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)ӸUSBPHY_PWD_SET_RSVD2_SHIFT (21U)ԸUSBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)׸USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)ظUSBPHY_PWD_CLR_RSVD0_SHIFT (0U)ٸUSBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)ڸUSBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)۸USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)ܸUSBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)ݸUSBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)޸USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)߸USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)USBPHY_PWD_CLR_RSVD1_SHIFT (13U)USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_CLR_RSVD2_SHIFT (21U)USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)USBPHY_PWD_TOG_RSVD0_SHIFT (0U)USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)USBPHY_PWD_TOG_RSVD1_SHIFT (13U)USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_TOG_RSVD2_SHIFT (21U)USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)USBPHY_TX_D_CAL_MASK (0xFU)USBPHY_TX_D_CAL_SHIFT (0U)USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)USBPHY_TX_RSVD0_MASK (0xF0U)USBPHY_TX_RSVD0_SHIFT (4U)USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)USBPHY_TX_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TXCAL45DN_SHIFT (8U)USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)USBPHY_TX_RSVD1_MASK (0xF000U)USBPHY_TX_RSVD1_SHIFT (12U)USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)USBPHY_TX_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TXCAL45DP_SHIFT (16U)USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)USBPHY_TX_RSVD2_MASK (0x3F00000U)USBPHY_TX_RSVD2_SHIFT (20U)USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_RSVD5_MASK (0xE0000000U)USBPHY_TX_RSVD5_SHIFT (29U)USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)USBPHY_TX_SET_D_CAL_MASK (0xFU)USBPHY_TX_SET_D_CAL_SHIFT (0U)USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)USBPHY_TX_SET_RSVD0_MASK (0xF0U)USBPHY_TX_SET_RSVD0_SHIFT (4U)USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)USBPHY_TX_SET_RSVD1_MASK (0xF000U)USBPHY_TX_SET_RSVD1_SHIFT (12U)USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)USBPHY_TX_SET_RSVD2_SHIFT (20U)¹USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)ùUSBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)ĹUSBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)ŹUSBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)ƹUSBPHY_TX_SET_RSVD5_MASK (0xE0000000U)ǹUSBPHY_TX_SET_RSVD5_SHIFT (29U)ȹUSBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)˹USBPHY_TX_CLR_D_CAL_MASK (0xFU)̹USBPHY_TX_CLR_D_CAL_SHIFT (0U)͹USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)ιUSBPHY_TX_CLR_RSVD0_MASK (0xF0U)ϹUSBPHY_TX_CLR_RSVD0_SHIFT (4U)йUSBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)ѹUSBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)ҹUSBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)ӹUSBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)ԹUSBPHY_TX_CLR_RSVD1_MASK (0xF000U)չUSBPHY_TX_CLR_RSVD1_SHIFT (12U)ֹUSBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)׹USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)عUSBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)ٹUSBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)ڹUSBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)۹USBPHY_TX_CLR_RSVD2_SHIFT (20U)ܹUSBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)ݹUSBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)޹USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)߹USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)USBPHY_TX_CLR_RSVD5_SHIFT (29U)USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)USBPHY_TX_TOG_D_CAL_MASK (0xFU)USBPHY_TX_TOG_D_CAL_SHIFT (0U)USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)USBPHY_TX_TOG_RSVD0_MASK (0xF0U)USBPHY_TX_TOG_RSVD0_SHIFT (4U)USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)USBPHY_TX_TOG_RSVD1_MASK (0xF000U)USBPHY_TX_TOG_RSVD1_SHIFT (12U)USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)USBPHY_TX_TOG_RSVD2_SHIFT (20U)USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)USBPHY_TX_TOG_RSVD5_SHIFT (29U)USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)USBPHY_RX_ENVADJ_MASK (0x7U)USBPHY_RX_ENVADJ_SHIFT (0U)USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)USBPHY_RX_RSVD0_MASK (0x8U)USBPHY_RX_RSVD0_SHIFT (3U)USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)USBPHY_RX_DISCONADJ_MASK (0x70U)USBPHY_RX_DISCONADJ_SHIFT (4U)USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)USBPHY_RX_RSVD1_MASK (0x3FFF80U)USBPHY_RX_RSVD1_SHIFT (7U)USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)USBPHY_RX_RXDBYPASS_MASK (0x400000U)USBPHY_RX_RXDBYPASS_SHIFT (22U)USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)USBPHY_RX_RSVD2_MASK (0xFF800000U)USBPHY_RX_RSVD2_SHIFT (23U)USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)USBPHY_RX_SET_ENVADJ_MASK (0x7U)USBPHY_RX_SET_ENVADJ_SHIFT (0U)USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)USBPHY_RX_SET_RSVD0_MASK (0x8U)USBPHY_RX_SET_RSVD0_SHIFT (3U)USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)USBPHY_RX_SET_DISCONADJ_MASK (0x70U)USBPHY_RX_SET_DISCONADJ_SHIFT (4U)USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)USBPHY_RX_SET_RSVD1_SHIFT (7U)USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)USBPHY_RX_SET_RSVD2_SHIFT (23U)USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)USBPHY_RX_CLR_ENVADJ_MASK (0x7U)USBPHY_RX_CLR_ENVADJ_SHIFT (0U)USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)USBPHY_RX_CLR_RSVD0_MASK (0x8U)USBPHY_RX_CLR_RSVD0_SHIFT (3U)USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)USBPHY_RX_CLR_RSVD1_SHIFT (7U)USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)USBPHY_RX_CLR_RSVD2_SHIFT (23U)USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)USBPHY_RX_TOG_ENVADJ_MASK (0x7U)USBPHY_RX_TOG_ENVADJ_SHIFT (0U)USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)USBPHY_RX_TOG_RSVD0_MASK (0x8U)USBPHY_RX_TOG_RSVD0_SHIFT (3U)USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)ºUSBPHY_RX_TOG_DISCONADJ_SHIFT (4U)úUSBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)ĺUSBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)źUSBPHY_RX_TOG_RSVD1_SHIFT (7U)ƺUSBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)ǺUSBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)ȺUSBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)ɺUSBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)ʺUSBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)˺USBPHY_RX_TOG_RSVD2_SHIFT (23U)̺USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)ϺUSBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)кUSBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)ѺUSBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)ҺUSBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)ӺUSBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)ԺUSBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)պUSBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)ֺUSBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)׺USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)غUSBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)ٺUSBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)ںUSBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)ۺUSBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)ܺUSBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)ݺUSBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)޺USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)ߺUSBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)USBPHY_CTRL_RSVD1_MASK (0x6000000U)USBPHY_CTRL_RSVD1_SHIFT (25U)USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)USBPHY_CTRL_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SFTRST_SHIFT (31U)USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)»USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)ûUSBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)ĻUSBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)ŻUSBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)ƻUSBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)ǻUSBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)ȻUSBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)ɻUSBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)ʻUSBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)˻USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)̻USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)ͻUSBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)λUSBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)ϻUSBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)лUSBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)ѻUSBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)һUSBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)ӻUSBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)ԻUSBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)ջUSBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)ֻUSBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)׻USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)ػUSBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)ٻUSBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)ڻUSBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)ۻUSBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)ܻUSBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)ݻUSBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)޻USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)߻USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)USBPHY_CTRL_SET_RSVD1_SHIFT (25U)USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SET_SFTRST_SHIFT (31U)USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)¼USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)üUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)ļUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)żUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)ƼUSBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)ǼUSBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)ȼUSBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)ɼUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)ʼUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)˼USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)̼USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)ͼUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)μUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)ϼUSBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)мUSBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)ѼUSBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)ҼUSBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)ӼUSBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)ԼUSBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)ռUSBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)ּUSBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)׼USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)ؼUSBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)ټUSBPHY_CTRL_CLR_RSVD1_SHIFT (25U)ڼUSBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)ۼUSBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)ܼUSBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)ݼUSBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)޼USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)߼USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)½USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)ýUSBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)ĽUSBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)ŽUSBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)ƽUSBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)ǽUSBPHY_CTRL_TOG_SFTRST_SHIFT (31U)ȽUSBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)˽USBPHY_STATUS_RSVD0_MASK (0x7U)̽USBPHY_STATUS_RSVD0_SHIFT (0U)ͽUSBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)νUSBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)ϽUSBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)нUSBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)ѽUSBPHY_STATUS_RSVD1_MASK (0x30U)ҽUSBPHY_STATUS_RSVD1_SHIFT (4U)ӽUSBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)ԽUSBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)սUSBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)ֽUSBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)׽USBPHY_STATUS_RSVD2_MASK (0x80U)ؽUSBPHY_STATUS_RSVD2_SHIFT (7U)ٽUSBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)ڽUSBPHY_STATUS_OTGID_STATUS_MASK (0x100U)۽USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)ܽUSBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)ݽUSBPHY_STATUS_RSVD3_MASK (0x200U)޽USBPHY_STATUS_RSVD3_SHIFT (9U)߽USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)USBPHY_STATUS_RSVD4_SHIFT (11U)USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_RSVD0_SHIFT (6U)USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_RSVD1_SHIFT (13U)USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_RSVD2_SHIFT (21U)USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)USBPHY_DEBUG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_RSVD3_SHIFT (31U)USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)¾USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)þUSBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)ƾUSBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)ǾUSBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)ȾUSBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)ɾUSBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)ʾUSBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)˾USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)̾USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU);USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)ξUSBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)ϾUSBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)оUSBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)ѾUSBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)ҾUSBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)ӾUSBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)ԾUSBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)վUSBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)־USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)׾USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)ؾUSBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)پUSBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)ھUSBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)۾USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)ܾUSBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)ݾUSBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)޾USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)߾USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_RSVD0_SHIFT (0U)USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_RSVD1_SHIFT (15U)USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)¿USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)ſUSBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)ƿUSBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)ǿUSBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)ȿUSBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)ɿUSBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)ʿUSBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)˿USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)̿USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)ͿUSBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)пUSBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)ѿUSBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)ҿUSBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)ӿUSBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)ԿUSBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)տUSBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)ֿUSBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)׿USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)ؿUSBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)ۿUSBPHY_VERSION_STEP_MASK (0xFFFFU)ܿUSBPHY_VERSION_STEP_SHIFT (0U)ݿUSBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)޿USBPHY_VERSION_MINOR_MASK (0xFF0000U)߿USBPHY_VERSION_MINOR_SHIFT (16U)USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)USBPHY_VERSION_MAJOR_MASK (0xFF000000U)USBPHY_VERSION_MAJOR_SHIFT (24U)USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)USBPHY1_BASE (0x400D9000u)USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)USBPHY2_BASE (0x400DA000u)USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASKUSBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFTUSBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASKUSBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFTUSBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_COUNT (2U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)USB_ANALOG_CHRG_DETECT_COUNT (2U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_COUNT (2U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_SET_COUNT (2U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_CLR_COUNT (2U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_TOG_COUNT (2U)USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU)USB_ANALOG_DIGPROG_MINOR_SHIFT (0U)USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK)USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U)USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U)USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK)USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U)USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U)USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK)USB_ANALOG_BASE (0x400D8000u)USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }USB_ANALOG_BASE_PTRS { USB_ANALOG }USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)USDHC_BLK_ATT_BLKCNT_SHIFT (16U)USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)USDHC_CMD_ARG_CMDARG_SHIFT (0U)USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)USDHC_PRES_STATE_CIHB_MASK (0x1U)USDHC_PRES_STATE_CIHB_SHIFT (0U)USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)USDHC_PRES_STATE_CDIHB_MASK (0x2U)USDHC_PRES_STATE_CDIHB_SHIFT (1U)USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)USDHC_PRES_STATE_DLA_MASK (0x4U)USDHC_PRES_STATE_DLA_SHIFT (2U)USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)USDHC_PRES_STATE_SDSTB_MASK (0x8U)USDHC_PRES_STATE_SDSTB_SHIFT (3U)USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)USDHC_PRES_STATE_IPGOFF_MASK (0x10U)USDHC_PRES_STATE_IPGOFF_SHIFT (4U)USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)USDHC_PRES_STATE_HCKOFF_MASK (0x20U)USDHC_PRES_STATE_HCKOFF_SHIFT (5U)USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)USDHC_PRES_STATE_PEROFF_MASK (0x40U)USDHC_PRES_STATE_PEROFF_SHIFT (6U)USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)USDHC_PRES_STATE_SDOFF_MASK (0x80U)USDHC_PRES_STATE_SDOFF_SHIFT (7U)USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)USDHC_PRES_STATE_WTA_MASK (0x100U)USDHC_PRES_STATE_WTA_SHIFT (8U)USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)USDHC_PRES_STATE_RTA_MASK (0x200U)USDHC_PRES_STATE_RTA_SHIFT (9U)USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)USDHC_PRES_STATE_BWEN_MASK (0x400U)USDHC_PRES_STATE_BWEN_SHIFT (10U)USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)USDHC_PRES_STATE_BREN_MASK (0x800U)USDHC_PRES_STATE_BREN_SHIFT (11U)USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)USDHC_PRES_STATE_RTR_MASK (0x1000U)USDHC_PRES_STATE_RTR_SHIFT (12U)USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)USDHC_PRES_STATE_TSCD_MASK (0x8000U)USDHC_PRES_STATE_TSCD_SHIFT (15U)USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)USDHC_PRES_STATE_CINST_MASK (0x10000U)USDHC_PRES_STATE_CINST_SHIFT (16U)USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)USDHC_PRES_STATE_CDPL_MASK (0x40000U)USDHC_PRES_STATE_CDPL_SHIFT (18U)USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)USDHC_PRES_STATE_WPSPL_MASK (0x80000U)USDHC_PRES_STATE_WPSPL_SHIFT (19U)USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)USDHC_PRES_STATE_CLSL_MASK (0x800000U)USDHC_PRES_STATE_CLSL_SHIFT (23U)USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)USDHC_PRES_STATE_DLSL_SHIFT (24U)USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)USDHC_PROT_CTRL_LCTL_MASK (0x1U)USDHC_PROT_CTRL_LCTL_SHIFT (0U)USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)USDHC_PROT_CTRL_DTW_MASK (0x6U)USDHC_PROT_CTRL_DTW_SHIFT (1U)USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)USDHC_PROT_CTRL_D3CD_MASK (0x8U)USDHC_PROT_CTRL_D3CD_SHIFT (3U)USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)USDHC_PROT_CTRL_EMODE_MASK (0x30U)USDHC_PROT_CTRL_EMODE_SHIFT (4U)USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)USDHC_PROT_CTRL_CDTL_MASK (0x40U)USDHC_PROT_CTRL_CDTL_SHIFT (6U)USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)USDHC_PROT_CTRL_CDSS_MASK (0x80U)USDHC_PROT_CTRL_CDSS_SHIFT (7U)USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)USDHC_PROT_CTRL_DMASEL_MASK (0x300U)USDHC_PROT_CTRL_DMASEL_SHIFT (8U)USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)USDHC_PROT_CTRL_CREQ_MASK (0x20000U)USDHC_PROT_CTRL_CREQ_SHIFT (17U)USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)USDHC_PROT_CTRL_RWCTL_SHIFT (18U)USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)USDHC_PROT_CTRL_IABG_MASK (0x80000U)USDHC_PROT_CTRL_IABG_SHIFT (19U)USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)USDHC_PROT_CTRL_WECINT_SHIFT (24U)USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)USDHC_PROT_CTRL_WECINS_SHIFT (25U)USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)USDHC_PROT_CTRL_WECRM_SHIFT (26U)USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)USDHC_SYS_CTRL_DVS_MASK (0xF0U)USDHC_SYS_CTRL_DVS_SHIFT (4U)USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)USDHC_SYS_CTRL_DTOCV_SHIFT (16U)USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)USDHC_SYS_CTRL_RSTA_SHIFT (24U)USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)USDHC_SYS_CTRL_RSTC_SHIFT (25U)USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)USDHC_SYS_CTRL_RSTD_SHIFT (26U)USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)USDHC_SYS_CTRL_INITA_MASK (0x8000000U)USDHC_SYS_CTRL_INITA_SHIFT (27U)USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)USDHC_SYS_CTRL_RSTT_SHIFT (28U)USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)USDHC_INT_STATUS_CC_MASK (0x1U)USDHC_INT_STATUS_CC_SHIFT (0U)USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)USDHC_INT_STATUS_TC_MASK (0x2U)USDHC_INT_STATUS_TC_SHIFT (1U)USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)USDHC_INT_STATUS_BGE_MASK (0x4U)USDHC_INT_STATUS_BGE_SHIFT (2U)USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)USDHC_INT_STATUS_DINT_MASK (0x8U)USDHC_INT_STATUS_DINT_SHIFT (3U)USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)USDHC_INT_STATUS_BWR_MASK (0x10U)USDHC_INT_STATUS_BWR_SHIFT (4U)USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)USDHC_INT_STATUS_BRR_MASK (0x20U)USDHC_INT_STATUS_BRR_SHIFT (5U)USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)USDHC_INT_STATUS_CINS_MASK (0x40U)USDHC_INT_STATUS_CINS_SHIFT (6U)USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)USDHC_INT_STATUS_CRM_MASK (0x80U)USDHC_INT_STATUS_CRM_SHIFT (7U)USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)USDHC_INT_STATUS_CINT_MASK (0x100U)USDHC_INT_STATUS_CINT_SHIFT (8U)USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)USDHC_INT_STATUS_RTE_MASK (0x1000U)USDHC_INT_STATUS_RTE_SHIFT (12U)USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)USDHC_INT_STATUS_TP_MASK (0x4000U)USDHC_INT_STATUS_TP_SHIFT (14U)USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)USDHC_INT_STATUS_CTOE_MASK (0x10000U)USDHC_INT_STATUS_CTOE_SHIFT (16U)USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)USDHC_INT_STATUS_CCE_MASK (0x20000U)USDHC_INT_STATUS_CCE_SHIFT (17U)USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)USDHC_INT_STATUS_CEBE_MASK (0x40000U)USDHC_INT_STATUS_CEBE_SHIFT (18U)USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)USDHC_INT_STATUS_CIE_MASK (0x80000U)USDHC_INT_STATUS_CIE_SHIFT (19U)USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)USDHC_INT_STATUS_DTOE_MASK (0x100000U)USDHC_INT_STATUS_DTOE_SHIFT (20U)USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)USDHC_INT_STATUS_DCE_MASK (0x200000U)USDHC_INT_STATUS_DCE_SHIFT (21U)USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)USDHC_INT_STATUS_DEBE_MASK (0x400000U)USDHC_INT_STATUS_DEBE_SHIFT (22U)USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)USDHC_INT_STATUS_AC12E_MASK (0x1000000U)USDHC_INT_STATUS_AC12E_SHIFT (24U)USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)USDHC_INT_STATUS_TNE_MASK (0x4000000U)USDHC_INT_STATUS_TNE_SHIFT (26U)USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)USDHC_INT_STATUS_DMAE_MASK (0x10000000U)USDHC_INT_STATUS_DMAE_SHIFT (28U)USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)USDHC_WTMK_LVL_RD_WML_SHIFT (0U)USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)USDHC_WTMK_LVL_WR_WML_SHIFT (16U)USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)USDHC_MIX_CTRL_DMAEN_MASK (0x1U)USDHC_MIX_CTRL_DMAEN_SHIFT (0U)USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)USDHC_MIX_CTRL_BCEN_MASK (0x2U)USDHC_MIX_CTRL_BCEN_SHIFT (1U)USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)USDHC_MIX_CTRL_AC12EN_MASK (0x4U)USDHC_MIX_CTRL_AC12EN_SHIFT (2U)USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)USDHC_MIX_CTRL_AC23EN_MASK (0x80U)USDHC_MIX_CTRL_AC23EN_SHIFT (7U)USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)USDHC_VEND_SPEC_VSELECT_MASK (0x2U)USDHC_VEND_SPEC_VSELECT_SHIFT (1U)USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U)USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U)USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK)USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)USDHC1_BASE (0x402C0000u)USDHC1 ((USDHC_Type *)USDHC1_BASE)USDHC2_BASE (0x402C4000u)USDHC2 ((USDHC_Type *)USDHC2_BASE)USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }WDOG_WCR_WDZST_MASK (0x1U)WDOG_WCR_WDZST_SHIFT (0U)WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)WDOG_WCR_WDBG_MASK (0x2U)WDOG_WCR_WDBG_SHIFT (1U)WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)WDOG_WCR_WDE_MASK (0x4U)WDOG_WCR_WDE_SHIFT (2U)WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)WDOG_WCR_WDT_MASK (0x8U)WDOG_WCR_WDT_SHIFT (3U)WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)WDOG_WCR_SRS_MASK (0x10U)WDOG_WCR_SRS_SHIFT (4U)WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)WDOG_WCR_WDA_MASK (0x20U)WDOG_WCR_WDA_SHIFT (5U)WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)WDOG_WCR_SRE_MASK (0x40U)WDOG_WCR_SRE_SHIFT (6U)WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)WDOG_WCR_WDW_MASK (0x80U)WDOG_WCR_WDW_SHIFT (7U)WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)WDOG_WCR_WT_MASK (0xFF00U)WDOG_WCR_WT_SHIFT (8U)WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)WDOG_WSR_WSR_MASK (0xFFFFU)WDOG_WSR_WSR_SHIFT (0U)WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)WDOG_WRSR_SFTW_MASK (0x1U)WDOG_WRSR_SFTW_SHIFT (0U)WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)WDOG_WRSR_TOUT_MASK (0x2U)WDOG_WRSR_TOUT_SHIFT (1U)WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)WDOG_WRSR_POR_MASK (0x10U)WDOG_WRSR_POR_SHIFT (4U)WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)WDOG_WICR_WICT_MASK (0xFFU)WDOG_WICR_WICT_SHIFT (0U)WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)WDOG_WICR_WTIS_MASK (0x4000U)WDOG_WICR_WTIS_SHIFT (14U)WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)WDOG_WICR_WIE_MASK (0x8000U)WDOG_WICR_WIE_SHIFT (15U)WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)WDOG_WMCR_PDE_MASK (0x1U)WDOG_WMCR_PDE_SHIFT (0U)WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)WDOG1_BASE (0x400B8000u)WDOG1 ((WDOG_Type *)WDOG1_BASE)WDOG2_BASE (0x400D0000u)WDOG2 ((WDOG_Type *)WDOG2_BASE)WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }XBARA_SEL0_SEL0_MASK (0x7FU)XBARA_SEL0_SEL0_SHIFT (0U)XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)XBARA_SEL0_SEL1_MASK (0x7F00U)XBARA_SEL0_SEL1_SHIFT (8U)XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)XBARA_SEL1_SEL2_MASK (0x7FU)XBARA_SEL1_SEL2_SHIFT (0U)XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)XBARA_SEL1_SEL3_MASK (0x7F00U)XBARA_SEL1_SEL3_SHIFT (8U)XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)XBARA_SEL2_SEL4_MASK (0x7FU)XBARA_SEL2_SEL4_SHIFT (0U)XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)XBARA_SEL2_SEL5_MASK (0x7F00U)XBARA_SEL2_SEL5_SHIFT (8U)XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)XBARA_SEL3_SEL6_MASK (0x7FU)XBARA_SEL3_SEL6_SHIFT (0U)XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)XBARA_SEL3_SEL7_MASK (0x7F00U)XBARA_SEL3_SEL7_SHIFT (8U)XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)XBARA_SEL4_SEL8_MASK (0x7FU)XBARA_SEL4_SEL8_SHIFT (0U)XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)XBARA_SEL4_SEL9_MASK (0x7F00U)XBARA_SEL4_SEL9_SHIFT (8U)XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)XBARA_SEL5_SEL10_MASK (0x7FU)XBARA_SEL5_SEL10_SHIFT (0U)XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)XBARA_SEL5_SEL11_MASK (0x7F00U)XBARA_SEL5_SEL11_SHIFT (8U)XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)XBARA_SEL6_SEL12_MASK (0x7FU)XBARA_SEL6_SEL12_SHIFT (0U)XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)XBARA_SEL6_SEL13_MASK (0x7F00U)XBARA_SEL6_SEL13_SHIFT (8U)XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)XBARA_SEL7_SEL14_MASK (0x7FU)XBARA_SEL7_SEL14_SHIFT (0U)XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)XBARA_SEL7_SEL15_MASK (0x7F00U)XBARA_SEL7_SEL15_SHIFT (8U)XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)XBARA_SEL8_SEL16_MASK (0x7FU)XBARA_SEL8_SEL16_SHIFT (0U)XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)XBARA_SEL8_SEL17_MASK (0x7F00U)XBARA_SEL8_SEL17_SHIFT (8U)XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)XBARA_SEL9_SEL18_MASK (0x7FU)XBARA_SEL9_SEL18_SHIFT (0U)XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)XBARA_SEL9_SEL19_MASK (0x7F00U)XBARA_SEL9_SEL19_SHIFT (8U)XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)XBARA_SEL10_SEL20_MASK (0x7FU)XBARA_SEL10_SEL20_SHIFT (0U)XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)XBARA_SEL10_SEL21_MASK (0x7F00U)XBARA_SEL10_SEL21_SHIFT (8U)XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)XBARA_SEL11_SEL22_MASK (0x7FU)XBARA_SEL11_SEL22_SHIFT (0U)XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)XBARA_SEL11_SEL23_MASK (0x7F00U)XBARA_SEL11_SEL23_SHIFT (8U)XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)XBARA_SEL12_SEL24_MASK (0x7FU)XBARA_SEL12_SEL24_SHIFT (0U)XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)XBARA_SEL12_SEL25_MASK (0x7F00U)XBARA_SEL12_SEL25_SHIFT (8U)XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)XBARA_SEL13_SEL26_MASK (0x7FU)XBARA_SEL13_SEL26_SHIFT (0U)XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)XBARA_SEL13_SEL27_MASK (0x7F00U)XBARA_SEL13_SEL27_SHIFT (8U)XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)XBARA_SEL14_SEL28_MASK (0x7FU)XBARA_SEL14_SEL28_SHIFT (0U)XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)XBARA_SEL14_SEL29_MASK (0x7F00U)XBARA_SEL14_SEL29_SHIFT (8U)XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)XBARA_SEL15_SEL30_MASK (0x7FU)XBARA_SEL15_SEL30_SHIFT (0U)XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)XBARA_SEL15_SEL31_MASK (0x7F00U)XBARA_SEL15_SEL31_SHIFT (8U)XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)XBARA_SEL16_SEL32_MASK (0x7FU)XBARA_SEL16_SEL32_SHIFT (0U)XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)XBARA_SEL16_SEL33_MASK (0x7F00U)XBARA_SEL16_SEL33_SHIFT (8U)XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)XBARA_SEL17_SEL34_MASK (0x7FU)XBARA_SEL17_SEL34_SHIFT (0U)XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)XBARA_SEL17_SEL35_MASK (0x7F00U)XBARA_SEL17_SEL35_SHIFT (8U)XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)XBARA_SEL18_SEL36_MASK (0x7FU)XBARA_SEL18_SEL36_SHIFT (0U)XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)XBARA_SEL18_SEL37_MASK (0x7F00U)XBARA_SEL18_SEL37_SHIFT (8U)XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)XBARA_SEL19_SEL38_MASK (0x7FU)XBARA_SEL19_SEL38_SHIFT (0U)XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)XBARA_SEL19_SEL39_MASK (0x7F00U)XBARA_SEL19_SEL39_SHIFT (8U)XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)XBARA_SEL20_SEL40_MASK (0x7FU)XBARA_SEL20_SEL40_SHIFT (0U)XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)XBARA_SEL20_SEL41_MASK (0x7F00U)XBARA_SEL20_SEL41_SHIFT (8U)XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)XBARA_SEL21_SEL42_MASK (0x7FU)XBARA_SEL21_SEL42_SHIFT (0U)XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)XBARA_SEL21_SEL43_MASK (0x7F00U)XBARA_SEL21_SEL43_SHIFT (8U)XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)XBARA_SEL22_SEL44_MASK (0x7FU)XBARA_SEL22_SEL44_SHIFT (0U)XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)XBARA_SEL22_SEL45_MASK (0x7F00U)XBARA_SEL22_SEL45_SHIFT (8U)XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)XBARA_SEL23_SEL46_MASK (0x7FU)XBARA_SEL23_SEL46_SHIFT (0U)XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)XBARA_SEL23_SEL47_MASK (0x7F00U)XBARA_SEL23_SEL47_SHIFT (8U)XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)XBARA_SEL24_SEL48_MASK (0x7FU)XBARA_SEL24_SEL48_SHIFT (0U)XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)XBARA_SEL24_SEL49_MASK (0x7F00U)XBARA_SEL24_SEL49_SHIFT (8U)XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)XBARA_SEL25_SEL50_MASK (0x7FU)XBARA_SEL25_SEL50_SHIFT (0U)XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)XBARA_SEL25_SEL51_MASK (0x7F00U)XBARA_SEL25_SEL51_SHIFT (8U)XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)XBARA_SEL26_SEL52_MASK (0x7FU)XBARA_SEL26_SEL52_SHIFT (0U)XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)XBARA_SEL26_SEL53_MASK (0x7F00U)XBARA_SEL26_SEL53_SHIFT (8U)XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)XBARA_SEL27_SEL54_MASK (0x7FU)XBARA_SEL27_SEL54_SHIFT (0U)XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)XBARA_SEL27_SEL55_MASK (0x7F00U)XBARA_SEL27_SEL55_SHIFT (8U)XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)XBARA_SEL28_SEL56_MASK (0x7FU)XBARA_SEL28_SEL56_SHIFT (0U)XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)XBARA_SEL28_SEL57_MASK (0x7F00U)XBARA_SEL28_SEL57_SHIFT (8U)XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)XBARA_SEL29_SEL58_MASK (0x7FU)XBARA_SEL29_SEL58_SHIFT (0U)XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)XBARA_SEL29_SEL59_MASK (0x7F00U)XBARA_SEL29_SEL59_SHIFT (8U)XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)XBARA_SEL30_SEL60_MASK (0x7FU)XBARA_SEL30_SEL60_SHIFT (0U)XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)XBARA_SEL30_SEL61_MASK (0x7F00U)XBARA_SEL30_SEL61_SHIFT (8U)XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)XBARA_SEL31_SEL62_MASK (0x7FU)XBARA_SEL31_SEL62_SHIFT (0U)XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)XBARA_SEL31_SEL63_MASK (0x7F00U)XBARA_SEL31_SEL63_SHIFT (8U)XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)XBARA_SEL32_SEL64_MASK (0x7FU)XBARA_SEL32_SEL64_SHIFT (0U)XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)XBARA_SEL32_SEL65_MASK (0x7F00U)XBARA_SEL32_SEL65_SHIFT (8U)XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)XBARA_SEL33_SEL66_MASK (0x7FU)XBARA_SEL33_SEL66_SHIFT (0U)XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)XBARA_SEL33_SEL67_MASK (0x7F00U)XBARA_SEL33_SEL67_SHIFT (8U)XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)XBARA_SEL34_SEL68_MASK (0x7FU)XBARA_SEL34_SEL68_SHIFT (0U)XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)XBARA_SEL34_SEL69_MASK (0x7F00U)XBARA_SEL34_SEL69_SHIFT (8U)XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)XBARA_SEL35_SEL70_MASK (0x7FU)XBARA_SEL35_SEL70_SHIFT (0U)XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)XBARA_SEL35_SEL71_MASK (0x7F00U)XBARA_SEL35_SEL71_SHIFT (8U)XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)XBARA_SEL36_SEL72_MASK (0x7FU)XBARA_SEL36_SEL72_SHIFT (0U)XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)XBARA_SEL36_SEL73_MASK (0x7F00U)XBARA_SEL36_SEL73_SHIFT (8U)XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)XBARA_SEL37_SEL74_MASK (0x7FU)XBARA_SEL37_SEL74_SHIFT (0U)XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)XBARA_SEL37_SEL75_MASK (0x7F00U)XBARA_SEL37_SEL75_SHIFT (8U)XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)XBARA_SEL38_SEL76_MASK (0x7FU)XBARA_SEL38_SEL76_SHIFT (0U)XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)XBARA_SEL38_SEL77_MASK (0x7F00U)XBARA_SEL38_SEL77_SHIFT (8U)XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)XBARA_SEL39_SEL78_MASK (0x7FU)XBARA_SEL39_SEL78_SHIFT (0U)XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)XBARA_SEL39_SEL79_MASK (0x7F00U)XBARA_SEL39_SEL79_SHIFT (8U)XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)XBARA_SEL40_SEL80_MASK (0x7FU)XBARA_SEL40_SEL80_SHIFT (0U)XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)XBARA_SEL40_SEL81_MASK (0x7F00U)XBARA_SEL40_SEL81_SHIFT (8U)XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)XBARA_SEL41_SEL82_MASK (0x7FU)XBARA_SEL41_SEL82_SHIFT (0U)XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)XBARA_SEL41_SEL83_MASK (0x7F00U)XBARA_SEL41_SEL83_SHIFT (8U)XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)XBARA_SEL42_SEL84_MASK (0x7FU)XBARA_SEL42_SEL84_SHIFT (0U)XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)XBARA_SEL42_SEL85_MASK (0x7F00U)XBARA_SEL42_SEL85_SHIFT (8U)XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)XBARA_SEL43_SEL86_MASK (0x7FU)XBARA_SEL43_SEL86_SHIFT (0U)XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)XBARA_SEL43_SEL87_MASK (0x7F00U)XBARA_SEL43_SEL87_SHIFT (8U)XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)XBARA_SEL44_SEL88_MASK (0x7FU)XBARA_SEL44_SEL88_SHIFT (0U)XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)XBARA_SEL44_SEL89_MASK (0x7F00U)XBARA_SEL44_SEL89_SHIFT (8U)XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)XBARA_SEL45_SEL90_MASK (0x7FU)XBARA_SEL45_SEL90_SHIFT (0U)XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)XBARA_SEL45_SEL91_MASK (0x7F00U)XBARA_SEL45_SEL91_SHIFT (8U)XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)XBARA_SEL46_SEL92_MASK (0x7FU)XBARA_SEL46_SEL92_SHIFT (0U)XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)XBARA_SEL46_SEL93_MASK (0x7F00U)XBARA_SEL46_SEL93_SHIFT (8U)XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)XBARA_SEL47_SEL94_MASK (0x7FU)XBARA_SEL47_SEL94_SHIFT (0U)XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)XBARA_SEL47_SEL95_MASK (0x7F00U)XBARA_SEL47_SEL95_SHIFT (8U)XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)XBARA_SEL48_SEL96_MASK (0x7FU)XBARA_SEL48_SEL96_SHIFT (0U)XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)XBARA_SEL48_SEL97_MASK (0x7F00U)XBARA_SEL48_SEL97_SHIFT (8U)XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)XBARA_SEL49_SEL98_MASK (0x7FU)XBARA_SEL49_SEL98_SHIFT (0U)XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)XBARA_SEL49_SEL99_MASK (0x7F00U)XBARA_SEL49_SEL99_SHIFT (8U)XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)XBARA_SEL50_SEL100_MASK (0x7FU)XBARA_SEL50_SEL100_SHIFT (0U)XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)XBARA_SEL50_SEL101_MASK (0x7F00U)XBARA_SEL50_SEL101_SHIFT (8U)XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)XBARA_SEL51_SEL102_MASK (0x7FU)XBARA_SEL51_SEL102_SHIFT (0U)XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)XBARA_SEL51_SEL103_MASK (0x7F00U)XBARA_SEL51_SEL103_SHIFT (8U)XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)XBARA_SEL52_SEL104_MASK (0x7FU)XBARA_SEL52_SEL104_SHIFT (0U)XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)XBARA_SEL52_SEL105_MASK (0x7F00U)XBARA_SEL52_SEL105_SHIFT (8U)XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)XBARA_SEL53_SEL106_MASK (0x7FU)XBARA_SEL53_SEL106_SHIFT (0U)XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)XBARA_SEL53_SEL107_MASK (0x7F00U)XBARA_SEL53_SEL107_SHIFT (8U)XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)XBARA_SEL54_SEL108_MASK (0x7FU)XBARA_SEL54_SEL108_SHIFT (0U)XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)XBARA_SEL54_SEL109_MASK (0x7F00U)XBARA_SEL54_SEL109_SHIFT (8U)XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)XBARA_SEL55_SEL110_MASK (0x7FU)XBARA_SEL55_SEL110_SHIFT (0U)XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)XBARA_SEL55_SEL111_MASK (0x7F00U)XBARA_SEL55_SEL111_SHIFT (8U)XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)XBARA_SEL56_SEL112_MASK (0x7FU)XBARA_SEL56_SEL112_SHIFT (0U)XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)XBARA_SEL56_SEL113_MASK (0x7F00U)XBARA_SEL56_SEL113_SHIFT (8U)XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)XBARA_SEL57_SEL114_MASK (0x7FU)XBARA_SEL57_SEL114_SHIFT (0U)XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)XBARA_SEL57_SEL115_MASK (0x7F00U)XBARA_SEL57_SEL115_SHIFT (8U)XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)XBARA_SEL58_SEL116_MASK (0x7FU)XBARA_SEL58_SEL116_SHIFT (0U)XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)XBARA_SEL58_SEL117_MASK (0x7F00U)XBARA_SEL58_SEL117_SHIFT (8U)XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)XBARA_SEL59_SEL118_MASK (0x7FU)XBARA_SEL59_SEL118_SHIFT (0U)XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)XBARA_SEL59_SEL119_MASK (0x7F00U)XBARA_SEL59_SEL119_SHIFT (8U)XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)XBARA_SEL60_SEL120_MASK (0x7FU)XBARA_SEL60_SEL120_SHIFT (0U)XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)XBARA_SEL60_SEL121_MASK (0x7F00U)XBARA_SEL60_SEL121_SHIFT (8U)XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)XBARA_SEL61_SEL122_MASK (0x7FU)XBARA_SEL61_SEL122_SHIFT (0U)XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)XBARA_SEL61_SEL123_MASK (0x7F00U)XBARA_SEL61_SEL123_SHIFT (8U)XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)XBARA_SEL62_SEL124_MASK (0x7FU)XBARA_SEL62_SEL124_SHIFT (0U)XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)XBARA_SEL62_SEL125_MASK (0x7F00U)XBARA_SEL62_SEL125_SHIFT (8U)XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)XBARA_SEL63_SEL126_MASK (0x7FU)XBARA_SEL63_SEL126_SHIFT (0U)XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)XBARA_SEL63_SEL127_MASK (0x7F00U)XBARA_SEL63_SEL127_SHIFT (8U)XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)XBARA_SEL64_SEL128_MASK (0x7FU)XBARA_SEL64_SEL128_SHIFT (0U)XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)XBARA_SEL64_SEL129_MASK (0x7F00U)XBARA_SEL64_SEL129_SHIFT (8U)XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)XBARA_SEL65_SEL130_MASK (0x7FU)XBARA_SEL65_SEL130_SHIFT (0U)XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)XBARA_SEL65_SEL131_MASK (0x7F00U)XBARA_SEL65_SEL131_SHIFT (8U)XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)XBARA_CTRL0_DEN0_MASK (0x1U)XBARA_CTRL0_DEN0_SHIFT (0U)XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)XBARA_CTRL0_IEN0_MASK (0x2U)XBARA_CTRL0_IEN0_SHIFT (1U)XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)XBARA_CTRL0_EDGE0_MASK (0xCU)XBARA_CTRL0_EDGE0_SHIFT (2U)XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)XBARA_CTRL0_STS0_MASK (0x10U)XBARA_CTRL0_STS0_SHIFT (4U)XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)XBARA_CTRL0_DEN1_MASK (0x100U)XBARA_CTRL0_DEN1_SHIFT (8U)XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)XBARA_CTRL0_IEN1_MASK (0x200U)XBARA_CTRL0_IEN1_SHIFT (9U)XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)XBARA_CTRL0_EDGE1_MASK (0xC00U)XBARA_CTRL0_EDGE1_SHIFT (10U)XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)XBARA_CTRL0_STS1_MASK (0x1000U)XBARA_CTRL0_STS1_SHIFT (12U)XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)XBARA_CTRL1_DEN2_MASK (0x1U)XBARA_CTRL1_DEN2_SHIFT (0U)XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)XBARA_CTRL1_IEN2_MASK (0x2U)XBARA_CTRL1_IEN2_SHIFT (1U)XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)XBARA_CTRL1_EDGE2_MASK (0xCU)XBARA_CTRL1_EDGE2_SHIFT (2U)XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)XBARA_CTRL1_STS2_MASK (0x10U)XBARA_CTRL1_STS2_SHIFT (4U)XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)XBARA_CTRL1_DEN3_MASK (0x100U)XBARA_CTRL1_DEN3_SHIFT (8U)XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)XBARA_CTRL1_IEN3_MASK (0x200U)XBARA_CTRL1_IEN3_SHIFT (9U)XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)XBARA_CTRL1_EDGE3_MASK (0xC00U)XBARA_CTRL1_EDGE3_SHIFT (10U)XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)XBARA_CTRL1_STS3_MASK (0x1000U)XBARA_CTRL1_STS3_SHIFT (12U)XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)XBARA1_BASE (0x403BC000u)XBARA1 ((XBARA_Type *)XBARA1_BASE)XBARA_BASE_ADDRS { XBARA1_BASE }XBARA_BASE_PTRS { XBARA1 }XBARB_SEL0_SEL0_MASK (0x3FU)XBARB_SEL0_SEL0_SHIFT (0U)XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)XBARB_SEL0_SEL1_MASK (0x3F00U)XBARB_SEL0_SEL1_SHIFT (8U)XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)XBARB_SEL1_SEL2_MASK (0x3FU)XBARB_SEL1_SEL2_SHIFT (0U)XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)XBARB_SEL1_SEL3_MASK (0x3F00U)XBARB_SEL1_SEL3_SHIFT (8U)XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)XBARB_SEL2_SEL4_MASK (0x3FU)XBARB_SEL2_SEL4_SHIFT (0U)XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)XBARB_SEL2_SEL5_MASK (0x3F00U)XBARB_SEL2_SEL5_SHIFT (8U)XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)XBARB_SEL3_SEL6_MASK (0x3FU)XBARB_SEL3_SEL6_SHIFT (0U)XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)XBARB_SEL3_SEL7_MASK (0x3F00U)XBARB_SEL3_SEL7_SHIFT (8U)XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)XBARB_SEL4_SEL8_MASK (0x3FU)XBARB_SEL4_SEL8_SHIFT (0U)XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)XBARB_SEL4_SEL9_MASK (0x3F00U)XBARB_SEL4_SEL9_SHIFT (8U)XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)XBARB_SEL5_SEL10_MASK (0x3FU)XBARB_SEL5_SEL10_SHIFT (0U)XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)XBARB_SEL5_SEL11_MASK (0x3F00U)XBARB_SEL5_SEL11_SHIFT (8U)XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)XBARB_SEL6_SEL12_MASK (0x3FU)XBARB_SEL6_SEL12_SHIFT (0U)XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)XBARB_SEL6_SEL13_MASK (0x3F00U)XBARB_SEL6_SEL13_SHIFT (8U)XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)XBARB_SEL7_SEL14_MASK (0x3FU)XBARB_SEL7_SEL14_SHIFT (0U)XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)XBARB_SEL7_SEL15_MASK (0x3F00U)XBARB_SEL7_SEL15_SHIFT (8U)XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)XBARB2_BASE (0x403C0000u)XBARB2 ((XBARB_Type *)XBARB2_BASE)XBARB3_BASE (0x403C4000u)XBARB3 ((XBARB_Type *)XBARB3_BASE)XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU)XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)XTALOSC24M_BASE (0x400D8000u)XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }XTALOSC24M_BASE_PTRS { XTALOSC24M }NXP_VAL2FLD(field,value) (((value) << (field ## _SHIFT)) & (field ## _MASK))NXP_FLD2VAL(field,value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) __CORE_CM7_H_GENERIC "?B__CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)C__CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB)D__CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB )G__CORTEX_M (7U)U__FPU_USED 0U__CORE_CM7_H_DEPENDANT __I volatile const__O volatile__IO volatile__IM volatile const__OM volatile__IOM volatileAPSR_N_Pos 31UAPSR_N_Msk (1UL << APSR_N_Pos)APSR_Z_Pos 30UAPSR_Z_Msk (1UL << APSR_Z_Pos)APSR_C_Pos 29UAPSR_C_Msk (1UL << APSR_C_Pos)APSR_V_Pos 28UAPSR_V_Msk (1UL << APSR_V_Pos)APSR_Q_Pos 27UAPSR_Q_Msk (1UL << APSR_Q_Pos)APSR_GE_Pos 16UAPSR_GE_Msk (0xFUL << APSR_GE_Pos)IPSR_ISR_Pos 0UIPSR_ISR_Msk (0x1FFUL )xPSR_N_Pos 31UxPSR_N_Msk (1UL << xPSR_N_Pos)xPSR_Z_Pos 30UxPSR_Z_Msk (1UL << xPSR_Z_Pos)xPSR_C_Pos 29UxPSR_C_Msk (1UL << xPSR_C_Pos)xPSR_V_Pos 28UxPSR_V_Msk (1UL << xPSR_V_Pos)xPSR_Q_Pos 27UxPSR_Q_Msk (1UL << xPSR_Q_Pos)xPSR_ICI_IT_2_Pos 25UxPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)xPSR_T_Pos 24UxPSR_T_Msk (1UL << xPSR_T_Pos)xPSR_GE_Pos 16UxPSR_GE_Msk (0xFUL << xPSR_GE_Pos)xPSR_ICI_IT_1_Pos 10UxPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)xPSR_ISR_Pos 0UxPSR_ISR_Msk (0x1FFUL )CONTROL_FPCA_Pos 2UCONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)CONTROL_SPSEL_Pos 1UCONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)CONTROL_nPRIV_Pos 0UCONTROL_nPRIV_Msk (1UL )NVIC_STIR_INTID_Pos 0UNVIC_STIR_INTID_Msk (0x1FFUL )SCB_CPUID_IMPLEMENTER_Pos 24USCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)SCB_CPUID_VARIANT_Pos 20USCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)SCB_CPUID_ARCHITECTURE_Pos 16USCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)SCB_CPUID_PARTNO_Pos 4USCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)SCB_CPUID_REVISION_Pos 0USCB_CPUID_REVISION_Msk (0xFUL )SCB_ICSR_NMIPENDSET_Pos 31USCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)SCB_ICSR_PENDSVSET_Pos 28USCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)SCB_ICSR_PENDSVCLR_Pos 27USCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)SCB_ICSR_PENDSTSET_Pos 26USCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)SCB_ICSR_PENDSTCLR_Pos 25USCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)SCB_ICSR_ISRPREEMPT_Pos 23USCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)SCB_ICSR_ISRPENDING_Pos 22USCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)SCB_ICSR_VECTPENDING_Pos 12USCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)SCB_ICSR_RETTOBASE_Pos 11USCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)SCB_ICSR_VECTACTIVE_Pos 0USCB_ICSR_VECTACTIVE_Msk (0x1FFUL )SCB_VTOR_TBLOFF_Pos 7USCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)SCB_AIRCR_VECTKEY_Pos 16USCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)SCB_AIRCR_VECTKEYSTAT_Pos 16USCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)SCB_AIRCR_ENDIANESS_Pos 15USCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)SCB_AIRCR_PRIGROUP_Pos 8USCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)SCB_AIRCR_SYSRESETREQ_Pos 2USCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)SCB_AIRCR_VECTCLRACTIVE_Pos 1USCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)SCB_AIRCR_VECTRESET_Pos 0USCB_AIRCR_VECTRESET_Msk (1UL )SCB_SCR_SEVONPEND_Pos 4USCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)SCB_SCR_SLEEPDEEP_Pos 2USCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)SCB_SCR_SLEEPONEXIT_Pos 1USCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)SCB_CCR_BP_Pos 18USCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)SCB_CCR_IC_Pos 17USCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)SCB_CCR_DC_Pos 16USCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)SCB_CCR_STKALIGN_Pos 9USCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)SCB_CCR_BFHFNMIGN_Pos 8USCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)SCB_CCR_DIV_0_TRP_Pos 4USCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)SCB_CCR_UNALIGN_TRP_Pos 3USCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)SCB_CCR_USERSETMPEND_Pos 1USCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)SCB_CCR_NONBASETHRDENA_Pos 0USCB_CCR_NONBASETHRDENA_Msk (1UL )SCB_SHCSR_USGFAULTENA_Pos 18USCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)SCB_SHCSR_BUSFAULTENA_Pos 17USCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)SCB_SHCSR_MEMFAULTENA_Pos 16USCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)SCB_SHCSR_SVCALLPENDED_Pos 15USCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)SCB_SHCSR_BUSFAULTPENDED_Pos 14USCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)SCB_SHCSR_MEMFAULTPENDED_Pos 13USCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)SCB_SHCSR_USGFAULTPENDED_Pos 12USCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)SCB_SHCSR_SYSTICKACT_Pos 11USCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)SCB_SHCSR_PENDSVACT_Pos 10USCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)SCB_SHCSR_MONITORACT_Pos 8USCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)SCB_SHCSR_SVCALLACT_Pos 7USCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)SCB_SHCSR_USGFAULTACT_Pos 3USCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)SCB_SHCSR_BUSFAULTACT_Pos 1USCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)SCB_SHCSR_MEMFAULTACT_Pos 0USCB_SHCSR_MEMFAULTACT_Msk (1UL )SCB_CFSR_USGFAULTSR_Pos 16USCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)SCB_CFSR_BUSFAULTSR_Pos 8USCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)SCB_CFSR_MEMFAULTSR_Pos 0USCB_CFSR_MEMFAULTSR_Msk (0xFFUL )SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)SCB_CFSR_IACCVIOL_Msk (1UL )SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)SCB_HFSR_DEBUGEVT_Pos 31USCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)SCB_HFSR_FORCED_Pos 30USCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)SCB_HFSR_VECTTBL_Pos 1USCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)SCB_DFSR_EXTERNAL_Pos 4USCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)SCB_DFSR_VCATCH_Pos 3USCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)SCB_DFSR_DWTTRAP_Pos 2USCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)SCB_DFSR_BKPT_Pos 1USCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)SCB_DFSR_HALTED_Pos 0USCB_DFSR_HALTED_Msk (1UL )SCB_CLIDR_LOUU_Pos 27USCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)SCB_CLIDR_LOC_Pos 24USCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)SCB_CTR_FORMAT_Pos 29USCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)SCB_CTR_CWG_Pos 24USCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)SCB_CTR_ERG_Pos 20USCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)SCB_CTR_DMINLINE_Pos 16USCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)SCB_CTR_IMINLINE_Pos 0USCB_CTR_IMINLINE_Msk (0xFUL )SCB_CCSIDR_WT_Pos 31USCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)SCB_CCSIDR_WB_Pos 30USCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)SCB_CCSIDR_RA_Pos 29USCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)SCB_CCSIDR_WA_Pos 28USCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)SCB_CCSIDR_NUMSETS_Pos 13USCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)SCB_CCSIDR_ASSOCIATIVITY_Pos 3USCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)SCB_CCSIDR_LINESIZE_Pos 0USCB_CCSIDR_LINESIZE_Msk (7UL )SCB_CSSELR_LEVEL_Pos 1USCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)SCB_CSSELR_IND_Pos 0USCB_CSSELR_IND_Msk (1UL )SCB_STIR_INTID_Pos 0USCB_STIR_INTID_Msk (0x1FFUL )SCB_DCISW_WAY_Pos 30USCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)SCB_DCISW_SET_Pos 5USCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)SCB_DCCSW_WAY_Pos 30USCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)SCB_DCCSW_SET_Pos 5USCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)SCB_DCCISW_WAY_Pos 30USCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)SCB_DCCISW_SET_Pos 5USCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)SCB_ITCMCR_SZ_Pos 3USCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)SCB_ITCMCR_RETEN_Pos 2USCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)SCB_ITCMCR_RMW_Pos 1USCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)SCB_ITCMCR_EN_Pos 0USCB_ITCMCR_EN_Msk (1UL )SCB_DTCMCR_SZ_Pos 3USCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)SCB_DTCMCR_RETEN_Pos 2USCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)SCB_DTCMCR_RMW_Pos 1USCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)SCB_DTCMCR_EN_Pos 0USCB_DTCMCR_EN_Msk (1UL )SCB_AHBPCR_SZ_Pos 1USCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)SCB_AHBPCR_EN_Pos 0USCB_AHBPCR_EN_Msk (1UL )SCB_CACR_FORCEWT_Pos 2USCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)SCB_CACR_ECCEN_Pos 1USCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)SCB_CACR_SIWT_Pos 0USCB_CACR_SIWT_Msk (1UL )SCB_AHBSCR_INITCOUNT_Pos 11USCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)SCB_AHBSCR_TPRI_Pos 2USCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)SCB_AHBSCR_CTL_Pos 0USCB_AHBSCR_CTL_Msk (3UL )SCB_ABFSR_AXIMTYPE_Pos 8USCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)SCB_ABFSR_EPPB_Pos 4USCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)SCB_ABFSR_AXIM_Pos 3USCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)SCB_ABFSR_AHBP_Pos 2USCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)SCB_ABFSR_DTCM_Pos 1USCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)SCB_ABFSR_ITCM_Pos 0USCB_ABFSR_ITCM_Msk (1UL )SCnSCB_ICTR_INTLINESNUM_Pos 0USCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12USCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)SCnSCB_ACTLR_DISRAMODE_Pos 11USCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)SCnSCB_ACTLR_FPEXCODIS_Pos 10USCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)SCnSCB_ACTLR_DISFOLD_Pos 2USCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)SCnSCB_ACTLR_DISMCYCINT_Pos 0USCnSCB_ACTLR_DISMCYCINT_Msk (1UL )SysTick_CTRL_COUNTFLAG_Pos 16USysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)SysTick_CTRL_CLKSOURCE_Pos 2USysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)SysTick_CTRL_TICKINT_Pos 1USysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)SysTick_CTRL_ENABLE_Pos 0USysTick_CTRL_ENABLE_Msk (1UL )SysTick_LOAD_RELOAD_Pos 0USysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )SysTick_VAL_CURRENT_Pos 0USysTick_VAL_CURRENT_Msk (0xFFFFFFUL )SysTick_CALIB_NOREF_Pos 31USysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)SysTick_CALIB_SKEW_Pos 30USysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)SysTick_CALIB_TENMS_Pos 0USysTick_CALIB_TENMS_Msk (0xFFFFFFUL )ITM_TPR_PRIVMASK_Pos 0UITM_TPR_PRIVMASK_Msk (0xFUL )ITM_TCR_BUSY_Pos 23UITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)ITM_TCR_TraceBusID_Pos 16UITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)ITM_TCR_GTSFREQ_Pos 10UITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)ITM_TCR_TSPrescale_Pos 8UITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)ITM_TCR_SWOENA_Pos 4UITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)ITM_TCR_DWTENA_Pos 3UITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)ITM_TCR_SYNCENA_Pos 2UITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)ITM_TCR_TSENA_Pos 1UITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)ITM_TCR_ITMENA_Pos 0UITM_TCR_ITMENA_Msk (1UL )ITM_IWR_ATVALIDM_Pos 0UITM_IWR_ATVALIDM_Msk (1UL )ITM_IRR_ATREADYM_Pos 0UITM_IRR_ATREADYM_Msk (1UL )ITM_IMCR_INTEGRATION_Pos 0UITM_IMCR_INTEGRATION_Msk (1UL )ITM_LSR_ByteAcc_Pos 2UITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)ITM_LSR_Access_Pos 1UITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)ITM_LSR_Present_Pos 0UITM_LSR_Present_Msk (1UL )DWT_CTRL_NUMCOMP_Pos 28UDWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)DWT_CTRL_NOTRCPKT_Pos 27UDWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) DWT_CTRL_NOEXTTRIG_Pos 26U DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) DWT_CTRL_NOCYCCNT_Pos 25U DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) DWT_CTRL_NOPRFCNT_Pos 24U DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) DWT_CTRL_CYCEVTENA_Pos 22U DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) DWT_CTRL_FOLDEVTENA_Pos 21U DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) DWT_CTRL_LSUEVTENA_Pos 20U DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) DWT_CTRL_SLEEPEVTENA_Pos 19U DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) DWT_CTRL_EXCEVTENA_Pos 18U DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) DWT_CTRL_CPIEVTENA_Pos 17U DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) DWT_CTRL_EXCTRCENA_Pos 16U DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) DWT_CTRL_PCSAMPLENA_Pos 12U DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) DWT_CTRL_SYNCTAP_Pos 10U DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) DWT_CTRL_CYCTAP_Pos 9U DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) DWT_CTRL_POSTINIT_Pos 5U DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) DWT_CTRL_POSTPRESET_Pos 1U DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) DWT_CTRL_CYCCNTENA_Pos 0U DWT_CTRL_CYCCNTENA_Msk (0x1UL ) DWT_CPICNT_CPICNT_Pos 0U DWT_CPICNT_CPICNT_Msk (0xFFUL ) DWT_EXCCNT_EXCCNT_Pos 0U DWT_EXCCNT_EXCCNT_Msk (0xFFUL ) DWT_SLEEPCNT_SLEEPCNT_Pos 0U DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL ) DWT_LSUCNT_LSUCNT_Pos 0U DWT_LSUCNT_LSUCNT_Msk (0xFFUL ) DWT_FOLDCNT_FOLDCNT_Pos 0U DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL ) DWT_MASK_MASK_Pos 0U DWT_MASK_MASK_Msk (0x1FUL ) DWT_FUNCTION_MATCHED_Pos 24U DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) DWT_FUNCTION_DATAVADDR1_Pos 16U DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) DWT_FUNCTION_DATAVADDR0_Pos 12U DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) DWT_FUNCTION_DATAVSIZE_Pos 10U DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) DWT_FUNCTION_LNK1ENA_Pos 9U DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) DWT_FUNCTION_DATAVMATCH_Pos 8U DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) DWT_FUNCTION_CYCMATCH_Pos 7U DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) DWT_FUNCTION_EMITRANGE_Pos 5U DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) DWT_FUNCTION_FUNCTION_Pos 0U DWT_FUNCTION_FUNCTION_Msk (0xFUL ) TPI_ACPR_PRESCALER_Pos 0U TPI_ACPR_PRESCALER_Msk (0x1FFFUL ) TPI_SPPR_TXMODE_Pos 0U TPI_SPPR_TXMODE_Msk (0x3UL ) TPI_FFSR_FtNonStop_Pos 3U TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) TPI_FFSR_TCPresent_Pos 2U TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) TPI_FFSR_FtStopped_Pos 1U TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) TPI_FFSR_FlInProg_Pos 0U TPI_FFSR_FlInProg_Msk (0x1UL ) TPI_FFCR_TrigIn_Pos 8U TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) TPI_FFCR_EnFCont_Pos 1U TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) TPI_TRIGGER_TRIGGER_Pos 0U TPI_TRIGGER_TRIGGER_Msk (0x1UL ) TPI_FIFO0_ITM_ATVALID_Pos 29U TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) TPI_FIFO0_ITM_bytecount_Pos 27U TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) TPI_FIFO0_ETM_ATVALID_Pos 26U TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) TPI_FIFO0_ETM_bytecount_Pos 24U TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) TPI_FIFO0_ETM2_Pos 16U TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) TPI_FIFO0_ETM1_Pos 8U TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) TPI_FIFO0_ETM0_Pos 0U TPI_FIFO0_ETM0_Msk (0xFFUL ) TPI_ITATBCTR2_ATREADY_Pos 0U TPI_ITATBCTR2_ATREADY_Msk (0x1UL ) TPI_FIFO1_ITM_ATVALID_Pos 29U TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) TPI_FIFO1_ITM_bytecount_Pos 27U TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) TPI_FIFO1_ETM_ATVALID_Pos 26U TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) TPI_FIFO1_ETM_bytecount_Pos 24U TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) TPI_FIFO1_ITM2_Pos 16U TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) TPI_FIFO1_ITM1_Pos 8U TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) TPI_FIFO1_ITM0_Pos 0U TPI_FIFO1_ITM0_Msk (0xFFUL ) TPI_ITATBCTR0_ATREADY_Pos 0U TPI_ITATBCTR0_ATREADY_Msk (0x1UL ) TPI_ITCTRL_Mode_Pos 0U TPI_ITCTRL_Mode_Msk (0x1UL ) TPI_DEVID_NRZVALID_Pos 11U TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) TPI_DEVID_MANCVALID_Pos 10U TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) TPI_DEVID_PTINVALID_Pos 9U TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) TPI_DEVID_MinBufSz_Pos 6U TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) TPI_DEVID_AsynClkIn_Pos 5U TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) TPI_DEVID_NrTraceInput_Pos 0U TPI_DEVID_NrTraceInput_Msk (0x1FUL ) TPI_DEVTYPE_MajorType_Pos 4U TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) TPI_DEVTYPE_SubType_Pos 0U TPI_DEVTYPE_SubType_Msk (0xFUL ) MPU_TYPE_IREGION_Pos 16U MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) MPU_TYPE_DREGION_Pos 8U MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) MPU_TYPE_SEPARATE_Pos 0U MPU_TYPE_SEPARATE_Msk (1UL ) MPU_CTRL_PRIVDEFENA_Pos 2U MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) MPU_CTRL_HFNMIENA_Pos 1U MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) MPU_CTRL_ENABLE_Pos 0U MPU_CTRL_ENABLE_Msk (1UL ) MPU_RNR_REGION_Pos 0U MPU_RNR_REGION_Msk (0xFFUL ) MPU_RBAR_ADDR_Pos 5U MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) MPU_RBAR_VALID_Pos 4U MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) MPU_RBAR_REGION_Pos 0U MPU_RBAR_REGION_Msk (0xFUL ) MPU_RASR_ATTRS_Pos 16U MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) MPU_RASR_XN_Pos 28U MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) MPU_RASR_AP_Pos 24U MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) MPU_RASR_TEX_Pos 19U MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) MPU_RASR_S_Pos 18U MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) MPU_RASR_C_Pos 17U MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) MPU_RASR_B_Pos 16U MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) MPU_RASR_SRD_Pos 8U MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) MPU_RASR_SIZE_Pos 1U MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) MPU_RASR_ENABLE_Pos 0U MPU_RASR_ENABLE_Msk (1UL ) FPU_FPCCR_ASPEN_Pos 31U FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) FPU_FPCCR_LSPEN_Pos 30U FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) FPU_FPCCR_MONRDY_Pos 8U FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) FPU_FPCCR_BFRDY_Pos 6U FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) FPU_FPCCR_MMRDY_Pos 5U FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) FPU_FPCCR_HFRDY_Pos 4U FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) FPU_FPCCR_THREAD_Pos 3U FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) FPU_FPCCR_USER_Pos 1U FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) FPU_FPCCR_LSPACT_Pos 0U FPU_FPCCR_LSPACT_Msk (1UL ) FPU_FPCAR_ADDRESS_Pos 3U FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) FPU_FPDSCR_AHP_Pos 26U FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) FPU_FPDSCR_DN_Pos 25U FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) FPU_FPDSCR_FZ_Pos 24U FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) FPU_FPDSCR_RMode_Pos 22U FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) FPU_MVFR0_FP_rounding_modes_Pos 28U FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) FPU_MVFR0_Short_vectors_Pos 24U FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) FPU_MVFR0_Square_root_Pos 20U FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) FPU_MVFR0_Divide_Pos 16U FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) FPU_MVFR0_FP_excep_trapping_Pos 12U FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) FPU_MVFR0_Double_precision_Pos 8U FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) FPU_MVFR0_Single_precision_Pos 4U FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) FPU_MVFR0_A_SIMD_registers_Pos 0U FPU_MVFR0_A_SIMD_registers_Msk (0xFUL ) FPU_MVFR1_FP_fused_MAC_Pos 28U FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) FPU_MVFR1_FP_HPFP_Pos 24U FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) FPU_MVFR1_D_NaN_mode_Pos 4U FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) FPU_MVFR1_FtZ_mode_Pos 0U FPU_MVFR1_FtZ_mode_Msk (0xFUL ) CoreDebug_DHCSR_DBGKEY_Pos 16U CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) CoreDebug_DHCSR_S_RESET_ST_Pos 25U CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) CoreDebug_DHCSR_S_LOCKUP_Pos 19U CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) CoreDebug_DHCSR_S_SLEEP_Pos 18U CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) CoreDebug_DHCSR_S_HALT_Pos 17U CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) CoreDebug_DHCSR_S_REGRDY_Pos 16U CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) CoreDebug_DHCSR_C_MASKINTS_Pos 3U CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) CoreDebug_DHCSR_C_STEP_Pos 2U CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) CoreDebug_DHCSR_C_HALT_Pos 1U CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) CoreDebug_DHCSR_C_DEBUGEN_Pos 0U CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL ) CoreDebug_DCRSR_REGWnR_Pos 16U CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) CoreDebug_DCRSR_REGSEL_Pos 0U CoreDebug_DCRSR_REGSEL_Msk (0x1FUL ) CoreDebug_DEMCR_TRCENA_Pos 24U CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) CoreDebug_DEMCR_MON_REQ_Pos 19U CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) CoreDebug_DEMCR_MON_STEP_Pos 18U CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) CoreDebug_DEMCR_MON_PEND_Pos 17U CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) CoreDebug_DEMCR_MON_EN_Pos 16U CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) CoreDebug_DEMCR_VC_HARDERR_Pos 10U CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) CoreDebug_DEMCR_VC_INTERR_Pos 9U CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) CoreDebug_DEMCR_VC_BUSERR_Pos 8U CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) CoreDebug_DEMCR_VC_STATERR_Pos 7U CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) CoreDebug_DEMCR_VC_CHKERR_Pos 6U CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) CoreDebug_DEMCR_VC_NOCPERR_Pos 5U CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) CoreDebug_DEMCR_VC_MMERR_Pos 4U CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) CoreDebug_DEMCR_VC_CORERESET_Pos 0U CoreDebug_DEMCR_VC_CORERESET_Msk (1UL ) _VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) _FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) SCS_BASE (0xE000E000UL) ITM_BASE (0xE0000000UL) DWT_BASE (0xE0001000UL) TPI_BASE (0xE0040000UL) CoreDebug_BASE (0xE000EDF0UL) SysTick_BASE (SCS_BASE + 0x0010UL) NVIC_BASE (SCS_BASE + 0x0100UL) SCB_BASE (SCS_BASE + 0x0D00UL) SCnSCB ((SCnSCB_Type *) SCS_BASE ) SCB ((SCB_Type *) SCB_BASE ) SysTick ((SysTick_Type *) SysTick_BASE ) NVIC ((NVIC_Type *) NVIC_BASE ) ITM ((ITM_Type *) ITM_BASE ) DWT ((DWT_Type *) DWT_BASE ) TPI ((TPI_Type *) TPI_BASE ) CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) MPU_BASE (SCS_BASE + 0x0D90UL) MPU ((MPU_Type *) MPU_BASE ) FPU_BASE (SCS_BASE + 0x0F30UL) FPU ((FPU_Type *) FPU_BASE )NVIC_SetPriorityGrouping __NVIC_SetPriorityGroupingNVIC_GetPriorityGrouping __NVIC_GetPriorityGroupingNVIC_EnableIRQ __NVIC_EnableIRQNVIC_GetEnableIRQ __NVIC_GetEnableIRQNVIC_DisableIRQ __NVIC_DisableIRQNVIC_GetPendingIRQ __NVIC_GetPendingIRQNVIC_SetPendingIRQ __NVIC_SetPendingIRQNVIC_ClearPendingIRQ __NVIC_ClearPendingIRQNVIC_GetActive __NVIC_GetActiveNVIC_SetPriority __NVIC_SetPriorityNVIC_GetPriority __NVIC_GetPriorityNVIC_SystemReset __NVIC_SystemResetNVIC_SetVector __NVIC_SetVectorNVIC_GetVector __NVIC_GetVectorNVIC_USER_IRQ_OFFSET 16CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)#$%&+FLEXSPI_LUT_KEY_VAL (0x5AF05AF0ul),FLEXSPI_WAIT_TIMEOUT_NS (500000000UL)-FLEXSPI_FREQ_1GHz (1000000000UL)/FREQ_1MHz (1000000UL)0FLEXSPI_DLLCR_DEFAULT (0x100UL)2FLEXSPI0_CLK_GATE_OFFSET 13U3FLEXSPI1_CLK_GATE_OFFSET 15U5CMD_LUT_FOR_IP_CMD 1=FLEXSPI_PINMUX_VAL 0x08'__FSL_FLEXSPI_H__ )/FlexSPI_LUT_COUNT (64)1FlexSPI_AHB_RX_BUF_COUNT (4U)3FlexSPI_ASFM_BASE (0x00000000U)5FlexSPI_AHB_RX_BUF_DEPTH (512U)7FlexSPI_AHB_TX_BUF_DEPTH (32U)9FlexSPI_IP_RX_BUF_DEPTH (256U);FlexSPI_IP_TX_BUF_DEPTH (256U)>FLEXSPI_CFG_BLK_TAG (0x42464346UL)?FLEXSPI_CFG_BLK_VERSION (0x56010400UL)@FLEXSPI_CFG_BLK_SIZE (512)CFLEXSPI_FEATURE_HAS_PARALLEL_MODE 1FCMD_INDEX_READ 0GCMD_INDEX_READSTATUS 1HCMD_INDEX_WRITEENABLE 2ICMD_INDEX_WRITE 4KCMD_LUT_SEQ_IDX_READ 0LCMD_LUT_SEQ_IDX_READSTATUS 1MCMD_LUT_SEQ_IDX_WRITEENABLE 3NCMD_LUT_SEQ_IDX_WRITE 9PCMD_SDR 0x01QCMD_DDR 0x21RRADDR_SDR 0x02SRADDR_DDR 0x22TCADDR_SDR 0x03UCADDR_DDR 0x23VMODE1_SDR 0x04WMODE1_DDR 0x24XMODE2_SDR 0x05YMODE2_DDR 0x25ZMODE4_SDR 0x06[MODE4_DDR 0x26\MODE8_SDR 0x07]MODE8_DDR 0x27^WRITE_SDR 0x08_WRITE_DDR 0x28`READ_SDR 0x09aREAD_DDR 0x29bLEARN_SDR 0x0AcLEARN_DDR 0x2AdDATSZ_SDR 0x0BeDATSZ_DDR 0x2BfDUMMY_SDR 0x0CgDUMMY_DDR 0x2ChDUMMY_RWDS_SDR 0x0DiDUMMY_RWDS_DDR 0x2DjJMP_ON_CS 0x1FkSTOP 0mFLEXSPI_1PAD 0nFLEXSPI_2PAD 1oFLEXSPI_4PAD 2pFLEXSPI_8PAD 3rFLEXSPI_LUT_SEQ(cmd0,pad0,op0,cmd1,pad1,op1) (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset))&'()*0MAX_24BIT_ADDRESSING_SIZE (16UL * 1024 * 1024)2NOR_CMD_LUT_FOR_IP_CMD 1~SFDP_SIGNATURE 0x50444653'__FLEXSPI_NOR_FLASH_H__ )*-NOR_CMD_INDEX_READ CMD_INDEX_READ.NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS/NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE0NOR_CMD_INDEX_ERASESECTOR 31NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE2NOR_CMD_INDEX_CHIPERASE 53NOR_CMD_INDEX_DUMMY 64NOR_CMD_INDEX_ERASEBLOCK 76NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ7NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS9NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2;NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE=NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4?NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5@NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8ANOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITECNOR_CMD_LUT_SEQ_IDX_CHIPERASE 11DNOR_CMD_LUT_SEQ_IDX_READ_SFDP 13ENOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14GNOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15_FSL_CLOCK_H_ !"#$.CCM_TUPLE(reg,shift,mask,busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))/CCM_TUPLE_REG(base,tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU))))0CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)1CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))2CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)4CCM_NO_BUSY_WAIT (0x20U)AFSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0GFSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))_CLOCK_SetXtal0Freq CLOCK_SetXtalFreq`CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreqcADC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Adc1 }iADC_5HC_CLOCKS { kCLOCK_Adc_5hc }oAOI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 }uBEE_CLOCKS { kCLOCK_Bee }{CMP_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 }CSI_CLOCKS { kCLOCK_Csi }DCDC_CLOCKS { kCLOCK_Dcdc }DCP_CLOCKS { kCLOCK_Dcp }DMAMUX_CLOCKS { kCLOCK_Dma }EDMA_CLOCKS { kCLOCK_Dma }ENC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 }ENET_CLOCKS { kCLOCK_Enet }EWM_CLOCKS { kCLOCK_Ewm0 }FLEXCAN_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 }FLEXCAN_PERIPH_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S }FLEXIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 }FLEXRAM_CLOCKS { kCLOCK_FlexRam }FLEXSPI_CLOCKS { kCLOCK_FlexSpi }GPIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 }GPT_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 }KPP_CLOCKS { kCLOCK_Kpp }LCDIF_CLOCKS { kCLOCK_Lcd }LCDIF_PERIPH_CLOCKS { kCLOCK_LcdPixel }LPI2C_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 }LPSPI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 }LPUART_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 }PIT_CLOCKS { kCLOCK_Pit }PWM_CLOCKS { { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid } , { kCLOCK_Pwm1, kCLOCK_Pwm1,kCLOCK_Pwm1, kCLOCK_Pwm1 } , { kCLOCK_Pwm2, kCLOCK_Pwm2,kCLOCK_Pwm2, kCLOCK_Pwm2 } , { kCLOCK_Pwm3, kCLOCK_Pwm3,kCLOCK_Pwm3, kCLOCK_Pwm3 } , { kCLOCK_Pwm4, kCLOCK_Pwm4,kCLOCK_Pwm4, kCLOCK_Pwm4 } }PXP_CLOCKS { kCLOCK_Pxp }RTWDOG_CLOCKS { kCLOCK_Wdog3 }SAI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 }SEMC_CLOCKS { kCLOCK_Semc }TMR_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 }TRNG_CLOCKS { kCLOCK_Trng }TSC_CLOCKS { kCLOCK_Tsc }WDOG_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 }USDHC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 }SPDIF_CLOCKS { kCLOCK_Spdif }XBARA_CLOCKS { kCLOCK_Xbar1 }XBARB_CLOCKS { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 }kCLOCK_CoreSysClk kCLOCK_CpuClkCLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq %FREQ_396MHz (396000000U)&FREQ_480MHz (480000000U)'FREQ_528MHz (528000000U)(FREQ_24MHz (24000000U)+SW_MUX_CTL_PAD_FLEXSPIB_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05,SW_MUX_CTL_PAD_FLEXSPIB_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00-SW_MUX_CTL_PAD_FLEXSPIB_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01.SW_MUX_CTL_PAD_FLEXSPIB_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02/SW_MUX_CTL_PAD_FLEXSPIB_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_030SW_MUX_CTL_PAD_FLEXSPIB_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_041SW_MUX_CTL_PAD_FLEXSPIB_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_012SW_MUX_CTL_PAD_FLEXSPIB_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_044SW_MUX_CTL_PAD_FLEXSPIA_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_055SW_MUX_CTL_PAD_FLEXSPIA_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_066SW_MUX_CTL_PAD_FLEXSPIA_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_007SW_MUX_CTL_PAD_FLEXSPIA_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_078SW_MUX_CTL_PAD_FLEXSPIA_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_089SW_MUX_CTL_PAD_FLEXSPIA_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09:SW_MUX_CTL_PAD_FLEXSPIA_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10;SW_MUX_CTL_PAD_FLEXSPIA_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11SW_PAD_CTL_PAD_FLEXSPIB_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05?SW_PAD_CTL_PAD_FLEXSPIB_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00@SW_PAD_CTL_PAD_FLEXSPIB_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01ASW_PAD_CTL_PAD_FLEXSPIB_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02BSW_PAD_CTL_PAD_FLEXSPIB_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03CSW_PAD_CTL_PAD_FLEXSPIB_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04DSW_PAD_CTL_PAD_FLEXSPIB_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01ESW_PAD_CTL_PAD_FLEXSPIB_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04GSW_PAD_CTL_PAD_FLEXSPIA_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05HSW_PAD_CTL_PAD_FLEXSPIA_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06ISW_PAD_CTL_PAD_FLEXSPIA_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00JSW_PAD_CTL_PAD_FLEXSPIA_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07KSW_PAD_CTL_PAD_FLEXSPIA_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08LSW_PAD_CTL_PAD_FLEXSPIA_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09MSW_PAD_CTL_PAD_FLEXSPIA_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10NSW_PAD_CTL_PAD_FLEXSPIA_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11OSW_PAD_CTL_PAD_FLEXSPIA_SCLK_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04QFLEXSPIA_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1)RFLEXSPIB_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1)SFLEXSPIA_SS1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(6)TFLEXSPIB_SS1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(6)UFLEXSPIB_SS0_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4)VFLEXSPIB_DQS_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4)]FLEXSPI_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(0) | IOMUXC_SW_PAD_CTL_PAD_PUS(0))gFLEXSPI_DQS_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | IOMUXC_SW_PAD_CTL_PAD_HYS(1)) %FREQ_396MHz (396UL * 1000 * 1000)&FREQ_528MHz (528UL * 1000 * 1000)'FREQ_24MHz (24UL * 1000 * 1000)(FREQ_480MHz (480UL * 1000 * 1000) _FSL_COMMON_H_ "#$%&,8MAKE_STATUS(group,code) ((((group)*100) + (code)));MAKE_VERSION(major,minor,bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))@FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))DDEBUG_CONSOLE_DEVICE_TYPE_NONE 0UEDEBUG_CONSOLE_DEVICE_TYPE_UART 1UFDEBUG_CONSOLE_DEVICE_TYPE_LPUART 2UGDEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3UHDEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4UIDEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5UJDEBUG_CONSOLE_DEVICE_TYPE_IUART 6UKDEBUG_CONSOLE_DEVICE_TYPE_VUSART 7UMIN(a,b) ((a) < (b) ? (a) : (b))MAX(a,b) ((a) > (b) ? (a) : (b))ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))USEC_TO_COUNT(us,clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)COUNT_TO_USEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)MSEC_TO_COUNT(ms,clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)COUNT_TO_MSEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)SDK_ALIGN(var,alignbytes) __align(alignbytes) varSDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) varSDK_SIZEALIGN(var,alignbytes) ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) varAT_NONCACHEABLE_SECTION_ALIGN(var,alignbytes) __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) varAT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) varAT_NONCACHEABLE_SECTION_ALIGN_INIT(var,alignbytes) __attribute__((section("NonCacheable.init"))) __align(alignbytes) varALIGN_DOWN(x,a) ((x) & -(a))ALIGN_UP(x,a) (-(-(x) & -(a)))_FSL_CLOCK_H_ !"#$.CCM_TUPLE(reg,shift,mask,busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))/CCM_TUPLE_REG(base,tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU))))0CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)1CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))2CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)4CCM_NO_BUSY_WAIT (0x20U)AFSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0GFSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))_CLOCK_SetXtal0Freq CLOCK_SetXtalFreq`CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreqcADC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Adc1 }iADC_5HC_CLOCKS { kCLOCK_Adc_5hc }oAOI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 }uBEE_CLOCKS { kCLOCK_Bee }{CMP_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 }CSI_CLOCKS { kCLOCK_Csi }DCDC_CLOCKS { kCLOCK_Dcdc }DCP_CLOCKS { kCLOCK_Dcp }DMAMUX_CLOCKS { kCLOCK_Dma }EDMA_CLOCKS { kCLOCK_Dma }ENC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 }ENET_CLOCKS { kCLOCK_Enet }EWM_CLOCKS { kCLOCK_Ewm0 }FLEXCAN_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 }FLEXCAN_PERIPH_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S }FLEXIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 }FLEXRAM_CLOCKS { kCLOCK_FlexRam }FLEXSPI_CLOCKS { kCLOCK_FlexSpi }GPIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 }GPT_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 }KPP_CLOCKS { kCLOCK_Kpp }LCDIF_CLOCKS { kCLOCK_Lcd }LCDIF_PERIPH_CLOCKS { kCLOCK_LcdPixel }LPI2C_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 }LPSPI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 }LPUART_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 }PIT_CLOCKS { kCLOCK_Pit }PWM_CLOCKS { { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid } , { kCLOCK_Pwm1, kCLOCK_Pwm1,kCLOCK_Pwm1, kCLOCK_Pwm1 } , { kCLOCK_Pwm2, kCLOCK_Pwm2,kCLOCK_Pwm2, kCLOCK_Pwm2 } , { kCLOCK_Pwm3, kCLOCK_Pwm3,kCLOCK_Pwm3, kCLOCK_Pwm3 } , { kCLOCK_Pwm4, kCLOCK_Pwm4,kCLOCK_Pwm4, kCLOCK_Pwm4 } }PXP_CLOCKS { kCLOCK_Pxp }RTWDOG_CLOCKS { kCLOCK_Wdog3 }SAI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 }SEMC_CLOCKS { kCLOCK_Semc }TMR_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 }TRNG_CLOCKS { kCLOCK_Trng }TSC_CLOCKS { kCLOCK_Tsc }WDOG_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 }USDHC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 }SPDIF_CLOCKS { kCLOCK_Spdif }XBARA_CLOCKS { kCLOCK_Xbar1 }XBARB_CLOCKS { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 }kCLOCK_CoreSysClk kCLOCK_CpuClkCLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq '__FLEXSPI_NOR_FLASH_H__ )*-NOR_CMD_INDEX_READ CMD_INDEX_READ.NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS/NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE0NOR_CMD_INDEX_ERASESECTOR 31NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE2NOR_CMD_INDEX_CHIPERASE 53NOR_CMD_INDEX_DUMMY 64NOR_CMD_INDEX_ERASEBLOCK 76NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ7NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS9NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2;NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE=NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4?NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5@NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8ANOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITECNOR_CMD_LUT_SEQ_IDX_CHIPERASE 11DNOR_CMD_LUT_SEQ_IDX_READ_SFDP 13ENOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14GNOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15'__FSL_FLEXSPI_H__ )/FlexSPI_LUT_COUNT (64)1FlexSPI_AHB_RX_BUF_COUNT (4U)3FlexSPI_ASFM_BASE (0x00000000U)5FlexSPI_AHB_RX_BUF_DEPTH (512U)7FlexSPI_AHB_TX_BUF_DEPTH (32U)9FlexSPI_IP_RX_BUF_DEPTH (256U);FlexSPI_IP_TX_BUF_DEPTH (256U)>FLEXSPI_CFG_BLK_TAG (0x42464346UL)?FLEXSPI_CFG_BLK_VERSION (0x56010400UL)@FLEXSPI_CFG_BLK_SIZE (512)CFLEXSPI_FEATURE_HAS_PARALLEL_MODE 1FCMD_INDEX_READ 0GCMD_INDEX_READSTATUS 1HCMD_INDEX_WRITEENABLE 2ICMD_INDEX_WRITE 4KCMD_LUT_SEQ_IDX_READ 0LCMD_LUT_SEQ_IDX_READSTATUS 1MCMD_LUT_SEQ_IDX_WRITEENABLE 3NCMD_LUT_SEQ_IDX_WRITE 9PCMD_SDR 0x01QCMD_DDR 0x21RRADDR_SDR 0x02SRADDR_DDR 0x22TCADDR_SDR 0x03UCADDR_DDR 0x23VMODE1_SDR 0x04WMODE1_DDR 0x24XMODE2_SDR 0x05YMODE2_DDR 0x25ZMODE4_SDR 0x06[MODE4_DDR 0x26\MODE8_SDR 0x07]MODE8_DDR 0x27^WRITE_SDR 0x08_WRITE_DDR 0x28`READ_SDR 0x09aREAD_DDR 0x29bLEARN_SDR 0x0AcLEARN_DDR 0x2AdDATSZ_SDR 0x0BeDATSZ_DDR 0x2BfDUMMY_SDR 0x0CgDUMMY_DDR 0x2ChDUMMY_RWDS_SDR 0x0DiDUMMY_RWDS_DDR 0x2DjJMP_ON_CS 0x1FkSTOP 0mFLEXSPI_1PAD 0nFLEXSPI_2PAD 1oFLEXSPI_4PAD 2pFLEXSPI_8PAD 3rFLEXSPI_LUT_SEQ(cmd0,pad0,op0,cmd1,pad1,op1) (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset)) _FSL_COMMON_H_ "#$%&,8MAKE_STATUS(group,code) ((((group)*100) + (code)));MAKE_VERSION(major,minor,bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))@FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))DDEBUG_CONSOLE_DEVICE_TYPE_NONE 0UEDEBUG_CONSOLE_DEVICE_TYPE_UART 1UFDEBUG_CONSOLE_DEVICE_TYPE_LPUART 2UGDEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3UHDEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4UIDEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5UJDEBUG_CONSOLE_DEVICE_TYPE_IUART 6UKDEBUG_CONSOLE_DEVICE_TYPE_VUSART 7UMIN(a,b) ((a) < (b) ? (a) : (b))MAX(a,b) ((a) > (b) ? (a) : (b))ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))USEC_TO_COUNT(us,clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)COUNT_TO_USEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)MSEC_TO_COUNT(ms,clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)COUNT_TO_MSEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)SDK_ALIGN(var,alignbytes) __align(alignbytes) varSDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) varSDK_SIZEALIGN(var,alignbytes) ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) varAT_NONCACHEABLE_SECTION_ALIGN(var,alignbytes) __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) varAT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) varAT_NONCACHEABLE_SECTION_ALIGN_INIT(var,alignbytes) __attribute__((section("NonCacheable.init"))) __align(alignbytes) varALIGN_DOWN(x,a) ((x) & -(a))ALIGN_UP(x,a) (-(-(x) & -(a)))B_MIMXRT1052_H_ FMCU_MEM_MAP_VERSION 0x0000UHMCU_MEM_MAP_VERSION_MINOR 0x0001UUNUMBER_OF_INT_VECTORS 176__MPU_PRESENT 1__ICACHE_PRESENT 1__DCACHE_PRESENT 1__DTCM_PRESENT 1__NVIC_PRIO_BITS 4__Vendor_SysTickConfig 0__FPU_PRESENT 1 ADC_HC_ADCH_MASK (0x1FU) ADC_HC_ADCH_SHIFT (0U) ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) ADC_HC_AIEN_MASK (0x80U) ADC_HC_AIEN_SHIFT (7U) ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) ADC_HC_COUNT (8U) ADC_HS_COCO0_MASK (0x1U) ADC_HS_COCO0_SHIFT (0U) ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) ADC_R_CDATA_MASK (0xFFFU) ADC_R_CDATA_SHIFT (0U) ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) ADC_R_COUNT (8U) ADC_CFG_ADICLK_MASK (0x3U) ADC_CFG_ADICLK_SHIFT (0U) ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) ADC_CFG_MODE_MASK (0xCU) ADC_CFG_MODE_SHIFT (2U) ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) ADC_CFG_ADLSMP_MASK (0x10U) ADC_CFG_ADLSMP_SHIFT (4U) ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) ADC_CFG_ADIV_MASK (0x60U) ADC_CFG_ADIV_SHIFT (5U) ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) ADC_CFG_ADLPC_MASK (0x80U) ADC_CFG_ADLPC_SHIFT (7U) ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) ADC_CFG_ADSTS_MASK (0x300U) ADC_CFG_ADSTS_SHIFT (8U) ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) ADC_CFG_ADHSC_MASK (0x400U) ADC_CFG_ADHSC_SHIFT (10U) ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) ADC_CFG_REFSEL_MASK (0x1800U) ADC_CFG_REFSEL_SHIFT (11U) ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) ADC_CFG_ADTRG_MASK (0x2000U) ADC_CFG_ADTRG_SHIFT (13U) ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) ADC_CFG_AVGS_MASK (0xC000U) ADC_CFG_AVGS_SHIFT (14U) ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) ADC_CFG_OVWREN_MASK (0x10000U) ADC_CFG_OVWREN_SHIFT (16U) ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) ADC_GC_ADACKEN_MASK (0x1U) ADC_GC_ADACKEN_SHIFT (0U) ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) ADC_GC_DMAEN_MASK (0x2U) ADC_GC_DMAEN_SHIFT (1U) ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) ADC_GC_ACREN_MASK (0x4U) ADC_GC_ACREN_SHIFT (2U) ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) ADC_GC_ACFGT_MASK (0x8U) ADC_GC_ACFGT_SHIFT (3U) ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) ADC_GC_ACFE_MASK (0x10U) ADC_GC_ACFE_SHIFT (4U) ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) ADC_GC_AVGE_MASK (0x20U) ADC_GC_AVGE_SHIFT (5U) ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) ADC_GC_ADCO_MASK (0x40U) ADC_GC_ADCO_SHIFT (6U) ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) ADC_GC_CAL_MASK (0x80U) ADC_GC_CAL_SHIFT (7U) ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) ADC_GS_ADACT_MASK (0x1U) ADC_GS_ADACT_SHIFT (0U) ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) ADC_GS_CALF_MASK (0x2U) ADC_GS_CALF_SHIFT (1U) ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) ADC_GS_AWKST_MASK (0x4U) ADC_GS_AWKST_SHIFT (2U) ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) ADC_CV_CV1_MASK (0xFFFU) ADC_CV_CV1_SHIFT (0U) ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) ADC_CV_CV2_MASK (0xFFF0000U) ADC_CV_CV2_SHIFT (16U) ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) ADC_OFS_OFS_MASK (0xFFFU) ADC_OFS_OFS_SHIFT (0U) ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) ADC_OFS_SIGN_MASK (0x1000U) ADC_OFS_SIGN_SHIFT (12U) ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) ADC_CAL_CAL_CODE_MASK (0xFU) ADC_CAL_CAL_CODE_SHIFT (0U) ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) ADC1_BASE (0x400C4000u) ADC1 ((ADC_Type *)ADC1_BASE) ADC2_BASE (0x400C8000u) ADC2 ((ADC_Type *)ADC2_BASE) ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) ADC_ETC_CTRL_SOFTRST_SHIFT (31U) ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) ADC_ETC_TRIGn_CTRL_COUNT (8U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) ADC_ETC_TRIGn_COUNTER_COUNT (8U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)ADC_ETC_BASE (0x403B0000u)ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }ADC_ETC_BASE_PTRS { ADC_ETC }ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }AIPSTZ_MPR_MPROT5_MASK (0xF00U)AIPSTZ_MPR_MPROT5_SHIFT (8U)AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)AIPSTZ_MPR_MPROT3_MASK (0xF0000U)AIPSTZ_MPR_MPROT3_SHIFT (16U)AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)AIPSTZ_MPR_MPROT2_MASK (0xF00000U)AIPSTZ_MPR_MPROT2_SHIFT (20U)AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)AIPSTZ_MPR_MPROT1_MASK (0xF000000U)AIPSTZ_MPR_MPROT1_SHIFT (24U)AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)AIPSTZ_MPR_MPROT0_SHIFT (28U)AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)AIPSTZ_OPACR_OPAC7_MASK (0xFU)AIPSTZ_OPACR_OPAC7_SHIFT (0U)AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)AIPSTZ_OPACR_OPAC6_MASK (0xF0U)AIPSTZ_OPACR_OPAC6_SHIFT (4U)AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)AIPSTZ_OPACR_OPAC5_MASK (0xF00U)AIPSTZ_OPACR_OPAC5_SHIFT (8U)AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)AIPSTZ_OPACR_OPAC4_MASK (0xF000U)AIPSTZ_OPACR_OPAC4_SHIFT (12U)AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)AIPSTZ_OPACR_OPAC3_SHIFT (16U)AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)AIPSTZ_OPACR_OPAC2_SHIFT (20U)AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)AIPSTZ_OPACR_OPAC1_SHIFT (24U)AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)AIPSTZ_OPACR_OPAC0_SHIFT (28U)AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)AIPSTZ_OPACR1_OPAC15_MASK (0xFU)AIPSTZ_OPACR1_OPAC15_SHIFT (0U)AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)AIPSTZ_OPACR1_OPAC14_SHIFT (4U)AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)AIPSTZ_OPACR1_OPAC13_SHIFT (8U)AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)AIPSTZ_OPACR1_OPAC12_SHIFT (12U)AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)AIPSTZ_OPACR1_OPAC11_SHIFT (16U)AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)AIPSTZ_OPACR1_OPAC10_SHIFT (20U)AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)AIPSTZ_OPACR1_OPAC9_SHIFT (24U)AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)AIPSTZ_OPACR1_OPAC8_SHIFT (28U)AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)AIPSTZ_OPACR2_OPAC23_MASK (0xFU)AIPSTZ_OPACR2_OPAC23_SHIFT (0U)AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)AIPSTZ_OPACR2_OPAC22_SHIFT (4U)AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)AIPSTZ_OPACR2_OPAC21_SHIFT (8U)AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)AIPSTZ_OPACR2_OPAC20_SHIFT (12U)AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)AIPSTZ_OPACR2_OPAC19_SHIFT (16U)AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)AIPSTZ_OPACR2_OPAC18_SHIFT (20U)AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)AIPSTZ_OPACR2_OPAC17_SHIFT (24U)AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)AIPSTZ_OPACR2_OPAC16_SHIFT (28U)AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)AIPSTZ_OPACR3_OPAC31_MASK (0xFU)AIPSTZ_OPACR3_OPAC31_SHIFT (0U)AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)AIPSTZ_OPACR3_OPAC30_SHIFT (4U)AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)AIPSTZ_OPACR3_OPAC29_SHIFT (8U)AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)AIPSTZ_OPACR3_OPAC28_SHIFT (12U)AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)AIPSTZ_OPACR3_OPAC27_SHIFT (16U)AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)AIPSTZ_OPACR3_OPAC26_SHIFT (20U)AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)AIPSTZ_OPACR3_OPAC25_SHIFT (24U)AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)AIPSTZ_OPACR3_OPAC24_SHIFT (28U)AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)AIPSTZ_OPACR4_OPAC33_SHIFT (24U)AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)AIPSTZ_OPACR4_OPAC32_SHIFT (28U)AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)AIPSTZ1_BASE (0x4007C000u)AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)AIPSTZ2_BASE (0x4017C000u)AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)AIPSTZ3_BASE (0x4027C000u)AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)AIPSTZ4_BASE (0x4037C000u)AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }AOI_BFCRT01_PT1_DC_MASK (0x3U)AOI_BFCRT01_PT1_DC_SHIFT (0U)AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)AOI_BFCRT01_PT1_CC_MASK (0xCU)AOI_BFCRT01_PT1_CC_SHIFT (2U)AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)AOI_BFCRT01_PT1_BC_MASK (0x30U)AOI_BFCRT01_PT1_BC_SHIFT (4U)AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)AOI_BFCRT01_PT1_AC_MASK (0xC0U)AOI_BFCRT01_PT1_AC_SHIFT (6U)AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)AOI_BFCRT01_PT0_DC_MASK (0x300U)AOI_BFCRT01_PT0_DC_SHIFT (8U)AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)AOI_BFCRT01_PT0_CC_MASK (0xC00U)AOI_BFCRT01_PT0_CC_SHIFT (10U)AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)AOI_BFCRT01_PT0_BC_MASK (0x3000U)AOI_BFCRT01_PT0_BC_SHIFT (12U)AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)AOI_BFCRT01_PT0_AC_MASK (0xC000U)AOI_BFCRT01_PT0_AC_SHIFT (14U)AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)AOI_BFCRT01_COUNT (4U)AOI_BFCRT23_PT3_DC_MASK (0x3U)AOI_BFCRT23_PT3_DC_SHIFT (0U)AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)AOI_BFCRT23_PT3_CC_MASK (0xCU)AOI_BFCRT23_PT3_CC_SHIFT (2U)AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)AOI_BFCRT23_PT3_BC_MASK (0x30U)AOI_BFCRT23_PT3_BC_SHIFT (4U)AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)AOI_BFCRT23_PT3_AC_MASK (0xC0U)AOI_BFCRT23_PT3_AC_SHIFT (6U)AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)AOI_BFCRT23_PT2_DC_MASK (0x300U)AOI_BFCRT23_PT2_DC_SHIFT (8U)AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)AOI_BFCRT23_PT2_CC_MASK (0xC00U)AOI_BFCRT23_PT2_CC_SHIFT (10U)AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)AOI_BFCRT23_PT2_BC_MASK (0x3000U)AOI_BFCRT23_PT2_BC_SHIFT (12U)AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)AOI_BFCRT23_PT2_AC_MASK (0xC000U)AOI_BFCRT23_PT2_AC_SHIFT (14U)AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)AOI_BFCRT23_COUNT (4U)AOI1_BASE (0x403B4000u)AOI1 ((AOI_Type *)AOI1_BASE)AOI2_BASE (0x403B8000u)AOI2 ((AOI_Type *)AOI2_BASE)AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }BEE_CTRL_BEE_ENABLE_MASK (0x1U)BEE_CTRL_BEE_ENABLE_SHIFT (0U)BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)BEE_CTRL_KEY_VALID_MASK (0x10U)BEE_CTRL_KEY_VALID_SHIFT (4U)BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)BEE_CTRL_AC_PROT_EN_MASK (0x40U)BEE_CTRL_AC_PROT_EN_SHIFT (6U)BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU)BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U)BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK)BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W0_KEY0_SHIFT (0U)BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W1_KEY1_SHIFT (0U)BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W2_KEY2_SHIFT (0U)BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W3_KEY3_SHIFT (0U)BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)BEE_STATUS_IRQ_VEC_MASK (0xFFU)BEE_STATUS_IRQ_VEC_SHIFT (0U)BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)BEE_STATUS_BEE_IDLE_MASK (0x100U)BEE_STATUS_BEE_IDLE_SHIFT (8U)BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)BEE_BASE (0x403EC000u)BEE ((BEE_Type *)BEE_BASE)BEE_BASE_ADDRS { BEE_BASE }BEE_BASE_PTRS { BEE }CAN_MCR_MAXMB_MASK (0x7FU)CAN_MCR_MAXMB_SHIFT (0U)CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)CAN_MCR_IDAM_MASK (0x300U)CAN_MCR_IDAM_SHIFT (8U)CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)CAN_MCR_AEN_MASK (0x1000U)CAN_MCR_AEN_SHIFT (12U)CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)CAN_MCR_LPRIOEN_MASK (0x2000U)CAN_MCR_LPRIOEN_SHIFT (13U)CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)CAN_MCR_IRMQ_MASK (0x10000U)CAN_MCR_IRMQ_SHIFT (16U)CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)CAN_MCR_SRXDIS_MASK (0x20000U)CAN_MCR_SRXDIS_SHIFT (17U)CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)CAN_MCR_WAKSRC_MASK (0x80000U)CAN_MCR_WAKSRC_SHIFT (19U)CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)CAN_MCR_LPMACK_MASK (0x100000U)CAN_MCR_LPMACK_SHIFT (20U)CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)CAN_MCR_WRNEN_MASK (0x200000U)CAN_MCR_WRNEN_SHIFT (21U)CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)CAN_MCR_SLFWAK_MASK (0x400000U)CAN_MCR_SLFWAK_SHIFT (22U)CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)CAN_MCR_SUPV_MASK (0x800000U)CAN_MCR_SUPV_SHIFT (23U)CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)CAN_MCR_FRZACK_MASK (0x1000000U)CAN_MCR_FRZACK_SHIFT (24U)CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)CAN_MCR_SOFTRST_MASK (0x2000000U)CAN_MCR_SOFTRST_SHIFT (25U)CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)CAN_MCR_WAKMSK_MASK (0x4000000U)CAN_MCR_WAKMSK_SHIFT (26U)CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)CAN_MCR_NOTRDY_MASK (0x8000000U)CAN_MCR_NOTRDY_SHIFT (27U)CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)CAN_MCR_HALT_MASK (0x10000000U)CAN_MCR_HALT_SHIFT (28U)CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)CAN_MCR_RFEN_MASK (0x20000000U)CAN_MCR_RFEN_SHIFT (29U)CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)CAN_MCR_FRZ_MASK (0x40000000U)CAN_MCR_FRZ_SHIFT (30U)CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)CAN_MCR_MDIS_MASK (0x80000000U)CAN_MCR_MDIS_SHIFT (31U)CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)CAN_CTRL1_PROPSEG_MASK (0x7U)CAN_CTRL1_PROPSEG_SHIFT (0U)CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)CAN_CTRL1_LOM_MASK (0x8U)CAN_CTRL1_LOM_SHIFT (3U)CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)CAN_CTRL1_LBUF_MASK (0x10U)CAN_CTRL1_LBUF_SHIFT (4U)CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)CAN_CTRL1_TSYN_MASK (0x20U)CAN_CTRL1_TSYN_SHIFT (5U)CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)CAN_CTRL1_BOFFREC_MASK (0x40U)CAN_CTRL1_BOFFREC_SHIFT (6U)CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)CAN_CTRL1_SMP_MASK (0x80U)CAN_CTRL1_SMP_SHIFT (7U)CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)CAN_CTRL1_RWRNMSK_MASK (0x400U)CAN_CTRL1_RWRNMSK_SHIFT (10U)CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)CAN_CTRL1_TWRNMSK_MASK (0x800U)CAN_CTRL1_TWRNMSK_SHIFT (11U)CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)CAN_CTRL1_LPB_MASK (0x1000U)CAN_CTRL1_LPB_SHIFT (12U)CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)CAN_CTRL1_ERRMSK_MASK (0x4000U)CAN_CTRL1_ERRMSK_SHIFT (14U)CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)CAN_CTRL1_BOFFMSK_MASK (0x8000U)CAN_CTRL1_BOFFMSK_SHIFT (15U)CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)CAN_CTRL1_PSEG2_MASK (0x70000U)CAN_CTRL1_PSEG2_SHIFT (16U)CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)CAN_CTRL1_PSEG1_MASK (0x380000U)CAN_CTRL1_PSEG1_SHIFT (19U)CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)CAN_CTRL1_RJW_MASK (0xC00000U)CAN_CTRL1_RJW_SHIFT (22U)CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)CAN_CTRL1_PRESDIV_MASK (0xFF000000U)CAN_CTRL1_PRESDIV_SHIFT (24U)CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)CAN_TIMER_TIMER_MASK (0xFFFFU)CAN_TIMER_TIMER_SHIFT (0U)CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)CAN_RXMGMASK_MG_SHIFT (0U)CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)CAN_RX14MASK_RX14M_SHIFT (0U)CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)CAN_RX15MASK_RX15M_SHIFT (0U)CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)CAN_ESR1_WAKINT_MASK (0x1U)CAN_ESR1_WAKINT_SHIFT (0U)CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)CAN_ESR1_ERRINT_MASK (0x2U)CAN_ESR1_ERRINT_SHIFT (1U)CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)CAN_ESR1_BOFFINT_MASK (0x4U)CAN_ESR1_BOFFINT_SHIFT (2U)CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)CAN_ESR1_RX_MASK (0x8U)CAN_ESR1_RX_SHIFT (3U)CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)CAN_ESR1_FLTCONF_MASK (0x30U)CAN_ESR1_FLTCONF_SHIFT (4U)CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)CAN_ESR1_TX_MASK (0x40U)CAN_ESR1_TX_SHIFT (6U)CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)CAN_ESR1_IDLE_MASK (0x80U)CAN_ESR1_IDLE_SHIFT (7U)CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)CAN_ESR1_RXWRN_MASK (0x100U)CAN_ESR1_RXWRN_SHIFT (8U)CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)CAN_ESR1_TXWRN_MASK (0x200U)CAN_ESR1_TXWRN_SHIFT (9U)CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)CAN_ESR1_STFERR_MASK (0x400U)CAN_ESR1_STFERR_SHIFT (10U)CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)CAN_ESR1_FRMERR_MASK (0x800U)CAN_ESR1_FRMERR_SHIFT (11U)CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)CAN_ESR1_CRCERR_MASK (0x1000U)CAN_ESR1_CRCERR_SHIFT (12U)CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)CAN_ESR1_ACKERR_MASK (0x2000U)CAN_ESR1_ACKERR_SHIFT (13U)CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)CAN_ESR1_BIT0ERR_MASK (0x4000U)CAN_ESR1_BIT0ERR_SHIFT (14U)CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)CAN_ESR1_BIT1ERR_MASK (0x8000U)CAN_ESR1_BIT1ERR_SHIFT (15U)CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)CAN_ESR1_RWRNINT_MASK (0x10000U)CAN_ESR1_RWRNINT_SHIFT (16U)CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)CAN_ESR1_TWRNINT_MASK (0x20000U)CAN_ESR1_TWRNINT_SHIFT (17U)CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)CAN_ESR1_SYNCH_MASK (0x40000U)CAN_ESR1_SYNCH_SHIFT (18U)CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)CAN_IMASK2_BUFHM_SHIFT (0U)CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)CAN_IMASK1_BUFLM_SHIFT (0U)CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)CAN_IFLAG2_BUFHI_SHIFT (0U)CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)CAN_IFLAG1_BUF4TO0I_SHIFT (0U)CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)CAN_IFLAG1_BUF5I_MASK (0x20U)CAN_IFLAG1_BUF5I_SHIFT (5U)CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)CAN_IFLAG1_BUF6I_MASK (0x40U)CAN_IFLAG1_BUF6I_SHIFT (6U)CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)CAN_IFLAG1_BUF7I_MASK (0x80U)CAN_IFLAG1_BUF7I_SHIFT (7U)CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)CAN_IFLAG1_BUF31TO8I_SHIFT (8U)CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)CAN_CTRL2_EACEN_MASK (0x10000U)CAN_CTRL2_EACEN_SHIFT (16U)CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)CAN_CTRL2_RRS_MASK (0x20000U)CAN_CTRL2_RRS_SHIFT (17U)CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)CAN_CTRL2_MRP_MASK (0x40000U)CAN_CTRL2_MRP_SHIFT (18U)CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)CAN_CTRL2_TASD_MASK (0xF80000U)CAN_CTRL2_TASD_SHIFT (19U)CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)CAN_CTRL2_RFFN_MASK (0xF000000U)CAN_CTRL2_RFFN_SHIFT (24U)CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)CAN_CTRL2_WRMFRZ_MASK (0x10000000U)CAN_CTRL2_WRMFRZ_SHIFT (28U)CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)CAN_ESR2_IMB_MASK (0x2000U)CAN_ESR2_IMB_SHIFT (13U)CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)CAN_ESR2_VPS_MASK (0x4000U)CAN_ESR2_VPS_SHIFT (14U)CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)CAN_ESR2_LPTM_MASK (0x7F0000U)CAN_ESR2_LPTM_SHIFT (16U)CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)CAN_CRCR_TXCRC_MASK (0x7FFFU)CAN_CRCR_TXCRC_SHIFT (0U)CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)CAN_CRCR_MBCRC_MASK (0x7F0000U)CAN_CRCR_MBCRC_SHIFT (16U)CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)CAN_RXFGMASK_FGM_SHIFT (0U)CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)CAN_RXFIR_IDHIT_MASK (0x1FFU)CAN_RXFIR_IDHIT_SHIFT (0U)CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)CAN_CS_TIME_STAMP_MASK (0xFFFFU)CAN_CS_TIME_STAMP_SHIFT (0U)CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)CAN_CS_DLC_MASK (0xF0000U)CAN_CS_DLC_SHIFT (16U)CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)CAN_CS_RTR_MASK (0x100000U)CAN_CS_RTR_SHIFT (20U)CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)CAN_CS_IDE_MASK (0x200000U)CAN_CS_IDE_SHIFT (21U)CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)CAN_CS_SRR_MASK (0x400000U)CAN_CS_SRR_SHIFT (22U)CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)CAN_CS_CODE_MASK (0xF000000U)CAN_CS_CODE_SHIFT (24U)CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)CAN_CS_COUNT (64U)CAN_ID_EXT_MASK (0x3FFFFU)CAN_ID_EXT_SHIFT (0U)CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)CAN_ID_STD_MASK (0x1FFC0000U)CAN_ID_STD_SHIFT (18U)CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)CAN_ID_PRIO_MASK (0xE0000000U)CAN_ID_PRIO_SHIFT (29U)CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)CAN_ID_COUNT (64U)CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)CAN_WORD0_DATA_BYTE_3_SHIFT (0U)CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)CAN_WORD0_DATA_BYTE_2_SHIFT (8U)CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)CAN_WORD0_DATA_BYTE_1_SHIFT (16U)CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)CAN_WORD0_DATA_BYTE_0_SHIFT (24U)CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)CAN_WORD0_COUNT (64U)CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)CAN_WORD1_DATA_BYTE_7_SHIFT (0U)CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)CAN_WORD1_DATA_BYTE_6_SHIFT (8U)CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)CAN_WORD1_DATA_BYTE_5_SHIFT (16U)CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)CAN_WORD1_DATA_BYTE_4_SHIFT (24U)CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)CAN_WORD1_COUNT (64U)CAN_RXIMR_MI_MASK (0xFFFFFFFFU)CAN_RXIMR_MI_SHIFT (0U)CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)CAN_RXIMR_COUNT (64U)CAN_GFWR_GFWR_MASK (0xFFU)CAN_GFWR_GFWR_SHIFT (0U)CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)CAN1_BASE (0x401D0000u)CAN1 ((CAN_Type *)CAN1_BASE)CAN2_BASE (0x401D4000u)CAN2 ((CAN_Type *)CAN2_BASE)CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASKCAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFTCAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASKCAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFTCAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)CCM_CCR_OSCNT_MASK (0xFFU)CCM_CCR_OSCNT_SHIFT (0U)CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)CCM_CCR_COSC_EN_MASK (0x1000U)CCM_CCR_COSC_EN_SHIFT (12U)CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)CCM_CCR_RBC_EN_MASK (0x8000000U)CCM_CCR_RBC_EN_SHIFT (27U)CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)CCM_CSR_REF_EN_B_MASK (0x1U)CCM_CSR_REF_EN_B_SHIFT (0U)CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)CCM_CSR_CAMP2_READY_MASK (0x8U)CCM_CSR_CAMP2_READY_SHIFT (3U)CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)CCM_CSR_COSC_READY_MASK (0x20U)CCM_CSR_COSC_READY_SHIFT (5U)CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)CCM_CACRR_ARM_PODF_MASK (0x7U)CCM_CACRR_ARM_PODF_SHIFT (0U)CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)CCM_CBCDR_IPG_PODF_MASK (0x300U)CCM_CBCDR_IPG_PODF_SHIFT (8U)CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)CCM_CBCDR_AHB_PODF_MASK (0x1C00U)CCM_CBCDR_AHB_PODF_SHIFT (10U)CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)CCM_CBCDR_SEMC_PODF_MASK (0x70000U)CCM_CBCDR_SEMC_PODF_SHIFT (16U)CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)CCM_CBCMR_LCDIF_PODF_SHIFT (23U)CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)CCM_CBCMR_LPSPI_PODF_SHIFT (26U)CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)CCM_CSCDR1_TRACE_PODF_MASK (0xE000000U)CCM_CSCDR1_TRACE_PODF_SHIFT (25U)CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0xE00U)CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9U)CCM_CSCDR2_LCDIF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_CLK_SEL_MASK)CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)CCM_CSCDR3_CSI_PODF_MASK (0x3800U)CCM_CSCDR3_CSI_PODF_SHIFT (11U)CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)CCM_CLPCR_LPM_MASK (0x3U)CCM_CLPCR_LPM_SHIFT (0U)CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)CCM_CLPCR_SBYOS_MASK (0x40U)CCM_CLPCR_SBYOS_SHIFT (6U)CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)CCM_CLPCR_VSTBY_MASK (0x100U)CCM_CLPCR_VSTBY_SHIFT (8U)CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)CCM_CLPCR_STBY_COUNT_MASK (0x600U)CCM_CLPCR_STBY_COUNT_SHIFT (9U)CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)CCM_CISR_LRF_PLL_MASK (0x1U)CCM_CISR_LRF_PLL_SHIFT (0U)CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)CCM_CISR_COSC_READY_MASK (0x40U)CCM_CISR_COSC_READY_SHIFT (6U)CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)CCM_CIMR_MASK_COSC_READY_MASK (0x40U)CCM_CIMR_MASK_COSC_READY_SHIFT (6U)CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)CCM_CCOSR_CLKO1_SEL_MASK (0xFU)CCM_CCOSR_CLKO1_SEL_SHIFT (0U)CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)CCM_CCOSR_CLKO1_DIV_MASK (0x70U)CCM_CCOSR_CLKO1_DIV_SHIFT (4U)CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)CCM_CCOSR_CLKO1_EN_MASK (0x80U)CCM_CCOSR_CLKO1_EN_SHIFT (7U)CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)CCM_CCOSR_CLKO2_SEL_SHIFT (16U)CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)CCM_CCOSR_CLKO2_DIV_SHIFT (21U)CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)CCM_CCOSR_CLKO2_EN_SHIFT (24U)CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)CCM_CGPR_FPL_MASK (0x10000U)CCM_CGPR_FPL_SHIFT (16U)CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)CCM_CCGR0_CG0_MASK (0x3U)CCM_CCGR0_CG0_SHIFT (0U)CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)CCM_CCGR0_CG1_MASK (0xCU)CCM_CCGR0_CG1_SHIFT (2U)CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)CCM_CCGR0_CG2_MASK (0x30U)CCM_CCGR0_CG2_SHIFT (4U)CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)CCM_CCGR0_CG3_MASK (0xC0U)CCM_CCGR0_CG3_SHIFT (6U)CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)CCM_CCGR0_CG4_MASK (0x300U)CCM_CCGR0_CG4_SHIFT (8U)CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)CCM_CCGR0_CG5_MASK (0xC00U)CCM_CCGR0_CG5_SHIFT (10U)CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)CCM_CCGR0_CG6_MASK (0x3000U)CCM_CCGR0_CG6_SHIFT (12U)CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)CCM_CCGR0_CG7_MASK (0xC000U)CCM_CCGR0_CG7_SHIFT (14U)CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)CCM_CCGR0_CG8_MASK (0x30000U)CCM_CCGR0_CG8_SHIFT (16U)CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)CCM_CCGR0_CG9_MASK (0xC0000U)CCM_CCGR0_CG9_SHIFT (18U)CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)CCM_CCGR0_CG10_MASK (0x300000U)CCM_CCGR0_CG10_SHIFT (20U)CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)CCM_CCGR0_CG11_MASK (0xC00000U)CCM_CCGR0_CG11_SHIFT (22U)CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)CCM_CCGR0_CG12_MASK (0x3000000U)CCM_CCGR0_CG12_SHIFT (24U)CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)CCM_CCGR0_CG13_MASK (0xC000000U)CCM_CCGR0_CG13_SHIFT (26U)CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)CCM_CCGR0_CG14_MASK (0x30000000U)CCM_CCGR0_CG14_SHIFT (28U)CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)CCM_CCGR0_CG15_MASK (0xC0000000U)CCM_CCGR0_CG15_SHIFT (30U)CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)CCM_CCGR1_CG0_MASK (0x3U)CCM_CCGR1_CG0_SHIFT (0U)CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)CCM_CCGR1_CG1_MASK (0xCU)CCM_CCGR1_CG1_SHIFT (2U)CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)CCM_CCGR1_CG2_MASK (0x30U)CCM_CCGR1_CG2_SHIFT (4U)CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)CCM_CCGR1_CG3_MASK (0xC0U)CCM_CCGR1_CG3_SHIFT (6U)CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)CCM_CCGR1_CG4_MASK (0x300U)CCM_CCGR1_CG4_SHIFT (8U)CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)CCM_CCGR1_CG5_MASK (0xC00U)CCM_CCGR1_CG5_SHIFT (10U)CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)CCM_CCGR1_CG6_MASK (0x3000U)CCM_CCGR1_CG6_SHIFT (12U)CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)CCM_CCGR1_CG7_MASK (0xC000U)CCM_CCGR1_CG7_SHIFT (14U)CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)CCM_CCGR1_CG8_MASK (0x30000U)CCM_CCGR1_CG8_SHIFT (16U)CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)CCM_CCGR1_CG9_MASK (0xC0000U)CCM_CCGR1_CG9_SHIFT (18U)CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)CCM_CCGR1_CG10_MASK (0x300000U)CCM_CCGR1_CG10_SHIFT (20U)CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)CCM_CCGR1_CG11_MASK (0xC00000U)CCM_CCGR1_CG11_SHIFT (22U)CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)CCM_CCGR1_CG12_MASK (0x3000000U)CCM_CCGR1_CG12_SHIFT (24U)CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)CCM_CCGR1_CG13_MASK (0xC000000U)CCM_CCGR1_CG13_SHIFT (26U)CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)CCM_CCGR1_CG14_MASK (0x30000000U)CCM_CCGR1_CG14_SHIFT (28U)CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)CCM_CCGR1_CG15_MASK (0xC0000000U)CCM_CCGR1_CG15_SHIFT (30U)CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)CCM_CCGR2_CG0_MASK (0x3U)CCM_CCGR2_CG0_SHIFT (0U)CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)CCM_CCGR2_CG1_MASK (0xCU)CCM_CCGR2_CG1_SHIFT (2U)CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)CCM_CCGR2_CG2_MASK (0x30U)CCM_CCGR2_CG2_SHIFT (4U)CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)CCM_CCGR2_CG3_MASK (0xC0U)CCM_CCGR2_CG3_SHIFT (6U)CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)CCM_CCGR2_CG4_MASK (0x300U)CCM_CCGR2_CG4_SHIFT (8U)CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)CCM_CCGR2_CG5_MASK (0xC00U)CCM_CCGR2_CG5_SHIFT (10U)CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)CCM_CCGR2_CG6_MASK (0x3000U)CCM_CCGR2_CG6_SHIFT (12U)CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)CCM_CCGR2_CG7_MASK (0xC000U)CCM_CCGR2_CG7_SHIFT (14U)CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)CCM_CCGR2_CG8_MASK (0x30000U)CCM_CCGR2_CG8_SHIFT (16U)CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)CCM_CCGR2_CG9_MASK (0xC0000U)CCM_CCGR2_CG9_SHIFT (18U)CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)CCM_CCGR2_CG10_MASK (0x300000U)CCM_CCGR2_CG10_SHIFT (20U)CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)CCM_CCGR2_CG11_MASK (0xC00000U)CCM_CCGR2_CG11_SHIFT (22U)CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)CCM_CCGR2_CG12_MASK (0x3000000U)CCM_CCGR2_CG12_SHIFT (24U)CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)CCM_CCGR2_CG13_MASK (0xC000000U)CCM_CCGR2_CG13_SHIFT (26U)CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)CCM_CCGR2_CG14_MASK (0x30000000U)CCM_CCGR2_CG14_SHIFT (28U)CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)CCM_CCGR2_CG15_MASK (0xC0000000U)CCM_CCGR2_CG15_SHIFT (30U)CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)CCM_CCGR3_CG0_MASK (0x3U)CCM_CCGR3_CG0_SHIFT (0U)CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)CCM_CCGR3_CG1_MASK (0xCU)CCM_CCGR3_CG1_SHIFT (2U)CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)CCM_CCGR3_CG2_MASK (0x30U)CCM_CCGR3_CG2_SHIFT (4U)CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)CCM_CCGR3_CG3_MASK (0xC0U)CCM_CCGR3_CG3_SHIFT (6U)CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)CCM_CCGR3_CG4_MASK (0x300U)CCM_CCGR3_CG4_SHIFT (8U)CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)CCM_CCGR3_CG5_MASK (0xC00U)CCM_CCGR3_CG5_SHIFT (10U)CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)CCM_CCGR3_CG6_MASK (0x3000U)CCM_CCGR3_CG6_SHIFT (12U)CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)CCM_CCGR3_CG7_MASK (0xC000U)CCM_CCGR3_CG7_SHIFT (14U)CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)CCM_CCGR3_CG8_MASK (0x30000U)CCM_CCGR3_CG8_SHIFT (16U)CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)CCM_CCGR3_CG9_MASK (0xC0000U)CCM_CCGR3_CG9_SHIFT (18U)CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)CCM_CCGR3_CG10_MASK (0x300000U)CCM_CCGR3_CG10_SHIFT (20U)CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)CCM_CCGR3_CG11_MASK (0xC00000U)CCM_CCGR3_CG11_SHIFT (22U)CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)CCM_CCGR3_CG12_MASK (0x3000000U)CCM_CCGR3_CG12_SHIFT (24U)CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)CCM_CCGR3_CG13_MASK (0xC000000U)CCM_CCGR3_CG13_SHIFT (26U)CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)CCM_CCGR3_CG14_MASK (0x30000000U)CCM_CCGR3_CG14_SHIFT (28U)CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)CCM_CCGR3_CG15_MASK (0xC0000000U)CCM_CCGR3_CG15_SHIFT (30U)CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)CCM_CCGR4_CG0_MASK (0x3U)CCM_CCGR4_CG0_SHIFT (0U)CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)CCM_CCGR4_CG1_MASK (0xCU)CCM_CCGR4_CG1_SHIFT (2U)CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)CCM_CCGR4_CG2_MASK (0x30U)CCM_CCGR4_CG2_SHIFT (4U)CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)CCM_CCGR4_CG3_MASK (0xC0U)CCM_CCGR4_CG3_SHIFT (6U)CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)CCM_CCGR4_CG4_MASK (0x300U)CCM_CCGR4_CG4_SHIFT (8U)CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)CCM_CCGR4_CG5_MASK (0xC00U)CCM_CCGR4_CG5_SHIFT (10U)CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)CCM_CCGR4_CG6_MASK (0x3000U)CCM_CCGR4_CG6_SHIFT (12U)CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)CCM_CCGR4_CG7_MASK (0xC000U)CCM_CCGR4_CG7_SHIFT (14U)CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)CCM_CCGR4_CG8_MASK (0x30000U)CCM_CCGR4_CG8_SHIFT (16U)CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)CCM_CCGR4_CG9_MASK (0xC0000U)CCM_CCGR4_CG9_SHIFT (18U)CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)CCM_CCGR4_CG10_MASK (0x300000U)CCM_CCGR4_CG10_SHIFT (20U)CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)CCM_CCGR4_CG11_MASK (0xC00000U)CCM_CCGR4_CG11_SHIFT (22U)CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)CCM_CCGR4_CG12_MASK (0x3000000U)CCM_CCGR4_CG12_SHIFT (24U)CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)CCM_CCGR4_CG13_MASK (0xC000000U)CCM_CCGR4_CG13_SHIFT (26U)CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)CCM_CCGR4_CG14_MASK (0x30000000U)CCM_CCGR4_CG14_SHIFT (28U)CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)CCM_CCGR4_CG15_MASK (0xC0000000U)CCM_CCGR4_CG15_SHIFT (30U)CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)CCM_CCGR5_CG0_MASK (0x3U)CCM_CCGR5_CG0_SHIFT (0U)CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)CCM_CCGR5_CG1_MASK (0xCU)CCM_CCGR5_CG1_SHIFT (2U)CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)CCM_CCGR5_CG2_MASK (0x30U)CCM_CCGR5_CG2_SHIFT (4U)CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)CCM_CCGR5_CG3_MASK (0xC0U)CCM_CCGR5_CG3_SHIFT (6U)CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)CCM_CCGR5_CG4_MASK (0x300U)CCM_CCGR5_CG4_SHIFT (8U)CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)CCM_CCGR5_CG5_MASK (0xC00U)CCM_CCGR5_CG5_SHIFT (10U)CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)CCM_CCGR5_CG6_MASK (0x3000U)CCM_CCGR5_CG6_SHIFT (12U)CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)CCM_CCGR5_CG7_MASK (0xC000U)CCM_CCGR5_CG7_SHIFT (14U)CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)CCM_CCGR5_CG8_MASK (0x30000U)CCM_CCGR5_CG8_SHIFT (16U)CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)CCM_CCGR5_CG9_MASK (0xC0000U)CCM_CCGR5_CG9_SHIFT (18U)CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)CCM_CCGR5_CG10_MASK (0x300000U)CCM_CCGR5_CG10_SHIFT (20U)CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)CCM_CCGR5_CG11_MASK (0xC00000U)CCM_CCGR5_CG11_SHIFT (22U)CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)CCM_CCGR5_CG12_MASK (0x3000000U)CCM_CCGR5_CG12_SHIFT (24U)CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)CCM_CCGR5_CG13_MASK (0xC000000U)CCM_CCGR5_CG13_SHIFT (26U)CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)CCM_CCGR5_CG14_MASK (0x30000000U)CCM_CCGR5_CG14_SHIFT (28U)CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)CCM_CCGR5_CG15_MASK (0xC0000000U)CCM_CCGR5_CG15_SHIFT (30U)CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)CCM_CCGR6_CG0_MASK (0x3U)CCM_CCGR6_CG0_SHIFT (0U)CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)CCM_CCGR6_CG1_MASK (0xCU)CCM_CCGR6_CG1_SHIFT (2U)CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)CCM_CCGR6_CG2_MASK (0x30U)CCM_CCGR6_CG2_SHIFT (4U)CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)CCM_CCGR6_CG3_MASK (0xC0U)CCM_CCGR6_CG3_SHIFT (6U)CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)CCM_CCGR6_CG4_MASK (0x300U)CCM_CCGR6_CG4_SHIFT (8U)CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)CCM_CCGR6_CG5_MASK (0xC00U)CCM_CCGR6_CG5_SHIFT (10U)CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)CCM_CCGR6_CG6_MASK (0x3000U)CCM_CCGR6_CG6_SHIFT (12U)CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)CCM_CCGR6_CG7_MASK (0xC000U)CCM_CCGR6_CG7_SHIFT (14U)CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)CCM_CCGR6_CG8_MASK (0x30000U)CCM_CCGR6_CG8_SHIFT (16U)CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)CCM_CCGR6_CG9_MASK (0xC0000U)CCM_CCGR6_CG9_SHIFT (18U)CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)CCM_CCGR6_CG10_MASK (0x300000U)CCM_CCGR6_CG10_SHIFT (20U)CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)CCM_CCGR6_CG11_MASK (0xC00000U)CCM_CCGR6_CG11_SHIFT (22U)CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)CCM_CCGR6_CG12_MASK (0x3000000U)CCM_CCGR6_CG12_SHIFT (24U)CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)CCM_CCGR6_CG13_MASK (0xC000000U)CCM_CCGR6_CG13_SHIFT (26U)CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)CCM_CCGR6_CG14_MASK (0x30000000U)CCM_CCGR6_CG14_SHIFT (28U)CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)CCM_CCGR6_CG15_MASK (0xC0000000U)CCM_CCGR6_CG15_SHIFT (30U)CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)CCM_BASE (0x400FC000u)CCM ((CCM_Type *)CCM_BASE)CCM_BASE_ADDRS { CCM_BASE }CCM_BASE_PTRS { CCM }CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U)CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U)CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK)CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)!CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)!CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)!CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)!CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)!CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)!CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)!CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)!CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)!CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)!CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)!CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)!CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)!CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)!CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)!CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)!CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)!CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)!CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)!CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)!CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)!CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)!CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)!CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)!CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)!CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)!CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)!CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)!CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)!CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)!CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)!CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)!CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)!CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)!CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)!CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)!CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)!CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)!CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)!CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)!CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)!CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)!CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U)!CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U)!CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)!CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)!CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)!CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)!CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)"CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)"CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)"CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)"CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)"CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)"CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)"CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)"CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U)"CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U)"CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)"CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)"CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)"CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)"CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)"CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)"CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)"CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)"CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)"CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)"CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)"CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)"CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U)"CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U)"CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU)"CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U)"CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)"CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)"CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)"CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U)"CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U)"CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)"CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)"CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)"CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)"CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)"CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)"CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U)"CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U)"CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK)"CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U)"CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U)"CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK)"CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U)"CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U)"CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)"CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)"CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)"CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)"CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)"CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U)"CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U)"CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU)"CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U)"CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)"CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)"CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U)"CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U)"CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)"CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)"CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)"CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)"CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)"CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)"CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U)"CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U)"CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK)"CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U)"CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U)"CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U)"CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U)"CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)"CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)"CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)"CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)"CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)"CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)"CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U)"CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U)"CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU)"CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U)"CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK)"CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)"CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)"CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)"CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U)"CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U)"CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)"CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)"CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)"CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U)#CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U)#CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK)#CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U)#CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U)#CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK)#CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U)#CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U)#CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK)#CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)#CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)#CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)#CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)#CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)#CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U)#CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U)#CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU)#CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U)#CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK)#CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)#CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)#CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U)#CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U)#CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)#CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)#CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)#CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U)#CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U)#CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U)#CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U)#CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U)#CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U)#CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK)#CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)#CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)#CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)#CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)#CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)#CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)#CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)#CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)#CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)#CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)#CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)#CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)#CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)#CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)#CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)#CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)#CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)#CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)#CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)#CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)#CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)#CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)#CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)#CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)#CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)#CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)#CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)#CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)#CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)#CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)#CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)#CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)#CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)#CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)#CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)#CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)#CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)#CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)#CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)#CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)#CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)#CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)#CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)#CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)#CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)#CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)#CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)#CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)#CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)#CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)#CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)#CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)#CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)#CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)#CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)#CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)#CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)#CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)#CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)#CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)#CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)#CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)#CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)#CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)#CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)#CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)#CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)#CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)#CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)#CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)#CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)#CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)#CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)#CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)#CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)#CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)#CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)#CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)#CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)$CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)$CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)$CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)$CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)$CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)$CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)$CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)$CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)$CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)$CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)$CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)$CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)$CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)$CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)$CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)$CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)$CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)$CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)$CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)$CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)$CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)$CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)$CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)$CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)$CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)$CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)$CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)$CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)$CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)$CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)$CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)$CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)$CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)$CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)$CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)$CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)$CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)$CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)$CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)$CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)$CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)$CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)$CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)$CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)$CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)$CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)$CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)$CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)$CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)$CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)$CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)$CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)$CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)$CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)$CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)$CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)$CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)$CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)$CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)$CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)$CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)$CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)$CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)$CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)$CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)$CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)$CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)$CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)$CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)$CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)$CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)$CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)$CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)$CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)$CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)$CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)$CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)$CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)$CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)$CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)$CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)$CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)$CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)$CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)$CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)$CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)$CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)$CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)$CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)$CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)$CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)$CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)$CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)$CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)$CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)$CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)$CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)$CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)$CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)$CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)$CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)$CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)$CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)$CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)$CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)$CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)$CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)$CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)$CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)%CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)%CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)%CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)%CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)%CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)%CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)%CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)%CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)%CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)%CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)%CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)%CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)%CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)%CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)%CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)%CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)%CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)%CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)%CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)%CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)%CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)%CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)%CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)%CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)%CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)%CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)%CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)%CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)%CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)%CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)%CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)%CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)%CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)%CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)%CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)%CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)%CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)%CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)%CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)%CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)%CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)%CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)%CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)%CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)%CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)%CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)%CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)%CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)%CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)%CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)%CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)%CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)%CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)%CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)%CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)%CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)%CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)%CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)%CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)%CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)%CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)%CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)%CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)%CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)%CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)%CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)%CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)%CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)%CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)%CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)%CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)%CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)%CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)%CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)%CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)%CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)%CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)%CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)%CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)%CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)%CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)%CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)%CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)%CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)%CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)%CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)%CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)%CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)%CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)%CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)%CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)%CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)%CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)%CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)%CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)%CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)%CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)%CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)%CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)%CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)%CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)%CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)%CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)%CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)%CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)%CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)%CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)%CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)&CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)&CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)&CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)&CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)&CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)&CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)&CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)&CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)&CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)&CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)&CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)&CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U)&CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK)&CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)&CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)&CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)&CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)&CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)&CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)&CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)&CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)&CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)&CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)&CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)&CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)&CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)&CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)&CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)&CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)&CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)&CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)&CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)&CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)&CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)&CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)&CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)&CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)&CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)&CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)&CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)&CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)&CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)&CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)&CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)&CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)&CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)&CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)&CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)&CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)&CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)&CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK)&CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)&CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)&CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)&CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)&CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)&CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)&CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)&CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)&CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)&CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)&CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)&CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)&CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)&CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)&CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)&CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)&CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)&CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)&CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)&CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)&CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)&CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)&CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)&CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)&CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)&CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)&CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)&CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)&CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)&CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)&CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)&CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK)&CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)&CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)&CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)&CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)&CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)&CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)&CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)&CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)&CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)&CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)&CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)&CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)&CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)&CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)&CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)&CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)&CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)&CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)&CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)&CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)'CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)'CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)'CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)'CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)'CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)'CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)'CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)'CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)'CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)'CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)'CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)'CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)'CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)'CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)'CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)'CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)'CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK)'CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)'CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)'CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)'CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)'CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)'CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)'CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)'CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)'CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)'CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)'CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)'CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)'CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)'CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)'CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)'CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)'CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)'CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)'CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)'CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)'CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)'CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)'CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)'CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)'CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)'CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)'CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)'CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)'CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)'CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)'CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)'CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)'CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)'CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)'CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)'CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)'CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)'CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)'CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)'CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)'CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)'CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)'CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)'CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)'CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)'CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)'CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)'CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)'CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)'CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)'CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)'CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)'CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)'CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)'CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)'CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)'CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)'CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)'CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)'CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)'CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)'CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)'CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)'CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)'CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)'CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)'CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)'CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)'CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)'CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)'CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)'CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)'CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)'CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)(CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)(CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)(CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)(CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)(CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)(CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)(CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)(CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)(CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)(CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)(CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)(CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)(CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)(CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)(CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)(CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)(CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)(CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)(CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U)(CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U)(CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)(CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)(CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)(CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)(CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)(CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)(CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)(CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)(CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)(CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)(CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)(CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)(CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)(CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)(CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)(CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)(CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)(CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)(CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)(CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)(CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)(CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)(CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)(CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)(CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)(CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)(CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)(CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)(CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)(CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)(CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)(CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)(CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)(CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)(CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)(CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)(CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)(CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)(CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)(CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)(CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)(CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)(CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)(CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)(CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)(CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)(CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)(CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U)(CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U)(CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)(CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)(CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)(CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)(CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)(CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)(CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)(CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)(CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)(CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)(CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)(CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)(CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)(CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)(CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)(CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)(CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)(CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)(CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)(CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)(CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)(CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)(CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)(CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)(CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)(CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)(CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)(CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)(CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U))CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK))CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U))CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U))CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK))CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U))CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U))CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK))CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U))CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U))CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK))CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U))CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U))CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK))CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U))CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U))CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK))CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U))CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U))CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK))CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U))CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U))CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK))CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U))CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U))CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK))CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U))CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U))CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK))CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U))CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U))CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK))CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U))CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U))CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK))CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U))CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U))CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK))CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U))CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U))CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK))CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U))CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U))CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK))CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U))CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U))CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U))CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK))CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U))CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U))CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK))CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U))CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U))CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK))CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U))CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U))CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK))CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U))CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U))CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK))CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U))CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U))CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK))CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U))CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U))CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK))CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U))CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U))CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK))CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U))CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U))CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK))CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U))CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U))CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK))CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U))CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U))CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK))CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U))CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U))CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK))CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U))CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U))CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK))CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U))CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U))CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK))CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U))CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U))CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK))CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U))CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U))CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK))CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U))CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U))CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK))CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U))CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U))CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U))CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK))CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U))CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U))CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK))CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U))CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U))CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK))CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U))CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U))CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK))CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U))CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U))CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)*CCM_ANALOG_BASE (0x400D8000u)*CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)*CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }*CCM_ANALOG_BASE_PTRS { CCM_ANALOG }*CMP_CR0_HYSTCTR_MASK (0x3U)*CMP_CR0_HYSTCTR_SHIFT (0U)*CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)*CMP_CR0_FILTER_CNT_MASK (0x70U)*CMP_CR0_FILTER_CNT_SHIFT (4U)*CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)*CMP_CR1_EN_MASK (0x1U)*CMP_CR1_EN_SHIFT (0U)*CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)*CMP_CR1_OPE_MASK (0x2U)*CMP_CR1_OPE_SHIFT (1U)*CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)*CMP_CR1_COS_MASK (0x4U)*CMP_CR1_COS_SHIFT (2U)*CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)*CMP_CR1_INV_MASK (0x8U)*CMP_CR1_INV_SHIFT (3U)*CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)*CMP_CR1_PMODE_MASK (0x10U)*CMP_CR1_PMODE_SHIFT (4U)*CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)*CMP_CR1_WE_MASK (0x40U)*CMP_CR1_WE_SHIFT (6U)*CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)*CMP_CR1_SE_MASK (0x80U)*CMP_CR1_SE_SHIFT (7U)*CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)*CMP_FPR_FILT_PER_MASK (0xFFU)*CMP_FPR_FILT_PER_SHIFT (0U)*CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)*CMP_SCR_COUT_MASK (0x1U)*CMP_SCR_COUT_SHIFT (0U)*CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)*CMP_SCR_CFF_MASK (0x2U)*CMP_SCR_CFF_SHIFT (1U)*CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)*CMP_SCR_CFR_MASK (0x4U)*CMP_SCR_CFR_SHIFT (2U)*CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)*CMP_SCR_IEF_MASK (0x8U)*CMP_SCR_IEF_SHIFT (3U)*CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)*CMP_SCR_IER_MASK (0x10U)*CMP_SCR_IER_SHIFT (4U)*CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)*CMP_SCR_DMAEN_MASK (0x40U)*CMP_SCR_DMAEN_SHIFT (6U)*CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)*CMP_DACCR_VOSEL_MASK (0x3FU)*CMP_DACCR_VOSEL_SHIFT (0U)*CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)*CMP_DACCR_VRSEL_MASK (0x40U)*CMP_DACCR_VRSEL_SHIFT (6U)*CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)*CMP_DACCR_DACEN_MASK (0x80U)*CMP_DACCR_DACEN_SHIFT (7U)*CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)*CMP_MUXCR_MSEL_MASK (0x7U)*CMP_MUXCR_MSEL_SHIFT (0U)*CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)*CMP_MUXCR_PSEL_MASK (0x38U)*CMP_MUXCR_PSEL_SHIFT (3U)*CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)+CMP1_BASE (0x40094000u)+CMP1 ((CMP_Type *)CMP1_BASE)+CMP2_BASE (0x40094008u)+CMP2 ((CMP_Type *)CMP2_BASE)+CMP3_BASE (0x40094010u)+CMP3 ((CMP_Type *)CMP3_BASE)+CMP4_BASE (0x40094018u)+CMP4 ((CMP_Type *)CMP4_BASE)+CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }+CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }+CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }+CSI_CSICR1_PIXEL_BIT_MASK (0x1U)+CSI_CSICR1_PIXEL_BIT_SHIFT (0U)+CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)+CSI_CSICR1_REDGE_MASK (0x2U)+CSI_CSICR1_REDGE_SHIFT (1U)+CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)+CSI_CSICR1_INV_PCLK_MASK (0x4U)+CSI_CSICR1_INV_PCLK_SHIFT (2U)+CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)+CSI_CSICR1_INV_DATA_MASK (0x8U)+CSI_CSICR1_INV_DATA_SHIFT (3U)+CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)+CSI_CSICR1_GCLK_MODE_MASK (0x10U)+CSI_CSICR1_GCLK_MODE_SHIFT (4U)+CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)+CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)+CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)+CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)+CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)+CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)+CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)+CSI_CSICR1_PACK_DIR_MASK (0x80U)+CSI_CSICR1_PACK_DIR_SHIFT (7U)+CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)+CSI_CSICR1_FCC_MASK (0x100U)+CSI_CSICR1_FCC_SHIFT (8U)+CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)+CSI_CSICR1_CCIR_EN_MASK (0x400U)+CSI_CSICR1_CCIR_EN_SHIFT (10U)+CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)+CSI_CSICR1_HSYNC_POL_MASK (0x800U)+CSI_CSICR1_HSYNC_POL_SHIFT (11U)+CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)+CSI_CSICR1_SOF_INTEN_MASK (0x10000U)+CSI_CSICR1_SOF_INTEN_SHIFT (16U)+CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)+CSI_CSICR1_SOF_POL_MASK (0x20000U)+CSI_CSICR1_SOF_POL_SHIFT (17U)+CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)+CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)+CSI_CSICR1_RXFF_INTEN_SHIFT (18U)+CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)+CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)+CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)+CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)+CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)+CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)+CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)+CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)+CSI_CSICR1_STATFF_INTEN_SHIFT (21U)+CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)+CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)+CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)+CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)+CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)+CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)+CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)+CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)+CSI_CSICR1_SF_OR_INTEN_SHIFT (25U),CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK),CSI_CSICR1_COF_INT_EN_MASK (0x4000000U),CSI_CSICR1_COF_INT_EN_SHIFT (26U),CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK),CSI_CSICR1_CCIR_MODE_MASK (0x8000000U),CSI_CSICR1_CCIR_MODE_SHIFT (27U),CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK),CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U),CSI_CSICR1_PrP_IF_EN_SHIFT (28U),CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK),CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U),CSI_CSICR1_EOF_INT_EN_SHIFT (29U),CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK),CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U),CSI_CSICR1_EXT_VSYNC_SHIFT (30U),CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK),CSI_CSICR1_SWAP16_EN_MASK (0x80000000U),CSI_CSICR1_SWAP16_EN_SHIFT (31U),CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK),CSI_CSICR2_HSC_MASK (0xFFU),CSI_CSICR2_HSC_SHIFT (0U),CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK),CSI_CSICR2_VSC_MASK (0xFF00U),CSI_CSICR2_VSC_SHIFT (8U),CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK),CSI_CSICR2_LVRM_MASK (0x70000U),CSI_CSICR2_LVRM_SHIFT (16U),CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK),CSI_CSICR2_BTS_MASK (0x180000U),CSI_CSICR2_BTS_SHIFT (19U),CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK),CSI_CSICR2_SCE_MASK (0x800000U),CSI_CSICR2_SCE_SHIFT (23U),CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK),CSI_CSICR2_AFS_MASK (0x3000000U),CSI_CSICR2_AFS_SHIFT (24U),CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK),CSI_CSICR2_DRM_MASK (0x4000000U),CSI_CSICR2_DRM_SHIFT (26U),CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK),CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U),CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U),CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK),CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U),CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U),CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK),CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U),CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U),CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK),CSI_CSICR3_ECC_INT_EN_MASK (0x2U),CSI_CSICR3_ECC_INT_EN_SHIFT (1U),CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK),CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U),CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U),CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK),CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U),CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U),CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK),CSI_CSICR3_RxFF_LEVEL_MASK (0x70U),CSI_CSICR3_RxFF_LEVEL_SHIFT (4U),CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK),CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U),CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U),CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK),CSI_CSICR3_STATFF_LEVEL_MASK (0x700U),CSI_CSICR3_STATFF_LEVEL_SHIFT (8U),CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK),CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U),CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U),CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK),CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U),CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U),CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK),CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U),CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U),CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK),CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U),CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U),CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK),CSI_CSICR3_FRMCNT_RST_MASK (0x8000U),CSI_CSICR3_FRMCNT_RST_SHIFT (15U),CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK),CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U),CSI_CSICR3_FRMCNT_SHIFT (16U),CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK),CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU),CSI_CSISTATFIFO_STAT_SHIFT (0U),CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK),CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU),CSI_CSIRFIFO_IMAGE_SHIFT (0U),CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK),CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU),CSI_CSIRXCNT_RXCNT_SHIFT (0U),CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK),CSI_CSISR_DRDY_MASK (0x1U),CSI_CSISR_DRDY_SHIFT (0U),CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK),CSI_CSISR_ECC_INT_MASK (0x2U),CSI_CSISR_ECC_INT_SHIFT (1U),CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK),CSI_CSISR_HRESP_ERR_INT_MASK (0x80U),CSI_CSISR_HRESP_ERR_INT_SHIFT (7U),CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK),CSI_CSISR_COF_INT_MASK (0x2000U),CSI_CSISR_COF_INT_SHIFT (13U),CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK),CSI_CSISR_F1_INT_MASK (0x4000U),CSI_CSISR_F1_INT_SHIFT (14U),CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK),CSI_CSISR_F2_INT_MASK (0x8000U),CSI_CSISR_F2_INT_SHIFT (15U),CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK),CSI_CSISR_SOF_INT_MASK (0x10000U),CSI_CSISR_SOF_INT_SHIFT (16U),CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK),CSI_CSISR_EOF_INT_MASK (0x20000U)-CSI_CSISR_EOF_INT_SHIFT (17U)-CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)-CSI_CSISR_RxFF_INT_MASK (0x40000U)-CSI_CSISR_RxFF_INT_SHIFT (18U)-CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)-CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)-CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)-CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)-CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)-CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)-CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)-CSI_CSISR_STATFF_INT_MASK (0x200000U)-CSI_CSISR_STATFF_INT_SHIFT (21U)-CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)-CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)-CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)-CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)-CSI_CSISR_RF_OR_INT_MASK (0x1000000U)-CSI_CSISR_RF_OR_INT_SHIFT (24U)-CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)-CSI_CSISR_SF_OR_INT_MASK (0x2000000U)-CSI_CSISR_SF_OR_INT_SHIFT (25U)-CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)-CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)-CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)-CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)-CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)-CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)-CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)-CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)-CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)-CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)-CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)-CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)-CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)-CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)-CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)-CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)-CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)-CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)-CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)-CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)-CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)-CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)-CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)-CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)-CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)-CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)-CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)-CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)-CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)-CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)-CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)-CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)-CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)-CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)-CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)-CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)-CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)-CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)-CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)-CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)-CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)-CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)-CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)-CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)-CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)-CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)-CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)-CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)-CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)-CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)-CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)-CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)-CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)-CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)-CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)-CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)-CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)-CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)-CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)-CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)-CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)-CSI_CSICR18_AHB_HPROT_MASK (0xF000U)-CSI_CSICR18_AHB_HPROT_SHIFT (12U)-CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)-CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U)-CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U)-CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK)-CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)-CSI_CSICR18_MASK_OPTION_SHIFT (18U)-CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)-CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)-CSI_CSICR18_CSI_ENABLE_SHIFT (31U)-CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)-CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)-CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)-CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)-CSI_BASE (0x402BC000u)-CSI ((CSI_Type *)CSI_BASE)-CSI_BASE_ADDRS { CSI_BASE }.CSI_BASE_PTRS { CSI }.CSI_IRQS { CSI_IRQn }.CSU_CSL_SUR_S2_MASK (0x1U).CSU_CSL_SUR_S2_SHIFT (0U).CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK).CSU_CSL_SSR_S2_MASK (0x2U).CSU_CSL_SSR_S2_SHIFT (1U).CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK).CSU_CSL_NUR_S2_MASK (0x4U).CSU_CSL_NUR_S2_SHIFT (2U).CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK).CSU_CSL_NSR_S2_MASK (0x8U).CSU_CSL_NSR_S2_SHIFT (3U).CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK).CSU_CSL_SUW_S2_MASK (0x10U).CSU_CSL_SUW_S2_SHIFT (4U).CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK).CSU_CSL_SSW_S2_MASK (0x20U).CSU_CSL_SSW_S2_SHIFT (5U).CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK).CSU_CSL_NUW_S2_MASK (0x40U).CSU_CSL_NUW_S2_SHIFT (6U).CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK).CSU_CSL_NSW_S2_MASK (0x80U).CSU_CSL_NSW_S2_SHIFT (7U).CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK).CSU_CSL_LOCK_S2_MASK (0x100U).CSU_CSL_LOCK_S2_SHIFT (8U).CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK).CSU_CSL_SUR_S1_MASK (0x10000U).CSU_CSL_SUR_S1_SHIFT (16U).CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK).CSU_CSL_SSR_S1_MASK (0x20000U).CSU_CSL_SSR_S1_SHIFT (17U).CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK).CSU_CSL_NUR_S1_MASK (0x40000U).CSU_CSL_NUR_S1_SHIFT (18U).CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK).CSU_CSL_NSR_S1_MASK (0x80000U).CSU_CSL_NSR_S1_SHIFT (19U).CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK).CSU_CSL_SUW_S1_MASK (0x100000U).CSU_CSL_SUW_S1_SHIFT (20U).CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK).CSU_CSL_SSW_S1_MASK (0x200000U).CSU_CSL_SSW_S1_SHIFT (21U).CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK).CSU_CSL_NUW_S1_MASK (0x400000U).CSU_CSL_NUW_S1_SHIFT (22U).CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK).CSU_CSL_NSW_S1_MASK (0x800000U).CSU_CSL_NSW_S1_SHIFT (23U).CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK).CSU_CSL_LOCK_S1_MASK (0x1000000U).CSU_CSL_LOCK_S1_SHIFT (24U).CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK).CSU_CSL_COUNT (32U).CSU_HP0_HP_DMA_MASK (0x4U).CSU_HP0_HP_DMA_SHIFT (2U).CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK).CSU_HP0_L_DMA_MASK (0x8U).CSU_HP0_L_DMA_SHIFT (3U).CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK).CSU_HP0_HP_LCDIF_MASK (0x10U).CSU_HP0_HP_LCDIF_SHIFT (4U).CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK).CSU_HP0_L_LCDIF_MASK (0x20U).CSU_HP0_L_LCDIF_SHIFT (5U).CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK).CSU_HP0_HP_CSI_MASK (0x40U).CSU_HP0_HP_CSI_SHIFT (6U).CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK).CSU_HP0_L_CSI_MASK (0x80U).CSU_HP0_L_CSI_SHIFT (7U).CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK).CSU_HP0_HP_PXP_MASK (0x100U).CSU_HP0_HP_PXP_SHIFT (8U).CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK).CSU_HP0_L_PXP_MASK (0x200U).CSU_HP0_L_PXP_SHIFT (9U).CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK).CSU_HP0_HP_DCP_MASK (0x400U).CSU_HP0_HP_DCP_SHIFT (10U).CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK).CSU_HP0_L_DCP_MASK (0x800U).CSU_HP0_L_DCP_SHIFT (11U)/CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)/CSU_HP0_HP_ENET_MASK (0x4000U)/CSU_HP0_HP_ENET_SHIFT (14U)/CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)/CSU_HP0_L_ENET_MASK (0x8000U)/CSU_HP0_L_ENET_SHIFT (15U)/CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)/CSU_HP0_HP_USDHC1_MASK (0x10000U)/CSU_HP0_HP_USDHC1_SHIFT (16U)/CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)/CSU_HP0_L_USDHC1_MASK (0x20000U)/CSU_HP0_L_USDHC1_SHIFT (17U)/CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)/CSU_HP0_HP_USDHC2_MASK (0x40000U)/CSU_HP0_HP_USDHC2_SHIFT (18U)/CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)/CSU_HP0_L_USDHC2_MASK (0x80000U)/CSU_HP0_L_USDHC2_SHIFT (19U)/CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)/CSU_HP0_HP_TPSMP_MASK (0x100000U)/CSU_HP0_HP_TPSMP_SHIFT (20U)/CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)/CSU_HP0_L_TPSMP_MASK (0x200000U)/CSU_HP0_L_TPSMP_SHIFT (21U)/CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)/CSU_HP0_HP_USB_MASK (0x400000U)/CSU_HP0_HP_USB_SHIFT (22U)/CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)/CSU_HP0_L_USB_MASK (0x800000U)/CSU_HP0_L_USB_SHIFT (23U)/CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)/CSU_SA_NSA_DMA_MASK (0x4U)/CSU_SA_NSA_DMA_SHIFT (2U)/CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)/CSU_SA_L_DMA_MASK (0x8U)/CSU_SA_L_DMA_SHIFT (3U)/CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)/CSU_SA_NSA_LCDIF_MASK (0x10U)/CSU_SA_NSA_LCDIF_SHIFT (4U)/CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)/CSU_SA_L_LCDIF_MASK (0x20U)/CSU_SA_L_LCDIF_SHIFT (5U)/CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)/CSU_SA_NSA_CSI_MASK (0x40U)/CSU_SA_NSA_CSI_SHIFT (6U)/CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)/CSU_SA_L_CSI_MASK (0x80U)/CSU_SA_L_CSI_SHIFT (7U)/CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)/CSU_SA_NSA_PXP_MASK (0x100U)/CSU_SA_NSA_PXP_SHIFT (8U)/CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)/CSU_SA_L_PXP_MASK (0x200U)/CSU_SA_L_PXP_SHIFT (9U)/CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)/CSU_SA_NSA_DCP_MASK (0x400U)/CSU_SA_NSA_DCP_SHIFT (10U)/CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)/CSU_SA_L_DCP_MASK (0x800U)/CSU_SA_L_DCP_SHIFT (11U)/CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)/CSU_SA_NSA_ENET_MASK (0x4000U)/CSU_SA_NSA_ENET_SHIFT (14U)/CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)/CSU_SA_L_ENET_MASK (0x8000U)/CSU_SA_L_ENET_SHIFT (15U)/CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)/CSU_SA_NSA_USDHC1_MASK (0x10000U)/CSU_SA_NSA_USDHC1_SHIFT (16U)/CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)/CSU_SA_L_USDHC1_MASK (0x20000U)/CSU_SA_L_USDHC1_SHIFT (17U)/CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)/CSU_SA_NSA_USDHC2_MASK (0x40000U)/CSU_SA_NSA_USDHC2_SHIFT (18U)/CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)/CSU_SA_L_USDHC2_MASK (0x80000U)/CSU_SA_L_USDHC2_SHIFT (19U)/CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)/CSU_SA_NSA_TPSMP_MASK (0x100000U)/CSU_SA_NSA_TPSMP_SHIFT (20U)/CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)/CSU_SA_L_TPSMP_MASK (0x200000U)/CSU_SA_L_TPSMP_SHIFT (21U)/CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)/CSU_SA_NSA_USB_MASK (0x400000U)/CSU_SA_NSA_USB_SHIFT (22U)/CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)/CSU_SA_L_USB_MASK (0x800000U)/CSU_SA_L_USB_SHIFT (23U)/CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)/CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)/CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)/CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)/CSU_HPCONTROL0_L_DMA_MASK (0x8U)/CSU_HPCONTROL0_L_DMA_SHIFT (3U)/CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)/CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)/CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)/CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)/CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)/CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)/CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)/CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)/CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)/CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)/CSU_HPCONTROL0_L_CSI_MASK (0x80U)/CSU_HPCONTROL0_L_CSI_SHIFT (7U)/CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)/CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)/CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)/CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)/CSU_HPCONTROL0_L_PXP_MASK (0x200U)/CSU_HPCONTROL0_L_PXP_SHIFT (9U)/CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)/CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)/CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)/CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)/CSU_HPCONTROL0_L_DCP_MASK (0x800U)/CSU_HPCONTROL0_L_DCP_SHIFT (11U)/CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)/CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)/CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)/CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)0CSU_HPCONTROL0_L_ENET_MASK (0x8000U)0CSU_HPCONTROL0_L_ENET_SHIFT (15U)0CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)0CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)0CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)0CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)0CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)0CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)0CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)0CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)0CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)0CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)0CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)0CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)0CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)0CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)0CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)0CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)0CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)0CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)0CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)0CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)0CSU_HPCONTROL0_HPC_USB_SHIFT (22U)0CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)0CSU_HPCONTROL0_L_USB_MASK (0x800000U)0CSU_HPCONTROL0_L_USB_SHIFT (23U)0CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)0CSU_BASE (0x400DC000u)0CSU ((CSU_Type *)CSU_BASE)0CSU_BASE_ADDRS { CSU_BASE }0CSU_BASE_PTRS { CSU }0DCDC_REG0_PWD_ZCD_MASK (0x1U)0DCDC_REG0_PWD_ZCD_SHIFT (0U)0DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)0DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)0DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)0DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)0DCDC_REG0_SEL_CLK_MASK (0x4U)0DCDC_REG0_SEL_CLK_SHIFT (2U)0DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)0DCDC_REG0_PWD_OSC_INT_MASK (0x8U)0DCDC_REG0_PWD_OSC_INT_SHIFT (3U)0DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)0DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)0DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)0DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)0DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)0DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)0DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)0DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)0DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)0DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)0DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)0DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)0DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)0DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)0DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)0DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)0DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)0DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)0DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)0DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)0DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)0DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)0DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)0DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)0DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)0DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)0DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)0DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)0DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)0DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)0DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)0DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)0DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)0DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)0DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)0DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)0DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)0DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)0DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)0DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)0DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)1DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)1DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)1DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)1DCDC_REG0_XTAL_24M_OK_SHIFT (29U)1DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)1DCDC_REG0_STS_DC_OK_MASK (0x80000000U)1DCDC_REG0_STS_DC_OK_SHIFT (31U)1DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)1DCDC_REG1_REG_FBK_SEL_MASK (0x180U)1DCDC_REG1_REG_FBK_SEL_SHIFT (7U)1DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)1DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)1DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)1DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)1DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)1DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)1DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)1DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)1DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)1DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)1DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)1DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)1DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)1DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)1DCDC_REG1_VBG_TRIM_SHIFT (24U)1DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)1DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)1DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)1DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)1DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)1DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)1DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)1DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)1DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)1DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)1DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)1DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)1DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)1DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)1DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)1DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)1DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)1DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)1DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)1DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)1DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)1DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)1DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)1DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)1DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)1DCDC_REG3_TRG_MASK (0x1FU)1DCDC_REG3_TRG_SHIFT (0U)1DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)1DCDC_REG3_TARGET_LP_MASK (0x700U)1DCDC_REG3_TARGET_LP_SHIFT (8U)1DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)1DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)1DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)1DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)1DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)1DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)1DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)1DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)1DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)1DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)1DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)1DCDC_REG3_DISABLE_STEP_SHIFT (30U)1DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)1DCDC_BASE (0x40080000u)1DCDC ((DCDC_Type *)DCDC_BASE)1DCDC_BASE_ADDRS { DCDC_BASE }1DCDC_BASE_PTRS { DCDC }1DCDC_IRQS { DCDC_IRQn }2DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)2DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)2DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)2DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)2DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)2DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)2DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)2DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)2DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)2DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)2DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)2DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)2DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)2DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)2DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)2DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)2DCP_CTRL_PRESENT_SHA_SHIFT (28U)2DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)2DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)2DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)2DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)2DCP_CTRL_CLKGATE_MASK (0x40000000U)2DCP_CTRL_CLKGATE_SHIFT (30U)2DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)2DCP_CTRL_SFTRST_MASK (0x80000000U)2DCP_CTRL_SFTRST_SHIFT (31U)2DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)2DCP_STAT_IRQ_MASK (0xFU)2DCP_STAT_IRQ_SHIFT (0U)2DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)2DCP_STAT_RSVD_IRQ_MASK (0x100U)2DCP_STAT_RSVD_IRQ_SHIFT (8U)2DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)2DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)2DCP_STAT_READY_CHANNELS_SHIFT (16U)2DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)2DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)2DCP_STAT_CUR_CHANNEL_SHIFT (24U)2DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)2DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)2DCP_STAT_OTP_KEY_READY_SHIFT (28U)2DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)2DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)2DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)2DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)2DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)2DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)2DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)2DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)2DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)2DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)2DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)2DCP_CHANNELCTRL_RSVD_SHIFT (17U)2DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)2DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)2DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)2DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)2DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)2DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)2DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)3DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)3DCP_CAPABILITY0_RSVD_SHIFT (12U)3DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)3DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)3DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)3DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)3DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)3DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)3DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)3DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)3DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)3DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)3DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)3DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)3DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)3DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)3DCP_CONTEXT_ADDR_SHIFT (0U)3DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)3DCP_KEY_SUBWORD_MASK (0x3U)3DCP_KEY_SUBWORD_SHIFT (0U)3DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)3DCP_KEY_RSVD_SUBWORD_MASK (0xCU)3DCP_KEY_RSVD_SUBWORD_SHIFT (2U)3DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)3DCP_KEY_INDEX_MASK (0x30U)3DCP_KEY_INDEX_SHIFT (4U)3DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)3DCP_KEY_RSVD_INDEX_MASK (0xC0U)3DCP_KEY_RSVD_INDEX_SHIFT (6U)3DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)3DCP_KEY_RSVD_MASK (0xFFFFFF00U)3DCP_KEY_RSVD_SHIFT (8U)3DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)3DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)3DCP_KEYDATA_DATA_SHIFT (0U)3DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)3DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)3DCP_PACKET0_ADDR_SHIFT (0U)3DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)3DCP_PACKET1_INTERRUPT_MASK (0x1U)3DCP_PACKET1_INTERRUPT_SHIFT (0U)3DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)3DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)3DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)3DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)3DCP_PACKET1_CHAIN_MASK (0x4U)3DCP_PACKET1_CHAIN_SHIFT (2U)3DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)3DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)3DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)3DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)3DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)3DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)3DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)3DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)3DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)3DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)3DCP_PACKET1_ENABLE_HASH_MASK (0x40U)3DCP_PACKET1_ENABLE_HASH_SHIFT (6U)3DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)3DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)3DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)3DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)3DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)3DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)3DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)3DCP_PACKET1_CIPHER_INIT_MASK (0x200U)3DCP_PACKET1_CIPHER_INIT_SHIFT (9U)3DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)3DCP_PACKET1_OTP_KEY_MASK (0x400U)3DCP_PACKET1_OTP_KEY_SHIFT (10U)3DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)3DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)3DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)3DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)3DCP_PACKET1_HASH_INIT_MASK (0x1000U)3DCP_PACKET1_HASH_INIT_SHIFT (12U)3DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)3DCP_PACKET1_HASH_TERM_MASK (0x2000U)3DCP_PACKET1_HASH_TERM_SHIFT (13U)3DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)3DCP_PACKET1_CHECK_HASH_MASK (0x4000U)3DCP_PACKET1_CHECK_HASH_SHIFT (14U)3DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)3DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)3DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)3DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)3DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)3DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)3DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)3DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)3DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)3DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)3DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)3DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)3DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)3DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)3DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)3DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)3DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)3DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)3DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)3DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)3DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)3DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)3DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)3DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)3DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)3DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)3DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)3DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)3DCP_PACKET1_TAG_MASK (0xFF000000U)3DCP_PACKET1_TAG_SHIFT (24U)3DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)4DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)4DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)4DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)4DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)4DCP_PACKET2_CIPHER_MODE_SHIFT (4U)4DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)4DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)4DCP_PACKET2_KEY_SELECT_SHIFT (8U)4DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)4DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)4DCP_PACKET2_HASH_SELECT_SHIFT (16U)4DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)4DCP_PACKET2_RSVD_MASK (0xF00000U)4DCP_PACKET2_RSVD_SHIFT (20U)4DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)4DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)4DCP_PACKET2_CIPHER_CFG_SHIFT (24U)4DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)4DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)4DCP_PACKET3_ADDR_SHIFT (0U)4DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)4DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)4DCP_PACKET4_ADDR_SHIFT (0U)4DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)4DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)4DCP_PACKET5_COUNT_SHIFT (0U)4DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)4DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)4DCP_PACKET6_ADDR_SHIFT (0U)4DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)4DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)4DCP_CH0CMDPTR_ADDR_SHIFT (0U)4DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)4DCP_CH0SEMA_INCREMENT_MASK (0xFFU)4DCP_CH0SEMA_INCREMENT_SHIFT (0U)4DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)4DCP_CH0SEMA_VALUE_MASK (0xFF0000U)4DCP_CH0SEMA_VALUE_SHIFT (16U)4DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)4DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)4DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)4DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)4DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)4DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)4DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)4DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)4DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)4DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)4DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)4DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)4DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)4DCP_CH0STAT_ERROR_SRC_MASK (0x10U)4DCP_CH0STAT_ERROR_SRC_SHIFT (4U)4DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)4DCP_CH0STAT_ERROR_DST_MASK (0x20U)4DCP_CH0STAT_ERROR_DST_SHIFT (5U)4DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)4DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)4DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)4DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)4DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)4DCP_CH0STAT_ERROR_CODE_SHIFT (16U)4DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)4DCP_CH0STAT_TAG_MASK (0xFF000000U)4DCP_CH0STAT_TAG_SHIFT (24U)4DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)4DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)4DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)4DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)4DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)4DCP_CH0OPTS_RSVD_SHIFT (16U)4DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)4DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)4DCP_CH1CMDPTR_ADDR_SHIFT (0U)4DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)4DCP_CH1SEMA_INCREMENT_MASK (0xFFU)4DCP_CH1SEMA_INCREMENT_SHIFT (0U)4DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)4DCP_CH1SEMA_VALUE_MASK (0xFF0000U)4DCP_CH1SEMA_VALUE_SHIFT (16U)4DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)4DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)4DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)4DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)4DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)4DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)4DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)4DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)4DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)4DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)4DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)4DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)4DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)4DCP_CH1STAT_ERROR_SRC_MASK (0x10U)4DCP_CH1STAT_ERROR_SRC_SHIFT (4U)4DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)4DCP_CH1STAT_ERROR_DST_MASK (0x20U)4DCP_CH1STAT_ERROR_DST_SHIFT (5U)4DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)4DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)4DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)4DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)4DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)4DCP_CH1STAT_ERROR_CODE_SHIFT (16U)4DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)4DCP_CH1STAT_TAG_MASK (0xFF000000U)5DCP_CH1STAT_TAG_SHIFT (24U)5DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)5DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)5DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)5DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)5DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)5DCP_CH1OPTS_RSVD_SHIFT (16U)5DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)5DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)5DCP_CH2CMDPTR_ADDR_SHIFT (0U)5DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)5DCP_CH2SEMA_INCREMENT_MASK (0xFFU)5DCP_CH2SEMA_INCREMENT_SHIFT (0U)5DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)5DCP_CH2SEMA_VALUE_MASK (0xFF0000U)5DCP_CH2SEMA_VALUE_SHIFT (16U)5DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)5DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)5DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)5DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)5DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)5DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)5DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)5DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)5DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)5DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)5DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)5DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)5DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)5DCP_CH2STAT_ERROR_SRC_MASK (0x10U)5DCP_CH2STAT_ERROR_SRC_SHIFT (4U)5DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)5DCP_CH2STAT_ERROR_DST_MASK (0x20U)5DCP_CH2STAT_ERROR_DST_SHIFT (5U)5DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)5DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)5DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)5DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)5DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)5DCP_CH2STAT_ERROR_CODE_SHIFT (16U)5DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)5DCP_CH2STAT_TAG_MASK (0xFF000000U)5DCP_CH2STAT_TAG_SHIFT (24U)5DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)5DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)5DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)5DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)5DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)5DCP_CH2OPTS_RSVD_SHIFT (16U)5DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)5DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)5DCP_CH3CMDPTR_ADDR_SHIFT (0U)5DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)5DCP_CH3SEMA_INCREMENT_MASK (0xFFU)5DCP_CH3SEMA_INCREMENT_SHIFT (0U)5DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)5DCP_CH3SEMA_VALUE_MASK (0xFF0000U)5DCP_CH3SEMA_VALUE_SHIFT (16U)5DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)5DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)5DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)5DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)5DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)5DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)5DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)5DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)5DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)5DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)5DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)5DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)5DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)5DCP_CH3STAT_ERROR_SRC_MASK (0x10U)5DCP_CH3STAT_ERROR_SRC_SHIFT (4U)5DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)5DCP_CH3STAT_ERROR_DST_MASK (0x20U)5DCP_CH3STAT_ERROR_DST_SHIFT (5U)5DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)5DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)5DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)5DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)5DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)5DCP_CH3STAT_ERROR_CODE_SHIFT (16U)5DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)5DCP_CH3STAT_TAG_MASK (0xFF000000U)5DCP_CH3STAT_TAG_SHIFT (24U)5DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)5DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)5DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)5DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)5DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)5DCP_CH3OPTS_RSVD_SHIFT (16U)5DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)5DCP_DBGSELECT_INDEX_MASK (0xFFU)5DCP_DBGSELECT_INDEX_SHIFT (0U)5DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)5DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)5DCP_DBGSELECT_RSVD_SHIFT (8U)5DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)5DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)5DCP_DBGDATA_DATA_SHIFT (0U)5DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)5DCP_PAGETABLE_ENABLE_MASK (0x1U)5DCP_PAGETABLE_ENABLE_SHIFT (0U)5DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)6DCP_PAGETABLE_FLUSH_MASK (0x2U)6DCP_PAGETABLE_FLUSH_SHIFT (1U)6DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)6DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)6DCP_PAGETABLE_BASE_SHIFT (2U)6DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)6DCP_VERSION_STEP_MASK (0xFFFFU)6DCP_VERSION_STEP_SHIFT (0U)6DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)6DCP_VERSION_MINOR_MASK (0xFF0000U)6DCP_VERSION_MINOR_SHIFT (16U)6DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)6DCP_VERSION_MAJOR_MASK (0xFF000000U)6DCP_VERSION_MAJOR_SHIFT (24U)6DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)6DCP_BASE (0x402FC000u)6DCP ((DCP_Type *)DCP_BASE)6DCP_BASE_ADDRS { DCP_BASE }6DCP_BASE_PTRS { DCP }6DCP_IRQS { DCP_IRQn }6DCP_VMI_IRQS { DCP_VMI_IRQn }7DMA_CR_EDBG_MASK (0x2U)7DMA_CR_EDBG_SHIFT (1U)7DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)7DMA_CR_ERCA_MASK (0x4U)7DMA_CR_ERCA_SHIFT (2U)7DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)7DMA_CR_ERGA_MASK (0x8U)7DMA_CR_ERGA_SHIFT (3U)7DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)7DMA_CR_HOE_MASK (0x10U)7DMA_CR_HOE_SHIFT (4U)7DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)7DMA_CR_HALT_MASK (0x20U)7DMA_CR_HALT_SHIFT (5U)7DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)7DMA_CR_CLM_MASK (0x40U)7DMA_CR_CLM_SHIFT (6U)7DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)7DMA_CR_EMLM_MASK (0x80U)7DMA_CR_EMLM_SHIFT (7U)7DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)7DMA_CR_GRP0PRI_MASK (0x100U)7DMA_CR_GRP0PRI_SHIFT (8U)7DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)7DMA_CR_GRP1PRI_MASK (0x400U)7DMA_CR_GRP1PRI_SHIFT (10U)7DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)7DMA_CR_ECX_MASK (0x10000U)7DMA_CR_ECX_SHIFT (16U)7DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)7DMA_CR_CX_MASK (0x20000U)7DMA_CR_CX_SHIFT (17U)7DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)7DMA_CR_ACTIVE_MASK (0x80000000U)7DMA_CR_ACTIVE_SHIFT (31U)7DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)7DMA_ES_DBE_MASK (0x1U)7DMA_ES_DBE_SHIFT (0U)7DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)7DMA_ES_SBE_MASK (0x2U)7DMA_ES_SBE_SHIFT (1U)7DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)7DMA_ES_SGE_MASK (0x4U)7DMA_ES_SGE_SHIFT (2U)7DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)7DMA_ES_NCE_MASK (0x8U)7DMA_ES_NCE_SHIFT (3U)7DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)7DMA_ES_DOE_MASK (0x10U)7DMA_ES_DOE_SHIFT (4U)7DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)7DMA_ES_DAE_MASK (0x20U)7DMA_ES_DAE_SHIFT (5U)7DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)7DMA_ES_SOE_MASK (0x40U)7DMA_ES_SOE_SHIFT (6U)7DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)7DMA_ES_SAE_MASK (0x80U)7DMA_ES_SAE_SHIFT (7U)7DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)7DMA_ES_ERRCHN_MASK (0x1F00U)7DMA_ES_ERRCHN_SHIFT (8U)7DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)7DMA_ES_CPE_MASK (0x4000U)7DMA_ES_CPE_SHIFT (14U)7DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)7DMA_ES_GPE_MASK (0x8000U)7DMA_ES_GPE_SHIFT (15U)7DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)7DMA_ES_ECX_MASK (0x10000U)7DMA_ES_ECX_SHIFT (16U)7DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)7DMA_ES_VLD_MASK (0x80000000U)7DMA_ES_VLD_SHIFT (31U)7DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)7DMA_ERQ_ERQ0_MASK (0x1U)7DMA_ERQ_ERQ0_SHIFT (0U)7DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)7DMA_ERQ_ERQ1_MASK (0x2U)7DMA_ERQ_ERQ1_SHIFT (1U)7DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)7DMA_ERQ_ERQ2_MASK (0x4U)7DMA_ERQ_ERQ2_SHIFT (2U)7DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)7DMA_ERQ_ERQ3_MASK (0x8U)7DMA_ERQ_ERQ3_SHIFT (3U)7DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)7DMA_ERQ_ERQ4_MASK (0x10U)7DMA_ERQ_ERQ4_SHIFT (4U)7DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)7DMA_ERQ_ERQ5_MASK (0x20U)7DMA_ERQ_ERQ5_SHIFT (5U)7DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)7DMA_ERQ_ERQ6_MASK (0x40U)7DMA_ERQ_ERQ6_SHIFT (6U)7DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)7DMA_ERQ_ERQ7_MASK (0x80U)7DMA_ERQ_ERQ7_SHIFT (7U)7DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)7DMA_ERQ_ERQ8_MASK (0x100U)7DMA_ERQ_ERQ8_SHIFT (8U)7DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)7DMA_ERQ_ERQ9_MASK (0x200U)7DMA_ERQ_ERQ9_SHIFT (9U)7DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)7DMA_ERQ_ERQ10_MASK (0x400U)7DMA_ERQ_ERQ10_SHIFT (10U)7DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)8DMA_ERQ_ERQ11_MASK (0x800U)8DMA_ERQ_ERQ11_SHIFT (11U)8DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)8DMA_ERQ_ERQ12_MASK (0x1000U)8DMA_ERQ_ERQ12_SHIFT (12U)8DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)8DMA_ERQ_ERQ13_MASK (0x2000U)8DMA_ERQ_ERQ13_SHIFT (13U)8DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)8DMA_ERQ_ERQ14_MASK (0x4000U)8DMA_ERQ_ERQ14_SHIFT (14U)8DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)8DMA_ERQ_ERQ15_MASK (0x8000U)8DMA_ERQ_ERQ15_SHIFT (15U)8DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)8DMA_ERQ_ERQ16_MASK (0x10000U)8DMA_ERQ_ERQ16_SHIFT (16U)8DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)8DMA_ERQ_ERQ17_MASK (0x20000U)8DMA_ERQ_ERQ17_SHIFT (17U)8DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)8DMA_ERQ_ERQ18_MASK (0x40000U)8DMA_ERQ_ERQ18_SHIFT (18U)8DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)8DMA_ERQ_ERQ19_MASK (0x80000U)8DMA_ERQ_ERQ19_SHIFT (19U)8DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)8DMA_ERQ_ERQ20_MASK (0x100000U)8DMA_ERQ_ERQ20_SHIFT (20U)8DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)8DMA_ERQ_ERQ21_MASK (0x200000U)8DMA_ERQ_ERQ21_SHIFT (21U)8DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)8DMA_ERQ_ERQ22_MASK (0x400000U)8DMA_ERQ_ERQ22_SHIFT (22U)8DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)8DMA_ERQ_ERQ23_MASK (0x800000U)8DMA_ERQ_ERQ23_SHIFT (23U)8DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)8DMA_ERQ_ERQ24_MASK (0x1000000U)8DMA_ERQ_ERQ24_SHIFT (24U)8DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)8DMA_ERQ_ERQ25_MASK (0x2000000U)8DMA_ERQ_ERQ25_SHIFT (25U)8DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)8DMA_ERQ_ERQ26_MASK (0x4000000U)8DMA_ERQ_ERQ26_SHIFT (26U)8DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)8DMA_ERQ_ERQ27_MASK (0x8000000U)8DMA_ERQ_ERQ27_SHIFT (27U)8DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)8DMA_ERQ_ERQ28_MASK (0x10000000U)8DMA_ERQ_ERQ28_SHIFT (28U)8DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)8DMA_ERQ_ERQ29_MASK (0x20000000U)8DMA_ERQ_ERQ29_SHIFT (29U)8DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)8DMA_ERQ_ERQ30_MASK (0x40000000U)8DMA_ERQ_ERQ30_SHIFT (30U)8DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)8DMA_ERQ_ERQ31_MASK (0x80000000U)8DMA_ERQ_ERQ31_SHIFT (31U)8DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)8DMA_EEI_EEI0_MASK (0x1U)8DMA_EEI_EEI0_SHIFT (0U)8DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)8DMA_EEI_EEI1_MASK (0x2U)8DMA_EEI_EEI1_SHIFT (1U)8DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)8DMA_EEI_EEI2_MASK (0x4U)8DMA_EEI_EEI2_SHIFT (2U)8DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)8DMA_EEI_EEI3_MASK (0x8U)8DMA_EEI_EEI3_SHIFT (3U)8DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)8DMA_EEI_EEI4_MASK (0x10U)8DMA_EEI_EEI4_SHIFT (4U)8DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)8DMA_EEI_EEI5_MASK (0x20U)8DMA_EEI_EEI5_SHIFT (5U)8DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)8DMA_EEI_EEI6_MASK (0x40U)8DMA_EEI_EEI6_SHIFT (6U)8DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)8DMA_EEI_EEI7_MASK (0x80U)8DMA_EEI_EEI7_SHIFT (7U)8DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)8DMA_EEI_EEI8_MASK (0x100U)8DMA_EEI_EEI8_SHIFT (8U)8DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)8DMA_EEI_EEI9_MASK (0x200U)8DMA_EEI_EEI9_SHIFT (9U)8DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)8DMA_EEI_EEI10_MASK (0x400U)8DMA_EEI_EEI10_SHIFT (10U)8DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)8DMA_EEI_EEI11_MASK (0x800U)8DMA_EEI_EEI11_SHIFT (11U)8DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)8DMA_EEI_EEI12_MASK (0x1000U)8DMA_EEI_EEI12_SHIFT (12U)8DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)8DMA_EEI_EEI13_MASK (0x2000U)8DMA_EEI_EEI13_SHIFT (13U)8DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)8DMA_EEI_EEI14_MASK (0x4000U)8DMA_EEI_EEI14_SHIFT (14U)8DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)8DMA_EEI_EEI15_MASK (0x8000U)8DMA_EEI_EEI15_SHIFT (15U)8DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)8DMA_EEI_EEI16_MASK (0x10000U)8DMA_EEI_EEI16_SHIFT (16U)8DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)8DMA_EEI_EEI17_MASK (0x20000U)8DMA_EEI_EEI17_SHIFT (17U)8DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)8DMA_EEI_EEI18_MASK (0x40000U)8DMA_EEI_EEI18_SHIFT (18U)8DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)8DMA_EEI_EEI19_MASK (0x80000U)8DMA_EEI_EEI19_SHIFT (19U)8DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)8DMA_EEI_EEI20_MASK (0x100000U)8DMA_EEI_EEI20_SHIFT (20U)8DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)9DMA_EEI_EEI21_MASK (0x200000U)9DMA_EEI_EEI21_SHIFT (21U)9DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)9DMA_EEI_EEI22_MASK (0x400000U)9DMA_EEI_EEI22_SHIFT (22U)9DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)9DMA_EEI_EEI23_MASK (0x800000U)9DMA_EEI_EEI23_SHIFT (23U)9DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)9DMA_EEI_EEI24_MASK (0x1000000U)9DMA_EEI_EEI24_SHIFT (24U)9DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)9DMA_EEI_EEI25_MASK (0x2000000U)9DMA_EEI_EEI25_SHIFT (25U)9DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)9DMA_EEI_EEI26_MASK (0x4000000U)9DMA_EEI_EEI26_SHIFT (26U)9DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)9DMA_EEI_EEI27_MASK (0x8000000U)9DMA_EEI_EEI27_SHIFT (27U)9DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)9DMA_EEI_EEI28_MASK (0x10000000U)9DMA_EEI_EEI28_SHIFT (28U)9DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)9DMA_EEI_EEI29_MASK (0x20000000U)9DMA_EEI_EEI29_SHIFT (29U)9DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)9DMA_EEI_EEI30_MASK (0x40000000U)9DMA_EEI_EEI30_SHIFT (30U)9DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)9DMA_EEI_EEI31_MASK (0x80000000U)9DMA_EEI_EEI31_SHIFT (31U)9DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)9DMA_CEEI_CEEI_MASK (0x1FU)9DMA_CEEI_CEEI_SHIFT (0U)9DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)9DMA_CEEI_CAEE_MASK (0x40U)9DMA_CEEI_CAEE_SHIFT (6U)9DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)9DMA_CEEI_NOP_MASK (0x80U)9DMA_CEEI_NOP_SHIFT (7U)9DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)9DMA_SEEI_SEEI_MASK (0x1FU)9DMA_SEEI_SEEI_SHIFT (0U)9DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)9DMA_SEEI_SAEE_MASK (0x40U)9DMA_SEEI_SAEE_SHIFT (6U)9DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)9DMA_SEEI_NOP_MASK (0x80U)9DMA_SEEI_NOP_SHIFT (7U)9DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)9DMA_CERQ_CERQ_MASK (0x1FU)9DMA_CERQ_CERQ_SHIFT (0U)9DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)9DMA_CERQ_CAER_MASK (0x40U)9DMA_CERQ_CAER_SHIFT (6U)9DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)9DMA_CERQ_NOP_MASK (0x80U)9DMA_CERQ_NOP_SHIFT (7U)9DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)9DMA_SERQ_SERQ_MASK (0x1FU)9DMA_SERQ_SERQ_SHIFT (0U)9DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)9DMA_SERQ_SAER_MASK (0x40U)9DMA_SERQ_SAER_SHIFT (6U)9DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)9DMA_SERQ_NOP_MASK (0x80U)9DMA_SERQ_NOP_SHIFT (7U)9DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)9DMA_CDNE_CDNE_MASK (0x1FU)9DMA_CDNE_CDNE_SHIFT (0U)9DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)9DMA_CDNE_CADN_MASK (0x40U)9DMA_CDNE_CADN_SHIFT (6U)9DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)9DMA_CDNE_NOP_MASK (0x80U)9DMA_CDNE_NOP_SHIFT (7U)9DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)9DMA_SSRT_SSRT_MASK (0x1FU)9DMA_SSRT_SSRT_SHIFT (0U)9DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)9DMA_SSRT_SAST_MASK (0x40U)9DMA_SSRT_SAST_SHIFT (6U)9DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)9DMA_SSRT_NOP_MASK (0x80U)9DMA_SSRT_NOP_SHIFT (7U)9DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)9DMA_CERR_CERR_MASK (0x1FU)9DMA_CERR_CERR_SHIFT (0U)9DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)9DMA_CERR_CAEI_MASK (0x40U)9DMA_CERR_CAEI_SHIFT (6U)9DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)9DMA_CERR_NOP_MASK (0x80U)9DMA_CERR_NOP_SHIFT (7U)9DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)9DMA_CINT_CINT_MASK (0x1FU)9DMA_CINT_CINT_SHIFT (0U)9DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)9DMA_CINT_CAIR_MASK (0x40U)9DMA_CINT_CAIR_SHIFT (6U)9DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)9DMA_CINT_NOP_MASK (0x80U)9DMA_CINT_NOP_SHIFT (7U)9DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)9DMA_INT_INT0_MASK (0x1U)9DMA_INT_INT0_SHIFT (0U)9DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)9DMA_INT_INT1_MASK (0x2U)9DMA_INT_INT1_SHIFT (1U):DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK):DMA_INT_INT2_MASK (0x4U):DMA_INT_INT2_SHIFT (2U):DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK):DMA_INT_INT3_MASK (0x8U):DMA_INT_INT3_SHIFT (3U):DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK):DMA_INT_INT4_MASK (0x10U):DMA_INT_INT4_SHIFT (4U):DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK):DMA_INT_INT5_MASK (0x20U):DMA_INT_INT5_SHIFT (5U):DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK):DMA_INT_INT6_MASK (0x40U):DMA_INT_INT6_SHIFT (6U):DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK):DMA_INT_INT7_MASK (0x80U):DMA_INT_INT7_SHIFT (7U):DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK):DMA_INT_INT8_MASK (0x100U):DMA_INT_INT8_SHIFT (8U):DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK):DMA_INT_INT9_MASK (0x200U):DMA_INT_INT9_SHIFT (9U):DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK):DMA_INT_INT10_MASK (0x400U):DMA_INT_INT10_SHIFT (10U):DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK):DMA_INT_INT11_MASK (0x800U):DMA_INT_INT11_SHIFT (11U):DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK):DMA_INT_INT12_MASK (0x1000U):DMA_INT_INT12_SHIFT (12U):DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK):DMA_INT_INT13_MASK (0x2000U):DMA_INT_INT13_SHIFT (13U):DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK):DMA_INT_INT14_MASK (0x4000U):DMA_INT_INT14_SHIFT (14U):DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK):DMA_INT_INT15_MASK (0x8000U):DMA_INT_INT15_SHIFT (15U):DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK):DMA_INT_INT16_MASK (0x10000U):DMA_INT_INT16_SHIFT (16U):DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK):DMA_INT_INT17_MASK (0x20000U):DMA_INT_INT17_SHIFT (17U):DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK):DMA_INT_INT18_MASK (0x40000U):DMA_INT_INT18_SHIFT (18U):DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK):DMA_INT_INT19_MASK (0x80000U):DMA_INT_INT19_SHIFT (19U):DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK):DMA_INT_INT20_MASK (0x100000U):DMA_INT_INT20_SHIFT (20U):DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK):DMA_INT_INT21_MASK (0x200000U):DMA_INT_INT21_SHIFT (21U):DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK):DMA_INT_INT22_MASK (0x400000U):DMA_INT_INT22_SHIFT (22U):DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK):DMA_INT_INT23_MASK (0x800000U):DMA_INT_INT23_SHIFT (23U):DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK):DMA_INT_INT24_MASK (0x1000000U):DMA_INT_INT24_SHIFT (24U):DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK):DMA_INT_INT25_MASK (0x2000000U):DMA_INT_INT25_SHIFT (25U):DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK):DMA_INT_INT26_MASK (0x4000000U):DMA_INT_INT26_SHIFT (26U):DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK):DMA_INT_INT27_MASK (0x8000000U):DMA_INT_INT27_SHIFT (27U):DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK):DMA_INT_INT28_MASK (0x10000000U):DMA_INT_INT28_SHIFT (28U):DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK):DMA_INT_INT29_MASK (0x20000000U):DMA_INT_INT29_SHIFT (29U):DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK):DMA_INT_INT30_MASK (0x40000000U):DMA_INT_INT30_SHIFT (30U):DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK):DMA_INT_INT31_MASK (0x80000000U):DMA_INT_INT31_SHIFT (31U):DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK):DMA_ERR_ERR0_MASK (0x1U):DMA_ERR_ERR0_SHIFT (0U):DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK):DMA_ERR_ERR1_MASK (0x2U):DMA_ERR_ERR1_SHIFT (1U):DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK):DMA_ERR_ERR2_MASK (0x4U):DMA_ERR_ERR2_SHIFT (2U):DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK):DMA_ERR_ERR3_MASK (0x8U):DMA_ERR_ERR3_SHIFT (3U):DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK):DMA_ERR_ERR4_MASK (0x10U):DMA_ERR_ERR4_SHIFT (4U):DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK):DMA_ERR_ERR5_MASK (0x20U):DMA_ERR_ERR5_SHIFT (5U):DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK):DMA_ERR_ERR6_MASK (0x40U):DMA_ERR_ERR6_SHIFT (6U):DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK):DMA_ERR_ERR7_MASK (0x80U):DMA_ERR_ERR7_SHIFT (7U):DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK):DMA_ERR_ERR8_MASK (0x100U):DMA_ERR_ERR8_SHIFT (8U):DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK):DMA_ERR_ERR9_MASK (0x200U):DMA_ERR_ERR9_SHIFT (9U):DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK):DMA_ERR_ERR10_MASK (0x400U):DMA_ERR_ERR10_SHIFT (10U):DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK):DMA_ERR_ERR11_MASK (0x800U):DMA_ERR_ERR11_SHIFT (11U);DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK);DMA_ERR_ERR12_MASK (0x1000U);DMA_ERR_ERR12_SHIFT (12U);DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK);DMA_ERR_ERR13_MASK (0x2000U);DMA_ERR_ERR13_SHIFT (13U);DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK);DMA_ERR_ERR14_MASK (0x4000U);DMA_ERR_ERR14_SHIFT (14U);DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK);DMA_ERR_ERR15_MASK (0x8000U);DMA_ERR_ERR15_SHIFT (15U);DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK);DMA_ERR_ERR16_MASK (0x10000U);DMA_ERR_ERR16_SHIFT (16U);DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK);DMA_ERR_ERR17_MASK (0x20000U);DMA_ERR_ERR17_SHIFT (17U);DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK);DMA_ERR_ERR18_MASK (0x40000U);DMA_ERR_ERR18_SHIFT (18U);DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK);DMA_ERR_ERR19_MASK (0x80000U);DMA_ERR_ERR19_SHIFT (19U);DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK);DMA_ERR_ERR20_MASK (0x100000U);DMA_ERR_ERR20_SHIFT (20U);DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK);DMA_ERR_ERR21_MASK (0x200000U);DMA_ERR_ERR21_SHIFT (21U);DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK);DMA_ERR_ERR22_MASK (0x400000U);DMA_ERR_ERR22_SHIFT (22U);DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK);DMA_ERR_ERR23_MASK (0x800000U);DMA_ERR_ERR23_SHIFT (23U);DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK);DMA_ERR_ERR24_MASK (0x1000000U);DMA_ERR_ERR24_SHIFT (24U);DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK);DMA_ERR_ERR25_MASK (0x2000000U);DMA_ERR_ERR25_SHIFT (25U);DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK);DMA_ERR_ERR26_MASK (0x4000000U);DMA_ERR_ERR26_SHIFT (26U);DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK);DMA_ERR_ERR27_MASK (0x8000000U);DMA_ERR_ERR27_SHIFT (27U);DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK);DMA_ERR_ERR28_MASK (0x10000000U);DMA_ERR_ERR28_SHIFT (28U);DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK);DMA_ERR_ERR29_MASK (0x20000000U);DMA_ERR_ERR29_SHIFT (29U);DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK);DMA_ERR_ERR30_MASK (0x40000000U);DMA_ERR_ERR30_SHIFT (30U);DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK);DMA_ERR_ERR31_MASK (0x80000000U);DMA_ERR_ERR31_SHIFT (31U);DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK);DMA_HRS_HRS0_MASK (0x1U);DMA_HRS_HRS0_SHIFT (0U);DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK);DMA_HRS_HRS1_MASK (0x2U);DMA_HRS_HRS1_SHIFT (1U);DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK);DMA_HRS_HRS2_MASK (0x4U);DMA_HRS_HRS2_SHIFT (2U);DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK);DMA_HRS_HRS3_MASK (0x8U);DMA_HRS_HRS3_SHIFT (3U);DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK);DMA_HRS_HRS4_MASK (0x10U);DMA_HRS_HRS4_SHIFT (4U);DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK);DMA_HRS_HRS5_MASK (0x20U);DMA_HRS_HRS5_SHIFT (5U);DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK);DMA_HRS_HRS6_MASK (0x40U);DMA_HRS_HRS6_SHIFT (6U);DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK);DMA_HRS_HRS7_MASK (0x80U);DMA_HRS_HRS7_SHIFT (7U);DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK);DMA_HRS_HRS8_MASK (0x100U);DMA_HRS_HRS8_SHIFT (8U);DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK);DMA_HRS_HRS9_MASK (0x200U);DMA_HRS_HRS9_SHIFT (9U);DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK);DMA_HRS_HRS10_MASK (0x400U);DMA_HRS_HRS10_SHIFT (10U);DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK);DMA_HRS_HRS11_MASK (0x800U);DMA_HRS_HRS11_SHIFT (11U);DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK);DMA_HRS_HRS12_MASK (0x1000U);DMA_HRS_HRS12_SHIFT (12U);DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK);DMA_HRS_HRS13_MASK (0x2000U);DMA_HRS_HRS13_SHIFT (13U);DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK);DMA_HRS_HRS14_MASK (0x4000U);DMA_HRS_HRS14_SHIFT (14U);DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK);DMA_HRS_HRS15_MASK (0x8000U);DMA_HRS_HRS15_SHIFT (15U);DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK);DMA_HRS_HRS16_MASK (0x10000U);DMA_HRS_HRS16_SHIFT (16U);DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK);DMA_HRS_HRS17_MASK (0x20000U);DMA_HRS_HRS17_SHIFT (17U);DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK);DMA_HRS_HRS18_MASK (0x40000U);DMA_HRS_HRS18_SHIFT (18U);DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK);DMA_HRS_HRS19_MASK (0x80000U);DMA_HRS_HRS19_SHIFT (19U);DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK);DMA_HRS_HRS20_MASK (0x100000U);DMA_HRS_HRS20_SHIFT (20U);DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK);DMA_HRS_HRS21_MASK (0x200000U);DMA_HRS_HRS21_SHIFT (21U)DMA_DCHPRI10_CHPRI_MASK (0xFU)>DMA_DCHPRI10_CHPRI_SHIFT (0U)>DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)>DMA_DCHPRI10_GRPPRI_MASK (0x30U)>DMA_DCHPRI10_GRPPRI_SHIFT (4U)>DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)>DMA_DCHPRI10_DPA_MASK (0x40U)>DMA_DCHPRI10_DPA_SHIFT (6U)>DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)>DMA_DCHPRI10_ECP_MASK (0x80U)>DMA_DCHPRI10_ECP_SHIFT (7U)>DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)>DMA_DCHPRI9_CHPRI_MASK (0xFU)>DMA_DCHPRI9_CHPRI_SHIFT (0U)>DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)>DMA_DCHPRI9_GRPPRI_MASK (0x30U)>DMA_DCHPRI9_GRPPRI_SHIFT (4U)>DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)>DMA_DCHPRI9_DPA_MASK (0x40U)>DMA_DCHPRI9_DPA_SHIFT (6U)>DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)>DMA_DCHPRI9_ECP_MASK (0x80U)>DMA_DCHPRI9_ECP_SHIFT (7U)>DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)>DMA_DCHPRI8_CHPRI_MASK (0xFU)>DMA_DCHPRI8_CHPRI_SHIFT (0U)>DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)>DMA_DCHPRI8_GRPPRI_MASK (0x30U)>DMA_DCHPRI8_GRPPRI_SHIFT (4U)>DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)>DMA_DCHPRI8_DPA_MASK (0x40U)>DMA_DCHPRI8_DPA_SHIFT (6U)>DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)>DMA_DCHPRI8_ECP_MASK (0x80U)>DMA_DCHPRI8_ECP_SHIFT (7U)>DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)>DMA_DCHPRI15_CHPRI_MASK (0xFU)>DMA_DCHPRI15_CHPRI_SHIFT (0U)>DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)>DMA_DCHPRI15_GRPPRI_MASK (0x30U)>DMA_DCHPRI15_GRPPRI_SHIFT (4U)>DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)>DMA_DCHPRI15_DPA_MASK (0x40U)>DMA_DCHPRI15_DPA_SHIFT (6U)>DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)>DMA_DCHPRI15_ECP_MASK (0x80U)>DMA_DCHPRI15_ECP_SHIFT (7U)>DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)>DMA_DCHPRI14_CHPRI_MASK (0xFU)>DMA_DCHPRI14_CHPRI_SHIFT (0U)>DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)>DMA_DCHPRI14_GRPPRI_MASK (0x30U)>DMA_DCHPRI14_GRPPRI_SHIFT (4U)>DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)>DMA_DCHPRI14_DPA_MASK (0x40U)>DMA_DCHPRI14_DPA_SHIFT (6U)>DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)>DMA_DCHPRI14_ECP_MASK (0x80U)>DMA_DCHPRI14_ECP_SHIFT (7U)>DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)>DMA_DCHPRI13_CHPRI_MASK (0xFU)>DMA_DCHPRI13_CHPRI_SHIFT (0U)>DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)>DMA_DCHPRI13_GRPPRI_MASK (0x30U)>DMA_DCHPRI13_GRPPRI_SHIFT (4U)>DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)>DMA_DCHPRI13_DPA_MASK (0x40U)>DMA_DCHPRI13_DPA_SHIFT (6U)>DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)>DMA_DCHPRI13_ECP_MASK (0x80U)>DMA_DCHPRI13_ECP_SHIFT (7U)>DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)>DMA_DCHPRI12_CHPRI_MASK (0xFU)>DMA_DCHPRI12_CHPRI_SHIFT (0U)>DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)>DMA_DCHPRI12_GRPPRI_MASK (0x30U)>DMA_DCHPRI12_GRPPRI_SHIFT (4U)>DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)>DMA_DCHPRI12_DPA_MASK (0x40U)>DMA_DCHPRI12_DPA_SHIFT (6U)>DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)>DMA_DCHPRI12_ECP_MASK (0x80U)>DMA_DCHPRI12_ECP_SHIFT (7U)>DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)>DMA_DCHPRI19_CHPRI_MASK (0xFU)>DMA_DCHPRI19_CHPRI_SHIFT (0U)>DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)>DMA_DCHPRI19_GRPPRI_MASK (0x30U)>DMA_DCHPRI19_GRPPRI_SHIFT (4U)>DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)>DMA_DCHPRI19_DPA_MASK (0x40U)>DMA_DCHPRI19_DPA_SHIFT (6U)>DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)>DMA_DCHPRI19_ECP_MASK (0x80U)>DMA_DCHPRI19_ECP_SHIFT (7U)>DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)>DMA_DCHPRI18_CHPRI_MASK (0xFU)>DMA_DCHPRI18_CHPRI_SHIFT (0U)>DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)>DMA_DCHPRI18_GRPPRI_MASK (0x30U)>DMA_DCHPRI18_GRPPRI_SHIFT (4U)>DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)>DMA_DCHPRI18_DPA_MASK (0x40U)>DMA_DCHPRI18_DPA_SHIFT (6U)>DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)>DMA_DCHPRI18_ECP_MASK (0x80U)>DMA_DCHPRI18_ECP_SHIFT (7U)>DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)>DMA_DCHPRI17_CHPRI_MASK (0xFU)?DMA_DCHPRI17_CHPRI_SHIFT (0U)?DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)?DMA_DCHPRI17_GRPPRI_MASK (0x30U)?DMA_DCHPRI17_GRPPRI_SHIFT (4U)?DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)?DMA_DCHPRI17_DPA_MASK (0x40U)?DMA_DCHPRI17_DPA_SHIFT (6U)?DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)?DMA_DCHPRI17_ECP_MASK (0x80U)?DMA_DCHPRI17_ECP_SHIFT (7U)?DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)?DMA_DCHPRI16_CHPRI_MASK (0xFU)?DMA_DCHPRI16_CHPRI_SHIFT (0U)?DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)?DMA_DCHPRI16_GRPPRI_MASK (0x30U)?DMA_DCHPRI16_GRPPRI_SHIFT (4U)?DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)?DMA_DCHPRI16_DPA_MASK (0x40U)?DMA_DCHPRI16_DPA_SHIFT (6U)?DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)?DMA_DCHPRI16_ECP_MASK (0x80U)?DMA_DCHPRI16_ECP_SHIFT (7U)?DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)?DMA_DCHPRI23_CHPRI_MASK (0xFU)?DMA_DCHPRI23_CHPRI_SHIFT (0U)?DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)?DMA_DCHPRI23_GRPPRI_MASK (0x30U)?DMA_DCHPRI23_GRPPRI_SHIFT (4U)?DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)?DMA_DCHPRI23_DPA_MASK (0x40U)?DMA_DCHPRI23_DPA_SHIFT (6U)?DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)?DMA_DCHPRI23_ECP_MASK (0x80U)?DMA_DCHPRI23_ECP_SHIFT (7U)?DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)?DMA_DCHPRI22_CHPRI_MASK (0xFU)?DMA_DCHPRI22_CHPRI_SHIFT (0U)?DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)?DMA_DCHPRI22_GRPPRI_MASK (0x30U)?DMA_DCHPRI22_GRPPRI_SHIFT (4U)?DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)?DMA_DCHPRI22_DPA_MASK (0x40U)?DMA_DCHPRI22_DPA_SHIFT (6U)?DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)?DMA_DCHPRI22_ECP_MASK (0x80U)?DMA_DCHPRI22_ECP_SHIFT (7U)?DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)?DMA_DCHPRI21_CHPRI_MASK (0xFU)?DMA_DCHPRI21_CHPRI_SHIFT (0U)?DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)?DMA_DCHPRI21_GRPPRI_MASK (0x30U)?DMA_DCHPRI21_GRPPRI_SHIFT (4U)?DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)?DMA_DCHPRI21_DPA_MASK (0x40U)?DMA_DCHPRI21_DPA_SHIFT (6U)?DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)?DMA_DCHPRI21_ECP_MASK (0x80U)?DMA_DCHPRI21_ECP_SHIFT (7U)?DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)?DMA_DCHPRI20_CHPRI_MASK (0xFU)?DMA_DCHPRI20_CHPRI_SHIFT (0U)?DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)?DMA_DCHPRI20_GRPPRI_MASK (0x30U)?DMA_DCHPRI20_GRPPRI_SHIFT (4U)?DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)?DMA_DCHPRI20_DPA_MASK (0x40U)?DMA_DCHPRI20_DPA_SHIFT (6U)?DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)?DMA_DCHPRI20_ECP_MASK (0x80U)?DMA_DCHPRI20_ECP_SHIFT (7U)?DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)?DMA_DCHPRI27_CHPRI_MASK (0xFU)?DMA_DCHPRI27_CHPRI_SHIFT (0U)?DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)?DMA_DCHPRI27_GRPPRI_MASK (0x30U)?DMA_DCHPRI27_GRPPRI_SHIFT (4U)?DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)?DMA_DCHPRI27_DPA_MASK (0x40U)?DMA_DCHPRI27_DPA_SHIFT (6U)?DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)?DMA_DCHPRI27_ECP_MASK (0x80U)?DMA_DCHPRI27_ECP_SHIFT (7U)?DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)?DMA_DCHPRI26_CHPRI_MASK (0xFU)?DMA_DCHPRI26_CHPRI_SHIFT (0U)?DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)?DMA_DCHPRI26_GRPPRI_MASK (0x30U)?DMA_DCHPRI26_GRPPRI_SHIFT (4U)?DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)?DMA_DCHPRI26_DPA_MASK (0x40U)?DMA_DCHPRI26_DPA_SHIFT (6U)?DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)?DMA_DCHPRI26_ECP_MASK (0x80U)?DMA_DCHPRI26_ECP_SHIFT (7U)?DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)?DMA_DCHPRI25_CHPRI_MASK (0xFU)?DMA_DCHPRI25_CHPRI_SHIFT (0U)?DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)?DMA_DCHPRI25_GRPPRI_MASK (0x30U)?DMA_DCHPRI25_GRPPRI_SHIFT (4U)?DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)?DMA_DCHPRI25_DPA_MASK (0x40U)?DMA_DCHPRI25_DPA_SHIFT (6U)?DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)?DMA_DCHPRI25_ECP_MASK (0x80U)?DMA_DCHPRI25_ECP_SHIFT (7U)?DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)?DMA_DCHPRI24_CHPRI_MASK (0xFU)?DMA_DCHPRI24_CHPRI_SHIFT (0U)?DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)@DMA_DCHPRI24_GRPPRI_MASK (0x30U)@DMA_DCHPRI24_GRPPRI_SHIFT (4U)@DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)@DMA_DCHPRI24_DPA_MASK (0x40U)@DMA_DCHPRI24_DPA_SHIFT (6U)@DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)@DMA_DCHPRI24_ECP_MASK (0x80U)@DMA_DCHPRI24_ECP_SHIFT (7U)@DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)@DMA_DCHPRI31_CHPRI_MASK (0xFU)@DMA_DCHPRI31_CHPRI_SHIFT (0U)@DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)@DMA_DCHPRI31_GRPPRI_MASK (0x30U)@DMA_DCHPRI31_GRPPRI_SHIFT (4U)@DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)@DMA_DCHPRI31_DPA_MASK (0x40U)@DMA_DCHPRI31_DPA_SHIFT (6U)@DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)@DMA_DCHPRI31_ECP_MASK (0x80U)@DMA_DCHPRI31_ECP_SHIFT (7U)@DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)@DMA_DCHPRI30_CHPRI_MASK (0xFU)@DMA_DCHPRI30_CHPRI_SHIFT (0U)@DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)@DMA_DCHPRI30_GRPPRI_MASK (0x30U)@DMA_DCHPRI30_GRPPRI_SHIFT (4U)@DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)@DMA_DCHPRI30_DPA_MASK (0x40U)@DMA_DCHPRI30_DPA_SHIFT (6U)@DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)@DMA_DCHPRI30_ECP_MASK (0x80U)@DMA_DCHPRI30_ECP_SHIFT (7U)@DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)@DMA_DCHPRI29_CHPRI_MASK (0xFU)@DMA_DCHPRI29_CHPRI_SHIFT (0U)@DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)@DMA_DCHPRI29_GRPPRI_MASK (0x30U)@DMA_DCHPRI29_GRPPRI_SHIFT (4U)@DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)@DMA_DCHPRI29_DPA_MASK (0x40U)@DMA_DCHPRI29_DPA_SHIFT (6U)@DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)@DMA_DCHPRI29_ECP_MASK (0x80U)@DMA_DCHPRI29_ECP_SHIFT (7U)@DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)@DMA_DCHPRI28_CHPRI_MASK (0xFU)@DMA_DCHPRI28_CHPRI_SHIFT (0U)@DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)@DMA_DCHPRI28_GRPPRI_MASK (0x30U)@DMA_DCHPRI28_GRPPRI_SHIFT (4U)@DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)@DMA_DCHPRI28_DPA_MASK (0x40U)@DMA_DCHPRI28_DPA_SHIFT (6U)@DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)@DMA_DCHPRI28_ECP_MASK (0x80U)@DMA_DCHPRI28_ECP_SHIFT (7U)@DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)@DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)@DMA_SADDR_SADDR_SHIFT (0U)@DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)@DMA_SADDR_COUNT (32U)@DMA_SOFF_SOFF_MASK (0xFFFFU)@DMA_SOFF_SOFF_SHIFT (0U)@DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)@DMA_SOFF_COUNT (32U)@DMA_ATTR_DSIZE_MASK (0x7U)@DMA_ATTR_DSIZE_SHIFT (0U)@DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)@DMA_ATTR_DMOD_MASK (0xF8U)@DMA_ATTR_DMOD_SHIFT (3U)@DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)@DMA_ATTR_SSIZE_MASK (0x700U)@DMA_ATTR_SSIZE_SHIFT (8U)@DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)@DMA_ATTR_SMOD_MASK (0xF800U)@DMA_ATTR_SMOD_SHIFT (11U)@DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)@DMA_ATTR_COUNT (32U)@DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)@DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)@DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)@DMA_NBYTES_MLNO_COUNT (32U)@DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)@DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)@DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)@DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)@DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)@DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)@DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)@DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)@DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)@DMA_NBYTES_MLOFFNO_COUNT (32U)@DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)@DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)@DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)@DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)@DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)@DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)ADMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)ADMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)ADMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)ADMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)ADMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)ADMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)ADMA_NBYTES_MLOFFYES_COUNT (32U)ADMA_SLAST_SLAST_MASK (0xFFFFFFFFU)ADMA_SLAST_SLAST_SHIFT (0U)ADMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)ADMA_SLAST_COUNT (32U)ADMA_DADDR_DADDR_MASK (0xFFFFFFFFU)ADMA_DADDR_DADDR_SHIFT (0U)ADMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)ADMA_DADDR_COUNT (32U)ADMA_DOFF_DOFF_MASK (0xFFFFU)ADMA_DOFF_DOFF_SHIFT (0U)ADMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)ADMA_DOFF_COUNT (32U)ADMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)ADMA_CITER_ELINKNO_CITER_SHIFT (0U)ADMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)ADMA_CITER_ELINKNO_ELINK_MASK (0x8000U)ADMA_CITER_ELINKNO_ELINK_SHIFT (15U)ADMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)ADMA_CITER_ELINKNO_COUNT (32U)ADMA_CITER_ELINKYES_CITER_MASK (0x1FFU)ADMA_CITER_ELINKYES_CITER_SHIFT (0U)ADMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)ADMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)ADMA_CITER_ELINKYES_LINKCH_SHIFT (9U)ADMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)ADMA_CITER_ELINKYES_ELINK_MASK (0x8000U)ADMA_CITER_ELINKYES_ELINK_SHIFT (15U)ADMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)ADMA_CITER_ELINKYES_COUNT (32U)ADMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)ADMA_DLAST_SGA_DLASTSGA_SHIFT (0U)ADMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)ADMA_DLAST_SGA_COUNT (32U)ADMA_CSR_START_MASK (0x1U)ADMA_CSR_START_SHIFT (0U)ADMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)ADMA_CSR_INTMAJOR_MASK (0x2U)ADMA_CSR_INTMAJOR_SHIFT (1U)ADMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)ADMA_CSR_INTHALF_MASK (0x4U)ADMA_CSR_INTHALF_SHIFT (2U)ADMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)ADMA_CSR_DREQ_MASK (0x8U)ADMA_CSR_DREQ_SHIFT (3U)ADMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)ADMA_CSR_ESG_MASK (0x10U)ADMA_CSR_ESG_SHIFT (4U)ADMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)ADMA_CSR_MAJORELINK_MASK (0x20U)ADMA_CSR_MAJORELINK_SHIFT (5U)ADMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)ADMA_CSR_ACTIVE_MASK (0x40U)ADMA_CSR_ACTIVE_SHIFT (6U)ADMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)ADMA_CSR_DONE_MASK (0x80U)ADMA_CSR_DONE_SHIFT (7U)ADMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)ADMA_CSR_MAJORLINKCH_MASK (0x1F00U)ADMA_CSR_MAJORLINKCH_SHIFT (8U)ADMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)ADMA_CSR_BWC_MASK (0xC000U)ADMA_CSR_BWC_SHIFT (14U)ADMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)ADMA_CSR_COUNT (32U)ADMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)ADMA_BITER_ELINKNO_BITER_SHIFT (0U)ADMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)ADMA_BITER_ELINKNO_ELINK_MASK (0x8000U)ADMA_BITER_ELINKNO_ELINK_SHIFT (15U)ADMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)ADMA_BITER_ELINKNO_COUNT (32U)ADMA_BITER_ELINKYES_BITER_MASK (0x1FFU)ADMA_BITER_ELINKYES_BITER_SHIFT (0U)ADMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)ADMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)ADMA_BITER_ELINKYES_LINKCH_SHIFT (9U)ADMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)ADMA_BITER_ELINKYES_ELINK_MASK (0x8000U)ADMA_BITER_ELINKYES_ELINK_SHIFT (15U)ADMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)ADMA_BITER_ELINKYES_COUNT (32U)BDMA0_BASE (0x400E8000u)BDMA0 ((DMA_Type *)DMA0_BASE)BDMA_BASE_ADDRS { DMA0_BASE }BDMA_BASE_PTRS { DMA0 }BDMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }BDMA_ERROR_IRQS { DMA_ERROR_IRQn }BDMAMUX_CHCFG_SOURCE_MASK (0x7FU)BDMAMUX_CHCFG_SOURCE_SHIFT (0U)BDMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)BDMAMUX_CHCFG_A_ON_MASK (0x20000000U)BDMAMUX_CHCFG_A_ON_SHIFT (29U)BDMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)BDMAMUX_CHCFG_TRIG_MASK (0x40000000U)BDMAMUX_CHCFG_TRIG_SHIFT (30U)BDMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)BDMAMUX_CHCFG_ENBL_MASK (0x80000000U)BDMAMUX_CHCFG_ENBL_SHIFT (31U)BDMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)BDMAMUX_CHCFG_COUNT (32U)BDMAMUX_BASE (0x400EC000u)BDMAMUX ((DMAMUX_Type *)DMAMUX_BASE)BDMAMUX_BASE_ADDRS { DMAMUX_BASE }BDMAMUX_BASE_PTRS { DMAMUX }CENC_CTRL_CMPIE_MASK (0x1U)CENC_CTRL_CMPIE_SHIFT (0U)CENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)CENC_CTRL_CMPIRQ_MASK (0x2U)CENC_CTRL_CMPIRQ_SHIFT (1U)CENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)CENC_CTRL_WDE_MASK (0x4U)CENC_CTRL_WDE_SHIFT (2U)CENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)CENC_CTRL_DIE_MASK (0x8U)CENC_CTRL_DIE_SHIFT (3U)CENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)CENC_CTRL_DIRQ_MASK (0x10U)CENC_CTRL_DIRQ_SHIFT (4U)CENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)CENC_CTRL_XNE_MASK (0x20U)CENC_CTRL_XNE_SHIFT (5U)CENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)CENC_CTRL_XIP_MASK (0x40U)CENC_CTRL_XIP_SHIFT (6U)CENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)CENC_CTRL_XIE_MASK (0x80U)CENC_CTRL_XIE_SHIFT (7U)CENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)CENC_CTRL_XIRQ_MASK (0x100U)CENC_CTRL_XIRQ_SHIFT (8U)CENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)CENC_CTRL_PH1_MASK (0x200U)CENC_CTRL_PH1_SHIFT (9U)CENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)CENC_CTRL_REV_MASK (0x400U)CENC_CTRL_REV_SHIFT (10U)CENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)CENC_CTRL_SWIP_MASK (0x800U)CENC_CTRL_SWIP_SHIFT (11U)CENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)CENC_CTRL_HNE_MASK (0x1000U)CENC_CTRL_HNE_SHIFT (12U)CENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)CENC_CTRL_HIP_MASK (0x2000U)CENC_CTRL_HIP_SHIFT (13U)CENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)CENC_CTRL_HIE_MASK (0x4000U)CENC_CTRL_HIE_SHIFT (14U)CENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)CENC_CTRL_HIRQ_MASK (0x8000U)CENC_CTRL_HIRQ_SHIFT (15U)CENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)CENC_FILT_FILT_PER_MASK (0xFFU)CENC_FILT_FILT_PER_SHIFT (0U)CENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)CENC_FILT_FILT_CNT_MASK (0x700U)CENC_FILT_FILT_CNT_SHIFT (8U)CENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)CENC_WTR_WDOG_MASK (0xFFFFU)CENC_WTR_WDOG_SHIFT (0U)CENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)CENC_POSD_POSD_MASK (0xFFFFU)CENC_POSD_POSD_SHIFT (0U)CENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)CENC_POSDH_POSDH_MASK (0xFFFFU)CENC_POSDH_POSDH_SHIFT (0U)CENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)CENC_REV_REV_MASK (0xFFFFU)CENC_REV_REV_SHIFT (0U)CENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)CENC_REVH_REVH_MASK (0xFFFFU)CENC_REVH_REVH_SHIFT (0U)CENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)CENC_UPOS_POS_MASK (0xFFFFU)CENC_UPOS_POS_SHIFT (0U)CENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)CENC_LPOS_POS_MASK (0xFFFFU)CENC_LPOS_POS_SHIFT (0U)CENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)CENC_UPOSH_POSH_MASK (0xFFFFU)CENC_UPOSH_POSH_SHIFT (0U)CENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)CENC_LPOSH_POSH_MASK (0xFFFFU)CENC_LPOSH_POSH_SHIFT (0U)CENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)CENC_UINIT_INIT_MASK (0xFFFFU)CENC_UINIT_INIT_SHIFT (0U)CENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)CENC_LINIT_INIT_MASK (0xFFFFU)CENC_LINIT_INIT_SHIFT (0U)CENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)CENC_IMR_HOME_MASK (0x1U)CENC_IMR_HOME_SHIFT (0U)CENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)CENC_IMR_INDEX_MASK (0x2U)CENC_IMR_INDEX_SHIFT (1U)CENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)CENC_IMR_PHB_MASK (0x4U)CENC_IMR_PHB_SHIFT (2U)DENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)DENC_IMR_PHA_MASK (0x8U)DENC_IMR_PHA_SHIFT (3U)DENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)DENC_IMR_FHOM_MASK (0x10U)DENC_IMR_FHOM_SHIFT (4U)DENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)DENC_IMR_FIND_MASK (0x20U)DENC_IMR_FIND_SHIFT (5U)DENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)DENC_IMR_FPHB_MASK (0x40U)DENC_IMR_FPHB_SHIFT (6U)DENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)DENC_IMR_FPHA_MASK (0x80U)DENC_IMR_FPHA_SHIFT (7U)DENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)DENC_TST_TEST_COUNT_MASK (0xFFU)DENC_TST_TEST_COUNT_SHIFT (0U)DENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)DENC_TST_TEST_PERIOD_MASK (0x1F00U)DENC_TST_TEST_PERIOD_SHIFT (8U)DENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)DENC_TST_QDN_MASK (0x2000U)DENC_TST_QDN_SHIFT (13U)DENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)DENC_TST_TCE_MASK (0x4000U)DENC_TST_TCE_SHIFT (14U)DENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)DENC_TST_TEN_MASK (0x8000U)DENC_TST_TEN_SHIFT (15U)DENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)DENC_CTRL2_UPDHLD_MASK (0x1U)DENC_CTRL2_UPDHLD_SHIFT (0U)DENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)DENC_CTRL2_UPDPOS_MASK (0x2U)DENC_CTRL2_UPDPOS_SHIFT (1U)DENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)DENC_CTRL2_MOD_MASK (0x4U)DENC_CTRL2_MOD_SHIFT (2U)DENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)DENC_CTRL2_DIR_MASK (0x8U)DENC_CTRL2_DIR_SHIFT (3U)DENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)DENC_CTRL2_RUIE_MASK (0x10U)DENC_CTRL2_RUIE_SHIFT (4U)DENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)DENC_CTRL2_RUIRQ_MASK (0x20U)DENC_CTRL2_RUIRQ_SHIFT (5U)DENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)DENC_CTRL2_ROIE_MASK (0x40U)DENC_CTRL2_ROIE_SHIFT (6U)DENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)DENC_CTRL2_ROIRQ_MASK (0x80U)DENC_CTRL2_ROIRQ_SHIFT (7U)DENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)DENC_CTRL2_REVMOD_MASK (0x100U)DENC_CTRL2_REVMOD_SHIFT (8U)DENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)DENC_CTRL2_OUTCTL_MASK (0x200U)DENC_CTRL2_OUTCTL_SHIFT (9U)DENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)DENC_CTRL2_SABIE_MASK (0x400U)DENC_CTRL2_SABIE_SHIFT (10U)DENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)DENC_CTRL2_SABIRQ_MASK (0x800U)DENC_CTRL2_SABIRQ_SHIFT (11U)DENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)DENC_UMOD_MOD_MASK (0xFFFFU)DENC_UMOD_MOD_SHIFT (0U)DENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)DENC_LMOD_MOD_MASK (0xFFFFU)DENC_LMOD_MOD_SHIFT (0U)DENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)DENC_UCOMP_COMP_MASK (0xFFFFU)DENC_UCOMP_COMP_SHIFT (0U)DENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)DENC_LCOMP_COMP_MASK (0xFFFFU)DENC_LCOMP_COMP_SHIFT (0U)DENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)DENC1_BASE (0x403C8000u)DENC1 ((ENC_Type *)ENC1_BASE)DENC2_BASE (0x403CC000u)DENC2 ((ENC_Type *)ENC2_BASE)DENC3_BASE (0x403D0000u)DENC3 ((ENC_Type *)ENC3_BASE)DENC4_BASE (0x403D4000u)DENC4 ((ENC_Type *)ENC4_BASE)DENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }DENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }DENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }DENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }DENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }DENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }DENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }FENET_EIR_TS_TIMER_MASK (0x8000U)FENET_EIR_TS_TIMER_SHIFT (15U)FENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)FENET_EIR_TS_AVAIL_MASK (0x10000U)FENET_EIR_TS_AVAIL_SHIFT (16U)FENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)FENET_EIR_WAKEUP_MASK (0x20000U)FENET_EIR_WAKEUP_SHIFT (17U)FENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)FENET_EIR_PLR_MASK (0x40000U)FENET_EIR_PLR_SHIFT (18U)FENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)FENET_EIR_UN_MASK (0x80000U)FENET_EIR_UN_SHIFT (19U)FENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)FENET_EIR_RL_MASK (0x100000U)FENET_EIR_RL_SHIFT (20U)FENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)FENET_EIR_LC_MASK (0x200000U)FENET_EIR_LC_SHIFT (21U)FENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)FENET_EIR_EBERR_MASK (0x400000U)FENET_EIR_EBERR_SHIFT (22U)FENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)FENET_EIR_MII_MASK (0x800000U)FENET_EIR_MII_SHIFT (23U)FENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)FENET_EIR_RXB_MASK (0x1000000U)FENET_EIR_RXB_SHIFT (24U)FENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)FENET_EIR_RXF_MASK (0x2000000U)FENET_EIR_RXF_SHIFT (25U)FENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)FENET_EIR_TXB_MASK (0x4000000U)FENET_EIR_TXB_SHIFT (26U)FENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)FENET_EIR_TXF_MASK (0x8000000U)FENET_EIR_TXF_SHIFT (27U)FENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)FENET_EIR_GRA_MASK (0x10000000U)FENET_EIR_GRA_SHIFT (28U)FENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)FENET_EIR_BABT_MASK (0x20000000U)FENET_EIR_BABT_SHIFT (29U)FENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)FENET_EIR_BABR_MASK (0x40000000U)FENET_EIR_BABR_SHIFT (30U)FENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)FENET_EIMR_TS_TIMER_MASK (0x8000U)FENET_EIMR_TS_TIMER_SHIFT (15U)FENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)FENET_EIMR_TS_AVAIL_MASK (0x10000U)FENET_EIMR_TS_AVAIL_SHIFT (16U)FENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)FENET_EIMR_WAKEUP_MASK (0x20000U)FENET_EIMR_WAKEUP_SHIFT (17U)FENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)FENET_EIMR_PLR_MASK (0x40000U)FENET_EIMR_PLR_SHIFT (18U)FENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)FENET_EIMR_UN_MASK (0x80000U)FENET_EIMR_UN_SHIFT (19U)FENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)FENET_EIMR_RL_MASK (0x100000U)FENET_EIMR_RL_SHIFT (20U)FENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)FENET_EIMR_LC_MASK (0x200000U)FENET_EIMR_LC_SHIFT (21U)FENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)FENET_EIMR_EBERR_MASK (0x400000U)FENET_EIMR_EBERR_SHIFT (22U)FENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)FENET_EIMR_MII_MASK (0x800000U)FENET_EIMR_MII_SHIFT (23U)FENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)FENET_EIMR_RXB_MASK (0x1000000U)FENET_EIMR_RXB_SHIFT (24U)FENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)FENET_EIMR_RXF_MASK (0x2000000U)FENET_EIMR_RXF_SHIFT (25U)FENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)FENET_EIMR_TXB_MASK (0x4000000U)FENET_EIMR_TXB_SHIFT (26U)FENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)FENET_EIMR_TXF_MASK (0x8000000U)FENET_EIMR_TXF_SHIFT (27U)FENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)FENET_EIMR_GRA_MASK (0x10000000U)FENET_EIMR_GRA_SHIFT (28U)FENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)FENET_EIMR_BABT_MASK (0x20000000U)FENET_EIMR_BABT_SHIFT (29U)FENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)FENET_EIMR_BABR_MASK (0x40000000U)FENET_EIMR_BABR_SHIFT (30U)FENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)FENET_RDAR_RDAR_MASK (0x1000000U)FENET_RDAR_RDAR_SHIFT (24U)FENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)FENET_TDAR_TDAR_MASK (0x1000000U)FENET_TDAR_TDAR_SHIFT (24U)FENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)FENET_ECR_RESET_MASK (0x1U)FENET_ECR_RESET_SHIFT (0U)GENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)GENET_ECR_ETHEREN_MASK (0x2U)GENET_ECR_ETHEREN_SHIFT (1U)GENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)GENET_ECR_MAGICEN_MASK (0x4U)GENET_ECR_MAGICEN_SHIFT (2U)GENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)GENET_ECR_SLEEP_MASK (0x8U)GENET_ECR_SLEEP_SHIFT (3U)GENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)GENET_ECR_EN1588_MASK (0x10U)GENET_ECR_EN1588_SHIFT (4U)GENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)GENET_ECR_DBGEN_MASK (0x40U)GENET_ECR_DBGEN_SHIFT (6U)GENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)GENET_ECR_DBSWP_MASK (0x100U)GENET_ECR_DBSWP_SHIFT (8U)GENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)GENET_MMFR_DATA_MASK (0xFFFFU)GENET_MMFR_DATA_SHIFT (0U)GENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)GENET_MMFR_TA_MASK (0x30000U)GENET_MMFR_TA_SHIFT (16U)GENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)GENET_MMFR_RA_MASK (0x7C0000U)GENET_MMFR_RA_SHIFT (18U)GENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)GENET_MMFR_PA_MASK (0xF800000U)GENET_MMFR_PA_SHIFT (23U)GENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)GENET_MMFR_OP_MASK (0x30000000U)GENET_MMFR_OP_SHIFT (28U)GENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)GENET_MMFR_ST_MASK (0xC0000000U)GENET_MMFR_ST_SHIFT (30U)GENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)GENET_MSCR_MII_SPEED_MASK (0x7EU)GENET_MSCR_MII_SPEED_SHIFT (1U)GENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)GENET_MSCR_DIS_PRE_MASK (0x80U)GENET_MSCR_DIS_PRE_SHIFT (7U)GENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)GENET_MSCR_HOLDTIME_MASK (0x700U)GENET_MSCR_HOLDTIME_SHIFT (8U)GENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)GENET_MIBC_MIB_CLEAR_MASK (0x20000000U)GENET_MIBC_MIB_CLEAR_SHIFT (29U)GENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)GENET_MIBC_MIB_IDLE_MASK (0x40000000U)GENET_MIBC_MIB_IDLE_SHIFT (30U)GENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)GENET_MIBC_MIB_DIS_MASK (0x80000000U)GENET_MIBC_MIB_DIS_SHIFT (31U)GENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)GENET_RCR_LOOP_MASK (0x1U)GENET_RCR_LOOP_SHIFT (0U)GENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)GENET_RCR_DRT_MASK (0x2U)GENET_RCR_DRT_SHIFT (1U)GENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)GENET_RCR_MII_MODE_MASK (0x4U)GENET_RCR_MII_MODE_SHIFT (2U)GENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)GENET_RCR_PROM_MASK (0x8U)GENET_RCR_PROM_SHIFT (3U)GENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)GENET_RCR_BC_REJ_MASK (0x10U)GENET_RCR_BC_REJ_SHIFT (4U)GENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)GENET_RCR_FCE_MASK (0x20U)GENET_RCR_FCE_SHIFT (5U)GENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)GENET_RCR_RMII_MODE_MASK (0x100U)GENET_RCR_RMII_MODE_SHIFT (8U)GENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)GENET_RCR_RMII_10T_MASK (0x200U)GENET_RCR_RMII_10T_SHIFT (9U)GENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)GENET_RCR_PADEN_MASK (0x1000U)GENET_RCR_PADEN_SHIFT (12U)GENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)GENET_RCR_PAUFWD_MASK (0x2000U)GENET_RCR_PAUFWD_SHIFT (13U)GENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)GENET_RCR_CRCFWD_MASK (0x4000U)GENET_RCR_CRCFWD_SHIFT (14U)GENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)GENET_RCR_CFEN_MASK (0x8000U)GENET_RCR_CFEN_SHIFT (15U)GENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)GENET_RCR_MAX_FL_MASK (0x3FFF0000U)GENET_RCR_MAX_FL_SHIFT (16U)GENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)GENET_RCR_NLC_MASK (0x40000000U)GENET_RCR_NLC_SHIFT (30U)GENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)GENET_RCR_GRS_MASK (0x80000000U)GENET_RCR_GRS_SHIFT (31U)GENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)GENET_TCR_GTS_MASK (0x1U)GENET_TCR_GTS_SHIFT (0U)GENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)GENET_TCR_FDEN_MASK (0x4U)GENET_TCR_FDEN_SHIFT (2U)GENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)GENET_TCR_TFC_PAUSE_MASK (0x8U)GENET_TCR_TFC_PAUSE_SHIFT (3U)GENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)GENET_TCR_RFC_PAUSE_MASK (0x10U)GENET_TCR_RFC_PAUSE_SHIFT (4U)GENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)GENET_TCR_ADDSEL_MASK (0xE0U)GENET_TCR_ADDSEL_SHIFT (5U)GENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)GENET_TCR_ADDINS_MASK (0x100U)GENET_TCR_ADDINS_SHIFT (8U)GENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)HENET_TCR_CRCFWD_MASK (0x200U)HENET_TCR_CRCFWD_SHIFT (9U)HENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)HENET_PALR_PADDR1_MASK (0xFFFFFFFFU)HENET_PALR_PADDR1_SHIFT (0U)HENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)HENET_PAUR_TYPE_MASK (0xFFFFU)HENET_PAUR_TYPE_SHIFT (0U)HENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)HENET_PAUR_PADDR2_MASK (0xFFFF0000U)HENET_PAUR_PADDR2_SHIFT (16U)HENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)HENET_OPD_PAUSE_DUR_MASK (0xFFFFU)HENET_OPD_PAUSE_DUR_SHIFT (0U)HENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)HENET_OPD_OPCODE_MASK (0xFFFF0000U)HENET_OPD_OPCODE_SHIFT (16U)HENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)HENET_TXIC_ICTT_MASK (0xFFFFU)HENET_TXIC_ICTT_SHIFT (0U)HENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)HENET_TXIC_ICFT_MASK (0xFF00000U)HENET_TXIC_ICFT_SHIFT (20U)HENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)HENET_TXIC_ICCS_MASK (0x40000000U)HENET_TXIC_ICCS_SHIFT (30U)HENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)HENET_TXIC_ICEN_MASK (0x80000000U)HENET_TXIC_ICEN_SHIFT (31U)HENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)HENET_RXIC_ICTT_MASK (0xFFFFU)HENET_RXIC_ICTT_SHIFT (0U)HENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)HENET_RXIC_ICFT_MASK (0xFF00000U)HENET_RXIC_ICFT_SHIFT (20U)HENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)HENET_RXIC_ICCS_MASK (0x40000000U)HENET_RXIC_ICCS_SHIFT (30U)HENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)HENET_RXIC_ICEN_MASK (0x80000000U)HENET_RXIC_ICEN_SHIFT (31U)HENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)HENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)HENET_IAUR_IADDR1_SHIFT (0U)HENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)HENET_IALR_IADDR2_MASK (0xFFFFFFFFU)HENET_IALR_IADDR2_SHIFT (0U)HENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)HENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)HENET_GAUR_GADDR1_SHIFT (0U)HENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)HENET_GALR_GADDR2_MASK (0xFFFFFFFFU)HENET_GALR_GADDR2_SHIFT (0U)HENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)HENET_TFWR_TFWR_MASK (0x3FU)HENET_TFWR_TFWR_SHIFT (0U)HENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)HENET_TFWR_STRFWD_MASK (0x100U)HENET_TFWR_STRFWD_SHIFT (8U)HENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)HENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)HENET_RDSR_R_DES_START_SHIFT (3U)HENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)HENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)HENET_TDSR_X_DES_START_SHIFT (3U)HENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)HENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)HENET_MRBR_R_BUF_SIZE_SHIFT (4U)HENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)HENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)HENET_RSFL_RX_SECTION_FULL_SHIFT (0U)HENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)HENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)HENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)HENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)HENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)HENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)HENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)HENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)HENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)HENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)HENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)HENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)HENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)HENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)HENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)HENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)HENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)HENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)HENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)IENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)IENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)IENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)IENET_TIPG_IPG_MASK (0x1FU)IENET_TIPG_IPG_SHIFT (0U)IENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)IENET_FTRL_TRUNC_FL_MASK (0x3FFFU)IENET_FTRL_TRUNC_FL_SHIFT (0U)IENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)IENET_TACC_SHIFT16_MASK (0x1U)IENET_TACC_SHIFT16_SHIFT (0U)IENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)IENET_TACC_IPCHK_MASK (0x8U)IENET_TACC_IPCHK_SHIFT (3U)IENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)IENET_TACC_PROCHK_MASK (0x10U)IENET_TACC_PROCHK_SHIFT (4U)IENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)IENET_RACC_PADREM_MASK (0x1U)IENET_RACC_PADREM_SHIFT (0U)IENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)IENET_RACC_IPDIS_MASK (0x2U)IENET_RACC_IPDIS_SHIFT (1U)IENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)IENET_RACC_PRODIS_MASK (0x4U)IENET_RACC_PRODIS_SHIFT (2U)IENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)IENET_RACC_LINEDIS_MASK (0x40U)IENET_RACC_LINEDIS_SHIFT (6U)IENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)IENET_RACC_SHIFT16_MASK (0x80U)IENET_RACC_SHIFT16_SHIFT (7U)IENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)IENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)IENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)IENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)IENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)IENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)IENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)IENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)IENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)IENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)IENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)IENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)IENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)IENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)IENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)IENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_JAB_TXPKTS_SHIFT (0U)IENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)IENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_COL_TXPKTS_SHIFT (0U)IENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)IENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P64_TXPKTS_SHIFT (0U)IENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)IENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)IENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)IENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)IENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)IENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)IENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)IENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)IENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)IENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)IENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)IENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)IENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)IENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)IENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)IENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)IENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)JENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)JENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)JENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)JENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)JENET_IEEE_T_1COL_COUNT_SHIFT (0U)JENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)JENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)JENET_IEEE_T_MCOL_COUNT_SHIFT (0U)JENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)JENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)JENET_IEEE_T_DEF_COUNT_SHIFT (0U)JENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)JENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)JENET_IEEE_T_LCOL_COUNT_SHIFT (0U)JENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)JENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)JENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)JENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)JENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)JENET_IEEE_T_MACERR_COUNT_SHIFT (0U)JENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)JENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)JENET_IEEE_T_CSERR_COUNT_SHIFT (0U)JENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)JENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)JENET_IEEE_T_SQE_COUNT_SHIFT (0U)JENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)JENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)JENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)JENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)JENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)JENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)JENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)JENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)JENET_RMON_R_PACKETS_COUNT_SHIFT (0U)JENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)JENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)JENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)JENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)JENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)JENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)JENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)JENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)JENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)JENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)JENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)JENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)JENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)JENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)JENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)JENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)JENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)JENET_RMON_R_FRAG_COUNT_SHIFT (0U)JENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)JENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)JENET_RMON_R_JAB_COUNT_SHIFT (0U)JENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)JENET_RMON_R_P64_COUNT_MASK (0xFFFFU)JENET_RMON_R_P64_COUNT_SHIFT (0U)JENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)JENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)JENET_RMON_R_P65TO127_COUNT_SHIFT (0U)JENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)JENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)JENET_RMON_R_P128TO255_COUNT_SHIFT (0U)JENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)JENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)JENET_RMON_R_P256TO511_COUNT_SHIFT (0U)JENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)JENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)JENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)JENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)JENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)JENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)JENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)JENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)KENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)KENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)KENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)KENET_RMON_R_OCTETS_COUNT_SHIFT (0U)KENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)KENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)KENET_IEEE_R_DROP_COUNT_SHIFT (0U)KENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)KENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)KENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)KENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)KENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)KENET_IEEE_R_CRC_COUNT_SHIFT (0U)KENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)KENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)KENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)KENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)KENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)KENET_IEEE_R_MACERR_COUNT_SHIFT (0U)KENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)KENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)KENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)KENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)KENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)KENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)KENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)KENET_ATCR_EN_MASK (0x1U)KENET_ATCR_EN_SHIFT (0U)KENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)KENET_ATCR_OFFEN_MASK (0x4U)KENET_ATCR_OFFEN_SHIFT (2U)KENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)KENET_ATCR_OFFRST_MASK (0x8U)KENET_ATCR_OFFRST_SHIFT (3U)KENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)KENET_ATCR_PEREN_MASK (0x10U)KENET_ATCR_PEREN_SHIFT (4U)KENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)KENET_ATCR_PINPER_MASK (0x80U)KENET_ATCR_PINPER_SHIFT (7U)KENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)KENET_ATCR_RESTART_MASK (0x200U)KENET_ATCR_RESTART_SHIFT (9U)KENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)KENET_ATCR_CAPTURE_MASK (0x800U)KENET_ATCR_CAPTURE_SHIFT (11U)KENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)KENET_ATCR_SLAVE_MASK (0x2000U)KENET_ATCR_SLAVE_SHIFT (13U)KENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)KENET_ATVR_ATIME_MASK (0xFFFFFFFFU)KENET_ATVR_ATIME_SHIFT (0U)KENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)KENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)KENET_ATOFF_OFFSET_SHIFT (0U)KENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)KENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)KENET_ATPER_PERIOD_SHIFT (0U)KENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)KENET_ATCOR_COR_MASK (0x7FFFFFFFU)KENET_ATCOR_COR_SHIFT (0U)KENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)KENET_ATINC_INC_MASK (0x7FU)KENET_ATINC_INC_SHIFT (0U)KENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)KENET_ATINC_INC_CORR_MASK (0x7F00U)KENET_ATINC_INC_CORR_SHIFT (8U)KENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)KENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)KENET_ATSTMP_TIMESTAMP_SHIFT (0U)KENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)KENET_TGSR_TF0_MASK (0x1U)KENET_TGSR_TF0_SHIFT (0U)KENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)KENET_TGSR_TF1_MASK (0x2U)KENET_TGSR_TF1_SHIFT (1U)KENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)KENET_TGSR_TF2_MASK (0x4U)KENET_TGSR_TF2_SHIFT (2U)KENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)KENET_TGSR_TF3_MASK (0x8U)KENET_TGSR_TF3_SHIFT (3U)KENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)KENET_TCSR_TDRE_MASK (0x1U)KENET_TCSR_TDRE_SHIFT (0U)KENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)KENET_TCSR_TMODE_MASK (0x3CU)KENET_TCSR_TMODE_SHIFT (2U)KENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)KENET_TCSR_TIE_MASK (0x40U)KENET_TCSR_TIE_SHIFT (6U)KENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)KENET_TCSR_TF_MASK (0x80U)KENET_TCSR_TF_SHIFT (7U)LENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)LENET_TCSR_TPWC_MASK (0xF800U)LENET_TCSR_TPWC_SHIFT (11U)LENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)LENET_TCSR_COUNT (4U)LENET_TCCR_TCC_MASK (0xFFFFFFFFU)LENET_TCCR_TCC_SHIFT (0U)LENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)LENET_TCCR_COUNT (4U)LENET_BASE (0x402D8000u)LENET ((ENET_Type *)ENET_BASE)LENET_BASE_ADDRS { ENET_BASE }LENET_BASE_PTRS { ENET }LENET_Transmit_IRQS { ENET_IRQn }LENET_Receive_IRQS { ENET_IRQn }LENET_Error_IRQS { ENET_IRQn }LENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }LENET_BUFF_ALIGNMENT (64U)LEWM_CTRL_EWMEN_MASK (0x1U)LEWM_CTRL_EWMEN_SHIFT (0U)LEWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)LEWM_CTRL_ASSIN_MASK (0x2U)LEWM_CTRL_ASSIN_SHIFT (1U)LEWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)LEWM_CTRL_INEN_MASK (0x4U)LEWM_CTRL_INEN_SHIFT (2U)LEWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)LEWM_CTRL_INTEN_MASK (0x8U)LEWM_CTRL_INTEN_SHIFT (3U)LEWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)LEWM_SERV_SERVICE_MASK (0xFFU)LEWM_SERV_SERVICE_SHIFT (0U)LEWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)LEWM_CMPL_COMPAREL_MASK (0xFFU)LEWM_CMPL_COMPAREL_SHIFT (0U)LEWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)LEWM_CMPH_COMPAREH_MASK (0xFFU)LEWM_CMPH_COMPAREH_SHIFT (0U)LEWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)LEWM_CLKCTRL_CLKSEL_MASK (0x3U)LEWM_CLKCTRL_CLKSEL_SHIFT (0U)LEWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)LEWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)LEWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)LEWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)LEWM_BASE (0x400B4000u)LEWM ((EWM_Type *)EWM_BASE)LEWM_BASE_ADDRS { EWM_BASE }LEWM_BASE_PTRS { EWM }MEWM_IRQS { EWM_IRQn }MFLEXIO_VERID_FEATURE_MASK (0xFFFFU)MFLEXIO_VERID_FEATURE_SHIFT (0U)MFLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)MFLEXIO_VERID_MINOR_MASK (0xFF0000U)MFLEXIO_VERID_MINOR_SHIFT (16U)MFLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)MFLEXIO_VERID_MAJOR_MASK (0xFF000000U)MFLEXIO_VERID_MAJOR_SHIFT (24U)MFLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)MFLEXIO_PARAM_SHIFTER_MASK (0xFFU)MFLEXIO_PARAM_SHIFTER_SHIFT (0U)MFLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)MFLEXIO_PARAM_TIMER_MASK (0xFF00U)MFLEXIO_PARAM_TIMER_SHIFT (8U)MFLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)MFLEXIO_PARAM_PIN_MASK (0xFF0000U)MFLEXIO_PARAM_PIN_SHIFT (16U)MFLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)MFLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)MFLEXIO_PARAM_TRIGGER_SHIFT (24U)MFLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)MFLEXIO_CTRL_FLEXEN_MASK (0x1U)MFLEXIO_CTRL_FLEXEN_SHIFT (0U)MFLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)MFLEXIO_CTRL_SWRST_MASK (0x2U)MFLEXIO_CTRL_SWRST_SHIFT (1U)MFLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)MFLEXIO_CTRL_FASTACC_MASK (0x4U)MFLEXIO_CTRL_FASTACC_SHIFT (2U)MFLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)MFLEXIO_CTRL_DBGE_MASK (0x40000000U)MFLEXIO_CTRL_DBGE_SHIFT (30U)MFLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)MFLEXIO_CTRL_DOZEN_MASK (0x80000000U)MFLEXIO_CTRL_DOZEN_SHIFT (31U)MFLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)MFLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)MFLEXIO_PIN_PDI_SHIFT (0U)MFLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)MFLEXIO_SHIFTSTAT_SSF_MASK (0xFU)MFLEXIO_SHIFTSTAT_SSF_SHIFT (0U)MFLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)MFLEXIO_SHIFTERR_SEF_MASK (0xFU)MFLEXIO_SHIFTERR_SEF_SHIFT (0U)MFLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)MFLEXIO_TIMSTAT_TSF_MASK (0xFU)MFLEXIO_TIMSTAT_TSF_SHIFT (0U)NFLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)NFLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)NFLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)NFLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)NFLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)NFLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)NFLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)NFLEXIO_TIMIEN_TEIE_MASK (0xFU)NFLEXIO_TIMIEN_TEIE_SHIFT (0U)NFLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)NFLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)NFLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)NFLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)NFLEXIO_SHIFTSTATE_STATE_MASK (0x7U)NFLEXIO_SHIFTSTATE_STATE_SHIFT (0U)NFLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)NFLEXIO_SHIFTCTL_SMOD_MASK (0x7U)NFLEXIO_SHIFTCTL_SMOD_SHIFT (0U)NFLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)NFLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)NFLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)NFLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)NFLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)NFLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)NFLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)NFLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)NFLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)NFLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)NFLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)NFLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)NFLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)NFLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)NFLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)NFLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)NFLEXIO_SHIFTCTL_COUNT (4U)NFLEXIO_SHIFTCFG_SSTART_MASK (0x3U)NFLEXIO_SHIFTCFG_SSTART_SHIFT (0U)NFLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)NFLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)NFLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)NFLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)NFLEXIO_SHIFTCFG_INSRC_MASK (0x100U)NFLEXIO_SHIFTCFG_INSRC_SHIFT (8U)NFLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)NFLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)NFLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)NFLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)NFLEXIO_SHIFTCFG_COUNT (4U)NFLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)NFLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)NFLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)NFLEXIO_SHIFTBUF_COUNT (4U)NFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)NFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)NFLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)NFLEXIO_SHIFTBUFBIS_COUNT (4U)NFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)NFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)NFLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)NFLEXIO_SHIFTBUFBYS_COUNT (4U)NFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)NFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)NFLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)NFLEXIO_SHIFTBUFBBS_COUNT (4U)NFLEXIO_TIMCTL_TIMOD_MASK (0x3U)NFLEXIO_TIMCTL_TIMOD_SHIFT (0U)NFLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)NFLEXIO_TIMCTL_PINPOL_MASK (0x80U)NFLEXIO_TIMCTL_PINPOL_SHIFT (7U)NFLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)NFLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)NFLEXIO_TIMCTL_PINSEL_SHIFT (8U)NFLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)NFLEXIO_TIMCTL_PINCFG_MASK (0x30000U)NFLEXIO_TIMCTL_PINCFG_SHIFT (16U)NFLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)NFLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)NFLEXIO_TIMCTL_TRGSRC_SHIFT (22U)NFLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)NFLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)NFLEXIO_TIMCTL_TRGPOL_SHIFT (23U)NFLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)NFLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)NFLEXIO_TIMCTL_TRGSEL_SHIFT (24U)NFLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)NFLEXIO_TIMCTL_COUNT (4U)NFLEXIO_TIMCFG_TSTART_MASK (0x2U)NFLEXIO_TIMCFG_TSTART_SHIFT (1U)OFLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)OFLEXIO_TIMCFG_TSTOP_MASK (0x30U)OFLEXIO_TIMCFG_TSTOP_SHIFT (4U)OFLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)OFLEXIO_TIMCFG_TIMENA_MASK (0x700U)OFLEXIO_TIMCFG_TIMENA_SHIFT (8U)OFLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)OFLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)OFLEXIO_TIMCFG_TIMDIS_SHIFT (12U)OFLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)OFLEXIO_TIMCFG_TIMRST_MASK (0x70000U)OFLEXIO_TIMCFG_TIMRST_SHIFT (16U)OFLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)OFLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)OFLEXIO_TIMCFG_TIMDEC_SHIFT (20U)OFLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)OFLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)OFLEXIO_TIMCFG_TIMOUT_SHIFT (24U)OFLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)OFLEXIO_TIMCFG_COUNT (4U)OFLEXIO_TIMCMP_CMP_MASK (0xFFFFU)OFLEXIO_TIMCMP_CMP_SHIFT (0U)OFLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)OFLEXIO_TIMCMP_COUNT (4U)OFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)OFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)OFLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)OFLEXIO_SHIFTBUFNBS_COUNT (4U)OFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)OFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)OFLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)OFLEXIO_SHIFTBUFHWS_COUNT (4U)OFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)OFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)OFLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)OFLEXIO_SHIFTBUFNIS_COUNT (4U)OFLEXIO1_BASE (0x401AC000u)OFLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)OFLEXIO2_BASE (0x401B0000u)OFLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)OFLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }OFLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }OFLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }OFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)OFLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)OFLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)OFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)OFLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)OFLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)OFLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)OFLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)OFLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)OFLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U)OFLEXRAM_TCM_CTRL_Reserved_SHIFT (3U)OFLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)OFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)OFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)PFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)PFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU)PFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)PFLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)PFLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)PFLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U)PFLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)PFLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)PFLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)PFLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U)PFLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)PFLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)PFLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)PFLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U)PFLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)PFLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U)PFLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)PFLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)PFLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U)PFLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)PFLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)PFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)PFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)PFLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)PFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)PFLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)PFLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)PFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)PFLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)PFLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)PFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)PFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)PFLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)PFLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U)PFLEXRAM_INT_STATUS_Reserved_SHIFT (6U)PFLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)PFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)PFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)PFLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)PFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)PFLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)PFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)PFLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)PFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)PFLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)PFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)PFLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)PFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)PFLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)PFLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U)PFLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U)PFLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)PFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U)PFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)PFLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U)PFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)PFLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)PFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)PFLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)PFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)PFLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)PFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)PFLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)PFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)PFLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)PFLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U)PFLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U)PFLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)PFLEXRAM_BASE (0x400B0000u)PFLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)PFLEXRAM_BASE_ADDRS { FLEXRAM_BASE }PFLEXRAM_BASE_PTRS { FLEXRAM }PFLEXRAM_IRQS { FLEXRAM_IRQn }QFLEXSPI_MCR0_SWRESET_MASK (0x1U)QFLEXSPI_MCR0_SWRESET_SHIFT (0U)QFLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)QFLEXSPI_MCR0_MDIS_MASK (0x2U)QFLEXSPI_MCR0_MDIS_SHIFT (1U)QFLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)QFLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)QFLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)QFLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)QFLEXSPI_MCR0_ARDFEN_MASK (0x40U)QFLEXSPI_MCR0_ARDFEN_SHIFT (6U)QFLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)QFLEXSPI_MCR0_ATDFEN_MASK (0x80U)QFLEXSPI_MCR0_ATDFEN_SHIFT (7U)QFLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)QFLEXSPI_MCR0_HSEN_MASK (0x800U)QFLEXSPI_MCR0_HSEN_SHIFT (11U)QFLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)QFLEXSPI_MCR0_DOZEEN_MASK (0x1000U)QFLEXSPI_MCR0_DOZEEN_SHIFT (12U)QFLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)QFLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)QFLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)QFLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)QFLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)QFLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)QFLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)QFLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)QFLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)QFLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)QFLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)QFLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)QFLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)QFLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)QFLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)QFLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)QFLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)QFLEXSPI_MCR1_SEQWAIT_SHIFT (16U)QFLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)QFLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)QFLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)QFLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)QFLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)QFLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)QFLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)QFLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)QFLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)QFLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)QFLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)QFLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)QFLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)QFLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)QFLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)QFLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)QFLEXSPI_AHBCR_APAREN_MASK (0x1U)QFLEXSPI_AHBCR_APAREN_SHIFT (0U)QFLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)QFLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)QFLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)QFLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)QFLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)QFLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)QFLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)QFLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)QFLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)QFLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)QFLEXSPI_AHBCR_READADDROPT_MASK (0x40U)QFLEXSPI_AHBCR_READADDROPT_SHIFT (6U)QFLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)RFLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)RFLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)RFLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)RFLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)RFLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)RFLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)RFLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)RFLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)RFLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)RFLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)RFLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)RFLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)RFLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)RFLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)RFLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)RFLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)RFLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)RFLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)RFLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)RFLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)RFLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)RFLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)RFLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)RFLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)RFLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)RFLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)RFLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)RFLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)RFLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)RFLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)RFLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)RFLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)RFLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)RFLEXSPI_INTR_IPCMDDONE_MASK (0x1U)RFLEXSPI_INTR_IPCMDDONE_SHIFT (0U)RFLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)RFLEXSPI_INTR_IPCMDGE_MASK (0x2U)RFLEXSPI_INTR_IPCMDGE_SHIFT (1U)RFLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)RFLEXSPI_INTR_AHBCMDGE_MASK (0x4U)RFLEXSPI_INTR_AHBCMDGE_SHIFT (2U)RFLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)RFLEXSPI_INTR_IPCMDERR_MASK (0x8U)RFLEXSPI_INTR_IPCMDERR_SHIFT (3U)RFLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)RFLEXSPI_INTR_AHBCMDERR_MASK (0x10U)RFLEXSPI_INTR_AHBCMDERR_SHIFT (4U)RFLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)RFLEXSPI_INTR_IPRXWA_MASK (0x20U)RFLEXSPI_INTR_IPRXWA_SHIFT (5U)RFLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)RFLEXSPI_INTR_IPTXWE_MASK (0x40U)RFLEXSPI_INTR_IPTXWE_SHIFT (6U)RFLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)RFLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)RFLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)RFLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)RFLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)RFLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)RFLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)RFLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)RFLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)RFLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)RFLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)RFLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)RFLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)RFLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)RFLEXSPI_LUTKEY_KEY_SHIFT (0U)RFLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)RFLEXSPI_LUTCR_LOCK_MASK (0x1U)RFLEXSPI_LUTCR_LOCK_SHIFT (0U)RFLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)RFLEXSPI_LUTCR_UNLOCK_MASK (0x2U)RFLEXSPI_LUTCR_UNLOCK_SHIFT (1U)RFLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)RFLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)RFLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)RFLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)RFLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)RFLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)RFLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)RFLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)RFLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)RFLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)RFLEXSPI_AHBRXBUFCR0_COUNT (4U)RFLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)RFLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)RFLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)RFLEXSPI_FLSHCR0_COUNT (4U)RFLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)RFLEXSPI_FLSHCR1_TCSS_SHIFT (0U)RFLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)RFLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)RFLEXSPI_FLSHCR1_TCSH_SHIFT (5U)RFLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)RFLEXSPI_FLSHCR1_WA_MASK (0x400U)RFLEXSPI_FLSHCR1_WA_SHIFT (10U)RFLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)RFLEXSPI_FLSHCR1_CAS_MASK (0x7800U)RFLEXSPI_FLSHCR1_CAS_SHIFT (11U)RFLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)RFLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)RFLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)RFLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)RFLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)RFLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)RFLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)RFLEXSPI_FLSHCR1_COUNT (4U)SFLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)SFLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)SFLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)SFLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)SFLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)SFLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)SFLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)SFLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)SFLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)SFLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)SFLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)SFLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)SFLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)SFLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)SFLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)SFLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)SFLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)SFLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)SFLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)SFLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)SFLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)SFLEXSPI_FLSHCR2_COUNT (4U)SFLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)SFLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)SFLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)SFLEXSPI_FLSHCR4_WMENA_MASK (0x4U)SFLEXSPI_FLSHCR4_WMENA_SHIFT (2U)SFLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)SFLEXSPI_FLSHCR4_WMENB_MASK (0x8U)SFLEXSPI_FLSHCR4_WMENB_SHIFT (3U)SFLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)SFLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)SFLEXSPI_IPCR0_SFAR_SHIFT (0U)SFLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)SFLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)SFLEXSPI_IPCR1_IDATSZ_SHIFT (0U)SFLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)SFLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)SFLEXSPI_IPCR1_ISEQID_SHIFT (16U)SFLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)SFLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)SFLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)SFLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)SFLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)SFLEXSPI_IPCR1_IPAREN_SHIFT (31U)SFLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)SFLEXSPI_IPCMD_TRG_MASK (0x1U)SFLEXSPI_IPCMD_TRG_SHIFT (0U)SFLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)SFLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)SFLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)SFLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)SFLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)SFLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)SFLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)SFLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)SFLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)SFLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)SFLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)SFLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)SFLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)SFLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)SFLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)SFLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)SFLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)SFLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)SFLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)SFLEXSPI_DLLCR_DLLEN_MASK (0x1U)SFLEXSPI_DLLCR_DLLEN_SHIFT (0U)SFLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)SFLEXSPI_DLLCR_DLLRESET_MASK (0x2U)SFLEXSPI_DLLCR_DLLRESET_SHIFT (1U)SFLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)SFLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)SFLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)SFLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)SFLEXSPI_DLLCR_OVRDEN_MASK (0x100U)SFLEXSPI_DLLCR_OVRDEN_SHIFT (8U)SFLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)SFLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)SFLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)SFLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)SFLEXSPI_DLLCR_COUNT (2U)SFLEXSPI_STS0_SEQIDLE_MASK (0x1U)SFLEXSPI_STS0_SEQIDLE_SHIFT (0U)SFLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)SFLEXSPI_STS0_ARBIDLE_MASK (0x2U)SFLEXSPI_STS0_ARBIDLE_SHIFT (1U)SFLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)SFLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)SFLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)SFLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)SFLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)SFLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)SFLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)SFLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)SFLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)SFLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)SFLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)SFLEXSPI_STS1_IPCMDERRID_SHIFT (16U)SFLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)SFLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)SFLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)SFLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)TFLEXSPI_STS2_ASLVLOCK_MASK (0x1U)TFLEXSPI_STS2_ASLVLOCK_SHIFT (0U)TFLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)TFLEXSPI_STS2_AREFLOCK_MASK (0x2U)TFLEXSPI_STS2_AREFLOCK_SHIFT (1U)TFLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)TFLEXSPI_STS2_ASLVSEL_MASK (0xFCU)TFLEXSPI_STS2_ASLVSEL_SHIFT (2U)TFLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)TFLEXSPI_STS2_AREFSEL_MASK (0x3F00U)TFLEXSPI_STS2_AREFSEL_SHIFT (8U)TFLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)TFLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)TFLEXSPI_STS2_BSLVLOCK_SHIFT (16U)TFLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)TFLEXSPI_STS2_BREFLOCK_MASK (0x20000U)TFLEXSPI_STS2_BREFLOCK_SHIFT (17U)TFLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)TFLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)TFLEXSPI_STS2_BSLVSEL_SHIFT (18U)TFLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)TFLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)TFLEXSPI_STS2_BREFSEL_SHIFT (24U)TFLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)TFLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)TFLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)TFLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)TFLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)TFLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)TFLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)TFLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)TFLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)TFLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)TFLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)TFLEXSPI_IPRXFSTS_FILL_SHIFT (0U)TFLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)TFLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)TFLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)TFLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)TFLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)TFLEXSPI_IPTXFSTS_FILL_SHIFT (0U)TFLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)TFLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)TFLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)TFLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)TFLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)TFLEXSPI_RFDR_RXDATA_SHIFT (0U)TFLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)TFLEXSPI_RFDR_COUNT (32U)TFLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)TFLEXSPI_TFDR_TXDATA_SHIFT (0U)TFLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)TFLEXSPI_TFDR_COUNT (32U)TFLEXSPI_LUT_OPERAND0_MASK (0xFFU)TFLEXSPI_LUT_OPERAND0_SHIFT (0U)TFLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)TFLEXSPI_LUT_NUM_PADS0_MASK (0x300U)TFLEXSPI_LUT_NUM_PADS0_SHIFT (8U)TFLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)TFLEXSPI_LUT_OPCODE0_MASK (0xFC00U)TFLEXSPI_LUT_OPCODE0_SHIFT (10U)TFLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)TFLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)TFLEXSPI_LUT_OPERAND1_SHIFT (16U)TFLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)TFLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)TFLEXSPI_LUT_NUM_PADS1_SHIFT (24U)TFLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)TFLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)TFLEXSPI_LUT_OPCODE1_SHIFT (26U)TFLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)TFLEXSPI_LUT_COUNT (64U)TFLEXSPI_BASE (0x402A8000u)TFLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)TFLEXSPI_BASE_ADDRS { FLEXSPI_BASE }TFLEXSPI_BASE_PTRS { FLEXSPI }TFLEXSPI_IRQS { FLEXSPI_IRQn }TFlexSPI_AMBA_BASE (0x60000000U)TFlexSPI_ASFM_BASE (0x00000000U)TFlexSPI_ARDF_BASE (0x7FC00000U)TFlexSPI_ATDF_BASE (0x7F800000U)UGPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)UGPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)UGPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)UGPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)UGPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)UGPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)UGPC_CNTR_PDRAM0_PGE_MASK (0x400000U)UGPC_CNTR_PDRAM0_PGE_SHIFT (22U)UGPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)UGPC_IMR_IMR1_MASK (0xFFFFFFFFU)UGPC_IMR_IMR1_SHIFT (0U)UGPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)UGPC_IMR_IMR2_MASK (0xFFFFFFFFU)UGPC_IMR_IMR2_SHIFT (0U)UGPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)UGPC_IMR_IMR3_MASK (0xFFFFFFFFU)UGPC_IMR_IMR3_SHIFT (0U)UGPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)UGPC_IMR_IMR4_MASK (0xFFFFFFFFU)UGPC_IMR_IMR4_SHIFT (0U)UGPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)UGPC_IMR_COUNT (4U)UGPC_ISR_ISR1_MASK (0xFFFFFFFFU)UGPC_ISR_ISR1_SHIFT (0U)UGPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)UGPC_ISR_ISR2_MASK (0xFFFFFFFFU)UGPC_ISR_ISR2_SHIFT (0U)UGPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)UGPC_ISR_ISR3_MASK (0xFFFFFFFFU)UGPC_ISR_ISR3_SHIFT (0U)UGPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)UGPC_ISR_ISR4_MASK (0xFFFFFFFFU)UGPC_ISR_ISR4_SHIFT (0U)UGPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)UGPC_ISR_COUNT (4U)UGPC_IMR5_IMR5_MASK (0xFFFFFFFFU)UGPC_IMR5_IMR5_SHIFT (0U)UGPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)UGPC_ISR5_ISR4_MASK (0xFFFFFFFFU)UGPC_ISR5_ISR4_SHIFT (0U)UGPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)UGPC_BASE (0x400F4000u)UGPC ((GPC_Type *)GPC_BASE)UGPC_BASE_ADDRS { GPC_BASE }UGPC_BASE_PTRS { GPC }UGPC_IRQS { GPC_IRQn }VGPIO_DR_DR_MASK (0xFFFFFFFFU)VGPIO_DR_DR_SHIFT (0U)VGPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)VGPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)VGPIO_GDIR_GDIR_SHIFT (0U)VGPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)VGPIO_PSR_PSR_MASK (0xFFFFFFFFU)VGPIO_PSR_PSR_SHIFT (0U)VGPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)VGPIO_ICR1_ICR0_MASK (0x3U)VGPIO_ICR1_ICR0_SHIFT (0U)VGPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)VGPIO_ICR1_ICR1_MASK (0xCU)VGPIO_ICR1_ICR1_SHIFT (2U)VGPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)VGPIO_ICR1_ICR2_MASK (0x30U)VGPIO_ICR1_ICR2_SHIFT (4U)VGPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)VGPIO_ICR1_ICR3_MASK (0xC0U)VGPIO_ICR1_ICR3_SHIFT (6U)VGPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)VGPIO_ICR1_ICR4_MASK (0x300U)VGPIO_ICR1_ICR4_SHIFT (8U)VGPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)VGPIO_ICR1_ICR5_MASK (0xC00U)VGPIO_ICR1_ICR5_SHIFT (10U)VGPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)VGPIO_ICR1_ICR6_MASK (0x3000U)VGPIO_ICR1_ICR6_SHIFT (12U)VGPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)VGPIO_ICR1_ICR7_MASK (0xC000U)VGPIO_ICR1_ICR7_SHIFT (14U)VGPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)VGPIO_ICR1_ICR8_MASK (0x30000U)VGPIO_ICR1_ICR8_SHIFT (16U)VGPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)VGPIO_ICR1_ICR9_MASK (0xC0000U)VGPIO_ICR1_ICR9_SHIFT (18U)VGPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)VGPIO_ICR1_ICR10_MASK (0x300000U)VGPIO_ICR1_ICR10_SHIFT (20U)VGPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)VGPIO_ICR1_ICR11_MASK (0xC00000U)VGPIO_ICR1_ICR11_SHIFT (22U)VGPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)VGPIO_ICR1_ICR12_MASK (0x3000000U)VGPIO_ICR1_ICR12_SHIFT (24U)VGPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)VGPIO_ICR1_ICR13_MASK (0xC000000U)VGPIO_ICR1_ICR13_SHIFT (26U)VGPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)VGPIO_ICR1_ICR14_MASK (0x30000000U)VGPIO_ICR1_ICR14_SHIFT (28U)VGPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)VGPIO_ICR1_ICR15_MASK (0xC0000000U)VGPIO_ICR1_ICR15_SHIFT (30U)VGPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)VGPIO_ICR2_ICR16_MASK (0x3U)VGPIO_ICR2_ICR16_SHIFT (0U)VGPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)VGPIO_ICR2_ICR17_MASK (0xCU)VGPIO_ICR2_ICR17_SHIFT (2U)VGPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)VGPIO_ICR2_ICR18_MASK (0x30U)VGPIO_ICR2_ICR18_SHIFT (4U)VGPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)VGPIO_ICR2_ICR19_MASK (0xC0U)VGPIO_ICR2_ICR19_SHIFT (6U)VGPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)VGPIO_ICR2_ICR20_MASK (0x300U)VGPIO_ICR2_ICR20_SHIFT (8U)VGPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)VGPIO_ICR2_ICR21_MASK (0xC00U)VGPIO_ICR2_ICR21_SHIFT (10U)VGPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)VGPIO_ICR2_ICR22_MASK (0x3000U)VGPIO_ICR2_ICR22_SHIFT (12U)VGPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)VGPIO_ICR2_ICR23_MASK (0xC000U)VGPIO_ICR2_ICR23_SHIFT (14U)VGPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)VGPIO_ICR2_ICR24_MASK (0x30000U)VGPIO_ICR2_ICR24_SHIFT (16U)VGPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)VGPIO_ICR2_ICR25_MASK (0xC0000U)VGPIO_ICR2_ICR25_SHIFT (18U)VGPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)VGPIO_ICR2_ICR26_MASK (0x300000U)VGPIO_ICR2_ICR26_SHIFT (20U)VGPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)VGPIO_ICR2_ICR27_MASK (0xC00000U)VGPIO_ICR2_ICR27_SHIFT (22U)VGPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)VGPIO_ICR2_ICR28_MASK (0x3000000U)VGPIO_ICR2_ICR28_SHIFT (24U)VGPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)VGPIO_ICR2_ICR29_MASK (0xC000000U)VGPIO_ICR2_ICR29_SHIFT (26U)VGPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)VGPIO_ICR2_ICR30_MASK (0x30000000U)VGPIO_ICR2_ICR30_SHIFT (28U)VGPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)VGPIO_ICR2_ICR31_MASK (0xC0000000U)VGPIO_ICR2_ICR31_SHIFT (30U)VGPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)VGPIO_IMR_IMR_MASK (0xFFFFFFFFU)VGPIO_IMR_IMR_SHIFT (0U)VGPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)VGPIO_ISR_ISR_MASK (0xFFFFFFFFU)VGPIO_ISR_ISR_SHIFT (0U)WGPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)WGPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)WGPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)WGPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)WGPIO1_BASE (0x401B8000u)WGPIO1 ((GPIO_Type *)GPIO1_BASE)WGPIO2_BASE (0x401BC000u)WGPIO2 ((GPIO_Type *)GPIO2_BASE)WGPIO3_BASE (0x401C0000u)WGPIO3 ((GPIO_Type *)GPIO3_BASE)WGPIO4_BASE (0x401C4000u)WGPIO4 ((GPIO_Type *)GPIO4_BASE)WGPIO5_BASE (0x400C0000u)WGPIO5 ((GPIO_Type *)GPIO5_BASE)WGPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }WGPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }WGPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }WGPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn }WGPT_CR_EN_MASK (0x1U)WGPT_CR_EN_SHIFT (0U)WGPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)WGPT_CR_ENMOD_MASK (0x2U)WGPT_CR_ENMOD_SHIFT (1U)WGPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)WGPT_CR_DBGEN_MASK (0x4U)WGPT_CR_DBGEN_SHIFT (2U)WGPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)WGPT_CR_WAITEN_MASK (0x8U)WGPT_CR_WAITEN_SHIFT (3U)WGPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)WGPT_CR_DOZEEN_MASK (0x10U)WGPT_CR_DOZEEN_SHIFT (4U)WGPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)WGPT_CR_STOPEN_MASK (0x20U)WGPT_CR_STOPEN_SHIFT (5U)WGPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)WGPT_CR_CLKSRC_MASK (0x1C0U)WGPT_CR_CLKSRC_SHIFT (6U)WGPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)WGPT_CR_FRR_MASK (0x200U)WGPT_CR_FRR_SHIFT (9U)WGPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)WGPT_CR_EN_24M_MASK (0x400U)WGPT_CR_EN_24M_SHIFT (10U)WGPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)WGPT_CR_SWR_MASK (0x8000U)WGPT_CR_SWR_SHIFT (15U)WGPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)WGPT_CR_IM1_MASK (0x30000U)WGPT_CR_IM1_SHIFT (16U)WGPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)WGPT_CR_IM2_MASK (0xC0000U)WGPT_CR_IM2_SHIFT (18U)WGPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)WGPT_CR_OM1_MASK (0x700000U)WGPT_CR_OM1_SHIFT (20U)WGPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)WGPT_CR_OM2_MASK (0x3800000U)WGPT_CR_OM2_SHIFT (23U)WGPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)WGPT_CR_OM3_MASK (0x1C000000U)WGPT_CR_OM3_SHIFT (26U)WGPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)WGPT_CR_FO1_MASK (0x20000000U)WGPT_CR_FO1_SHIFT (29U)WGPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)WGPT_CR_FO2_MASK (0x40000000U)WGPT_CR_FO2_SHIFT (30U)WGPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)XGPT_CR_FO3_MASK (0x80000000U)XGPT_CR_FO3_SHIFT (31U)XGPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)XGPT_PR_PRESCALER_MASK (0xFFFU)XGPT_PR_PRESCALER_SHIFT (0U)XGPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)XGPT_PR_PRESCALER24M_MASK (0xF000U)XGPT_PR_PRESCALER24M_SHIFT (12U)XGPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)XGPT_SR_OF1_MASK (0x1U)XGPT_SR_OF1_SHIFT (0U)XGPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)XGPT_SR_OF2_MASK (0x2U)XGPT_SR_OF2_SHIFT (1U)XGPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)XGPT_SR_OF3_MASK (0x4U)XGPT_SR_OF3_SHIFT (2U)XGPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)XGPT_SR_IF1_MASK (0x8U)XGPT_SR_IF1_SHIFT (3U)XGPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)XGPT_SR_IF2_MASK (0x10U)XGPT_SR_IF2_SHIFT (4U)XGPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)XGPT_SR_ROV_MASK (0x20U)XGPT_SR_ROV_SHIFT (5U)XGPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)XGPT_IR_OF1IE_MASK (0x1U)XGPT_IR_OF1IE_SHIFT (0U)XGPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)XGPT_IR_OF2IE_MASK (0x2U)XGPT_IR_OF2IE_SHIFT (1U)XGPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)XGPT_IR_OF3IE_MASK (0x4U)XGPT_IR_OF3IE_SHIFT (2U)XGPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)XGPT_IR_IF1IE_MASK (0x8U)XGPT_IR_IF1IE_SHIFT (3U)XGPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)XGPT_IR_IF2IE_MASK (0x10U)XGPT_IR_IF2IE_SHIFT (4U)XGPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)XGPT_IR_ROVIE_MASK (0x20U)XGPT_IR_ROVIE_SHIFT (5U)XGPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)XGPT_OCR_COMP_MASK (0xFFFFFFFFU)XGPT_OCR_COMP_SHIFT (0U)XGPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)XGPT_OCR_COUNT (3U)XGPT_ICR_CAPT_MASK (0xFFFFFFFFU)XGPT_ICR_CAPT_SHIFT (0U)XGPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)XGPT_ICR_COUNT (2U)XGPT_CNT_COUNT_MASK (0xFFFFFFFFU)XGPT_CNT_COUNT_SHIFT (0U)XGPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)XGPT1_BASE (0x401EC000u)XGPT1 ((GPT_Type *)GPT1_BASE)XGPT2_BASE (0x401F0000u)XGPT2 ((GPT_Type *)GPT2_BASE)XGPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }XGPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }XGPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }YI2S_VERID_FEATURE_MASK (0xFFFFU)YI2S_VERID_FEATURE_SHIFT (0U)YI2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)YI2S_VERID_MINOR_MASK (0xFF0000U)YI2S_VERID_MINOR_SHIFT (16U)YI2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)YI2S_VERID_MAJOR_MASK (0xFF000000U)YI2S_VERID_MAJOR_SHIFT (24U)YI2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)YI2S_PARAM_DATALINE_MASK (0xFU)YI2S_PARAM_DATALINE_SHIFT (0U)YI2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)YI2S_PARAM_FIFO_MASK (0xF00U)YI2S_PARAM_FIFO_SHIFT (8U)YI2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)YI2S_PARAM_FRAME_MASK (0xF0000U)YI2S_PARAM_FRAME_SHIFT (16U)YI2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)YI2S_TCSR_FRDE_MASK (0x1U)YI2S_TCSR_FRDE_SHIFT (0U)YI2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)YI2S_TCSR_FWDE_MASK (0x2U)YI2S_TCSR_FWDE_SHIFT (1U)YI2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)YI2S_TCSR_FRIE_MASK (0x100U)YI2S_TCSR_FRIE_SHIFT (8U)YI2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)YI2S_TCSR_FWIE_MASK (0x200U)YI2S_TCSR_FWIE_SHIFT (9U)YI2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)YI2S_TCSR_FEIE_MASK (0x400U)YI2S_TCSR_FEIE_SHIFT (10U)YI2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)YI2S_TCSR_SEIE_MASK (0x800U)YI2S_TCSR_SEIE_SHIFT (11U)YI2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)YI2S_TCSR_WSIE_MASK (0x1000U)YI2S_TCSR_WSIE_SHIFT (12U)YI2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)YI2S_TCSR_FRF_MASK (0x10000U)YI2S_TCSR_FRF_SHIFT (16U)YI2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)YI2S_TCSR_FWF_MASK (0x20000U)YI2S_TCSR_FWF_SHIFT (17U)YI2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)YI2S_TCSR_FEF_MASK (0x40000U)YI2S_TCSR_FEF_SHIFT (18U)YI2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)YI2S_TCSR_SEF_MASK (0x80000U)YI2S_TCSR_SEF_SHIFT (19U)YI2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)YI2S_TCSR_WSF_MASK (0x100000U)YI2S_TCSR_WSF_SHIFT (20U)YI2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)YI2S_TCSR_SR_MASK (0x1000000U)YI2S_TCSR_SR_SHIFT (24U)YI2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)YI2S_TCSR_FR_MASK (0x2000000U)YI2S_TCSR_FR_SHIFT (25U)YI2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)YI2S_TCSR_BCE_MASK (0x10000000U)YI2S_TCSR_BCE_SHIFT (28U)YI2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)YI2S_TCSR_DBGE_MASK (0x20000000U)YI2S_TCSR_DBGE_SHIFT (29U)YI2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)YI2S_TCSR_STOPE_MASK (0x40000000U)YI2S_TCSR_STOPE_SHIFT (30U)YI2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)YI2S_TCSR_TE_MASK (0x80000000U)YI2S_TCSR_TE_SHIFT (31U)YI2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)YI2S_TCR1_TFW_MASK (0x1FU)YI2S_TCR1_TFW_SHIFT (0U)YI2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)YI2S_TCR2_DIV_MASK (0xFFU)YI2S_TCR2_DIV_SHIFT (0U)YI2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)YI2S_TCR2_BCD_MASK (0x1000000U)YI2S_TCR2_BCD_SHIFT (24U)YI2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)YI2S_TCR2_BCP_MASK (0x2000000U)YI2S_TCR2_BCP_SHIFT (25U)YI2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)YI2S_TCR2_MSEL_MASK (0xC000000U)YI2S_TCR2_MSEL_SHIFT (26U)YI2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)YI2S_TCR2_BCI_MASK (0x10000000U)YI2S_TCR2_BCI_SHIFT (28U)YI2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)YI2S_TCR2_BCS_MASK (0x20000000U)YI2S_TCR2_BCS_SHIFT (29U)YI2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)YI2S_TCR2_SYNC_MASK (0xC0000000U)YI2S_TCR2_SYNC_SHIFT (30U)YI2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)YI2S_TCR3_WDFL_MASK (0x1FU)YI2S_TCR3_WDFL_SHIFT (0U)ZI2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)ZI2S_TCR3_TCE_MASK (0xF0000U)ZI2S_TCR3_TCE_SHIFT (16U)ZI2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)ZI2S_TCR3_CFR_MASK (0xF000000U)ZI2S_TCR3_CFR_SHIFT (24U)ZI2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)ZI2S_TCR4_FSD_MASK (0x1U)ZI2S_TCR4_FSD_SHIFT (0U)ZI2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)ZI2S_TCR4_FSP_MASK (0x2U)ZI2S_TCR4_FSP_SHIFT (1U)ZI2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)ZI2S_TCR4_ONDEM_MASK (0x4U)ZI2S_TCR4_ONDEM_SHIFT (2U)ZI2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)ZI2S_TCR4_FSE_MASK (0x8U)ZI2S_TCR4_FSE_SHIFT (3U)ZI2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)ZI2S_TCR4_MF_MASK (0x10U)ZI2S_TCR4_MF_SHIFT (4U)ZI2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)ZI2S_TCR4_CHMOD_MASK (0x20U)ZI2S_TCR4_CHMOD_SHIFT (5U)ZI2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)ZI2S_TCR4_SYWD_MASK (0x1F00U)ZI2S_TCR4_SYWD_SHIFT (8U)ZI2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)ZI2S_TCR4_FRSZ_MASK (0x1F0000U)ZI2S_TCR4_FRSZ_SHIFT (16U)ZI2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)ZI2S_TCR4_FPACK_MASK (0x3000000U)ZI2S_TCR4_FPACK_SHIFT (24U)ZI2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)ZI2S_TCR4_FCOMB_MASK (0xC000000U)ZI2S_TCR4_FCOMB_SHIFT (26U)ZI2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)ZI2S_TCR4_FCONT_MASK (0x10000000U)ZI2S_TCR4_FCONT_SHIFT (28U)ZI2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)ZI2S_TCR5_FBT_MASK (0x1F00U)ZI2S_TCR5_FBT_SHIFT (8U)ZI2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)ZI2S_TCR5_W0W_MASK (0x1F0000U)ZI2S_TCR5_W0W_SHIFT (16U)ZI2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)ZI2S_TCR5_WNW_MASK (0x1F000000U)ZI2S_TCR5_WNW_SHIFT (24U)ZI2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)ZI2S_TDR_TDR_MASK (0xFFFFFFFFU)ZI2S_TDR_TDR_SHIFT (0U)ZI2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)ZI2S_TDR_COUNT (4U)ZI2S_TFR_RFP_MASK (0x3FU)ZI2S_TFR_RFP_SHIFT (0U)ZI2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)ZI2S_TFR_WFP_MASK (0x3F0000U)ZI2S_TFR_WFP_SHIFT (16U)ZI2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)ZI2S_TFR_WCP_MASK (0x80000000U)ZI2S_TFR_WCP_SHIFT (31U)ZI2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)ZI2S_TFR_COUNT (4U)ZI2S_TMR_TWM_MASK (0xFFFFFFFFU)ZI2S_TMR_TWM_SHIFT (0U)ZI2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)ZI2S_RCSR_FRDE_MASK (0x1U)ZI2S_RCSR_FRDE_SHIFT (0U)ZI2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)ZI2S_RCSR_FWDE_MASK (0x2U)ZI2S_RCSR_FWDE_SHIFT (1U)ZI2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)ZI2S_RCSR_FRIE_MASK (0x100U)ZI2S_RCSR_FRIE_SHIFT (8U)ZI2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)ZI2S_RCSR_FWIE_MASK (0x200U)ZI2S_RCSR_FWIE_SHIFT (9U)ZI2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)ZI2S_RCSR_FEIE_MASK (0x400U)ZI2S_RCSR_FEIE_SHIFT (10U)ZI2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)ZI2S_RCSR_SEIE_MASK (0x800U)ZI2S_RCSR_SEIE_SHIFT (11U)ZI2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)ZI2S_RCSR_WSIE_MASK (0x1000U)ZI2S_RCSR_WSIE_SHIFT (12U)ZI2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)ZI2S_RCSR_FRF_MASK (0x10000U)ZI2S_RCSR_FRF_SHIFT (16U)ZI2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)ZI2S_RCSR_FWF_MASK (0x20000U)ZI2S_RCSR_FWF_SHIFT (17U)ZI2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)ZI2S_RCSR_FEF_MASK (0x40000U)ZI2S_RCSR_FEF_SHIFT (18U)ZI2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)ZI2S_RCSR_SEF_MASK (0x80000U)ZI2S_RCSR_SEF_SHIFT (19U)ZI2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)ZI2S_RCSR_WSF_MASK (0x100000U)ZI2S_RCSR_WSF_SHIFT (20U)ZI2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)ZI2S_RCSR_SR_MASK (0x1000000U)ZI2S_RCSR_SR_SHIFT (24U)ZI2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)ZI2S_RCSR_FR_MASK (0x2000000U)ZI2S_RCSR_FR_SHIFT (25U)ZI2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)ZI2S_RCSR_BCE_MASK (0x10000000U)ZI2S_RCSR_BCE_SHIFT (28U)ZI2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)ZI2S_RCSR_DBGE_MASK (0x20000000U)[I2S_RCSR_DBGE_SHIFT (29U)[I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)[I2S_RCSR_STOPE_MASK (0x40000000U)[I2S_RCSR_STOPE_SHIFT (30U)[I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)[I2S_RCSR_RE_MASK (0x80000000U)[I2S_RCSR_RE_SHIFT (31U)[I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)[I2S_RCR1_RFW_MASK (0x1FU)[I2S_RCR1_RFW_SHIFT (0U)[I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)[I2S_RCR2_DIV_MASK (0xFFU)[I2S_RCR2_DIV_SHIFT (0U)[I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)[I2S_RCR2_BCD_MASK (0x1000000U)[I2S_RCR2_BCD_SHIFT (24U)[I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)[I2S_RCR2_BCP_MASK (0x2000000U)[I2S_RCR2_BCP_SHIFT (25U)[I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)[I2S_RCR2_MSEL_MASK (0xC000000U)[I2S_RCR2_MSEL_SHIFT (26U)[I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)[I2S_RCR2_BCI_MASK (0x10000000U)[I2S_RCR2_BCI_SHIFT (28U)[I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)[I2S_RCR2_BCS_MASK (0x20000000U)[I2S_RCR2_BCS_SHIFT (29U)[I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)[I2S_RCR2_SYNC_MASK (0xC0000000U)[I2S_RCR2_SYNC_SHIFT (30U)[I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)[I2S_RCR3_WDFL_MASK (0x1FU)[I2S_RCR3_WDFL_SHIFT (0U)[I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)[I2S_RCR3_RCE_MASK (0xF0000U)[I2S_RCR3_RCE_SHIFT (16U)[I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)[I2S_RCR3_CFR_MASK (0xF000000U)[I2S_RCR3_CFR_SHIFT (24U)[I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)[I2S_RCR4_FSD_MASK (0x1U)[I2S_RCR4_FSD_SHIFT (0U)[I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)[I2S_RCR4_FSP_MASK (0x2U)[I2S_RCR4_FSP_SHIFT (1U)[I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)[I2S_RCR4_ONDEM_MASK (0x4U)[I2S_RCR4_ONDEM_SHIFT (2U)[I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)[I2S_RCR4_FSE_MASK (0x8U)[I2S_RCR4_FSE_SHIFT (3U)[I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)[I2S_RCR4_MF_MASK (0x10U)[I2S_RCR4_MF_SHIFT (4U)[I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)[I2S_RCR4_SYWD_MASK (0x1F00U)[I2S_RCR4_SYWD_SHIFT (8U)[I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)[I2S_RCR4_FRSZ_MASK (0x1F0000U)[I2S_RCR4_FRSZ_SHIFT (16U)[I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)[I2S_RCR4_FPACK_MASK (0x3000000U)[I2S_RCR4_FPACK_SHIFT (24U)[I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)[I2S_RCR4_FCOMB_MASK (0xC000000U)[I2S_RCR4_FCOMB_SHIFT (26U)[I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)[I2S_RCR4_FCONT_MASK (0x10000000U)[I2S_RCR4_FCONT_SHIFT (28U)[I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)[I2S_RCR5_FBT_MASK (0x1F00U)[I2S_RCR5_FBT_SHIFT (8U)[I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)[I2S_RCR5_W0W_MASK (0x1F0000U)[I2S_RCR5_W0W_SHIFT (16U)[I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)[I2S_RCR5_WNW_MASK (0x1F000000U)[I2S_RCR5_WNW_SHIFT (24U)[I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)[I2S_RDR_RDR_MASK (0xFFFFFFFFU)[I2S_RDR_RDR_SHIFT (0U)[I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)[I2S_RDR_COUNT (4U)[I2S_RFR_RFP_MASK (0x3FU)[I2S_RFR_RFP_SHIFT (0U)[I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)[I2S_RFR_RCP_MASK (0x8000U)[I2S_RFR_RCP_SHIFT (15U)[I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)[I2S_RFR_WFP_MASK (0x3F0000U)[I2S_RFR_WFP_SHIFT (16U)[I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)[I2S_RFR_COUNT (4U)[I2S_RMR_RWM_MASK (0xFFFFFFFFU)[I2S_RMR_RWM_SHIFT (0U)[I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)[SAI1_BASE (0x40384000u)\SAI1 ((I2S_Type *)SAI1_BASE)\SAI2_BASE (0x40388000u)\SAI2 ((I2S_Type *)SAI2_BASE)\SAI3_BASE (0x4038C000u)\SAI3 ((I2S_Type *)SAI3_BASE)\I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }\I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }\I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }\I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }\IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)\IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)\IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)\IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)\IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)\IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)\IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)\IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)\IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)\IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)\IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)\IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)\IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)\IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)\IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)\IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)\IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)\IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)\IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)\IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)\IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)\IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)\IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)\IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)\IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)\IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)\IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)\IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)\IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)\IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)\IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)\IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)\IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U)\IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)\IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)\IOMUXC_SELECT_INPUT_COUNT (154U)\IOMUXC_BASE (0x401F8000u)\IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)\IOMUXC_BASE_ADDRS { IOMUXC_BASE }\IOMUXC_BASE_PTRS { IOMUXC }]IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)]IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)]IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)]IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)]IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)]IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)]IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)]IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)]IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)]IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)]IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)]IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)]IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)]IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)]IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)]IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)]IOMUXC_GPR_GPR1_GINT_SHIFT (12U)]IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)]IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)]IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)]IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)]IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)]IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)]IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)]IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)]IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)]IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)]IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)]IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)]IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)]IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)]IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)]IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)]IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)]IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)]IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)]IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)]IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)]IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)]IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)]IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)]IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)]IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)]IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)]IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)]IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)]IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)]IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)]IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)]IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)]IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)]IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)]IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)]IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)]IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)]IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)]IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)]IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)]IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)]IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)]IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)]IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)]IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)]IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)]IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)]IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)]IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)]IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)]IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)]IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)]IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)]IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)]IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)]IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)]IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)]IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)]IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)]IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)]IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)]IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)]IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)]IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)]IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)]IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)^IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)^IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)^IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)^IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)^IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)^IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)^IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)^IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)^IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)^IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)^IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)^IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)^IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)^IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)^IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)^IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)^IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)^IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)^IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)^IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)^IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)^IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)^IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)^IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)^IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)^IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)^IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)^IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)^IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)^IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)^IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)^IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)^IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)^IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)^IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)^IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)^IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)^IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)^IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)^IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)^IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)^IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)^IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)^IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)^IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)^IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)^IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)^IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)^IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)^IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)^IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)^IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)^IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)^IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)^IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U)^IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U)^IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK)^IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)^IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)^IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)^IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)^IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)^IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)^IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)^IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)^IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)^IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)^IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)^IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)^IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)^IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)^IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)^IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)^IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)^IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)^IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)^IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)^IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)^IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)_IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)_IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)_IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)_IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)_IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)_IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)_IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)_IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)_IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)_IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)_IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)_IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)_IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)_IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)_IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)_IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)_IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)_IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)_IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)_IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)_IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)_IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)_IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)_IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)_IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)_IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)_IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)_IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)_IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)_IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)_IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)_IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)_IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)_IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)_IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)_IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)_IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)_IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)_IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)_IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)_IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)_IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)_IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)_IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)_IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)_IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)_IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)_IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)_IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)_IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)_IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)_IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)_IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)_IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)_IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)_IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)_IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)`IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)`IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)`IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)`IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)`IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)`IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)`IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)`IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)`IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)`IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)`IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)`IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)`IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)`IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)`IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)`IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)`IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)`IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)`IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)`IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)`IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)`IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)`IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)`IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)`IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)`IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)`IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)`IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)`IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)`IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)`IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)`IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)`IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)`IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)`IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)`IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)`IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)`IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)`IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)`IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)`IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)`IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)`IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)`IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)`IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)`IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)`IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)`IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)`IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)`IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)`IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)`IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)`IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)`IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)`IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)`IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)`IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)`IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)`IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)`IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)`IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)`IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)`IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)`IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)`IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)`IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)`IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)`IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)`IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)`IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)`IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)`IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)`IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)`IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)`IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)`IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)`IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)`IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)`IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)`IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)`IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)`IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)`IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)`IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)`IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)`IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)`IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)`IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)aIOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)aIOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)aIOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)aIOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)aIOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)aIOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)aIOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)aIOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)aIOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)aIOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)aIOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)aIOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)aIOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)aIOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)aIOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)aIOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)aIOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)aIOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)aIOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)aIOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)aIOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)aIOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)aIOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)aIOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)aIOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)aIOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)aIOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)aIOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)aIOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)aIOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)aIOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)aIOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)aIOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)aIOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)aIOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)aIOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)aIOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)aIOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)aIOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)aIOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)aIOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)aIOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)aIOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)aIOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)aIOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)aIOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)aIOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)aIOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)aIOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)aIOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)aIOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)aIOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)aIOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)aIOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)aIOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)aIOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)aIOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)aIOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)aIOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)aIOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)aIOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)aIOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)aIOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)aIOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)aIOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)aIOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)aIOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)aIOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)aIOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)aIOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)aIOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)aIOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)aIOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)aIOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)aIOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)aIOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)aIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)aIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)aIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)aIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)aIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)aIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)aIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)aIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)aIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)aIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)bIOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)bIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)bIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)bIOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)bIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)bIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)bIOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)bIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)bIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)bIOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)bIOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)bIOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)bIOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)bIOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)bIOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)bIOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)bIOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)bIOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)bIOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)bIOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)bIOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)bIOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK (0xF0000U)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT (16U)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK (0xF00000U)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT (20U)bIOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK)bIOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)bIOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)bIOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)bIOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)bIOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)bIOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)bIOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)bIOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)bIOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)bIOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U)bIOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U)bIOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)bIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)bIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)bIOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)bIOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)bIOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)bIOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)bIOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)bIOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)bIOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)bIOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)bIOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)bIOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)bIOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)bIOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)bIOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)bIOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)bIOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)bIOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)bIOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)bIOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)bIOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)bIOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)bIOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)bIOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)bIOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)bIOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)bIOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)bIOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)bIOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)bIOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)bIOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK)bIOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)bIOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)bIOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)bIOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)bIOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)bIOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U)bIOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK)bIOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)bIOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)bIOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)bIOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)bIOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)bIOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)bIOMUXC_GPR_BASE (0x400AC000u)bIOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)bIOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }bIOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)cIOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)cIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)dIOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)dIOMUXC_SNVS_BASE (0x400A8000u)dIOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)dIOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }dIOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }eIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)eIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)eIOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)eIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)eIOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)eIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)eIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)eIOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK (0x10000U)eIOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT (16U)eIOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_LOW_BAT_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)eIOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)eIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)eIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)eIOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)eIOMUXC_SNVS_GPR_BASE (0x400A4000u)eIOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)eIOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }eIOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }eKPP_KPCR_KRE_MASK (0xFFU)eKPP_KPCR_KRE_SHIFT (0U)eKPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)eKPP_KPCR_KCO_MASK (0xFF00U)eKPP_KPCR_KCO_SHIFT (8U)eKPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)eKPP_KPSR_KPKD_MASK (0x1U)eKPP_KPSR_KPKD_SHIFT (0U)eKPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)eKPP_KPSR_KPKR_MASK (0x2U)eKPP_KPSR_KPKR_SHIFT (1U)eKPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)eKPP_KPSR_KDSC_MASK (0x4U)eKPP_KPSR_KDSC_SHIFT (2U)eKPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)eKPP_KPSR_KRSS_MASK (0x8U)eKPP_KPSR_KRSS_SHIFT (3U)eKPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)eKPP_KPSR_KDIE_MASK (0x100U)eKPP_KPSR_KDIE_SHIFT (8U)eKPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)eKPP_KPSR_KRIE_MASK (0x200U)eKPP_KPSR_KRIE_SHIFT (9U)eKPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)eKPP_KDDR_KRDD_MASK (0xFFU)eKPP_KDDR_KRDD_SHIFT (0U)eKPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)eKPP_KDDR_KCDD_MASK (0xFF00U)eKPP_KDDR_KCDD_SHIFT (8U)eKPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)eKPP_KPDR_KRD_MASK (0xFFU)eKPP_KPDR_KRD_SHIFT (0U)eKPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)eKPP_KPDR_KCD_MASK (0xFF00U)eKPP_KPDR_KCD_SHIFT (8U)eKPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)fKPP_BASE (0x401FC000u)fKPP ((KPP_Type *)KPP_BASE)fKPP_BASE_ADDRS { KPP_BASE }fKPP_BASE_PTRS { KPP }fKPP_IRQS { KPP_IRQn }fLCDIF_CTRL_RUN_MASK (0x1U)fLCDIF_CTRL_RUN_SHIFT (0U)fLCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)fLCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)fLCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)fLCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)fLCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)fLCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)fLCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)fLCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)fLCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)fLCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)fLCDIF_CTRL_RSRVD0_MASK (0x10U)fLCDIF_CTRL_RSRVD0_SHIFT (4U)fLCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)fLCDIF_CTRL_MASTER_MASK (0x20U)fLCDIF_CTRL_MASTER_SHIFT (5U)fLCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)fLCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)fLCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)fLCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)gLCDIF_CTRL_WORD_LENGTH_MASK (0x300U)gLCDIF_CTRL_WORD_LENGTH_SHIFT (8U)gLCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)gLCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)gLCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)gLCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)gLCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)gLCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)gLCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)gLCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)gLCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)gLCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)gLCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)gLCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)gLCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)gLCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)gLCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)gLCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)gLCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)gLCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)gLCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)gLCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)gLCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)gLCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)gLCDIF_CTRL_CLKGATE_MASK (0x40000000U)gLCDIF_CTRL_CLKGATE_SHIFT (30U)gLCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)gLCDIF_CTRL_SFTRST_MASK (0x80000000U)gLCDIF_CTRL_SFTRST_SHIFT (31U)gLCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)gLCDIF_CTRL_SET_RUN_MASK (0x1U)gLCDIF_CTRL_SET_RUN_SHIFT (0U)gLCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)gLCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)gLCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)gLCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)gLCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)gLCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)gLCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)gLCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)gLCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)gLCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)gLCDIF_CTRL_SET_RSRVD0_MASK (0x10U)gLCDIF_CTRL_SET_RSRVD0_SHIFT (4U)gLCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)gLCDIF_CTRL_SET_MASTER_MASK (0x20U)gLCDIF_CTRL_SET_MASTER_SHIFT (5U)gLCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)gLCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)gLCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)gLCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)gLCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)gLCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)gLCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)gLCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)gLCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)gLCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)gLCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)gLCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)gLCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)gLCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)gLCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)gLCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)gLCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)gLCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)gLCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)gLCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)gLCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)gLCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)gLCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)gLCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)gLCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)gLCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)gLCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)gLCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)gLCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)gLCDIF_CTRL_SET_CLKGATE_SHIFT (30U)gLCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)gLCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)gLCDIF_CTRL_SET_SFTRST_SHIFT (31U)gLCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)gLCDIF_CTRL_CLR_RUN_MASK (0x1U)gLCDIF_CTRL_CLR_RUN_SHIFT (0U)gLCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)gLCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)gLCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)gLCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)gLCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)gLCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)gLCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)gLCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)gLCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)gLCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)gLCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)gLCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)gLCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)gLCDIF_CTRL_CLR_MASTER_MASK (0x20U)gLCDIF_CTRL_CLR_MASTER_SHIFT (5U)gLCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)gLCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)gLCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)gLCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)gLCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)gLCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)gLCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)gLCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)gLCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)gLCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)gLCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)gLCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)gLCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)gLCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)gLCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)gLCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)gLCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)gLCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)gLCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)gLCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)gLCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)gLCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)gLCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)gLCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)gLCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)gLCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)hLCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)hLCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)hLCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)hLCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)hLCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)hLCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)hLCDIF_CTRL_CLR_SFTRST_SHIFT (31U)hLCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)hLCDIF_CTRL_TOG_RUN_MASK (0x1U)hLCDIF_CTRL_TOG_RUN_SHIFT (0U)hLCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)hLCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)hLCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)hLCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)hLCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)hLCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)hLCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)hLCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)hLCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)hLCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)hLCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)hLCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)hLCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)hLCDIF_CTRL_TOG_MASTER_MASK (0x20U)hLCDIF_CTRL_TOG_MASTER_SHIFT (5U)hLCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)hLCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)hLCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)hLCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)hLCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)hLCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)hLCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)hLCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)hLCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)hLCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)hLCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)hLCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)hLCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)hLCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)hLCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)hLCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)hLCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)hLCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)hLCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)hLCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)hLCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)hLCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)hLCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)hLCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)hLCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)hLCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)hLCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)hLCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)hLCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)hLCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)hLCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)hLCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)hLCDIF_CTRL_TOG_SFTRST_SHIFT (31U)hLCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)hLCDIF_CTRL1_RSRVD0_MASK (0xF8U)hLCDIF_CTRL1_RSRVD0_SHIFT (3U)hLCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)hLCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)hLCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)hLCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)hLCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)hLCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)hLCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)hLCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)hLCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)hLCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)hLCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)hLCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)hLCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)hLCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)hLCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)hLCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)hLCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)hLCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)hLCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)hLCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)hLCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)hLCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)hLCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)hLCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)hLCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)hLCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)hLCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)hLCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)hLCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)hLCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)hLCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)hLCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)hLCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)hLCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)hLCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)hLCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)hLCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)hLCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)hLCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)hLCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)hLCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)hLCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)hLCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)hLCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)hLCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)hLCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)hLCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)hLCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)hLCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)hLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)hLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)hLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)iLCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)iLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)iLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)iLCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)iLCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)iLCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)iLCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)iLCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)iLCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)iLCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)iLCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)iLCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)iLCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)iLCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)iLCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)iLCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)iLCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)iLCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)iLCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)iLCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)iLCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)iLCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)iLCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)iLCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)iLCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)iLCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)iLCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)iLCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)iLCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)iLCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)iLCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)iLCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)iLCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)iLCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)iLCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)iLCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)iLCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)iLCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)iLCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)iLCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)iLCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)iLCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)iLCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)iLCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)iLCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)iLCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)iLCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)iLCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)iLCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)iLCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)iLCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)iLCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)iLCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)iLCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)iLCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)iLCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)iLCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)iLCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)iLCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)iLCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)iLCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)iLCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)iLCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)iLCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)iLCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)iLCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)iLCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)iLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)iLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)iLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)iLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)iLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)iLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)iLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)iLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)iLCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)iLCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)iLCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)iLCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)iLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)jLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)jLCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)jLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)jLCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)jLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)jLCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)jLCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)jLCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)jLCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)jLCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)jLCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)jLCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)jLCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)jLCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)jLCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)jLCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)jLCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)jLCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)jLCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)jLCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)jLCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)jLCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)jLCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)jLCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)jLCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)jLCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)jLCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)jLCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)jLCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)jLCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)jLCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)jLCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)jLCDIF_CTRL2_RSRVD0_MASK (0xFFFU)jLCDIF_CTRL2_RSRVD0_SHIFT (0U)jLCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)jLCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)jLCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)jLCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)jLCDIF_CTRL2_RSRVD3_MASK (0x8000U)jLCDIF_CTRL2_RSRVD3_SHIFT (15U)jLCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)jLCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)jLCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)jLCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)jLCDIF_CTRL2_RSRVD4_MASK (0x80000U)jLCDIF_CTRL2_RSRVD4_SHIFT (19U)jLCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)jLCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)jLCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)jLCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)jLCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)jLCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)jLCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)jLCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)jLCDIF_CTRL2_RSRVD5_SHIFT (24U)jLCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)jLCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)jLCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)jLCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)jLCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)jLCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)jLCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)jLCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)jLCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)jLCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)jLCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)jLCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)jLCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)jLCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)jLCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)jLCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)jLCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)jLCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)jLCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)jLCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)jLCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)jLCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)jLCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)jLCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)jLCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)jLCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)jLCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)jLCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)jLCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)jLCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)jLCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)jLCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)jLCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)jLCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)jLCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)jLCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)jLCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)jLCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)jLCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)jLCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)jLCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)jLCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)jLCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)jLCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)jLCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)jLCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)jLCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)jLCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)jLCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)jLCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)jLCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)jLCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)jLCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)jLCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)jLCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)jLCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)kLCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)kLCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)kLCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)kLCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)kLCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)kLCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)kLCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)kLCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)kLCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)kLCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)kLCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)kLCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)kLCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)kLCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)kLCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)kLCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)kLCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)kLCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)kLCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)kLCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)kLCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)kLCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)kLCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)kLCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)kLCDIF_CUR_BUF_ADDR_SHIFT (0U)kLCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)kLCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)kLCDIF_NEXT_BUF_ADDR_SHIFT (0U)kLCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)kLCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)kLCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)kLCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)kLCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)kLCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)kLCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)kLCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)kLCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)kLCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)kLCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)kLCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)kLCDIF_VDCTRL0_RSRVD1_SHIFT (22U)kLCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)kLCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)kLCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)kLCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)kLCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)kLCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)kLCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)kLCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)kLCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)kLCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)kLCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)kLCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)kLCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)kLCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)kLCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)kLCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)kLCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)kLCDIF_VDCTRL0_RSRVD2_SHIFT (29U)kLCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)kLCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)kLCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)kLCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)kLCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)kLCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)kLCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)kLCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)kLCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)kLCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)kLCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)kLCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)kLCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)kLCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)kLCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)kLCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)kLCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)kLCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)kLCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)kLCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)kLCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)kLCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)kLCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)kLCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)kLCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)kLCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)kLCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)kLCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)kLCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)kLCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)kLCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)kLCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)kLCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)kLCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)kLCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)kLCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)kLCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)kLCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)kLCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)kLCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)kLCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)kLCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)lLCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)lLCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)lLCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)lLCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)lLCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)lLCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)lLCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)lLCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)lLCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)lLCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)lLCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)lLCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)lLCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)lLCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)lLCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)lLCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)lLCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)lLCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)lLCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)lLCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)lLCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)lLCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)lLCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)lLCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)lLCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)lLCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)lLCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)lLCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)lLCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)lLCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)lLCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)lLCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)lLCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)lLCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)lLCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)lLCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)lLCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)lLCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)lLCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)lLCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)lLCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)lLCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)lLCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)lLCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)lLCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)lLCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)lLCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)lLCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)lLCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)lLCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)lLCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)lLCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)lLCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)lLCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)lLCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)lLCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)lLCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)lLCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)lLCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)lLCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)lLCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)lLCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)lLCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)lLCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)lLCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)lLCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)lLCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)lLCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)lLCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)lLCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)lLCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)lLCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)lLCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)lLCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)lLCDIF_VDCTRL3_RSRVD0_SHIFT (30U)lLCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)lLCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)lLCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)lLCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)lLCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)lLCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)lLCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)lLCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)lLCDIF_VDCTRL4_RSRVD0_SHIFT (19U)lLCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)lLCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)lLCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)lLCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)lLCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)lLCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)lLCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)lLCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)lLCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)lLCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)lLCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)lLCDIF_STAT_LFIFO_COUNT_SHIFT (0U)lLCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)lLCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)lLCDIF_STAT_RSRVD0_SHIFT (9U)lLCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)lLCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)lLCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)lLCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)lLCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)lLCDIF_STAT_TXFIFO_FULL_SHIFT (27U)lLCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)lLCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)mLCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)mLCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)mLCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)mLCDIF_STAT_LFIFO_FULL_SHIFT (29U)mLCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)mLCDIF_STAT_DMA_REQ_MASK (0x40000000U)mLCDIF_STAT_DMA_REQ_SHIFT (30U)mLCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)mLCDIF_STAT_PRESENT_MASK (0x80000000U)mLCDIF_STAT_PRESENT_SHIFT (31U)mLCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)mLCDIF_THRES_PANIC_MASK (0x1FFU)mLCDIF_THRES_PANIC_SHIFT (0U)mLCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK)mLCDIF_THRES_RSRVD1_MASK (0xFE00U)mLCDIF_THRES_RSRVD1_SHIFT (9U)mLCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)mLCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)mLCDIF_THRES_FASTCLOCK_SHIFT (16U)mLCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)mLCDIF_THRES_RSRVD2_MASK (0xFE000000U)mLCDIF_THRES_RSRVD2_SHIFT (25U)mLCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)mLCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)mLCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)mLCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)mLCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)mLCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)mLCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)mLCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)mLCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)mLCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)mLCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)mLCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)mLCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)mLCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)mLCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)mLCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)mLCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)mLCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)mLCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)mLCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)mLCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)mLCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)mLCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)mLCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)mLCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)mLCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)mLCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)mLCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)mLCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)mLCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)mLCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)mLCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)mLCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)mLCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)mLCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)mLCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)mLCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)mLCDIF_PIGEON_0_EN_MASK (0x1U)mLCDIF_PIGEON_0_EN_SHIFT (0U)mLCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)mLCDIF_PIGEON_0_POL_MASK (0x2U)mLCDIF_PIGEON_0_POL_SHIFT (1U)nLCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)nLCDIF_PIGEON_0_INC_SEL_MASK (0xCU)nLCDIF_PIGEON_0_INC_SEL_SHIFT (2U)nLCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)nLCDIF_PIGEON_0_OFFSET_MASK (0xF0U)nLCDIF_PIGEON_0_OFFSET_SHIFT (4U)nLCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)nLCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)nLCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)nLCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)nLCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)nLCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)nLCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)nLCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)nLCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)nLCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)nLCDIF_PIGEON_0_COUNT (12U)nLCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)nLCDIF_PIGEON_1_SET_CNT_SHIFT (0U)nLCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)nLCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)nLCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)nLCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)nLCDIF_PIGEON_1_COUNT (12U)nLCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)nLCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)nLCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)nLCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)nLCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)nLCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)nLCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)nLCDIF_PIGEON_2_RSVD_SHIFT (9U)nLCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)nLCDIF_PIGEON_2_COUNT (12U)nLCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)nLCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)nLCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)nLCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)nLCDIF_LUT0_ADDR_ADDR_SHIFT (0U)nLCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)nLCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)nLCDIF_LUT0_DATA_DATA_SHIFT (0U)nLCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)nLCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)nLCDIF_LUT1_ADDR_ADDR_SHIFT (0U)nLCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)nLCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)nLCDIF_LUT1_DATA_DATA_SHIFT (0U)nLCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)nLCDIF_BASE (0x402B8000u)nLCDIF ((LCDIF_Type *)LCDIF_BASE)nLCDIF_BASE_ADDRS { LCDIF_BASE }nLCDIF_BASE_PTRS { LCDIF }nLCDIF_IRQ0_IRQS { LCDIF_IRQn }oLPI2C_VERID_FEATURE_MASK (0xFFFFU)oLPI2C_VERID_FEATURE_SHIFT (0U)oLPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)oLPI2C_VERID_MINOR_MASK (0xFF0000U)oLPI2C_VERID_MINOR_SHIFT (16U)oLPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)oLPI2C_VERID_MAJOR_MASK (0xFF000000U)oLPI2C_VERID_MAJOR_SHIFT (24U)oLPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)oLPI2C_PARAM_MTXFIFO_MASK (0xFU)oLPI2C_PARAM_MTXFIFO_SHIFT (0U)oLPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)oLPI2C_PARAM_MRXFIFO_MASK (0xF00U)oLPI2C_PARAM_MRXFIFO_SHIFT (8U)oLPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)oLPI2C_MCR_MEN_MASK (0x1U)oLPI2C_MCR_MEN_SHIFT (0U)oLPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)oLPI2C_MCR_RST_MASK (0x2U)oLPI2C_MCR_RST_SHIFT (1U)oLPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)oLPI2C_MCR_DOZEN_MASK (0x4U)oLPI2C_MCR_DOZEN_SHIFT (2U)oLPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)oLPI2C_MCR_DBGEN_MASK (0x8U)oLPI2C_MCR_DBGEN_SHIFT (3U)oLPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)oLPI2C_MCR_RTF_MASK (0x100U)oLPI2C_MCR_RTF_SHIFT (8U)oLPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)oLPI2C_MCR_RRF_MASK (0x200U)oLPI2C_MCR_RRF_SHIFT (9U)oLPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)oLPI2C_MSR_TDF_MASK (0x1U)oLPI2C_MSR_TDF_SHIFT (0U)oLPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)oLPI2C_MSR_RDF_MASK (0x2U)oLPI2C_MSR_RDF_SHIFT (1U)oLPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)oLPI2C_MSR_EPF_MASK (0x100U)oLPI2C_MSR_EPF_SHIFT (8U)oLPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)oLPI2C_MSR_SDF_MASK (0x200U)oLPI2C_MSR_SDF_SHIFT (9U)oLPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)oLPI2C_MSR_NDF_MASK (0x400U)oLPI2C_MSR_NDF_SHIFT (10U)oLPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)oLPI2C_MSR_ALF_MASK (0x800U)oLPI2C_MSR_ALF_SHIFT (11U)oLPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)oLPI2C_MSR_FEF_MASK (0x1000U)oLPI2C_MSR_FEF_SHIFT (12U)oLPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)oLPI2C_MSR_PLTF_MASK (0x2000U)oLPI2C_MSR_PLTF_SHIFT (13U)oLPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)oLPI2C_MSR_DMF_MASK (0x4000U)oLPI2C_MSR_DMF_SHIFT (14U)oLPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)oLPI2C_MSR_MBF_MASK (0x1000000U)oLPI2C_MSR_MBF_SHIFT (24U)oLPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)oLPI2C_MSR_BBF_MASK (0x2000000U)oLPI2C_MSR_BBF_SHIFT (25U)oLPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)oLPI2C_MIER_TDIE_MASK (0x1U)oLPI2C_MIER_TDIE_SHIFT (0U)oLPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)oLPI2C_MIER_RDIE_MASK (0x2U)oLPI2C_MIER_RDIE_SHIFT (1U)oLPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)oLPI2C_MIER_EPIE_MASK (0x100U)oLPI2C_MIER_EPIE_SHIFT (8U)oLPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)oLPI2C_MIER_SDIE_MASK (0x200U)oLPI2C_MIER_SDIE_SHIFT (9U)oLPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)oLPI2C_MIER_NDIE_MASK (0x400U)oLPI2C_MIER_NDIE_SHIFT (10U)oLPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)oLPI2C_MIER_ALIE_MASK (0x800U)oLPI2C_MIER_ALIE_SHIFT (11U)oLPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)oLPI2C_MIER_FEIE_MASK (0x1000U)oLPI2C_MIER_FEIE_SHIFT (12U)oLPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)oLPI2C_MIER_PLTIE_MASK (0x2000U)oLPI2C_MIER_PLTIE_SHIFT (13U)oLPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)oLPI2C_MIER_DMIE_MASK (0x4000U)oLPI2C_MIER_DMIE_SHIFT (14U)pLPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)pLPI2C_MDER_TDDE_MASK (0x1U)pLPI2C_MDER_TDDE_SHIFT (0U)pLPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)pLPI2C_MDER_RDDE_MASK (0x2U)pLPI2C_MDER_RDDE_SHIFT (1U)pLPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)pLPI2C_MCFGR0_HREN_MASK (0x1U)pLPI2C_MCFGR0_HREN_SHIFT (0U)pLPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)pLPI2C_MCFGR0_HRPOL_MASK (0x2U)pLPI2C_MCFGR0_HRPOL_SHIFT (1U)pLPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)pLPI2C_MCFGR0_HRSEL_MASK (0x4U)pLPI2C_MCFGR0_HRSEL_SHIFT (2U)pLPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)pLPI2C_MCFGR0_CIRFIFO_MASK (0x100U)pLPI2C_MCFGR0_CIRFIFO_SHIFT (8U)pLPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)pLPI2C_MCFGR0_RDMO_MASK (0x200U)pLPI2C_MCFGR0_RDMO_SHIFT (9U)pLPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)pLPI2C_MCFGR1_PRESCALE_MASK (0x7U)pLPI2C_MCFGR1_PRESCALE_SHIFT (0U)pLPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)pLPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)pLPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)pLPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)pLPI2C_MCFGR1_IGNACK_MASK (0x200U)pLPI2C_MCFGR1_IGNACK_SHIFT (9U)pLPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)pLPI2C_MCFGR1_TIMECFG_MASK (0x400U)pLPI2C_MCFGR1_TIMECFG_SHIFT (10U)pLPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)pLPI2C_MCFGR1_MATCFG_MASK (0x70000U)pLPI2C_MCFGR1_MATCFG_SHIFT (16U)pLPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)pLPI2C_MCFGR1_PINCFG_MASK (0x7000000U)pLPI2C_MCFGR1_PINCFG_SHIFT (24U)pLPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)pLPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)pLPI2C_MCFGR2_BUSIDLE_SHIFT (0U)pLPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)pLPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)pLPI2C_MCFGR2_FILTSCL_SHIFT (16U)pLPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)pLPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)pLPI2C_MCFGR2_FILTSDA_SHIFT (24U)pLPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)pLPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)pLPI2C_MCFGR3_PINLOW_SHIFT (8U)pLPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)pLPI2C_MDMR_MATCH0_MASK (0xFFU)pLPI2C_MDMR_MATCH0_SHIFT (0U)pLPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)pLPI2C_MDMR_MATCH1_MASK (0xFF0000U)pLPI2C_MDMR_MATCH1_SHIFT (16U)pLPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)pLPI2C_MCCR0_CLKLO_MASK (0x3FU)pLPI2C_MCCR0_CLKLO_SHIFT (0U)pLPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)pLPI2C_MCCR0_CLKHI_MASK (0x3F00U)pLPI2C_MCCR0_CLKHI_SHIFT (8U)pLPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)pLPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)pLPI2C_MCCR0_SETHOLD_SHIFT (16U)pLPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)pLPI2C_MCCR0_DATAVD_MASK (0x3F000000U)pLPI2C_MCCR0_DATAVD_SHIFT (24U)pLPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)pLPI2C_MCCR1_CLKLO_MASK (0x3FU)pLPI2C_MCCR1_CLKLO_SHIFT (0U)pLPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)pLPI2C_MCCR1_CLKHI_MASK (0x3F00U)pLPI2C_MCCR1_CLKHI_SHIFT (8U)pLPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)pLPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)pLPI2C_MCCR1_SETHOLD_SHIFT (16U)pLPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)pLPI2C_MCCR1_DATAVD_MASK (0x3F000000U)pLPI2C_MCCR1_DATAVD_SHIFT (24U)pLPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)pLPI2C_MFCR_TXWATER_MASK (0x3U)pLPI2C_MFCR_TXWATER_SHIFT (0U)pLPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)pLPI2C_MFCR_RXWATER_MASK (0x30000U)pLPI2C_MFCR_RXWATER_SHIFT (16U)pLPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)pLPI2C_MFSR_TXCOUNT_MASK (0x7U)pLPI2C_MFSR_TXCOUNT_SHIFT (0U)pLPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)pLPI2C_MFSR_RXCOUNT_MASK (0x70000U)pLPI2C_MFSR_RXCOUNT_SHIFT (16U)pLPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)pLPI2C_MTDR_DATA_MASK (0xFFU)pLPI2C_MTDR_DATA_SHIFT (0U)pLPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)pLPI2C_MTDR_CMD_MASK (0x700U)pLPI2C_MTDR_CMD_SHIFT (8U)pLPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)pLPI2C_MRDR_DATA_MASK (0xFFU)pLPI2C_MRDR_DATA_SHIFT (0U)pLPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)pLPI2C_MRDR_RXEMPTY_MASK (0x4000U)qLPI2C_MRDR_RXEMPTY_SHIFT (14U)qLPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)qLPI2C_SCR_SEN_MASK (0x1U)qLPI2C_SCR_SEN_SHIFT (0U)qLPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)qLPI2C_SCR_RST_MASK (0x2U)qLPI2C_SCR_RST_SHIFT (1U)qLPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)qLPI2C_SCR_FILTEN_MASK (0x10U)qLPI2C_SCR_FILTEN_SHIFT (4U)qLPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)qLPI2C_SCR_FILTDZ_MASK (0x20U)qLPI2C_SCR_FILTDZ_SHIFT (5U)qLPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)qLPI2C_SCR_RTF_MASK (0x100U)qLPI2C_SCR_RTF_SHIFT (8U)qLPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)qLPI2C_SCR_RRF_MASK (0x200U)qLPI2C_SCR_RRF_SHIFT (9U)qLPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)qLPI2C_SSR_TDF_MASK (0x1U)qLPI2C_SSR_TDF_SHIFT (0U)qLPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)qLPI2C_SSR_RDF_MASK (0x2U)qLPI2C_SSR_RDF_SHIFT (1U)qLPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)qLPI2C_SSR_AVF_MASK (0x4U)qLPI2C_SSR_AVF_SHIFT (2U)qLPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)qLPI2C_SSR_TAF_MASK (0x8U)qLPI2C_SSR_TAF_SHIFT (3U)qLPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)qLPI2C_SSR_RSF_MASK (0x100U)qLPI2C_SSR_RSF_SHIFT (8U)qLPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)qLPI2C_SSR_SDF_MASK (0x200U)qLPI2C_SSR_SDF_SHIFT (9U)qLPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)qLPI2C_SSR_BEF_MASK (0x400U)qLPI2C_SSR_BEF_SHIFT (10U)qLPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)qLPI2C_SSR_FEF_MASK (0x800U)qLPI2C_SSR_FEF_SHIFT (11U)qLPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)qLPI2C_SSR_AM0F_MASK (0x1000U)qLPI2C_SSR_AM0F_SHIFT (12U)qLPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)qLPI2C_SSR_AM1F_MASK (0x2000U)qLPI2C_SSR_AM1F_SHIFT (13U)qLPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)qLPI2C_SSR_GCF_MASK (0x4000U)qLPI2C_SSR_GCF_SHIFT (14U)qLPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)qLPI2C_SSR_SARF_MASK (0x8000U)qLPI2C_SSR_SARF_SHIFT (15U)qLPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)qLPI2C_SSR_SBF_MASK (0x1000000U)qLPI2C_SSR_SBF_SHIFT (24U)qLPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)qLPI2C_SSR_BBF_MASK (0x2000000U)qLPI2C_SSR_BBF_SHIFT (25U)qLPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)qLPI2C_SIER_TDIE_MASK (0x1U)qLPI2C_SIER_TDIE_SHIFT (0U)qLPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)qLPI2C_SIER_RDIE_MASK (0x2U)qLPI2C_SIER_RDIE_SHIFT (1U)qLPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)qLPI2C_SIER_AVIE_MASK (0x4U)qLPI2C_SIER_AVIE_SHIFT (2U)qLPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)qLPI2C_SIER_TAIE_MASK (0x8U)qLPI2C_SIER_TAIE_SHIFT (3U)qLPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)qLPI2C_SIER_RSIE_MASK (0x100U)qLPI2C_SIER_RSIE_SHIFT (8U)qLPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)qLPI2C_SIER_SDIE_MASK (0x200U)qLPI2C_SIER_SDIE_SHIFT (9U)qLPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)qLPI2C_SIER_BEIE_MASK (0x400U)qLPI2C_SIER_BEIE_SHIFT (10U)qLPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)qLPI2C_SIER_FEIE_MASK (0x800U)qLPI2C_SIER_FEIE_SHIFT (11U)qLPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)qLPI2C_SIER_AM0IE_MASK (0x1000U)qLPI2C_SIER_AM0IE_SHIFT (12U)qLPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)qLPI2C_SIER_AM1F_MASK (0x2000U)qLPI2C_SIER_AM1F_SHIFT (13U)qLPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)qLPI2C_SIER_GCIE_MASK (0x4000U)qLPI2C_SIER_GCIE_SHIFT (14U)qLPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)qLPI2C_SIER_SARIE_MASK (0x8000U)qLPI2C_SIER_SARIE_SHIFT (15U)qLPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)qLPI2C_SDER_TDDE_MASK (0x1U)qLPI2C_SDER_TDDE_SHIFT (0U)qLPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)qLPI2C_SDER_RDDE_MASK (0x2U)qLPI2C_SDER_RDDE_SHIFT (1U)qLPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)qLPI2C_SDER_AVDE_MASK (0x4U)qLPI2C_SDER_AVDE_SHIFT (2U)qLPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)qLPI2C_SCFGR1_ADRSTALL_MASK (0x1U)qLPI2C_SCFGR1_ADRSTALL_SHIFT (0U)qLPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)qLPI2C_SCFGR1_RXSTALL_MASK (0x2U)qLPI2C_SCFGR1_RXSTALL_SHIFT (1U)qLPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)qLPI2C_SCFGR1_TXDSTALL_MASK (0x4U)qLPI2C_SCFGR1_TXDSTALL_SHIFT (2U)qLPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)qLPI2C_SCFGR1_ACKSTALL_MASK (0x8U)qLPI2C_SCFGR1_ACKSTALL_SHIFT (3U)rLPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)rLPI2C_SCFGR1_GCEN_MASK (0x100U)rLPI2C_SCFGR1_GCEN_SHIFT (8U)rLPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)rLPI2C_SCFGR1_SAEN_MASK (0x200U)rLPI2C_SCFGR1_SAEN_SHIFT (9U)rLPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)rLPI2C_SCFGR1_TXCFG_MASK (0x400U)rLPI2C_SCFGR1_TXCFG_SHIFT (10U)rLPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)rLPI2C_SCFGR1_RXCFG_MASK (0x800U)rLPI2C_SCFGR1_RXCFG_SHIFT (11U)rLPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)rLPI2C_SCFGR1_IGNACK_MASK (0x1000U)rLPI2C_SCFGR1_IGNACK_SHIFT (12U)rLPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)rLPI2C_SCFGR1_HSMEN_MASK (0x2000U)rLPI2C_SCFGR1_HSMEN_SHIFT (13U)rLPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)rLPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)rLPI2C_SCFGR1_ADDRCFG_SHIFT (16U)rLPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)rLPI2C_SCFGR2_CLKHOLD_MASK (0xFU)rLPI2C_SCFGR2_CLKHOLD_SHIFT (0U)rLPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)rLPI2C_SCFGR2_DATAVD_MASK (0x3F00U)rLPI2C_SCFGR2_DATAVD_SHIFT (8U)rLPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)rLPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)rLPI2C_SCFGR2_FILTSCL_SHIFT (16U)rLPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)rLPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)rLPI2C_SCFGR2_FILTSDA_SHIFT (24U)rLPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)rLPI2C_SAMR_ADDR0_MASK (0x7FEU)rLPI2C_SAMR_ADDR0_SHIFT (1U)rLPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)rLPI2C_SAMR_ADDR1_MASK (0x7FE0000U)rLPI2C_SAMR_ADDR1_SHIFT (17U)rLPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)rLPI2C_SASR_RADDR_MASK (0x7FFU)rLPI2C_SASR_RADDR_SHIFT (0U)rLPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)rLPI2C_SASR_ANV_MASK (0x4000U)rLPI2C_SASR_ANV_SHIFT (14U)rLPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)rLPI2C_STAR_TXNACK_MASK (0x1U)rLPI2C_STAR_TXNACK_SHIFT (0U)rLPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)rLPI2C_STDR_DATA_MASK (0xFFU)rLPI2C_STDR_DATA_SHIFT (0U)rLPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)rLPI2C_SRDR_DATA_MASK (0xFFU)rLPI2C_SRDR_DATA_SHIFT (0U)rLPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)rLPI2C_SRDR_RXEMPTY_MASK (0x4000U)rLPI2C_SRDR_RXEMPTY_SHIFT (14U)rLPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)rLPI2C_SRDR_SOF_MASK (0x8000U)rLPI2C_SRDR_SOF_SHIFT (15U)rLPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)rLPI2C1_BASE (0x403F0000u)rLPI2C1 ((LPI2C_Type *)LPI2C1_BASE)rLPI2C2_BASE (0x403F4000u)rLPI2C2 ((LPI2C_Type *)LPI2C2_BASE)rLPI2C3_BASE (0x403F8000u)rLPI2C3 ((LPI2C_Type *)LPI2C3_BASE)rLPI2C4_BASE (0x403FC000u)rLPI2C4 ((LPI2C_Type *)LPI2C4_BASE)rLPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }rLPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }rLPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }sLPSPI_VERID_FEATURE_MASK (0xFFFFU)sLPSPI_VERID_FEATURE_SHIFT (0U)sLPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)sLPSPI_VERID_MINOR_MASK (0xFF0000U)sLPSPI_VERID_MINOR_SHIFT (16U)sLPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)sLPSPI_VERID_MAJOR_MASK (0xFF000000U)sLPSPI_VERID_MAJOR_SHIFT (24U)sLPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)sLPSPI_PARAM_TXFIFO_MASK (0xFFU)sLPSPI_PARAM_TXFIFO_SHIFT (0U)sLPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)sLPSPI_PARAM_RXFIFO_MASK (0xFF00U)sLPSPI_PARAM_RXFIFO_SHIFT (8U)sLPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)sLPSPI_PARAM_PCSNUM_MASK (0xFF0000U)sLPSPI_PARAM_PCSNUM_SHIFT (16U)sLPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)sLPSPI_CR_MEN_MASK (0x1U)sLPSPI_CR_MEN_SHIFT (0U)sLPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)sLPSPI_CR_RST_MASK (0x2U)sLPSPI_CR_RST_SHIFT (1U)sLPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)sLPSPI_CR_DOZEN_MASK (0x4U)sLPSPI_CR_DOZEN_SHIFT (2U)sLPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)sLPSPI_CR_DBGEN_MASK (0x8U)sLPSPI_CR_DBGEN_SHIFT (3U)sLPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)sLPSPI_CR_RTF_MASK (0x100U)sLPSPI_CR_RTF_SHIFT (8U)sLPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)sLPSPI_CR_RRF_MASK (0x200U)sLPSPI_CR_RRF_SHIFT (9U)sLPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)sLPSPI_SR_TDF_MASK (0x1U)sLPSPI_SR_TDF_SHIFT (0U)sLPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)sLPSPI_SR_RDF_MASK (0x2U)sLPSPI_SR_RDF_SHIFT (1U)sLPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)sLPSPI_SR_WCF_MASK (0x100U)sLPSPI_SR_WCF_SHIFT (8U)sLPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)sLPSPI_SR_FCF_MASK (0x200U)sLPSPI_SR_FCF_SHIFT (9U)sLPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)sLPSPI_SR_TCF_MASK (0x400U)sLPSPI_SR_TCF_SHIFT (10U)sLPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)sLPSPI_SR_TEF_MASK (0x800U)sLPSPI_SR_TEF_SHIFT (11U)sLPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)sLPSPI_SR_REF_MASK (0x1000U)sLPSPI_SR_REF_SHIFT (12U)sLPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)sLPSPI_SR_DMF_MASK (0x2000U)sLPSPI_SR_DMF_SHIFT (13U)sLPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)sLPSPI_SR_MBF_MASK (0x1000000U)sLPSPI_SR_MBF_SHIFT (24U)sLPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)sLPSPI_IER_TDIE_MASK (0x1U)sLPSPI_IER_TDIE_SHIFT (0U)sLPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)sLPSPI_IER_RDIE_MASK (0x2U)sLPSPI_IER_RDIE_SHIFT (1U)sLPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)sLPSPI_IER_WCIE_MASK (0x100U)sLPSPI_IER_WCIE_SHIFT (8U)sLPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)sLPSPI_IER_FCIE_MASK (0x200U)sLPSPI_IER_FCIE_SHIFT (9U)sLPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)sLPSPI_IER_TCIE_MASK (0x400U)sLPSPI_IER_TCIE_SHIFT (10U)sLPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)sLPSPI_IER_TEIE_MASK (0x800U)sLPSPI_IER_TEIE_SHIFT (11U)sLPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)sLPSPI_IER_REIE_MASK (0x1000U)sLPSPI_IER_REIE_SHIFT (12U)sLPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)sLPSPI_IER_DMIE_MASK (0x2000U)sLPSPI_IER_DMIE_SHIFT (13U)sLPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)sLPSPI_DER_TDDE_MASK (0x1U)sLPSPI_DER_TDDE_SHIFT (0U)sLPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)sLPSPI_DER_RDDE_MASK (0x2U)sLPSPI_DER_RDDE_SHIFT (1U)tLPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)tLPSPI_CFGR0_HREN_MASK (0x1U)tLPSPI_CFGR0_HREN_SHIFT (0U)tLPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)tLPSPI_CFGR0_HRPOL_MASK (0x2U)tLPSPI_CFGR0_HRPOL_SHIFT (1U)tLPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)tLPSPI_CFGR0_HRSEL_MASK (0x4U)tLPSPI_CFGR0_HRSEL_SHIFT (2U)tLPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)tLPSPI_CFGR0_CIRFIFO_MASK (0x100U)tLPSPI_CFGR0_CIRFIFO_SHIFT (8U)tLPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)tLPSPI_CFGR0_RDMO_MASK (0x200U)tLPSPI_CFGR0_RDMO_SHIFT (9U)tLPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)tLPSPI_CFGR1_MASTER_MASK (0x1U)tLPSPI_CFGR1_MASTER_SHIFT (0U)tLPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)tLPSPI_CFGR1_SAMPLE_MASK (0x2U)tLPSPI_CFGR1_SAMPLE_SHIFT (1U)tLPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)tLPSPI_CFGR1_AUTOPCS_MASK (0x4U)tLPSPI_CFGR1_AUTOPCS_SHIFT (2U)tLPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)tLPSPI_CFGR1_NOSTALL_MASK (0x8U)tLPSPI_CFGR1_NOSTALL_SHIFT (3U)tLPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)tLPSPI_CFGR1_PCSPOL_MASK (0xF00U)tLPSPI_CFGR1_PCSPOL_SHIFT (8U)tLPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)tLPSPI_CFGR1_MATCFG_MASK (0x70000U)tLPSPI_CFGR1_MATCFG_SHIFT (16U)tLPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)tLPSPI_CFGR1_PINCFG_MASK (0x3000000U)tLPSPI_CFGR1_PINCFG_SHIFT (24U)tLPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)tLPSPI_CFGR1_OUTCFG_MASK (0x4000000U)tLPSPI_CFGR1_OUTCFG_SHIFT (26U)tLPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)tLPSPI_CFGR1_PCSCFG_MASK (0x8000000U)tLPSPI_CFGR1_PCSCFG_SHIFT (27U)tLPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)tLPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)tLPSPI_DMR0_MATCH0_SHIFT (0U)tLPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)tLPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)tLPSPI_DMR1_MATCH1_SHIFT (0U)tLPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)tLPSPI_CCR_SCKDIV_MASK (0xFFU)tLPSPI_CCR_SCKDIV_SHIFT (0U)tLPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)tLPSPI_CCR_DBT_MASK (0xFF00U)tLPSPI_CCR_DBT_SHIFT (8U)tLPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)tLPSPI_CCR_PCSSCK_MASK (0xFF0000U)tLPSPI_CCR_PCSSCK_SHIFT (16U)tLPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)tLPSPI_CCR_SCKPCS_MASK (0xFF000000U)tLPSPI_CCR_SCKPCS_SHIFT (24U)tLPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)tLPSPI_FCR_TXWATER_MASK (0xFU)tLPSPI_FCR_TXWATER_SHIFT (0U)tLPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)tLPSPI_FCR_RXWATER_MASK (0xF0000U)tLPSPI_FCR_RXWATER_SHIFT (16U)tLPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)tLPSPI_FSR_TXCOUNT_MASK (0x1FU)tLPSPI_FSR_TXCOUNT_SHIFT (0U)tLPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)tLPSPI_FSR_RXCOUNT_MASK (0x1F0000U)tLPSPI_FSR_RXCOUNT_SHIFT (16U)tLPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)tLPSPI_TCR_FRAMESZ_MASK (0xFFFU)tLPSPI_TCR_FRAMESZ_SHIFT (0U)tLPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)tLPSPI_TCR_WIDTH_MASK (0x30000U)tLPSPI_TCR_WIDTH_SHIFT (16U)tLPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)tLPSPI_TCR_TXMSK_MASK (0x40000U)tLPSPI_TCR_TXMSK_SHIFT (18U)tLPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)tLPSPI_TCR_RXMSK_MASK (0x80000U)tLPSPI_TCR_RXMSK_SHIFT (19U)tLPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)tLPSPI_TCR_CONTC_MASK (0x100000U)tLPSPI_TCR_CONTC_SHIFT (20U)tLPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)tLPSPI_TCR_CONT_MASK (0x200000U)tLPSPI_TCR_CONT_SHIFT (21U)tLPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)tLPSPI_TCR_BYSW_MASK (0x400000U)tLPSPI_TCR_BYSW_SHIFT (22U)tLPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)tLPSPI_TCR_LSBF_MASK (0x800000U)tLPSPI_TCR_LSBF_SHIFT (23U)tLPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)tLPSPI_TCR_PCS_MASK (0x3000000U)tLPSPI_TCR_PCS_SHIFT (24U)tLPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)tLPSPI_TCR_PRESCALE_MASK (0x38000000U)tLPSPI_TCR_PRESCALE_SHIFT (27U)tLPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)tLPSPI_TCR_CPHA_MASK (0x40000000U)tLPSPI_TCR_CPHA_SHIFT (30U)tLPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)tLPSPI_TCR_CPOL_MASK (0x80000000U)tLPSPI_TCR_CPOL_SHIFT (31U)tLPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)tLPSPI_TDR_DATA_MASK (0xFFFFFFFFU)uLPSPI_TDR_DATA_SHIFT (0U)uLPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)uLPSPI_RSR_SOF_MASK (0x1U)uLPSPI_RSR_SOF_SHIFT (0U)uLPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)uLPSPI_RSR_RXEMPTY_MASK (0x2U)uLPSPI_RSR_RXEMPTY_SHIFT (1U)uLPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)uLPSPI_RDR_DATA_MASK (0xFFFFFFFFU)uLPSPI_RDR_DATA_SHIFT (0U)uLPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)uLPSPI1_BASE (0x40394000u)uLPSPI1 ((LPSPI_Type *)LPSPI1_BASE)uLPSPI2_BASE (0x40398000u)uLPSPI2 ((LPSPI_Type *)LPSPI2_BASE)uLPSPI3_BASE (0x4039C000u)uLPSPI3 ((LPSPI_Type *)LPSPI3_BASE)uLPSPI4_BASE (0x403A0000u)uLPSPI4 ((LPSPI_Type *)LPSPI4_BASE)uLPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }uLPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }uLPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }uLPUART_VERID_FEATURE_MASK (0xFFFFU)uLPUART_VERID_FEATURE_SHIFT (0U)uLPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)uLPUART_VERID_MINOR_MASK (0xFF0000U)uLPUART_VERID_MINOR_SHIFT (16U)uLPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)uLPUART_VERID_MAJOR_MASK (0xFF000000U)uLPUART_VERID_MAJOR_SHIFT (24U)uLPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)uLPUART_PARAM_TXFIFO_MASK (0xFFU)uLPUART_PARAM_TXFIFO_SHIFT (0U)uLPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)uLPUART_PARAM_RXFIFO_MASK (0xFF00U)uLPUART_PARAM_RXFIFO_SHIFT (8U)uLPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)uLPUART_GLOBAL_RST_MASK (0x2U)uLPUART_GLOBAL_RST_SHIFT (1U)uLPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)uLPUART_PINCFG_TRGSEL_MASK (0x3U)uLPUART_PINCFG_TRGSEL_SHIFT (0U)uLPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)uLPUART_BAUD_SBR_MASK (0x1FFFU)uLPUART_BAUD_SBR_SHIFT (0U)uLPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)uLPUART_BAUD_SBNS_MASK (0x2000U)uLPUART_BAUD_SBNS_SHIFT (13U)uLPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)uLPUART_BAUD_RXEDGIE_MASK (0x4000U)uLPUART_BAUD_RXEDGIE_SHIFT (14U)uLPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)uLPUART_BAUD_LBKDIE_MASK (0x8000U)uLPUART_BAUD_LBKDIE_SHIFT (15U)uLPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)uLPUART_BAUD_RESYNCDIS_MASK (0x10000U)vLPUART_BAUD_RESYNCDIS_SHIFT (16U)vLPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)vLPUART_BAUD_BOTHEDGE_MASK (0x20000U)vLPUART_BAUD_BOTHEDGE_SHIFT (17U)vLPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)vLPUART_BAUD_MATCFG_MASK (0xC0000U)vLPUART_BAUD_MATCFG_SHIFT (18U)vLPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)vLPUART_BAUD_RDMAE_MASK (0x200000U)vLPUART_BAUD_RDMAE_SHIFT (21U)vLPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)vLPUART_BAUD_TDMAE_MASK (0x800000U)vLPUART_BAUD_TDMAE_SHIFT (23U)vLPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)vLPUART_BAUD_OSR_MASK (0x1F000000U)vLPUART_BAUD_OSR_SHIFT (24U)vLPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)vLPUART_BAUD_M10_MASK (0x20000000U)vLPUART_BAUD_M10_SHIFT (29U)vLPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)vLPUART_BAUD_MAEN2_MASK (0x40000000U)vLPUART_BAUD_MAEN2_SHIFT (30U)vLPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)vLPUART_BAUD_MAEN1_MASK (0x80000000U)vLPUART_BAUD_MAEN1_SHIFT (31U)vLPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)vLPUART_STAT_MA2F_MASK (0x4000U)vLPUART_STAT_MA2F_SHIFT (14U)vLPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)vLPUART_STAT_MA1F_MASK (0x8000U)vLPUART_STAT_MA1F_SHIFT (15U)vLPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)vLPUART_STAT_PF_MASK (0x10000U)vLPUART_STAT_PF_SHIFT (16U)vLPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)vLPUART_STAT_FE_MASK (0x20000U)vLPUART_STAT_FE_SHIFT (17U)vLPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)vLPUART_STAT_NF_MASK (0x40000U)vLPUART_STAT_NF_SHIFT (18U)vLPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)vLPUART_STAT_OR_MASK (0x80000U)vLPUART_STAT_OR_SHIFT (19U)vLPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)vLPUART_STAT_IDLE_MASK (0x100000U)vLPUART_STAT_IDLE_SHIFT (20U)vLPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)vLPUART_STAT_RDRF_MASK (0x200000U)vLPUART_STAT_RDRF_SHIFT (21U)vLPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)vLPUART_STAT_TC_MASK (0x400000U)vLPUART_STAT_TC_SHIFT (22U)vLPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)vLPUART_STAT_TDRE_MASK (0x800000U)vLPUART_STAT_TDRE_SHIFT (23U)vLPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)vLPUART_STAT_RAF_MASK (0x1000000U)vLPUART_STAT_RAF_SHIFT (24U)vLPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)vLPUART_STAT_LBKDE_MASK (0x2000000U)vLPUART_STAT_LBKDE_SHIFT (25U)vLPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)vLPUART_STAT_BRK13_MASK (0x4000000U)vLPUART_STAT_BRK13_SHIFT (26U)vLPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)vLPUART_STAT_RWUID_MASK (0x8000000U)vLPUART_STAT_RWUID_SHIFT (27U)vLPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)vLPUART_STAT_RXINV_MASK (0x10000000U)vLPUART_STAT_RXINV_SHIFT (28U)vLPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)vLPUART_STAT_MSBF_MASK (0x20000000U)vLPUART_STAT_MSBF_SHIFT (29U)vLPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)vLPUART_STAT_RXEDGIF_MASK (0x40000000U)vLPUART_STAT_RXEDGIF_SHIFT (30U)vLPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)vLPUART_STAT_LBKDIF_MASK (0x80000000U)vLPUART_STAT_LBKDIF_SHIFT (31U)vLPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)vLPUART_CTRL_PT_MASK (0x1U)vLPUART_CTRL_PT_SHIFT (0U)vLPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)vLPUART_CTRL_PE_MASK (0x2U)vLPUART_CTRL_PE_SHIFT (1U)vLPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)vLPUART_CTRL_ILT_MASK (0x4U)vLPUART_CTRL_ILT_SHIFT (2U)vLPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)vLPUART_CTRL_WAKE_MASK (0x8U)vLPUART_CTRL_WAKE_SHIFT (3U)vLPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)vLPUART_CTRL_M_MASK (0x10U)vLPUART_CTRL_M_SHIFT (4U)vLPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)vLPUART_CTRL_RSRC_MASK (0x20U)vLPUART_CTRL_RSRC_SHIFT (5U)vLPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)vLPUART_CTRL_DOZEEN_MASK (0x40U)vLPUART_CTRL_DOZEEN_SHIFT (6U)vLPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)vLPUART_CTRL_LOOPS_MASK (0x80U)vLPUART_CTRL_LOOPS_SHIFT (7U)vLPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)vLPUART_CTRL_IDLECFG_MASK (0x700U)vLPUART_CTRL_IDLECFG_SHIFT (8U)vLPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)vLPUART_CTRL_M7_MASK (0x800U)vLPUART_CTRL_M7_SHIFT (11U)vLPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)vLPUART_CTRL_MA2IE_MASK (0x4000U)vLPUART_CTRL_MA2IE_SHIFT (14U)vLPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)vLPUART_CTRL_MA1IE_MASK (0x8000U)vLPUART_CTRL_MA1IE_SHIFT (15U)vLPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)vLPUART_CTRL_SBK_MASK (0x10000U)vLPUART_CTRL_SBK_SHIFT (16U)vLPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)vLPUART_CTRL_RWU_MASK (0x20000U)vLPUART_CTRL_RWU_SHIFT (17U)vLPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)vLPUART_CTRL_RE_MASK (0x40000U)vLPUART_CTRL_RE_SHIFT (18U)wLPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)wLPUART_CTRL_TE_MASK (0x80000U)wLPUART_CTRL_TE_SHIFT (19U)wLPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)wLPUART_CTRL_ILIE_MASK (0x100000U)wLPUART_CTRL_ILIE_SHIFT (20U)wLPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)wLPUART_CTRL_RIE_MASK (0x200000U)wLPUART_CTRL_RIE_SHIFT (21U)wLPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)wLPUART_CTRL_TCIE_MASK (0x400000U)wLPUART_CTRL_TCIE_SHIFT (22U)wLPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)wLPUART_CTRL_TIE_MASK (0x800000U)wLPUART_CTRL_TIE_SHIFT (23U)wLPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)wLPUART_CTRL_PEIE_MASK (0x1000000U)wLPUART_CTRL_PEIE_SHIFT (24U)wLPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)wLPUART_CTRL_FEIE_MASK (0x2000000U)wLPUART_CTRL_FEIE_SHIFT (25U)wLPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)wLPUART_CTRL_NEIE_MASK (0x4000000U)wLPUART_CTRL_NEIE_SHIFT (26U)wLPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)wLPUART_CTRL_ORIE_MASK (0x8000000U)wLPUART_CTRL_ORIE_SHIFT (27U)wLPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)wLPUART_CTRL_TXINV_MASK (0x10000000U)wLPUART_CTRL_TXINV_SHIFT (28U)wLPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)wLPUART_CTRL_TXDIR_MASK (0x20000000U)wLPUART_CTRL_TXDIR_SHIFT (29U)wLPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)wLPUART_CTRL_R9T8_MASK (0x40000000U)wLPUART_CTRL_R9T8_SHIFT (30U)wLPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)wLPUART_CTRL_R8T9_MASK (0x80000000U)wLPUART_CTRL_R8T9_SHIFT (31U)wLPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)wLPUART_DATA_R0T0_MASK (0x1U)wLPUART_DATA_R0T0_SHIFT (0U)wLPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)wLPUART_DATA_R1T1_MASK (0x2U)wLPUART_DATA_R1T1_SHIFT (1U)wLPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)wLPUART_DATA_R2T2_MASK (0x4U)wLPUART_DATA_R2T2_SHIFT (2U)wLPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)wLPUART_DATA_R3T3_MASK (0x8U)wLPUART_DATA_R3T3_SHIFT (3U)wLPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)wLPUART_DATA_R4T4_MASK (0x10U)wLPUART_DATA_R4T4_SHIFT (4U)wLPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)wLPUART_DATA_R5T5_MASK (0x20U)wLPUART_DATA_R5T5_SHIFT (5U)wLPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)wLPUART_DATA_R6T6_MASK (0x40U)wLPUART_DATA_R6T6_SHIFT (6U)wLPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)wLPUART_DATA_R7T7_MASK (0x80U)wLPUART_DATA_R7T7_SHIFT (7U)wLPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)wLPUART_DATA_R8T8_MASK (0x100U)wLPUART_DATA_R8T8_SHIFT (8U)wLPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)wLPUART_DATA_R9T9_MASK (0x200U)wLPUART_DATA_R9T9_SHIFT (9U)wLPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)wLPUART_DATA_IDLINE_MASK (0x800U)wLPUART_DATA_IDLINE_SHIFT (11U)wLPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)wLPUART_DATA_RXEMPT_MASK (0x1000U)wLPUART_DATA_RXEMPT_SHIFT (12U)wLPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)wLPUART_DATA_FRETSC_MASK (0x2000U)wLPUART_DATA_FRETSC_SHIFT (13U)wLPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)wLPUART_DATA_PARITYE_MASK (0x4000U)wLPUART_DATA_PARITYE_SHIFT (14U)wLPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)wLPUART_DATA_NOISY_MASK (0x8000U)wLPUART_DATA_NOISY_SHIFT (15U)wLPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)wLPUART_MATCH_MA1_MASK (0x3FFU)wLPUART_MATCH_MA1_SHIFT (0U)wLPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)wLPUART_MATCH_MA2_MASK (0x3FF0000U)wLPUART_MATCH_MA2_SHIFT (16U)wLPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)wLPUART_MODIR_TXCTSE_MASK (0x1U)wLPUART_MODIR_TXCTSE_SHIFT (0U)wLPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)wLPUART_MODIR_TXRTSE_MASK (0x2U)wLPUART_MODIR_TXRTSE_SHIFT (1U)wLPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)wLPUART_MODIR_TXRTSPOL_MASK (0x4U)wLPUART_MODIR_TXRTSPOL_SHIFT (2U)wLPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)wLPUART_MODIR_RXRTSE_MASK (0x8U)wLPUART_MODIR_RXRTSE_SHIFT (3U)wLPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)wLPUART_MODIR_TXCTSC_MASK (0x10U)wLPUART_MODIR_TXCTSC_SHIFT (4U)wLPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)wLPUART_MODIR_TXCTSSRC_MASK (0x20U)wLPUART_MODIR_TXCTSSRC_SHIFT (5U)wLPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)wLPUART_MODIR_RTSWATER_MASK (0x300U)wLPUART_MODIR_RTSWATER_SHIFT (8U)wLPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)wLPUART_MODIR_TNP_MASK (0x30000U)wLPUART_MODIR_TNP_SHIFT (16U)wLPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)wLPUART_MODIR_IREN_MASK (0x40000U)wLPUART_MODIR_IREN_SHIFT (18U)wLPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)wLPUART_FIFO_RXFIFOSIZE_MASK (0x7U)wLPUART_FIFO_RXFIFOSIZE_SHIFT (0U)xLPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)xLPUART_FIFO_RXFE_MASK (0x8U)xLPUART_FIFO_RXFE_SHIFT (3U)xLPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)xLPUART_FIFO_TXFIFOSIZE_MASK (0x70U)xLPUART_FIFO_TXFIFOSIZE_SHIFT (4U)xLPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)xLPUART_FIFO_TXFE_MASK (0x80U)xLPUART_FIFO_TXFE_SHIFT (7U)xLPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)xLPUART_FIFO_RXUFE_MASK (0x100U)xLPUART_FIFO_RXUFE_SHIFT (8U)xLPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)xLPUART_FIFO_TXOFE_MASK (0x200U)xLPUART_FIFO_TXOFE_SHIFT (9U)xLPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)xLPUART_FIFO_RXIDEN_MASK (0x1C00U)xLPUART_FIFO_RXIDEN_SHIFT (10U)xLPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)xLPUART_FIFO_RXFLUSH_MASK (0x4000U)xLPUART_FIFO_RXFLUSH_SHIFT (14U)xLPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)xLPUART_FIFO_TXFLUSH_MASK (0x8000U)xLPUART_FIFO_TXFLUSH_SHIFT (15U)xLPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)xLPUART_FIFO_RXUF_MASK (0x10000U)xLPUART_FIFO_RXUF_SHIFT (16U)xLPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)xLPUART_FIFO_TXOF_MASK (0x20000U)xLPUART_FIFO_TXOF_SHIFT (17U)xLPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)xLPUART_FIFO_RXEMPT_MASK (0x400000U)xLPUART_FIFO_RXEMPT_SHIFT (22U)xLPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)xLPUART_FIFO_TXEMPT_MASK (0x800000U)xLPUART_FIFO_TXEMPT_SHIFT (23U)xLPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)xLPUART_WATER_TXWATER_MASK (0x3U)xLPUART_WATER_TXWATER_SHIFT (0U)xLPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)xLPUART_WATER_TXCOUNT_MASK (0x700U)xLPUART_WATER_TXCOUNT_SHIFT (8U)xLPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)xLPUART_WATER_RXWATER_MASK (0x30000U)xLPUART_WATER_RXWATER_SHIFT (16U)xLPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)xLPUART_WATER_RXCOUNT_MASK (0x7000000U)xLPUART_WATER_RXCOUNT_SHIFT (24U)xLPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)xLPUART1_BASE (0x40184000u)xLPUART1 ((LPUART_Type *)LPUART1_BASE)xLPUART2_BASE (0x40188000u)xLPUART2 ((LPUART_Type *)LPUART2_BASE)xLPUART3_BASE (0x4018C000u)xLPUART3 ((LPUART_Type *)LPUART3_BASE)xLPUART4_BASE (0x40190000u)xLPUART4 ((LPUART_Type *)LPUART4_BASE)xLPUART5_BASE (0x40194000u)xLPUART5 ((LPUART_Type *)LPUART5_BASE)xLPUART6_BASE (0x40198000u)xLPUART6 ((LPUART_Type *)LPUART6_BASE)xLPUART7_BASE (0x4019C000u)xLPUART7 ((LPUART_Type *)LPUART7_BASE)xLPUART8_BASE (0x401A0000u)xLPUART8 ((LPUART_Type *)LPUART8_BASE)xLPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }xLPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }xLPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }yOCOTP_CTRL_ADDR_MASK (0x3FU)yOCOTP_CTRL_ADDR_SHIFT (0U)yOCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)yOCOTP_CTRL_BUSY_MASK (0x100U)yOCOTP_CTRL_BUSY_SHIFT (8U)yOCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)yOCOTP_CTRL_ERROR_MASK (0x200U)yOCOTP_CTRL_ERROR_SHIFT (9U)yOCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)yOCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)yOCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)yOCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)yOCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)yOCOTP_CTRL_WR_UNLOCK_SHIFT (16U)yOCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)yOCOTP_CTRL_SET_ADDR_MASK (0x3FU)yOCOTP_CTRL_SET_ADDR_SHIFT (0U)yOCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)yOCOTP_CTRL_SET_BUSY_MASK (0x100U)yOCOTP_CTRL_SET_BUSY_SHIFT (8U)yOCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)yOCOTP_CTRL_SET_ERROR_MASK (0x200U)yOCOTP_CTRL_SET_ERROR_SHIFT (9U)yOCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)yOCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)yOCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)yOCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)yOCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)zOCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)zOCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)zOCOTP_CTRL_CLR_ADDR_MASK (0x3FU)zOCOTP_CTRL_CLR_ADDR_SHIFT (0U)zOCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)zOCOTP_CTRL_CLR_BUSY_MASK (0x100U)zOCOTP_CTRL_CLR_BUSY_SHIFT (8U)zOCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)zOCOTP_CTRL_CLR_ERROR_MASK (0x200U)zOCOTP_CTRL_CLR_ERROR_SHIFT (9U)zOCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)zOCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)zOCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)zOCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)zOCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)zOCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)zOCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)zOCOTP_CTRL_TOG_ADDR_MASK (0x3FU)zOCOTP_CTRL_TOG_ADDR_SHIFT (0U)zOCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)zOCOTP_CTRL_TOG_BUSY_MASK (0x100U)zOCOTP_CTRL_TOG_BUSY_SHIFT (8U)zOCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)zOCOTP_CTRL_TOG_ERROR_MASK (0x200U)zOCOTP_CTRL_TOG_ERROR_SHIFT (9U)zOCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)zOCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)zOCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)zOCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)zOCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)zOCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)zOCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)zOCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)zOCOTP_TIMING_STROBE_PROG_SHIFT (0U)zOCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)zOCOTP_TIMING_RELAX_MASK (0xF000U)zOCOTP_TIMING_RELAX_SHIFT (12U)zOCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)zOCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)zOCOTP_TIMING_STROBE_READ_SHIFT (16U)zOCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)zOCOTP_TIMING_WAIT_MASK (0xFC00000U)zOCOTP_TIMING_WAIT_SHIFT (22U)zOCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)zOCOTP_DATA_DATA_MASK (0xFFFFFFFFU)zOCOTP_DATA_DATA_SHIFT (0U)zOCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)zOCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)zOCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)zOCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)zOCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)zOCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)zOCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)zOCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)zOCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)zOCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)zOCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)zOCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)zOCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)zOCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)zOCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)zOCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)zOCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)zOCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)zOCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)zOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)zOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)zOCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)zOCOTP_SCS_HAB_JDE_MASK (0x1U)zOCOTP_SCS_HAB_JDE_SHIFT (0U)zOCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)zOCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)zOCOTP_SCS_SPARE_SHIFT (1U)zOCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)zOCOTP_SCS_LOCK_MASK (0x80000000U)zOCOTP_SCS_LOCK_SHIFT (31U)zOCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)zOCOTP_SCS_SET_HAB_JDE_MASK (0x1U)zOCOTP_SCS_SET_HAB_JDE_SHIFT (0U)zOCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)zOCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)zOCOTP_SCS_SET_SPARE_SHIFT (1U)zOCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)zOCOTP_SCS_SET_LOCK_MASK (0x80000000U)zOCOTP_SCS_SET_LOCK_SHIFT (31U)zOCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)zOCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)zOCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)zOCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)zOCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)zOCOTP_SCS_CLR_SPARE_SHIFT (1U)zOCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)zOCOTP_SCS_CLR_LOCK_MASK (0x80000000U)zOCOTP_SCS_CLR_LOCK_SHIFT (31U)zOCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)zOCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)zOCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)zOCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)zOCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)zOCOTP_SCS_TOG_SPARE_SHIFT (1U)zOCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)zOCOTP_SCS_TOG_LOCK_MASK (0x80000000U)zOCOTP_SCS_TOG_LOCK_SHIFT (31U)zOCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK){OCOTP_VERSION_STEP_MASK (0xFFFFU){OCOTP_VERSION_STEP_SHIFT (0U){OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK){OCOTP_VERSION_MINOR_MASK (0xFF0000U){OCOTP_VERSION_MINOR_SHIFT (16U){OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK){OCOTP_VERSION_MAJOR_MASK (0xFF000000U){OCOTP_VERSION_MAJOR_SHIFT (24U){OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK){OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU){OCOTP_TIMING2_RELAX_PROG_SHIFT (0U){OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK){OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U){OCOTP_TIMING2_RELAX_READ_SHIFT (16U){OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK){OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U){OCOTP_TIMING2_RELAX1_SHIFT (22U){OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK){OCOTP_LOCK_TESTER_MASK (0x3U){OCOTP_LOCK_TESTER_SHIFT (0U){OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK){OCOTP_LOCK_BOOT_CFG_MASK (0xCU){OCOTP_LOCK_BOOT_CFG_SHIFT (2U){OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK){OCOTP_LOCK_MEM_TRIM_MASK (0x30U){OCOTP_LOCK_MEM_TRIM_SHIFT (4U){OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK){OCOTP_LOCK_SJC_RESP_MASK (0x40U){OCOTP_LOCK_SJC_RESP_SHIFT (6U){OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK){OCOTP_LOCK_MAC_ADDR_MASK (0x300U){OCOTP_LOCK_MAC_ADDR_SHIFT (8U){OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK){OCOTP_LOCK_GP1_MASK (0xC00U){OCOTP_LOCK_GP1_SHIFT (10U){OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK){OCOTP_LOCK_GP2_MASK (0x3000U){OCOTP_LOCK_GP2_SHIFT (12U){OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK){OCOTP_LOCK_SRK_MASK (0x4000U){OCOTP_LOCK_SRK_SHIFT (14U){OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK){OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U){OCOTP_LOCK_OTPMK_MSB_SHIFT (15U){OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK){OCOTP_LOCK_SW_GP1_MASK (0x10000U){OCOTP_LOCK_SW_GP1_SHIFT (16U){OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK){OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U){OCOTP_LOCK_OTPMK_LSB_SHIFT (17U){OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK){OCOTP_LOCK_ANALOG_MASK (0xC0000U){OCOTP_LOCK_ANALOG_SHIFT (18U){OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK){OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U){OCOTP_LOCK_OTPMK_CRC_SHIFT (20U){OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK){OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U){OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U){OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK){OCOTP_LOCK_MISC_CONF_MASK (0x400000U){OCOTP_LOCK_MISC_CONF_SHIFT (22U){OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK){OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U){OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U){OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK){OCOTP_LOCK_GP3_MASK (0xC000000U){OCOTP_LOCK_GP3_SHIFT (26U){OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK){OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U){OCOTP_LOCK_FIELD_RETURN_SHIFT (28U){OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK){OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG0_BITS_SHIFT (0U){OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK){OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG1_BITS_SHIFT (0U){OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK){OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG2_BITS_SHIFT (0U){OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK){OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG3_BITS_SHIFT (0U){OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK){OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG4_BITS_SHIFT (0U){OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK){OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG5_BITS_SHIFT (0U){OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK){OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU){OCOTP_CFG6_BITS_SHIFT (0U){OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK){OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU){OCOTP_MEM0_BITS_SHIFT (0U){OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK){OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU){OCOTP_MEM1_BITS_SHIFT (0U){OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK){OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU){OCOTP_MEM2_BITS_SHIFT (0U){OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)|OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)|OCOTP_MEM3_BITS_SHIFT (0U)|OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)|OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)|OCOTP_MEM4_BITS_SHIFT (0U)|OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)|OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)|OCOTP_ANA0_BITS_SHIFT (0U)|OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)|OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)|OCOTP_ANA1_BITS_SHIFT (0U)|OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)|OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)|OCOTP_ANA2_BITS_SHIFT (0U)|OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)|OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK0_BITS_SHIFT (0U)|OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)|OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK1_BITS_SHIFT (0U)|OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)|OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK2_BITS_SHIFT (0U)|OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)|OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK3_BITS_SHIFT (0U)|OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)|OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK4_BITS_SHIFT (0U)|OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)|OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK5_BITS_SHIFT (0U)|OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)|OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK6_BITS_SHIFT (0U)|OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)|OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)|OCOTP_SRK7_BITS_SHIFT (0U)|OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)|OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)|OCOTP_SJC_RESP0_BITS_SHIFT (0U)|OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)|OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)|OCOTP_SJC_RESP1_BITS_SHIFT (0U)|OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)|OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)|OCOTP_MAC0_BITS_SHIFT (0U)|OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)|OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)|OCOTP_MAC1_BITS_SHIFT (0U)|OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)|OCOTP_GP3_BITS_MASK (0xFFFFFFFFU)|OCOTP_GP3_BITS_SHIFT (0U)|OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)|OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)|OCOTP_GP1_BITS_SHIFT (0U)|OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)|OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)|OCOTP_GP2_BITS_SHIFT (0U)|OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)|OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP1_BITS_SHIFT (0U)|OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)|OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP20_BITS_SHIFT (0U)|OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)|OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP21_BITS_SHIFT (0U)|OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)|OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP22_BITS_SHIFT (0U)|OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)|OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)|OCOTP_SW_GP23_BITS_SHIFT (0U)|OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)|OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)|OCOTP_MISC_CONF0_BITS_SHIFT (0U)|OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)}OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)}OCOTP_MISC_CONF1_BITS_SHIFT (0U)}OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)}OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)}OCOTP_SRK_REVOKE_BITS_SHIFT (0U)}OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)}OCOTP_BASE (0x401F4000u)}OCOTP ((OCOTP_Type *)OCOTP_BASE)}OCOTP_BASE_ADDRS { OCOTP_BASE }}OCOTP_BASE_PTRS { OCOTP }}PGC_MEGA_CTRL_PCR_MASK (0x1U)}PGC_MEGA_CTRL_PCR_SHIFT (0U)}PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)}PGC_MEGA_PUPSCR_SW_MASK (0x3FU)}PGC_MEGA_PUPSCR_SW_SHIFT (0U)}PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)}PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)}PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)}PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)}PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)}PGC_MEGA_PDNSCR_ISO_SHIFT (0U)}PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)}PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)}PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)}PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)}PGC_MEGA_SR_PSR_MASK (0x1U)}PGC_MEGA_SR_PSR_SHIFT (0U)}PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)}PGC_CPU_CTRL_PCR_MASK (0x1U)}PGC_CPU_CTRL_PCR_SHIFT (0U)}PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)}PGC_CPU_PUPSCR_SW_MASK (0x3FU)}PGC_CPU_PUPSCR_SW_SHIFT (0U)}PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)}PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)}PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)}PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)}PGC_CPU_PDNSCR_ISO_MASK (0x3FU)}PGC_CPU_PDNSCR_ISO_SHIFT (0U)}PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)}PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)}PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)}PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)}PGC_CPU_SR_PSR_MASK (0x1U)}PGC_CPU_SR_PSR_SHIFT (0U)}PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)}PGC_BASE (0x400F4000u)}PGC ((PGC_Type *)PGC_BASE)~PGC_BASE_ADDRS { PGC_BASE }~PGC_BASE_PTRS { PGC }~PIT_MCR_FRZ_MASK (0x1U)~PIT_MCR_FRZ_SHIFT (0U)~PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)~PIT_MCR_MDIS_MASK (0x2U)~PIT_MCR_MDIS_SHIFT (1U)~PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)~PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)~PIT_LTMR64H_LTH_SHIFT (0U)~PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)~PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)~PIT_LTMR64L_LTL_SHIFT (0U)~PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)~PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)~PIT_LDVAL_TSV_SHIFT (0U)~PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)~PIT_LDVAL_COUNT (4U)~PIT_CVAL_TVL_MASK (0xFFFFFFFFU)~PIT_CVAL_TVL_SHIFT (0U)~PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)~PIT_CVAL_COUNT (4U)~PIT_TCTRL_TEN_MASK (0x1U)~PIT_TCTRL_TEN_SHIFT (0U)~PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)~PIT_TCTRL_TIE_MASK (0x2U)~PIT_TCTRL_TIE_SHIFT (1U)~PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)~PIT_TCTRL_CHN_MASK (0x4U)~PIT_TCTRL_CHN_SHIFT (2U)~PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)~PIT_TCTRL_COUNT (4U)~PIT_TFLG_TIF_MASK (0x1U)~PIT_TFLG_TIF_SHIFT (0U)~PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)~PIT_TFLG_COUNT (4U)~PIT_BASE (0x40084000u)~PIT ((PIT_Type *)PIT_BASE)~PIT_BASE_ADDRS { PIT_BASE }~PIT_BASE_PTRS { PIT }~PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)PMU_REG_1P1_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)PMU_REG_3P0_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)PMU_REG_3P0_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)PMU_REG_3P0_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)€PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)ÀPMU_REG_3P0_OK_VDD3P0_SHIFT (17U)ĀPMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)ǀPMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)ȀPMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)ɀPMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)ʀPMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)ˀPMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)̀PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)̀PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)΀PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)πPMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)ЀPMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)рPMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)ҀPMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)ӀPMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)ԀPMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)ՀPMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)րPMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)׀PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)؀PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)ـPMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)ڀPMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)ۀPMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)܀PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)݀PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)ހPMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)PMU_REG_2P5_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)ÁPMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)āPMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)ŁPMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)ƁPMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)ǁPMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)ȁPMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)ɁPMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)ʁPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)ˁPMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)́PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)ρPMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)ЁPMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)сPMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)ҁPMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)ӁPMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)ԁPMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)ՁPMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)ցPMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)ׁPMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)؁PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)فPMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)ځPMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)ہPMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)܁PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)݁PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)ށPMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)߁PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)PMU_REG_CORE_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_REG0_TARG_SHIFT (0U)PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_REG2_TARG_SHIFT (18U)PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)PMU_MISC0_REFTOP_PWD_MASK (0x1U)‚PMU_MISC0_REFTOP_PWD_SHIFT (0U)ÂPMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)ĂPMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)łPMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)ƂPMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)ǂPMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)ȂPMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)ɂPMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)ʂPMU_MISC0_REFTOP_VBGUP_MASK (0x80U)˂PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)̂PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)͂PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)΂PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)ςPMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)ЂPMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)тPMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)҂PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)ӂPMU_MISC0_OSC_I_MASK (0x6000U)ԂPMU_MISC0_OSC_I_SHIFT (13U)ՂPMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)ւPMU_MISC0_OSC_XTALOK_MASK (0x8000U)ׂPMU_MISC0_OSC_XTALOK_SHIFT (15U)؂PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)قPMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)ڂPMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)ۂPMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)܂PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)݂PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)ނPMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)߂PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)PMU_MISC0_SET_OSC_I_MASK (0x6000U)PMU_MISC0_SET_OSC_I_SHIFT (13U)PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)PMU_MISC0_CLR_OSC_I_MASK (0x6000U)PMU_MISC0_CLR_OSC_I_SHIFT (13U)PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)ƒPMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)ŃPMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)ƃPMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)ǃPMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)ȃPMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)ɃPMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)ʃPMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)˃PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)̃PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)̓PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)΃PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)σPMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)ЃPMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)уPMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)҃PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)ӃPMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)ԃPMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)ՃPMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)փPMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)׃PMU_MISC0_TOG_OSC_I_MASK (0x6000U)؃PMU_MISC0_TOG_OSC_I_SHIFT (13U)كPMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)ڃPMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)ۃPMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)܃PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)݃PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)ރPMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)߃PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)„PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)ÄPMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)ĄPMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)ńPMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)ƄPMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)DŽPMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)ȄPMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)ɄPMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)ʄPMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)˄PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)̄PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)̈́PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)΄PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)фPMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)҄PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)ӄPMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)ԄPMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)ՄPMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)քPMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)ׄPMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)؄PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)لPMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)ڄPMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)ۄPMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)܄PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)݄PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)ބPMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)߄PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)PMU_MISC2_PLL3_disable_MASK (0x80U)PMU_MISC2_PLL3_disable_SHIFT (7U)PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)PMU_MISC2_REG2_OK_MASK (0x400000U)PMU_MISC2_REG2_OK_SHIFT (22U)PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)PMU_MISC2_VIDEO_DIV_SHIFT (30U)PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)PMU_MISC2_SET_PLL3_disable_MASK (0x80U)PMU_MISC2_SET_PLL3_disable_SHIFT (7U)PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)PMU_MISC2_SET_REG2_OK_MASK (0x400000U)PMU_MISC2_SET_REG2_OK_SHIFT (22U)PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)ÅPMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)ąPMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)ŅPMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)ƅPMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)DžPMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)ȅPMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)ɅPMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)ʅPMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)˅PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)̅PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)ͅPMU_MISC2_CLR_PLL3_disable_SHIFT (7U)΅PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)υPMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)ЅPMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)хPMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)҅PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)ӅPMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)ԅPMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)ՅPMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)օPMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)ׅPMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)؅PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)مPMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)څPMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)ۅPMU_MISC2_CLR_REG2_OK_MASK (0x400000U)܅PMU_MISC2_CLR_REG2_OK_SHIFT (22U)݅PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)ޅPMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)߅PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)PMU_MISC2_TOG_REG2_OK_SHIFT (22U)PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)PMU_BASE (0x400D8000u)PMU ((PMU_Type *)PMU_BASE)PMU_BASE_ADDRS { PMU_BASE }PMU_BASE_PTRS { PMU }PWM_CNT_CNT_MASK (0xFFFFU)PWM_CNT_CNT_SHIFT (0U)PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)PWM_CNT_COUNT (4U)PWM_INIT_INIT_MASK (0xFFFFU)PWM_INIT_INIT_SHIFT (0U)PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)PWM_INIT_COUNT (4U)PWM_CTRL2_CLK_SEL_MASK (0x3U)PWM_CTRL2_CLK_SEL_SHIFT (0U)PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)PWM_CTRL2_RELOAD_SEL_MASK (0x4U)PWM_CTRL2_RELOAD_SEL_SHIFT (2U)PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)PWM_CTRL2_FORCE_SEL_MASK (0x38U)PWM_CTRL2_FORCE_SEL_SHIFT (3U)PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)PWM_CTRL2_FORCE_MASK (0x40U)PWM_CTRL2_FORCE_SHIFT (6U)PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)PWM_CTRL2_FRCEN_MASK (0x80U)PWM_CTRL2_FRCEN_SHIFT (7U)PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)PWM_CTRL2_INIT_SEL_MASK (0x300U)PWM_CTRL2_INIT_SEL_SHIFT (8U)PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)PWM_CTRL2_PWMX_INIT_MASK (0x400U)PWM_CTRL2_PWMX_INIT_SHIFT (10U)PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)PWM_CTRL2_PWM45_INIT_MASK (0x800U)PWM_CTRL2_PWM45_INIT_SHIFT (11U)PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)PWM_CTRL2_PWM23_INIT_MASK (0x1000U)PWM_CTRL2_PWM23_INIT_SHIFT (12U)PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)PWM_CTRL2_INDEP_MASK (0x2000U)PWM_CTRL2_INDEP_SHIFT (13U)PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)PWM_CTRL2_WAITEN_MASK (0x4000U)PWM_CTRL2_WAITEN_SHIFT (14U)PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)PWM_CTRL2_DBGEN_MASK (0x8000U)PWM_CTRL2_DBGEN_SHIFT (15U)PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)PWM_CTRL2_COUNT (4U)PWM_CTRL_DBLEN_MASK (0x1U)PWM_CTRL_DBLEN_SHIFT (0U)PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)PWM_CTRL_DBLX_MASK (0x2U)PWM_CTRL_DBLX_SHIFT (1U)PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)PWM_CTRL_LDMOD_MASK (0x4U)PWM_CTRL_LDMOD_SHIFT (2U)PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)PWM_CTRL_SPLIT_MASK (0x8U)PWM_CTRL_SPLIT_SHIFT (3U)PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)PWM_CTRL_PRSC_MASK (0x70U)PWM_CTRL_PRSC_SHIFT (4U)PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)PWM_CTRL_COMPMODE_MASK (0x80U)‡PWM_CTRL_COMPMODE_SHIFT (7U)ÇPWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)ćPWM_CTRL_DT_MASK (0x300U)ŇPWM_CTRL_DT_SHIFT (8U)ƇPWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)LJPWM_CTRL_FULL_MASK (0x400U)ȇPWM_CTRL_FULL_SHIFT (10U)ɇPWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)ʇPWM_CTRL_HALF_MASK (0x800U)ˇPWM_CTRL_HALF_SHIFT (11U)̇PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)͇PWM_CTRL_LDFQ_MASK (0xF000U)·PWM_CTRL_LDFQ_SHIFT (12U)χPWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)҇PWM_CTRL_COUNT (4U)ՇPWM_VAL0_VAL0_MASK (0xFFFFU)ևPWM_VAL0_VAL0_SHIFT (0U)ׇPWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)ڇPWM_VAL0_COUNT (4U)݇PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)އPWM_FRACVAL1_FRACVAL1_SHIFT (11U)߇PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)PWM_FRACVAL1_COUNT (4U)PWM_VAL1_VAL1_MASK (0xFFFFU)PWM_VAL1_VAL1_SHIFT (0U)PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)PWM_VAL1_COUNT (4U)PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)PWM_FRACVAL2_FRACVAL2_SHIFT (11U)PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)PWM_FRACVAL2_COUNT (4U)PWM_VAL2_VAL2_MASK (0xFFFFU)PWM_VAL2_VAL2_SHIFT (0U)PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)PWM_VAL2_COUNT (4U)PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)PWM_FRACVAL3_FRACVAL3_SHIFT (11U)PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)PWM_FRACVAL3_COUNT (4U)PWM_VAL3_VAL3_MASK (0xFFFFU)PWM_VAL3_VAL3_SHIFT (0U)PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)PWM_VAL3_COUNT (4U)PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)PWM_FRACVAL4_FRACVAL4_SHIFT (11U)PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)PWM_FRACVAL4_COUNT (4U)PWM_VAL4_VAL4_MASK (0xFFFFU)PWM_VAL4_VAL4_SHIFT (0U)PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)PWM_VAL4_COUNT (4U)PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)PWM_FRACVAL5_FRACVAL5_SHIFT (11U)PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)PWM_FRACVAL5_COUNT (4U)PWM_VAL5_VAL5_MASK (0xFFFFU)PWM_VAL5_VAL5_SHIFT (0U)PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)PWM_VAL5_COUNT (4U)PWM_FRCTRL_FRAC1_EN_MASK (0x2U)PWM_FRCTRL_FRAC1_EN_SHIFT (1U)PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)PWM_FRCTRL_FRAC23_EN_MASK (0x4U)PWM_FRCTRL_FRAC23_EN_SHIFT (2U)PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)PWM_FRCTRL_FRAC45_EN_MASK (0x10U)PWM_FRCTRL_FRAC45_EN_SHIFT (4U)PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)PWM_FRCTRL_FRAC_PU_MASK (0x100U)PWM_FRCTRL_FRAC_PU_SHIFT (8U)PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)PWM_FRCTRL_TEST_MASK (0x8000U)PWM_FRCTRL_TEST_SHIFT (15U)PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)PWM_FRCTRL_COUNT (4U)PWM_OCTRL_PWMXFS_MASK (0x3U)ˆPWM_OCTRL_PWMXFS_SHIFT (0U)ÈPWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)ĈPWM_OCTRL_PWMBFS_MASK (0xCU)ňPWM_OCTRL_PWMBFS_SHIFT (2U)ƈPWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)LjPWM_OCTRL_PWMAFS_MASK (0x30U)ȈPWM_OCTRL_PWMAFS_SHIFT (4U)ɈPWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)ʈPWM_OCTRL_POLX_MASK (0x100U)ˈPWM_OCTRL_POLX_SHIFT (8U)̈PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)͈PWM_OCTRL_POLB_MASK (0x200U)ΈPWM_OCTRL_POLB_SHIFT (9U)ψPWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)ЈPWM_OCTRL_POLA_MASK (0x400U)шPWM_OCTRL_POLA_SHIFT (10U)҈PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)ӈPWM_OCTRL_PWMX_IN_MASK (0x2000U)ԈPWM_OCTRL_PWMX_IN_SHIFT (13U)ՈPWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)ֈPWM_OCTRL_PWMB_IN_MASK (0x4000U)׈PWM_OCTRL_PWMB_IN_SHIFT (14U)؈PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)وPWM_OCTRL_PWMA_IN_MASK (0x8000U)ڈPWM_OCTRL_PWMA_IN_SHIFT (15U)ۈPWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)ވPWM_OCTRL_COUNT (4U)PWM_STS_CMPF_MASK (0x3FU)PWM_STS_CMPF_SHIFT (0U)PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)PWM_STS_CFX0_MASK (0x40U)PWM_STS_CFX0_SHIFT (6U)PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)PWM_STS_CFX1_MASK (0x80U)PWM_STS_CFX1_SHIFT (7U)PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)PWM_STS_CFB0_MASK (0x100U)PWM_STS_CFB0_SHIFT (8U)PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)PWM_STS_CFB1_MASK (0x200U)PWM_STS_CFB1_SHIFT (9U)PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)PWM_STS_CFA0_MASK (0x400U)PWM_STS_CFA0_SHIFT (10U)PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)PWM_STS_CFA1_MASK (0x800U)PWM_STS_CFA1_SHIFT (11U)PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)PWM_STS_RF_MASK (0x1000U)PWM_STS_RF_SHIFT (12U)PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)PWM_STS_REF_MASK (0x2000U)PWM_STS_REF_SHIFT (13U)PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)PWM_STS_RUF_MASK (0x4000U)PWM_STS_RUF_SHIFT (14U)PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)PWM_STS_COUNT (4U)PWM_INTEN_CMPIE_MASK (0x3FU)PWM_INTEN_CMPIE_SHIFT (0U)PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)PWM_INTEN_CX0IE_MASK (0x40U)PWM_INTEN_CX0IE_SHIFT (6U)PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)PWM_INTEN_CX1IE_MASK (0x80U)PWM_INTEN_CX1IE_SHIFT (7U)PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)PWM_INTEN_CB0IE_MASK (0x100U)PWM_INTEN_CB0IE_SHIFT (8U)PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)PWM_INTEN_CB1IE_MASK (0x200U)PWM_INTEN_CB1IE_SHIFT (9U)PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)PWM_INTEN_CA0IE_MASK (0x400U)PWM_INTEN_CA0IE_SHIFT (10U)PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)PWM_INTEN_CA1IE_MASK (0x800U)PWM_INTEN_CA1IE_SHIFT (11U)PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)PWM_INTEN_RIE_MASK (0x1000U)PWM_INTEN_RIE_SHIFT (12U)PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)PWM_INTEN_REIE_MASK (0x2000U)PWM_INTEN_REIE_SHIFT (13U)PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)PWM_INTEN_COUNT (4U)PWM_DMAEN_CX0DE_MASK (0x1U)PWM_DMAEN_CX0DE_SHIFT (0U)PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)PWM_DMAEN_CX1DE_MASK (0x2U)PWM_DMAEN_CX1DE_SHIFT (1U)PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)PWM_DMAEN_CB0DE_MASK (0x4U)PWM_DMAEN_CB0DE_SHIFT (2U)PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)PWM_DMAEN_CB1DE_MASK (0x8U)PWM_DMAEN_CB1DE_SHIFT (3U)PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)PWM_DMAEN_CA0DE_MASK (0x10U)PWM_DMAEN_CA0DE_SHIFT (4U)PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)PWM_DMAEN_CA1DE_MASK (0x20U)PWM_DMAEN_CA1DE_SHIFT (5U)PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)PWM_DMAEN_CAPTDE_MASK (0xC0U)PWM_DMAEN_CAPTDE_SHIFT (6U)PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)PWM_DMAEN_FAND_MASK (0x100U)PWM_DMAEN_FAND_SHIFT (8U)PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)PWM_DMAEN_VALDE_MASK (0x200U)PWM_DMAEN_VALDE_SHIFT (9U)PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)PWM_DMAEN_COUNT (4U)ĉPWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)ʼnPWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)ƉPWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)ljPWM_TCTRL_TRGFRQ_MASK (0x1000U)ȉPWM_TCTRL_TRGFRQ_SHIFT (12U)ɉPWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)ʉPWM_TCTRL_PWBOT1_MASK (0x4000U)ˉPWM_TCTRL_PWBOT1_SHIFT (14U)̉PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)͉PWM_TCTRL_PWAOT0_MASK (0x8000U)ΉPWM_TCTRL_PWAOT0_SHIFT (15U)ωPWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)҉PWM_TCTRL_COUNT (4U)ՉPWM_DISMAP_DIS0A_MASK (0xFU)։PWM_DISMAP_DIS0A_SHIFT (0U)׉PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)؉PWM_DISMAP_DIS1A_MASK (0xFU)ىPWM_DISMAP_DIS1A_SHIFT (0U)ډPWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)ۉPWM_DISMAP_DIS0B_MASK (0xF0U)܉PWM_DISMAP_DIS0B_SHIFT (4U)݉PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)މPWM_DISMAP_DIS1B_MASK (0xF0U)߉PWM_DISMAP_DIS1B_SHIFT (4U)PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)PWM_DISMAP_DIS1X_MASK (0xF00U)PWM_DISMAP_DIS1X_SHIFT (8U)PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)PWM_DISMAP_DIS0X_MASK (0xF00U)PWM_DISMAP_DIS0X_SHIFT (8U)PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)PWM_DISMAP_COUNT (4U)PWM_DISMAP_COUNT2 (2U)PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)PWM_DTCNT0_DTCNT0_SHIFT (0U)PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)PWM_DTCNT0_COUNT (4U)PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)PWM_DTCNT1_DTCNT1_SHIFT (0U)PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)PWM_DTCNT1_COUNT (4U)PWM_CAPTCTRLA_ARMA_MASK (0x1U)PWM_CAPTCTRLA_ARMA_SHIFT (0U)PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)PWM_CAPTCTRLA_EDGA0_MASK (0xCU)PWM_CAPTCTRLA_EDGA0_SHIFT (2U)PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)PWM_CAPTCTRLA_EDGA1_MASK (0x30U)PWM_CAPTCTRLA_EDGA1_SHIFT (4U)PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)PWM_CAPTCTRLA_CFAWM_MASK (0x300U)PWM_CAPTCTRLA_CFAWM_SHIFT (8U)PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)PWM_CAPTCTRLA_COUNT (4U)PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)PWM_CAPTCOMPA_COUNT (4U)PWM_CAPTCTRLB_ARMB_MASK (0x1U)PWM_CAPTCTRLB_ARMB_SHIFT (0U)PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)PWM_CAPTCTRLB_EDGB0_MASK (0xCU)PWM_CAPTCTRLB_EDGB0_SHIFT (2U)PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)PWM_CAPTCTRLB_EDGB1_MASK (0x30U)PWM_CAPTCTRLB_EDGB1_SHIFT (4U)PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)PWM_CAPTCTRLB_CFBWM_MASK (0x300U)PWM_CAPTCTRLB_CFBWM_SHIFT (8U)PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)ŠPWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)ÊPWM_CAPTCTRLB_CB1CNT_SHIFT (13U)ĊPWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)NJPWM_CAPTCTRLB_COUNT (4U)ʊPWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)ˊPWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)̊PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)͊PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)ΊPWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)ϊPWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)ҊPWM_CAPTCOMPB_COUNT (4U)ՊPWM_CAPTCTRLX_ARMX_MASK (0x1U)֊PWM_CAPTCTRLX_ARMX_SHIFT (0U)׊PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)؊PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)يPWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)ڊPWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)ۊPWM_CAPTCTRLX_EDGX0_MASK (0xCU)܊PWM_CAPTCTRLX_EDGX0_SHIFT (2U)݊PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)ފPWM_CAPTCTRLX_EDGX1_MASK (0x30U)ߊPWM_CAPTCTRLX_EDGX1_SHIFT (4U)PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)PWM_CAPTCTRLX_CFXWM_MASK (0x300U)PWM_CAPTCTRLX_CFXWM_SHIFT (8U)PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)PWM_CAPTCTRLX_COUNT (4U)PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)PWM_CAPTCOMPX_COUNT (4U)PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)PWM_CVAL0_CAPTVAL0_SHIFT (0U)PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)PWM_CVAL0_COUNT (4U)PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)PWM_CVAL0CYC_COUNT (4U)PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)PWM_CVAL1_CAPTVAL1_SHIFT (0U)PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)PWM_CVAL1_COUNT (4U)PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)PWM_CVAL1CYC_COUNT (4U)PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)PWM_CVAL2_CAPTVAL2_SHIFT (0U)PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)PWM_CVAL2_COUNT (4U)PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)PWM_CVAL2CYC_COUNT (4U)PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)PWM_CVAL3_CAPTVAL3_SHIFT (0U)PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)PWM_CVAL3_COUNT (4U)PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)PWM_CVAL3CYC_COUNT (4U)PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)PWM_CVAL4_CAPTVAL4_SHIFT (0U)‹PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)ŋPWM_CVAL4_COUNT (4U)ȋPWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)ɋPWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)ʋPWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)͋PWM_CVAL4CYC_COUNT (4U)ЋPWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)ыPWM_CVAL5_CAPTVAL5_SHIFT (0U)ҋPWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)ՋPWM_CVAL5_COUNT (4U)؋PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)ًPWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)ڋPWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)݋PWM_CVAL5CYC_COUNT (4U)PWM_OUTEN_PWMX_EN_MASK (0xFU)PWM_OUTEN_PWMX_EN_SHIFT (0U)PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)PWM_OUTEN_PWMB_EN_MASK (0xF0U)PWM_OUTEN_PWMB_EN_SHIFT (4U)PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)PWM_OUTEN_PWMA_EN_MASK (0xF00U)PWM_OUTEN_PWMA_EN_SHIFT (8U)PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)PWM_MASK_MASKX_MASK (0xFU)PWM_MASK_MASKX_SHIFT (0U)PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)PWM_MASK_MASKB_MASK (0xF0U)PWM_MASK_MASKB_SHIFT (4U)PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)PWM_MASK_MASKA_MASK (0xF00U)PWM_MASK_MASKA_SHIFT (8U)PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)PWM_MASK_UPDATE_MASK_MASK (0xF000U)PWM_MASK_UPDATE_MASK_SHIFT (12U)PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)PWM_SWCOUT_SM0OUT45_MASK (0x1U)PWM_SWCOUT_SM0OUT45_SHIFT (0U)PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)PWM_SWCOUT_SM0OUT23_MASK (0x2U)PWM_SWCOUT_SM0OUT23_SHIFT (1U)PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)PWM_SWCOUT_SM1OUT45_MASK (0x4U)PWM_SWCOUT_SM1OUT45_SHIFT (2U)PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)PWM_SWCOUT_SM1OUT23_MASK (0x8U)PWM_SWCOUT_SM1OUT23_SHIFT (3U)PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)PWM_SWCOUT_SM2OUT45_MASK (0x10U)PWM_SWCOUT_SM2OUT45_SHIFT (4U)PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)PWM_SWCOUT_SM2OUT23_MASK (0x20U)PWM_SWCOUT_SM2OUT23_SHIFT (5U)PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)PWM_SWCOUT_SM3OUT45_MASK (0x40U)PWM_SWCOUT_SM3OUT45_SHIFT (6U)PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)PWM_SWCOUT_SM3OUT23_MASK (0x80U)PWM_SWCOUT_SM3OUT23_SHIFT (7U)PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)PWM_MCTRL_LDOK_MASK (0xFU)PWM_MCTRL_LDOK_SHIFT (0U)PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)PWM_MCTRL_CLDOK_MASK (0xF0U)PWM_MCTRL_CLDOK_SHIFT (4U)PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)PWM_MCTRL_RUN_MASK (0xF00U)PWM_MCTRL_RUN_SHIFT (8U)PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)PWM_MCTRL_IPOL_MASK (0xF000U)PWM_MCTRL_IPOL_SHIFT (12U)PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)PWM_MCTRL2_MONPLL_MASK (0x3U)PWM_MCTRL2_MONPLL_SHIFT (0U)PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)PWM_FCTRL_FIE_MASK (0xFU)PWM_FCTRL_FIE_SHIFT (0U)ŒPWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)ÌPWM_FCTRL_FSAFE_MASK (0xF0U)ČPWM_FCTRL_FSAFE_SHIFT (4U)ŌPWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)ƌPWM_FCTRL_FAUTO_MASK (0xF00U)njPWM_FCTRL_FAUTO_SHIFT (8U)ȌPWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)ɌPWM_FCTRL_FLVL_MASK (0xF000U)ʌPWM_FCTRL_FLVL_SHIFT (12U)ˌPWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)ΌPWM_FSTS_FFLAG_MASK (0xFU)όPWM_FSTS_FFLAG_SHIFT (0U)ЌPWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)ьPWM_FSTS_FFULL_MASK (0xF0U)ҌPWM_FSTS_FFULL_SHIFT (4U)ӌPWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)ԌPWM_FSTS_FFPIN_MASK (0xF00U)ՌPWM_FSTS_FFPIN_SHIFT (8U)֌PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)׌PWM_FSTS_FHALF_MASK (0xF000U)،PWM_FSTS_FHALF_SHIFT (12U)ٌPWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)܌PWM_FFILT_FILT_PER_MASK (0xFFU)݌PWM_FFILT_FILT_PER_SHIFT (0U)ތPWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)ߌPWM_FFILT_FILT_CNT_MASK (0x700U)PWM_FFILT_FILT_CNT_SHIFT (8U)PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)PWM_FFILT_GSTR_MASK (0x8000U)PWM_FFILT_GSTR_SHIFT (15U)PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)PWM_FTST_FTEST_MASK (0x1U)PWM_FTST_FTEST_SHIFT (0U)PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)PWM_FCTRL2_NOCOMB_MASK (0xFU)PWM_FCTRL2_NOCOMB_SHIFT (0U)PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)PWM1_BASE (0x403DC000u)PWM1 ((PWM_Type *)PWM1_BASE)PWM2_BASE (0x403E0000u)PWM2 ((PWM_Type *)PWM2_BASE)PWM3_BASE (0x403E4000u)PWM3 ((PWM_Type *)PWM3_BASE)PWM4_BASE (0x403E8000u)PWM4 ((PWM_Type *)PWM4_BASE)PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }PXP_CTRL_ENABLE_MASK (0x1U)PXP_CTRL_ENABLE_SHIFT (0U)PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)PXP_CTRL_IRQ_ENABLE_MASK (0x2U)PXP_CTRL_IRQ_ENABLE_SHIFT (1U)PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)PXP_CTRL_RSVD0_MASK (0xE0U)PXP_CTRL_RSVD0_SHIFT (5U)PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)PXP_CTRL_ROTATE_MASK (0x300U)PXP_CTRL_ROTATE_SHIFT (8U)PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)PXP_CTRL_HFLIP_MASK (0x400U)PXP_CTRL_HFLIP_SHIFT (10U)PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)PXP_CTRL_VFLIP_MASK (0x800U)PXP_CTRL_VFLIP_SHIFT (11U)PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)PXP_CTRL_RSVD1_MASK (0x3FF000U)PXP_CTRL_RSVD1_SHIFT (12U)PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK)PXP_CTRL_ROT_POS_MASK (0x400000U)PXP_CTRL_ROT_POS_SHIFT (22U)PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)PXP_CTRL_BLOCK_SIZE_SHIFT (23U)PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)PXP_CTRL_RSVD3_MASK (0xF000000U)PXP_CTRL_RSVD3_SHIFT (24U)PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK)PXP_CTRL_EN_REPEAT_MASK (0x10000000U)PXP_CTRL_EN_REPEAT_SHIFT (28U)PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)PXP_CTRL_RSVD4_MASK (0x20000000U)PXP_CTRL_RSVD4_SHIFT (29U)PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK)PXP_CTRL_CLKGATE_MASK (0x40000000U)PXP_CTRL_CLKGATE_SHIFT (30U)PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)PXP_CTRL_SFTRST_MASK (0x80000000U)PXP_CTRL_SFTRST_SHIFT (31U)PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)PXP_CTRL_SET_ENABLE_MASK (0x1U)PXP_CTRL_SET_ENABLE_SHIFT (0U)PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)PXP_CTRL_SET_RSVD0_MASK (0xE0U)PXP_CTRL_SET_RSVD0_SHIFT (5U)PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)PXP_CTRL_SET_ROTATE_MASK (0x300U)PXP_CTRL_SET_ROTATE_SHIFT (8U)PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)PXP_CTRL_SET_HFLIP_MASK (0x400U)PXP_CTRL_SET_HFLIP_SHIFT (10U)PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)PXP_CTRL_SET_VFLIP_MASK (0x800U)PXP_CTRL_SET_VFLIP_SHIFT (11U)PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)PXP_CTRL_SET_RSVD1_MASK (0x3FF000U)PXP_CTRL_SET_RSVD1_SHIFT (12U)PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK)ŽPXP_CTRL_SET_ROT_POS_MASK (0x400000U)ÎPXP_CTRL_SET_ROT_POS_SHIFT (22U)ĎPXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)ŎPXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)ƎPXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)ǎPXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)ȎPXP_CTRL_SET_RSVD3_MASK (0xF000000U)ɎPXP_CTRL_SET_RSVD3_SHIFT (24U)ʎPXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK)ˎPXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)̎PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)͎PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)ΎPXP_CTRL_SET_RSVD4_MASK (0x20000000U)ώPXP_CTRL_SET_RSVD4_SHIFT (29U)ЎPXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK)юPXP_CTRL_SET_CLKGATE_MASK (0x40000000U)ҎPXP_CTRL_SET_CLKGATE_SHIFT (30U)ӎPXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)ԎPXP_CTRL_SET_SFTRST_MASK (0x80000000U)ՎPXP_CTRL_SET_SFTRST_SHIFT (31U)֎PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)َPXP_CTRL_CLR_ENABLE_MASK (0x1U)ڎPXP_CTRL_CLR_ENABLE_SHIFT (0U)ێPXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)܎PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)ݎPXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)ގPXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)ߎPXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)PXP_CTRL_CLR_RSVD0_MASK (0xE0U)PXP_CTRL_CLR_RSVD0_SHIFT (5U)PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)PXP_CTRL_CLR_ROTATE_MASK (0x300U)PXP_CTRL_CLR_ROTATE_SHIFT (8U)PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)PXP_CTRL_CLR_HFLIP_MASK (0x400U)PXP_CTRL_CLR_HFLIP_SHIFT (10U)PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)PXP_CTRL_CLR_VFLIP_MASK (0x800U)PXP_CTRL_CLR_VFLIP_SHIFT (11U)PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U)PXP_CTRL_CLR_RSVD1_SHIFT (12U)PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK)PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)PXP_CTRL_CLR_ROT_POS_SHIFT (22U)PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)PXP_CTRL_CLR_RSVD3_MASK (0xF000000U)PXP_CTRL_CLR_RSVD3_SHIFT (24U)PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK)PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)PXP_CTRL_CLR_RSVD4_MASK (0x20000000U)PXP_CTRL_CLR_RSVD4_SHIFT (29U)PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK)PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)PXP_CTRL_CLR_CLKGATE_SHIFT (30U)PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)PXP_CTRL_CLR_SFTRST_SHIFT (31U)PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)PXP_CTRL_TOG_ENABLE_MASK (0x1U)PXP_CTRL_TOG_ENABLE_SHIFT (0U)PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)PXP_CTRL_TOG_RSVD0_MASK (0xE0U)PXP_CTRL_TOG_RSVD0_SHIFT (5U)PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)PXP_CTRL_TOG_ROTATE_MASK (0x300U)PXP_CTRL_TOG_ROTATE_SHIFT (8U)PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)PXP_CTRL_TOG_HFLIP_MASK (0x400U)PXP_CTRL_TOG_HFLIP_SHIFT (10U)PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)PXP_CTRL_TOG_VFLIP_MASK (0x800U)PXP_CTRL_TOG_VFLIP_SHIFT (11U)PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U)PXP_CTRL_TOG_RSVD1_SHIFT (12U)PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK)PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)PXP_CTRL_TOG_ROT_POS_SHIFT (22U)PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)PXP_CTRL_TOG_RSVD3_MASK (0xF000000U)PXP_CTRL_TOG_RSVD3_SHIFT (24U)PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK)PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)PXP_CTRL_TOG_RSVD4_MASK (0x20000000U)PXP_CTRL_TOG_RSVD4_SHIFT (29U)PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK)PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)PXP_CTRL_TOG_CLKGATE_SHIFT (30U)PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)PXP_CTRL_TOG_SFTRST_SHIFT (31U)PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)PXP_STAT_IRQ_MASK (0x1U)PXP_STAT_IRQ_SHIFT (0U)PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)ÏPXP_STAT_AXI_READ_ERROR_MASK (0x4U)ďPXP_STAT_AXI_READ_ERROR_SHIFT (2U)ŏPXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)ƏPXP_STAT_NEXT_IRQ_MASK (0x8U)ǏPXP_STAT_NEXT_IRQ_SHIFT (3U)ȏPXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)ɏPXP_STAT_AXI_ERROR_ID_MASK (0xF0U)ʏPXP_STAT_AXI_ERROR_ID_SHIFT (4U)ˏPXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)̏PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)͏PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)ΏPXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)ϏPXP_STAT_RSVD2_MASK (0xFE00U)ЏPXP_STAT_RSVD2_SHIFT (9U)яPXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK)ҏPXP_STAT_BLOCKY_MASK (0xFF0000U)ӏPXP_STAT_BLOCKY_SHIFT (16U)ԏPXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)ՏPXP_STAT_BLOCKX_MASK (0xFF000000U)֏PXP_STAT_BLOCKX_SHIFT (24U)׏PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)ڏPXP_STAT_SET_IRQ_MASK (0x1U)ۏPXP_STAT_SET_IRQ_SHIFT (0U)܏PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)ݏPXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)ޏPXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)ߏPXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)PXP_STAT_SET_RSVD2_MASK (0xFE00U)PXP_STAT_SET_RSVD2_SHIFT (9U)PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK)PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)PXP_STAT_SET_BLOCKY_SHIFT (16U)PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)PXP_STAT_SET_BLOCKX_SHIFT (24U)PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)PXP_STAT_CLR_IRQ_MASK (0x1U)PXP_STAT_CLR_IRQ_SHIFT (0U)PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)PXP_STAT_CLR_RSVD2_MASK (0xFE00U)PXP_STAT_CLR_RSVD2_SHIFT (9U)PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK)PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)PXP_STAT_CLR_BLOCKY_SHIFT (16U)PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)PXP_STAT_CLR_BLOCKX_SHIFT (24U)PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)PXP_STAT_TOG_IRQ_MASK (0x1U)PXP_STAT_TOG_IRQ_SHIFT (0U)PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)PXP_STAT_TOG_RSVD2_MASK (0xFE00U)PXP_STAT_TOG_RSVD2_SHIFT (9U)PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK)PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)PXP_STAT_TOG_BLOCKY_SHIFT (16U)PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)PXP_STAT_TOG_BLOCKX_SHIFT (24U)PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)PXP_OUT_CTRL_FORMAT_MASK (0x1FU)PXP_OUT_CTRL_FORMAT_SHIFT (0U)PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)PXP_OUT_CTRL_RSVD0_MASK (0xE0U)PXP_OUT_CTRL_RSVD0_SHIFT (5U)PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U)PXP_OUT_CTRL_RSVD1_SHIFT (10U)PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK)PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)PXP_OUT_CTRL_ALPHA_SHIFT (24U)PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)ŐPXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)ƐPXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)ǐPXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)ȐPXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U)ɐPXP_OUT_CTRL_SET_RSVD0_SHIFT (5U)ʐPXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)ːPXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)̐PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)͐PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)ΐPXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U)ϐPXP_OUT_CTRL_SET_RSVD1_SHIFT (10U)АPXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK)ѐPXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)ҐPXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)ӐPXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)ԐPXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)ՐPXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)֐PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)ِPXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)ڐPXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)ېPXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)ܐPXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U)ݐPXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U)ސPXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)ߐPXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U)PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U)PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK)PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U)PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U)PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U)PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U)PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK)PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)PXP_OUT_BUF_ADDR_SHIFT (0U)PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)PXP_OUT_BUF2_ADDR_SHIFT (0U)PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)PXP_OUT_PITCH_PITCH_SHIFT (0U)PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U)PXP_OUT_PITCH_RSVD_SHIFT (16U)PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK)PXP_OUT_LRC_Y_MASK (0x3FFFU)PXP_OUT_LRC_Y_SHIFT (0U)PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)PXP_OUT_LRC_RSVD0_MASK (0xC000U)PXP_OUT_LRC_RSVD0_SHIFT (14U)PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK)PXP_OUT_LRC_X_MASK (0x3FFF0000U)PXP_OUT_LRC_X_SHIFT (16U)PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)PXP_OUT_LRC_RSVD1_MASK (0xC0000000U)PXP_OUT_LRC_RSVD1_SHIFT (30U)PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK)PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)PXP_OUT_PS_ULC_Y_SHIFT (0U)PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U)PXP_OUT_PS_ULC_RSVD0_SHIFT (14U)PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK)PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)PXP_OUT_PS_ULC_X_SHIFT (16U)PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U)PXP_OUT_PS_ULC_RSVD1_SHIFT (30U)PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK)PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)PXP_OUT_PS_LRC_Y_SHIFT (0U)PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U)PXP_OUT_PS_LRC_RSVD0_SHIFT (14U)PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK)PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)PXP_OUT_PS_LRC_X_SHIFT (16U)PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U)PXP_OUT_PS_LRC_RSVD1_SHIFT (30U)PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK)PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)PXP_OUT_AS_ULC_Y_SHIFT (0U)PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U)PXP_OUT_AS_ULC_RSVD0_SHIFT (14U)‘PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK)ÑPXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)đPXP_OUT_AS_ULC_X_SHIFT (16U)őPXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)ƑPXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U)ǑPXP_OUT_AS_ULC_RSVD1_SHIFT (30U)ȑPXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK)ˑPXP_OUT_AS_LRC_Y_MASK (0x3FFFU)̑PXP_OUT_AS_LRC_Y_SHIFT (0U)͑PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)ΑPXP_OUT_AS_LRC_RSVD0_MASK (0xC000U)ϑPXP_OUT_AS_LRC_RSVD0_SHIFT (14U)БPXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK)ёPXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)ґPXP_OUT_AS_LRC_X_SHIFT (16U)ӑPXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)ԑPXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U)ՑPXP_OUT_AS_LRC_RSVD1_SHIFT (30U)֑PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK)ّPXP_PS_CTRL_FORMAT_MASK (0x1FU)ڑPXP_PS_CTRL_FORMAT_SHIFT (0U)ۑPXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)ܑPXP_PS_CTRL_WB_SWAP_MASK (0x20U)ݑPXP_PS_CTRL_WB_SWAP_SHIFT (5U)ޑPXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)ߑPXP_PS_CTRL_RSVD0_MASK (0xC0U)PXP_PS_CTRL_RSVD0_SHIFT (6U)PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)PXP_PS_CTRL_DECY_MASK (0x300U)PXP_PS_CTRL_DECY_SHIFT (8U)PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)PXP_PS_CTRL_DECX_MASK (0xC00U)PXP_PS_CTRL_DECX_SHIFT (10U)PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U)PXP_PS_CTRL_RSVD1_SHIFT (12U)PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK)PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU)PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U)PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U)PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U)PXP_PS_CTRL_SET_RSVD0_SHIFT (6U)PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)PXP_PS_CTRL_SET_DECY_MASK (0x300U)PXP_PS_CTRL_SET_DECY_SHIFT (8U)PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)PXP_PS_CTRL_SET_DECX_MASK (0xC00U)PXP_PS_CTRL_SET_DECX_SHIFT (10U)PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U)PXP_PS_CTRL_SET_RSVD1_SHIFT (12U)PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK)PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU)PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U)PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U)PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U)PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U)PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)PXP_PS_CTRL_CLR_DECY_MASK (0x300U)PXP_PS_CTRL_CLR_DECY_SHIFT (8U)PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)PXP_PS_CTRL_CLR_DECX_SHIFT (10U)PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U)PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U)PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK)PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU)PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U)PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U)PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U)PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U)PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)PXP_PS_CTRL_TOG_DECY_MASK (0x300U)PXP_PS_CTRL_TOG_DECY_SHIFT (8U)PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)PXP_PS_CTRL_TOG_DECX_SHIFT (10U)PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U)PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U)PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK)PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)PXP_PS_BUF_ADDR_SHIFT (0U)PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)PXP_PS_UBUF_ADDR_SHIFT (0U)PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)PXP_PS_VBUF_ADDR_SHIFT (0U)PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)PXP_PS_PITCH_PITCH_MASK (0xFFFFU)PXP_PS_PITCH_PITCH_SHIFT (0U)PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U)PXP_PS_PITCH_RSVD_SHIFT (16U)PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK)PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)PXP_PS_BACKGROUND_COLOR_SHIFT (0U)’PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)ÒPXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U)ĒPXP_PS_BACKGROUND_RSVD_SHIFT (24U)ŒPXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK)ȒPXP_PS_SCALE_XSCALE_MASK (0x7FFFU)ɒPXP_PS_SCALE_XSCALE_SHIFT (0U)ʒPXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)˒PXP_PS_SCALE_RSVD1_MASK (0x8000U)̒PXP_PS_SCALE_RSVD1_SHIFT (15U)͒PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK)ΒPXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)ϒPXP_PS_SCALE_YSCALE_SHIFT (16U)ВPXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)ђPXP_PS_SCALE_RSVD2_MASK (0x80000000U)ҒPXP_PS_SCALE_RSVD2_SHIFT (31U)ӒPXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK)֒PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)גPXP_PS_OFFSET_XOFFSET_SHIFT (0U)ؒPXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)ْPXP_PS_OFFSET_RSVD1_MASK (0xF000U)ڒPXP_PS_OFFSET_RSVD1_SHIFT (12U)ےPXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK)ܒPXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)ݒPXP_PS_OFFSET_YOFFSET_SHIFT (16U)ޒPXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)ߒPXP_PS_OFFSET_RSVD2_MASK (0xF0000000U)PXP_PS_OFFSET_RSVD2_SHIFT (28U)PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK)PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U)PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK)PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U)PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK)PXP_AS_CTRL_RSVD0_MASK (0x1U)PXP_AS_CTRL_RSVD0_SHIFT (0U)PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)PXP_AS_CTRL_FORMAT_MASK (0xF0U)PXP_AS_CTRL_FORMAT_SHIFT (4U)PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)PXP_AS_CTRL_ALPHA_MASK (0xFF00U)PXP_AS_CTRL_ALPHA_SHIFT (8U)PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)PXP_AS_CTRL_ROP_MASK (0xF0000U)PXP_AS_CTRL_ROP_SHIFT (16U)PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U)PXP_AS_CTRL_RSVD1_SHIFT (21U)PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK)PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)PXP_AS_BUF_ADDR_SHIFT (0U)PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)PXP_AS_PITCH_PITCH_MASK (0xFFFFU)PXP_AS_PITCH_PITCH_SHIFT (0U)PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U)PXP_AS_PITCH_RSVD_SHIFT (16U)PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK)PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U)PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK)PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK)PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)PXP_CSC1_COEF0_C0_SHIFT (18U)PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U)PXP_CSC1_COEF0_RSVD1_SHIFT (29U)PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK)PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)PXP_CSC1_COEF0_BYPASS_SHIFT (30U)PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)PXP_CSC1_COEF1_C4_MASK (0x7FFU)PXP_CSC1_COEF1_C4_SHIFT (0U)PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)“PXP_CSC1_COEF1_RSVD0_MASK (0xF800U)ÓPXP_CSC1_COEF1_RSVD0_SHIFT (11U)ēPXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK)œPXP_CSC1_COEF1_C1_MASK (0x7FF0000U)ƓPXP_CSC1_COEF1_C1_SHIFT (16U)ǓPXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)ȓPXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U)ɓPXP_CSC1_COEF1_RSVD1_SHIFT (27U)ʓPXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK)͓PXP_CSC1_COEF2_C3_MASK (0x7FFU)ΓPXP_CSC1_COEF2_C3_SHIFT (0U)ϓPXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)ГPXP_CSC1_COEF2_RSVD0_MASK (0xF800U)ѓPXP_CSC1_COEF2_RSVD0_SHIFT (11U)ғPXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK)ӓPXP_CSC1_COEF2_C2_MASK (0x7FF0000U)ԓPXP_CSC1_COEF2_C2_SHIFT (16U)ՓPXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)֓PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U)דPXP_CSC1_COEF2_RSVD1_SHIFT (27U)ؓPXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK)ۓPXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)ܓPXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)ݓPXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)ޓPXP_POWER_CTRL_MASK (0xFFFFF000U)ߓPXP_POWER_CTRL_SHIFT (12U)PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)PXP_NEXT_ENABLED_MASK (0x1U)PXP_NEXT_ENABLED_SHIFT (0U)PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)PXP_NEXT_RSVD_MASK (0x2U)PXP_NEXT_RSVD_SHIFT (1U)PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK)PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)PXP_NEXT_POINTER_SHIFT (2U)PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U)PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U)PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK)PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)PXP_BASE (0x402B4000u)PXP ((PXP_Type *)PXP_BASE)PXP_BASE_ADDRS { PXP_BASE }PXP_BASE_PTRS { PXP }PXP_IRQ0_IRQS { PXP_IRQn }ƔROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)ǔROMC_ROMPATCHD_DATAX_SHIFT (0U)ȔROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)˔ROMC_ROMPATCHD_COUNT (8U)ΔROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)ϔROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)ДROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)єROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)ҔROMC_ROMPATCHCNTL_DIS_SHIFT (29U)ӔROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)֔ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)הROMC_ROMPATCHENL_ENABLE_SHIFT (0U)ؔROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)۔ROMC_ROMPATCHA_THUMBX_MASK (0x1U)ܔROMC_ROMPATCHA_THUMBX_SHIFT (0U)ݔROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)ޔROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)ߔROMC_ROMPATCHA_ADDRX_SHIFT (1U)ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)ROMC_ROMPATCHA_COUNT (16U)ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)ROMC_ROMPATCHSR_SW_MASK (0x20000U)ROMC_ROMPATCHSR_SW_SHIFT (17U)ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)ROMC_BASE (0x40180000u)ROMC ((ROMC_Type *)ROMC_BASE)ROMC_BASE_ADDRS { ROMC_BASE }ROMC_BASE_PTRS { ROMC }RTWDOG_CS_STOP_MASK (0x1U)RTWDOG_CS_STOP_SHIFT (0U)RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)RTWDOG_CS_WAIT_MASK (0x2U)RTWDOG_CS_WAIT_SHIFT (1U)RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)RTWDOG_CS_DBG_MASK (0x4U)RTWDOG_CS_DBG_SHIFT (2U)RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)RTWDOG_CS_TST_MASK (0x18U)RTWDOG_CS_TST_SHIFT (3U)RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)RTWDOG_CS_UPDATE_MASK (0x20U)RTWDOG_CS_UPDATE_SHIFT (5U)RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)RTWDOG_CS_INT_MASK (0x40U)RTWDOG_CS_INT_SHIFT (6U)RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)RTWDOG_CS_EN_MASK (0x80U)RTWDOG_CS_EN_SHIFT (7U)RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)RTWDOG_CS_CLK_MASK (0x300U)RTWDOG_CS_CLK_SHIFT (8U)RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)RTWDOG_CS_RCS_MASK (0x400U)RTWDOG_CS_RCS_SHIFT (10U)RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)RTWDOG_CS_ULK_MASK (0x800U)RTWDOG_CS_ULK_SHIFT (11U)RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)RTWDOG_CS_PRES_MASK (0x1000U)RTWDOG_CS_PRES_SHIFT (12U)RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)RTWDOG_CS_CMD32EN_MASK (0x2000U)RTWDOG_CS_CMD32EN_SHIFT (13U)RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)RTWDOG_CS_FLG_MASK (0x4000U)•RTWDOG_CS_FLG_SHIFT (14U)ÕRTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)ĕRTWDOG_CS_WIN_MASK (0x8000U)ŕRTWDOG_CS_WIN_SHIFT (15U)ƕRTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)ɕRTWDOG_CNT_CNTLOW_MASK (0xFFU)ʕRTWDOG_CNT_CNTLOW_SHIFT (0U)˕RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)̕RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)͕RTWDOG_CNT_CNTHIGH_SHIFT (8U)ΕRTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)ѕRTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)ҕRTWDOG_TOVAL_TOVALLOW_SHIFT (0U)ӕRTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)ԕRTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)ՕRTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)֕RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)ٕRTWDOG_WIN_WINLOW_MASK (0xFFU)ڕRTWDOG_WIN_WINLOW_SHIFT (0U)ەRTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)ܕRTWDOG_WIN_WINHIGH_MASK (0xFF00U)ݕRTWDOG_WIN_WINHIGH_SHIFT (8U)ޕRTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)RTWDOG_BASE (0x400BC000u)RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)RTWDOG_BASE_ADDRS { RTWDOG_BASE }RTWDOG_BASE_PTRS { RTWDOG }RTWDOG_IRQS { RTWDOG_IRQn }RTWDOG_UPDATE_KEY (0xD928C520U)RTWDOG_REFRESH_KEY (0xB480A602U)ŖSEMC_MCR_SWRST_MASK (0x1U)ƖSEMC_MCR_SWRST_SHIFT (0U)ǖSEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)ȖSEMC_MCR_MDIS_MASK (0x2U)ɖSEMC_MCR_MDIS_SHIFT (1U)ʖSEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)˖SEMC_MCR_DQSMD_MASK (0x4U)̖SEMC_MCR_DQSMD_SHIFT (2U)͖SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)ΖSEMC_MCR_WPOL0_MASK (0x40U)ϖSEMC_MCR_WPOL0_SHIFT (6U)ЖSEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)іSEMC_MCR_WPOL1_MASK (0x80U)ҖSEMC_MCR_WPOL1_SHIFT (7U)ӖSEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)ԖSEMC_MCR_CTO_MASK (0xFF0000U)ՖSEMC_MCR_CTO_SHIFT (16U)֖SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)זSEMC_MCR_BTO_MASK (0x1F000000U)ؖSEMC_MCR_BTO_SHIFT (24U)ٖSEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)ܖSEMC_IOCR_MUX_A8_MASK (0x7U)ݖSEMC_IOCR_MUX_A8_SHIFT (0U)ޖSEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)ߖSEMC_IOCR_MUX_CSX0_MASK (0x38U)SEMC_IOCR_MUX_CSX0_SHIFT (3U)SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)SEMC_IOCR_MUX_CSX1_SHIFT (6U)SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)SEMC_IOCR_MUX_CSX2_MASK (0xE00U)SEMC_IOCR_MUX_CSX2_SHIFT (9U)SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)SEMC_IOCR_MUX_CSX3_MASK (0x7000U)SEMC_IOCR_MUX_CSX3_SHIFT (12U)SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)SEMC_IOCR_MUX_RDY_MASK (0x38000U)SEMC_IOCR_MUX_RDY_SHIFT (15U)SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)SEMC_BMCR0_WQOS_MASK (0xFU)SEMC_BMCR0_WQOS_SHIFT (0U)SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)SEMC_BMCR0_WAGE_MASK (0xF0U)SEMC_BMCR0_WAGE_SHIFT (4U)SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)SEMC_BMCR0_WSH_MASK (0xFF00U)SEMC_BMCR0_WSH_SHIFT (8U)SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)SEMC_BMCR0_WRWS_MASK (0xFF0000U)SEMC_BMCR0_WRWS_SHIFT (16U)SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)SEMC_BMCR1_WQOS_MASK (0xFU)SEMC_BMCR1_WQOS_SHIFT (0U)SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)SEMC_BMCR1_WAGE_MASK (0xF0U)SEMC_BMCR1_WAGE_SHIFT (4U)SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)SEMC_BMCR1_WPH_MASK (0xFF00U)SEMC_BMCR1_WPH_SHIFT (8U)SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)SEMC_BMCR1_WRWS_MASK (0xFF0000U)SEMC_BMCR1_WRWS_SHIFT (16U)SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)SEMC_BMCR1_WBR_MASK (0xFF000000U)SEMC_BMCR1_WBR_SHIFT (24U)SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)SEMC_BR_VLD_MASK (0x1U)SEMC_BR_VLD_SHIFT (0U)SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)SEMC_BR_MS_MASK (0x3EU)SEMC_BR_MS_SHIFT (1U)SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)SEMC_BR_BA_MASK (0xFFFFF000U)SEMC_BR_BA_SHIFT (12U)SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)SEMC_BR_COUNT (9U)SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)SEMC_INTEN_IPCMDERREN_MASK (0x2U)SEMC_INTEN_IPCMDERREN_SHIFT (1U)SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)SEMC_INTEN_AXICMDERREN_MASK (0x4U)SEMC_INTEN_AXICMDERREN_SHIFT (2U)SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)SEMC_INTEN_AXIBUSERREN_MASK (0x8U)SEMC_INTEN_AXIBUSERREN_SHIFT (3U)SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)SEMC_INTEN_NDNOPENDEN_MASK (0x20U)SEMC_INTEN_NDNOPENDEN_SHIFT (5U)SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)SEMC_INTR_IPCMDDONE_MASK (0x1U)SEMC_INTR_IPCMDDONE_SHIFT (0U)SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)SEMC_INTR_IPCMDERR_MASK (0x2U)SEMC_INTR_IPCMDERR_SHIFT (1U)SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)SEMC_INTR_AXICMDERR_MASK (0x4U)SEMC_INTR_AXICMDERR_SHIFT (2U)SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)SEMC_INTR_AXIBUSERR_MASK (0x8U)SEMC_INTR_AXIBUSERR_SHIFT (3U)SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)SEMC_INTR_NDPAGEEND_MASK (0x10U)SEMC_INTR_NDPAGEEND_SHIFT (4U)SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)SEMC_INTR_NDNOPEND_MASK (0x20U)SEMC_INTR_NDNOPEND_SHIFT (5U)—SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)ŗSEMC_SDRAMCR0_PS_MASK (0x1U)ƗSEMC_SDRAMCR0_PS_SHIFT (0U)ǗSEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)ȗSEMC_SDRAMCR0_BL_MASK (0x70U)ɗSEMC_SDRAMCR0_BL_SHIFT (4U)ʗSEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)˗SEMC_SDRAMCR0_COL_MASK (0x300U)̗SEMC_SDRAMCR0_COL_SHIFT (8U)͗SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)ΗSEMC_SDRAMCR0_CL_MASK (0xC00U)ϗSEMC_SDRAMCR0_CL_SHIFT (10U)ЗSEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)ӗSEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)ԗSEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)՗SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)֗SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)חSEMC_SDRAMCR1_ACT2RW_SHIFT (4U)ؗSEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)ٗSEMC_SDRAMCR1_RFRC_MASK (0x1F00U)ڗSEMC_SDRAMCR1_RFRC_SHIFT (8U)ۗSEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)ܗSEMC_SDRAMCR1_WRC_MASK (0xE000U)ݗSEMC_SDRAMCR1_WRC_SHIFT (13U)ޗSEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)ߗSEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)SEMC_SDRAMCR2_SRRC_MASK (0xFFU)SEMC_SDRAMCR2_SRRC_SHIFT (0U)SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)SEMC_SDRAMCR2_REF2REF_SHIFT (8U)SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)SEMC_SDRAMCR2_ITO_SHIFT (24U)SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)SEMC_SDRAMCR3_REN_MASK (0x1U)SEMC_SDRAMCR3_REN_SHIFT (0U)SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)SEMC_SDRAMCR3_REBL_MASK (0xEU)SEMC_SDRAMCR3_REBL_SHIFT (1U)SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)SEMC_SDRAMCR3_RT_MASK (0xFF0000U)SEMC_SDRAMCR3_RT_SHIFT (16U)SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)SEMC_SDRAMCR3_UT_MASK (0xFF000000U)SEMC_SDRAMCR3_UT_SHIFT (24U)SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)SEMC_NANDCR0_PS_MASK (0x1U)SEMC_NANDCR0_PS_SHIFT (0U)SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)SEMC_NANDCR0_BL_MASK (0x70U)SEMC_NANDCR0_BL_SHIFT (4U)SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)SEMC_NANDCR0_EDO_MASK (0x80U)SEMC_NANDCR0_EDO_SHIFT (7U)SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)SEMC_NANDCR0_COL_MASK (0x700U)SEMC_NANDCR0_COL_SHIFT (8U)SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)SEMC_NANDCR1_CES_MASK (0xFU)SEMC_NANDCR1_CES_SHIFT (0U)SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)SEMC_NANDCR1_CEH_MASK (0xF0U)SEMC_NANDCR1_CEH_SHIFT (4U)SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)SEMC_NANDCR1_WEL_MASK (0xF00U)SEMC_NANDCR1_WEL_SHIFT (8U)SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)SEMC_NANDCR1_WEH_MASK (0xF000U)SEMC_NANDCR1_WEH_SHIFT (12U)SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)SEMC_NANDCR1_REL_MASK (0xF0000U)SEMC_NANDCR1_REL_SHIFT (16U)SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)SEMC_NANDCR1_REH_MASK (0xF00000U)SEMC_NANDCR1_REH_SHIFT (20U)SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)SEMC_NANDCR1_TA_MASK (0xF000000U)SEMC_NANDCR1_TA_SHIFT (24U)SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)SEMC_NANDCR1_CEITV_MASK (0xF0000000U)SEMC_NANDCR1_CEITV_SHIFT (28U)SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)SEMC_NANDCR2_TWHR_MASK (0x3FU)SEMC_NANDCR2_TWHR_SHIFT (0U)SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)SEMC_NANDCR2_TRHW_MASK (0xFC0U)SEMC_NANDCR2_TRHW_SHIFT (6U)SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)SEMC_NANDCR2_TADL_MASK (0x3F000U)SEMC_NANDCR2_TADL_SHIFT (12U)SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)SEMC_NANDCR2_TRR_MASK (0xFC0000U)SEMC_NANDCR2_TRR_SHIFT (18U)SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)SEMC_NANDCR2_TWB_MASK (0x3F000000U)SEMC_NANDCR2_TWB_SHIFT (24U)SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)SEMC_NANDCR3_NDOPT1_MASK (0x1U)SEMC_NANDCR3_NDOPT1_SHIFT (0U)SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)˜SEMC_NANDCR3_NDOPT2_MASK (0x2U)ØSEMC_NANDCR3_NDOPT2_SHIFT (1U)ĘSEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)ŘSEMC_NANDCR3_NDOPT3_MASK (0x4U)ƘSEMC_NANDCR3_NDOPT3_SHIFT (2U)ǘSEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)ʘSEMC_NORCR0_PS_MASK (0x1U)˘SEMC_NORCR0_PS_SHIFT (0U)̘SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)͘SEMC_NORCR0_BL_MASK (0x70U)ΘSEMC_NORCR0_BL_SHIFT (4U)ϘSEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)ИSEMC_NORCR0_AM_MASK (0x300U)јSEMC_NORCR0_AM_SHIFT (8U)ҘSEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)ӘSEMC_NORCR0_ADVP_MASK (0x400U)ԘSEMC_NORCR0_ADVP_SHIFT (10U)՘SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)֘SEMC_NORCR0_COL_MASK (0xF000U)טSEMC_NORCR0_COL_SHIFT (12U)ؘSEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)ۘSEMC_NORCR1_CES_MASK (0xFU)ܘSEMC_NORCR1_CES_SHIFT (0U)ݘSEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)ޘSEMC_NORCR1_CEH_MASK (0xF0U)ߘSEMC_NORCR1_CEH_SHIFT (4U)SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)SEMC_NORCR1_AS_MASK (0xF00U)SEMC_NORCR1_AS_SHIFT (8U)SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)SEMC_NORCR1_AH_MASK (0xF000U)SEMC_NORCR1_AH_SHIFT (12U)SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)SEMC_NORCR1_WEL_MASK (0xF0000U)SEMC_NORCR1_WEL_SHIFT (16U)SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)SEMC_NORCR1_WEH_MASK (0xF00000U)SEMC_NORCR1_WEH_SHIFT (20U)SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)SEMC_NORCR1_REL_MASK (0xF000000U)SEMC_NORCR1_REL_SHIFT (24U)SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)SEMC_NORCR1_REH_MASK (0xF0000000U)SEMC_NORCR1_REH_SHIFT (28U)SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)SEMC_NORCR2_WDS_MASK (0xFU)SEMC_NORCR2_WDS_SHIFT (0U)SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)SEMC_NORCR2_WDH_MASK (0xF0U)SEMC_NORCR2_WDH_SHIFT (4U)SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)SEMC_NORCR2_TA_MASK (0xF00U)SEMC_NORCR2_TA_SHIFT (8U)SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)SEMC_NORCR2_AWDH_MASK (0xF000U)SEMC_NORCR2_AWDH_SHIFT (12U)SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)SEMC_NORCR2_LC_MASK (0xF0000U)SEMC_NORCR2_LC_SHIFT (16U)SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)SEMC_NORCR2_RD_MASK (0xF00000U)SEMC_NORCR2_RD_SHIFT (20U)SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)SEMC_NORCR2_CEITV_MASK (0xF000000U)SEMC_NORCR2_CEITV_SHIFT (24U)SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)SEMC_SRAMCR0_PS_MASK (0x1U)SEMC_SRAMCR0_PS_SHIFT (0U)SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)SEMC_SRAMCR0_BL_MASK (0x70U)SEMC_SRAMCR0_BL_SHIFT (4U)SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)SEMC_SRAMCR0_AM_MASK (0x300U)SEMC_SRAMCR0_AM_SHIFT (8U)SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)SEMC_SRAMCR0_ADVP_MASK (0x400U)SEMC_SRAMCR0_ADVP_SHIFT (10U)SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)SEMC_SRAMCR0_COL_MASK (0xF000U)SEMC_SRAMCR0_COL_SHIFT (12U)SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)SEMC_SRAMCR1_CES_MASK (0xFU)SEMC_SRAMCR1_CES_SHIFT (0U)SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)SEMC_SRAMCR1_CEH_MASK (0xF0U)SEMC_SRAMCR1_CEH_SHIFT (4U)SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)SEMC_SRAMCR1_AS_MASK (0xF00U)SEMC_SRAMCR1_AS_SHIFT (8U)SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)SEMC_SRAMCR1_AH_MASK (0xF000U)SEMC_SRAMCR1_AH_SHIFT (12U)SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)SEMC_SRAMCR1_WEL_MASK (0xF0000U)SEMC_SRAMCR1_WEL_SHIFT (16U)SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)SEMC_SRAMCR1_WEH_MASK (0xF00000U)SEMC_SRAMCR1_WEH_SHIFT (20U)SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)SEMC_SRAMCR1_REL_MASK (0xF000000U)SEMC_SRAMCR1_REL_SHIFT (24U)SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)SEMC_SRAMCR1_REH_MASK (0xF0000000U)SEMC_SRAMCR1_REH_SHIFT (28U)SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)SEMC_SRAMCR2_WDS_MASK (0xFU)SEMC_SRAMCR2_WDS_SHIFT (0U)SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)SEMC_SRAMCR2_WDH_MASK (0xF0U)SEMC_SRAMCR2_WDH_SHIFT (4U)SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)SEMC_SRAMCR2_TA_MASK (0xF00U)SEMC_SRAMCR2_TA_SHIFT (8U)SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)SEMC_SRAMCR2_AWDH_MASK (0xF000U)SEMC_SRAMCR2_AWDH_SHIFT (12U)™SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)ÙSEMC_SRAMCR2_LC_MASK (0xF0000U)ęSEMC_SRAMCR2_LC_SHIFT (16U)řSEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)ƙSEMC_SRAMCR2_RD_MASK (0xF00000U)ǙSEMC_SRAMCR2_RD_SHIFT (20U)șSEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)əSEMC_SRAMCR2_CEITV_MASK (0xF000000U)ʙSEMC_SRAMCR2_CEITV_SHIFT (24U)˙SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)ΙSEMC_DBICR0_PS_MASK (0x1U)ϙSEMC_DBICR0_PS_SHIFT (0U)ЙSEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)љSEMC_DBICR0_BL_MASK (0x70U)ҙSEMC_DBICR0_BL_SHIFT (4U)әSEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)ԙSEMC_DBICR0_COL_MASK (0xF000U)ՙSEMC_DBICR0_COL_SHIFT (12U)֙SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)ٙSEMC_DBICR1_CES_MASK (0xFU)ڙSEMC_DBICR1_CES_SHIFT (0U)ۙSEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)ܙSEMC_DBICR1_CEH_MASK (0xF0U)ݙSEMC_DBICR1_CEH_SHIFT (4U)ޙSEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)ߙSEMC_DBICR1_WEL_MASK (0xF00U)SEMC_DBICR1_WEL_SHIFT (8U)SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)SEMC_DBICR1_WEH_MASK (0xF000U)SEMC_DBICR1_WEH_SHIFT (12U)SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)SEMC_DBICR1_REL_MASK (0xF0000U)SEMC_DBICR1_REL_SHIFT (16U)SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)SEMC_DBICR1_REH_MASK (0xF00000U)SEMC_DBICR1_REH_SHIFT (20U)SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)SEMC_DBICR1_CEITV_MASK (0xF000000U)SEMC_DBICR1_CEITV_SHIFT (24U)SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)SEMC_IPCR0_SA_SHIFT (0U)SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)SEMC_IPCR1_DATSZ_MASK (0x7U)SEMC_IPCR1_DATSZ_SHIFT (0U)SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)SEMC_IPCR2_BM0_MASK (0x1U)SEMC_IPCR2_BM0_SHIFT (0U)SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)SEMC_IPCR2_BM1_MASK (0x2U)SEMC_IPCR2_BM1_SHIFT (1U)SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)SEMC_IPCR2_BM2_MASK (0x4U)SEMC_IPCR2_BM2_SHIFT (2U)SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)SEMC_IPCR2_BM3_MASK (0x8U)SEMC_IPCR2_BM3_SHIFT (3U)SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)SEMC_IPCMD_CMD_MASK (0xFFFFU)SEMC_IPCMD_CMD_SHIFT (0U)SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)SEMC_IPCMD_KEY_MASK (0xFFFF0000U)SEMC_IPCMD_KEY_SHIFT (16U)SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)SEMC_IPTXDAT_DAT_SHIFT (0U)SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)SEMC_IPRXDAT_DAT_SHIFT (0U)SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)SEMC_STS0_IDLE_MASK (0x1U)SEMC_STS0_IDLE_SHIFT (0U)SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)SEMC_STS0_NARDY_MASK (0x2U)SEMC_STS0_NARDY_SHIFT (1U)SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)SEMC_STS2_NDWRPEND_MASK (0x8U)SEMC_STS2_NDWRPEND_SHIFT (3U)SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)SEMC_STS12_NDADDR_SHIFT (0U)SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)SEMC_BASE (0x402F0000u)SEMC ((SEMC_Type *)SEMC_BASE)SEMC_BASE_ADDRS { SEMC_BASE }SEMC_BASE_PTRS { SEMC }SEMC_IRQS { SEMC_IRQn }SNVS_HPLR_ZMK_WSL_MASK (0x1U)SNVS_HPLR_ZMK_WSL_SHIFT (0U)SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)SNVS_HPLR_ZMK_RSL_MASK (0x2U)SNVS_HPLR_ZMK_RSL_SHIFT (1U)SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)SNVS_HPLR_SRTC_SL_MASK (0x4U)SNVS_HPLR_SRTC_SL_SHIFT (2U)SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)SNVS_HPLR_LPCALB_SL_MASK (0x8U)SNVS_HPLR_LPCALB_SL_SHIFT (3U)SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)SNVS_HPLR_MC_SL_MASK (0x10U)SNVS_HPLR_MC_SL_SHIFT (4U)SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)SNVS_HPLR_GPR_SL_MASK (0x20U)SNVS_HPLR_GPR_SL_SHIFT (5U)SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)SNVS_HPLR_LPSVCR_SL_MASK (0x40U)SNVS_HPLR_LPSVCR_SL_SHIFT (6U)SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)SNVS_HPLR_LPTDCR_SL_MASK (0x100U)SNVS_HPLR_LPTDCR_SL_SHIFT (8U)SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)SNVS_HPLR_MKS_SL_MASK (0x200U)SNVS_HPLR_MKS_SL_SHIFT (9U)SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)SNVS_HPLR_HPSVCR_L_MASK (0x10000U)SNVS_HPLR_HPSVCR_L_SHIFT (16U)SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)SNVS_HPLR_HPSICR_L_MASK (0x20000U)SNVS_HPLR_HPSICR_L_SHIFT (17U)SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)SNVS_HPLR_HAC_L_MASK (0x40000U)SNVS_HPLR_HAC_L_SHIFT (18U)SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)SNVS_HPCOMR_SSM_ST_MASK (0x1U)SNVS_HPCOMR_SSM_ST_SHIFT (0U)SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)SNVS_HPCOMR_LP_SWR_MASK (0x10U)SNVS_HPCOMR_LP_SWR_SHIFT (4U)SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)SNVS_HPCOMR_SW_SV_MASK (0x100U)SNVS_HPCOMR_SW_SV_SHIFT (8U)SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)SNVS_HPCOMR_SW_FSV_MASK (0x200U)SNVS_HPCOMR_SW_FSV_SHIFT (9U)SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)SNVS_HPCOMR_SW_LPSV_MASK (0x400U)SNVS_HPCOMR_SW_LPSV_SHIFT (10U)SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)SNVS_HPCOMR_MKS_EN_MASK (0x2000U)SNVS_HPCOMR_MKS_EN_SHIFT (13U)SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)SNVS_HPCOMR_HAC_EN_MASK (0x10000U)SNVS_HPCOMR_HAC_EN_SHIFT (16U)›SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)ÛSNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)ěSNVS_HPCOMR_HAC_LOAD_SHIFT (17U)śSNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)ƛSNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)ǛSNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)țSNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)ɛSNVS_HPCOMR_HAC_STOP_MASK (0x80000U)ʛSNVS_HPCOMR_HAC_STOP_SHIFT (19U)˛SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)̛SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)͛SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)ΛSNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)ћSNVS_HPCR_RTC_EN_MASK (0x1U)қSNVS_HPCR_RTC_EN_SHIFT (0U)ӛSNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)ԛSNVS_HPCR_HPTA_EN_MASK (0x2U)՛SNVS_HPCR_HPTA_EN_SHIFT (1U)֛SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)כSNVS_HPCR_PI_EN_MASK (0x8U)؛SNVS_HPCR_PI_EN_SHIFT (3U)ٛSNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)ڛSNVS_HPCR_PI_FREQ_MASK (0xF0U)ۛSNVS_HPCR_PI_FREQ_SHIFT (4U)ܛSNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)ݛSNVS_HPCR_HPCALB_EN_MASK (0x100U)ޛSNVS_HPCR_HPCALB_EN_SHIFT (8U)ߛSNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)SNVS_HPCR_HPCALB_VAL_SHIFT (10U)SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)SNVS_HPCR_HP_TS_MASK (0x10000U)SNVS_HPCR_HP_TS_SHIFT (16U)SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)SNVS_HPCR_BTN_CONFIG_SHIFT (24U)SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)SNVS_HPCR_BTN_MASK_MASK (0x8000000U)SNVS_HPCR_BTN_MASK_SHIFT (27U)SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)SNVS_HPSICR_SV0_EN_MASK (0x1U)SNVS_HPSICR_SV0_EN_SHIFT (0U)SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)SNVS_HPSICR_SV1_EN_MASK (0x2U)SNVS_HPSICR_SV1_EN_SHIFT (1U)SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)SNVS_HPSICR_SV2_EN_MASK (0x4U)SNVS_HPSICR_SV2_EN_SHIFT (2U)SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)SNVS_HPSICR_SV3_EN_MASK (0x8U)SNVS_HPSICR_SV3_EN_SHIFT (3U)SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)SNVS_HPSICR_SV4_EN_MASK (0x10U)SNVS_HPSICR_SV4_EN_SHIFT (4U)SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)SNVS_HPSICR_SV5_EN_MASK (0x20U)SNVS_HPSICR_SV5_EN_SHIFT (5U)SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)SNVS_HPSICR_LPSVI_EN_SHIFT (31U)SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)SNVS_HPSVCR_SV0_CFG_MASK (0x1U)SNVS_HPSVCR_SV0_CFG_SHIFT (0U)SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)SNVS_HPSVCR_SV1_CFG_MASK (0x2U)SNVS_HPSVCR_SV1_CFG_SHIFT (1U)SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)SNVS_HPSVCR_SV2_CFG_MASK (0x4U)SNVS_HPSVCR_SV2_CFG_SHIFT (2U)SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)SNVS_HPSVCR_SV3_CFG_MASK (0x8U)SNVS_HPSVCR_SV3_CFG_SHIFT (3U)SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)SNVS_HPSVCR_SV4_CFG_MASK (0x10U)SNVS_HPSVCR_SV4_CFG_SHIFT (4U)SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)SNVS_HPSVCR_SV5_CFG_MASK (0x60U)SNVS_HPSVCR_SV5_CFG_SHIFT (5U)SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)SNVS_HPSR_HPTA_MASK (0x1U)SNVS_HPSR_HPTA_SHIFT (0U)SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)SNVS_HPSR_PI_MASK (0x2U)SNVS_HPSR_PI_SHIFT (1U)SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)SNVS_HPSR_LPDIS_MASK (0x10U)SNVS_HPSR_LPDIS_SHIFT (4U)SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)SNVS_HPSR_BTN_MASK (0x40U)SNVS_HPSR_BTN_SHIFT (6U)SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)SNVS_HPSR_BI_MASK (0x80U)SNVS_HPSR_BI_SHIFT (7U)SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)SNVS_HPSR_SSM_STATE_MASK (0xF00U)SNVS_HPSR_SSM_STATE_SHIFT (8U)SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U)SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U)SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U)SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U)SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)SNVS_HPSR_ZMK_ZERO_SHIFT (31U)SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)SNVS_HPSVSR_SV0_MASK (0x1U)SNVS_HPSVSR_SV0_SHIFT (0U)SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)œSNVS_HPSVSR_SV1_MASK (0x2U)ÜSNVS_HPSVSR_SV1_SHIFT (1U)ĜSNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)ŜSNVS_HPSVSR_SV2_MASK (0x4U)ƜSNVS_HPSVSR_SV2_SHIFT (2U)ǜSNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)ȜSNVS_HPSVSR_SV3_MASK (0x8U)ɜSNVS_HPSVSR_SV3_SHIFT (3U)ʜSNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)˜SNVS_HPSVSR_SV4_MASK (0x10U)̜SNVS_HPSVSR_SV4_SHIFT (4U)͜SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)ΜSNVS_HPSVSR_SV5_MASK (0x20U)ϜSNVS_HPSVSR_SV5_SHIFT (5U)МSNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)ќSNVS_HPSVSR_SW_SV_MASK (0x2000U)ҜSNVS_HPSVSR_SW_SV_SHIFT (13U)ӜSNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)ԜSNVS_HPSVSR_SW_FSV_MASK (0x4000U)՜SNVS_HPSVSR_SW_FSV_SHIFT (14U)֜SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)לSNVS_HPSVSR_SW_LPSV_MASK (0x8000U)؜SNVS_HPSVSR_SW_LPSV_SHIFT (15U)ٜSNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)ڜSNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)ۜSNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)ܜSNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)ݜSNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)ޜSNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)ߜSNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)SNVS_HPRTCMR_RTC_MASK (0x7FFFU)SNVS_HPRTCMR_RTC_SHIFT (0U)SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)SNVS_HPRTCLR_RTC_SHIFT (0U)SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)SNVS_HPTAMR_HPTA_MS_SHIFT (0U)SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)SNVS_HPTALR_HPTA_LS_SHIFT (0U)SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)SNVS_LPLR_ZMK_WHL_MASK (0x1U)SNVS_LPLR_ZMK_WHL_SHIFT (0U)SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)SNVS_LPLR_ZMK_RHL_MASK (0x2U)SNVS_LPLR_ZMK_RHL_SHIFT (1U)SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)SNVS_LPLR_SRTC_HL_MASK (0x4U)SNVS_LPLR_SRTC_HL_SHIFT (2U)SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)SNVS_LPLR_LPCALB_HL_MASK (0x8U)SNVS_LPLR_LPCALB_HL_SHIFT (3U)SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)SNVS_LPLR_MC_HL_MASK (0x10U)SNVS_LPLR_MC_HL_SHIFT (4U)SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)SNVS_LPLR_GPR_HL_MASK (0x20U)SNVS_LPLR_GPR_HL_SHIFT (5U)SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)SNVS_LPLR_LPSVCR_HL_MASK (0x40U)SNVS_LPLR_LPSVCR_HL_SHIFT (6U)SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)SNVS_LPLR_LPTDCR_HL_MASK (0x100U)SNVS_LPLR_LPTDCR_HL_SHIFT (8U)SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)SNVS_LPLR_MKS_HL_MASK (0x200U)SNVS_LPLR_MKS_HL_SHIFT (9U)SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)SNVS_LPCR_SRTC_ENV_MASK (0x1U)SNVS_LPCR_SRTC_ENV_SHIFT (0U)SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)SNVS_LPCR_LPTA_EN_MASK (0x2U)SNVS_LPCR_LPTA_EN_SHIFT (1U)SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)SNVS_LPCR_MC_ENV_MASK (0x4U)SNVS_LPCR_MC_ENV_SHIFT (2U)SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)SNVS_LPCR_LPWUI_EN_MASK (0x8U)SNVS_LPCR_LPWUI_EN_SHIFT (3U)SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)SNVS_LPCR_DP_EN_MASK (0x20U)SNVS_LPCR_DP_EN_SHIFT (5U)SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)SNVS_LPCR_TOP_MASK (0x40U)SNVS_LPCR_TOP_SHIFT (6U)SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)SNVS_LPCR_LPCALB_EN_MASK (0x100U)SNVS_LPCR_LPCALB_EN_SHIFT (8U)SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)SNVS_LPCR_LPCALB_VAL_SHIFT (10U)SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)SNVS_LPCR_DEBOUNCE_SHIFT (18U)ÝSNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)ĝSNVS_LPCR_ON_TIME_MASK (0x300000U)ŝSNVS_LPCR_ON_TIME_SHIFT (20U)ƝSNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)ǝSNVS_LPCR_PK_EN_MASK (0x400000U)ȝSNVS_LPCR_PK_EN_SHIFT (22U)ɝSNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)ʝSNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)˝SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)̝SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)͝SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)ΝSNVS_LPCR_GPR_Z_DIS_SHIFT (24U)ϝSNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)ҝSNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)ӝSNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)ԝSNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)՝SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)֝SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)םSNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)؝SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)ٝSNVS_LPMKCR_ZMK_VAL_SHIFT (3U)ڝSNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)۝SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)ܝSNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)ݝSNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)ޝSNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)ߝSNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)SNVS_LPSVCR_SV0_EN_MASK (0x1U)SNVS_LPSVCR_SV0_EN_SHIFT (0U)SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)SNVS_LPSVCR_SV1_EN_MASK (0x2U)SNVS_LPSVCR_SV1_EN_SHIFT (1U)SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)SNVS_LPSVCR_SV2_EN_MASK (0x4U)SNVS_LPSVCR_SV2_EN_SHIFT (2U)SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)SNVS_LPSVCR_SV3_EN_MASK (0x8U)SNVS_LPSVCR_SV3_EN_SHIFT (3U)SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)SNVS_LPSVCR_SV4_EN_MASK (0x10U)SNVS_LPSVCR_SV4_EN_SHIFT (4U)SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)SNVS_LPSVCR_SV5_EN_MASK (0x20U)SNVS_LPSVCR_SV5_EN_SHIFT (5U)SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)SNVS_LPTDCR_MCR_EN_MASK (0x4U)SNVS_LPTDCR_MCR_EN_SHIFT (2U)SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)SNVS_LPTDCR_ET1_EN_MASK (0x200U)SNVS_LPTDCR_ET1_EN_SHIFT (9U)SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)SNVS_LPTDCR_ET1P_MASK (0x800U)SNVS_LPTDCR_ET1P_SHIFT (11U)SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)SNVS_LPTDCR_OSCB_MASK (0x10000000U)SNVS_LPTDCR_OSCB_SHIFT (28U)SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)SNVS_LPSR_LPTA_MASK (0x1U)SNVS_LPSR_LPTA_SHIFT (0U)SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)SNVS_LPSR_SRTCR_MASK (0x2U)SNVS_LPSR_SRTCR_SHIFT (1U)SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)SNVS_LPSR_MCR_MASK (0x4U)SNVS_LPSR_MCR_SHIFT (2U)SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)SNVS_LPSR_PGD_MASK (0x8U)SNVS_LPSR_PGD_SHIFT (3U)SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)SNVS_LPSR_ET1D_MASK (0x200U)SNVS_LPSR_ET1D_SHIFT (9U)SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)SNVS_LPSR_ESVD_MASK (0x10000U)SNVS_LPSR_ESVD_SHIFT (16U)SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)SNVS_LPSR_EO_MASK (0x20000U)SNVS_LPSR_EO_SHIFT (17U)SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)SNVS_LPSR_SPO_MASK (0x40000U)SNVS_LPSR_SPO_SHIFT (18U)SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)SNVS_LPSR_SED_MASK (0x100000U)SNVS_LPSR_SED_SHIFT (20U)SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)SNVS_LPSR_LPNS_MASK (0x40000000U)SNVS_LPSR_LPNS_SHIFT (30U)SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)SNVS_LPSR_LPS_MASK (0x80000000U)SNVS_LPSR_LPS_SHIFT (31U)SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)SNVS_LPSRTCMR_SRTC_SHIFT (0U)SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)SNVS_LPSRTCLR_SRTC_SHIFT (0U)SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)SNVS_LPTAR_LPTA_SHIFT (0U)SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)žSNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)ÞSNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)ĞSNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)ŞSNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)ȞSNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)ɞSNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)ʞSNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)͞SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)ΞSNVS_LPPGDR_PGD_SHIFT (0U)ϞSNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)ҞSNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)ӞSNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)ԞSNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)מSNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)؞SNVS_LPZMKR_ZMK_SHIFT (0U)ٞSNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)ܞSNVS_LPZMKR_COUNT (8U)ߞSNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)SNVS_LPGPR_ALIAS_COUNT (4U)SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)SNVS_LPGPR_GPR_SHIFT (0U)SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)SNVS_LPGPR_COUNT (4U)SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)SNVS_HPVIDR1_IP_ID_SHIFT (16U)SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)SNVS_HPVIDR2_ECO_REV_SHIFT (8U)SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)SNVS_HPVIDR2_IP_ERA_SHIFT (24U)SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)SNVS_BASE (0x400D4000u)SNVS ((SNVS_Type *)SNVS_BASE)SNVS_BASE_ADDRS { SNVS_BASE }SNVS_BASE_PTRS { SNVS }SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }͟SPDIF_SCR_USRC_SEL_MASK (0x3U)ΟSPDIF_SCR_USRC_SEL_SHIFT (0U)ϟSPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)ПSPDIF_SCR_TXSEL_MASK (0x1CU)џSPDIF_SCR_TXSEL_SHIFT (2U)ҟSPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)ӟSPDIF_SCR_VALCTRL_MASK (0x20U)ԟSPDIF_SCR_VALCTRL_SHIFT (5U)՟SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)֟SPDIF_SCR_DMA_TX_EN_MASK (0x100U)ןSPDIF_SCR_DMA_TX_EN_SHIFT (8U)؟SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)ٟSPDIF_SCR_DMA_RX_EN_MASK (0x200U)ڟSPDIF_SCR_DMA_RX_EN_SHIFT (9U)۟SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)ܟSPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)ݟSPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)ޟSPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)ߟSPDIF_SCR_SOFT_RESET_MASK (0x1000U)SPDIF_SCR_SOFT_RESET_SHIFT (12U)SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)SPDIF_SCR_LOW_POWER_MASK (0x2000U)SPDIF_SCR_LOW_POWER_SHIFT (13U)SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)SPDIF_SCR_RXFIFO_RST_SHIFT (21U)SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)SPDIF_SRCD_USYNCMODE_MASK (0x2U)SPDIF_SRCD_USYNCMODE_SHIFT (1U)SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)SPDIF_SRPC_GAINSEL_MASK (0x38U)SPDIF_SRPC_GAINSEL_SHIFT (3U)SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)SPDIF_SRPC_LOCK_MASK (0x40U)SPDIF_SRPC_LOCK_SHIFT (6U)SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)SPDIF_SIE_RXFIFOFUL_MASK (0x1U)SPDIF_SIE_RXFIFOFUL_SHIFT (0U)SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)SPDIF_SIE_TXEM_MASK (0x2U)SPDIF_SIE_TXEM_SHIFT (1U)SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)SPDIF_SIE_LOCKLOSS_MASK (0x4U)SPDIF_SIE_LOCKLOSS_SHIFT (2U)SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)SPDIF_SIE_RXFIFORESYN_MASK (0x8U)SPDIF_SIE_RXFIFORESYN_SHIFT (3U)SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)SPDIF_SIE_UQERR_MASK (0x20U)SPDIF_SIE_UQERR_SHIFT (5U)SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)SPDIF_SIE_UQSYNC_MASK (0x40U)SPDIF_SIE_UQSYNC_SHIFT (6U)SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)SPDIF_SIE_QRXOV_MASK (0x80U)SPDIF_SIE_QRXOV_SHIFT (7U)SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)SPDIF_SIE_QRXFUL_MASK (0x100U)SPDIF_SIE_QRXFUL_SHIFT (8U)SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)SPDIF_SIE_URXOV_MASK (0x200U)SPDIF_SIE_URXOV_SHIFT (9U)SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)SPDIF_SIE_URXFUL_MASK (0x400U)SPDIF_SIE_URXFUL_SHIFT (10U)SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)SPDIF_SIE_BITERR_MASK (0x4000U)SPDIF_SIE_BITERR_SHIFT (14U)SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)SPDIF_SIE_SYMERR_MASK (0x8000U)SPDIF_SIE_SYMERR_SHIFT (15U)SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)SPDIF_SIE_VALNOGOOD_MASK (0x10000U)SPDIF_SIE_VALNOGOOD_SHIFT (16U)SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)SPDIF_SIE_CNEW_MASK (0x20000U)SPDIF_SIE_CNEW_SHIFT (17U)SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)SPDIF_SIE_TXRESYN_MASK (0x40000U)SPDIF_SIE_TXRESYN_SHIFT (18U)SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)SPDIF_SIE_TXUNOV_MASK (0x80000U)SPDIF_SIE_TXUNOV_SHIFT (19U)SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)SPDIF_SIE_LOCK_MASK (0x100000U)SPDIF_SIE_LOCK_SHIFT (20U)SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)ĠSPDIF_SIC_LOCKLOSS_MASK (0x4U)ŠSPDIF_SIC_LOCKLOSS_SHIFT (2U)ƠSPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)ǠSPDIF_SIC_RXFIFORESYN_MASK (0x8U)ȠSPDIF_SIC_RXFIFORESYN_SHIFT (3U)ɠSPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)ʠSPDIF_SIC_RXFIFOUNOV_MASK (0x10U)ˠSPDIF_SIC_RXFIFOUNOV_SHIFT (4U)̠SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)͠SPDIF_SIC_UQERR_MASK (0x20U)ΠSPDIF_SIC_UQERR_SHIFT (5U)ϠSPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)РSPDIF_SIC_UQSYNC_MASK (0x40U)ѠSPDIF_SIC_UQSYNC_SHIFT (6U)ҠSPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)ӠSPDIF_SIC_QRXOV_MASK (0x80U)ԠSPDIF_SIC_QRXOV_SHIFT (7U)ՠSPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)֠SPDIF_SIC_URXOV_MASK (0x200U)נSPDIF_SIC_URXOV_SHIFT (9U)ؠSPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)٠SPDIF_SIC_BITERR_MASK (0x4000U)ڠSPDIF_SIC_BITERR_SHIFT (14U)۠SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)ܠSPDIF_SIC_SYMERR_MASK (0x8000U)ݠSPDIF_SIC_SYMERR_SHIFT (15U)ޠSPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)ߠSPDIF_SIC_VALNOGOOD_MASK (0x10000U)SPDIF_SIC_VALNOGOOD_SHIFT (16U)SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)SPDIF_SIC_CNEW_MASK (0x20000U)SPDIF_SIC_CNEW_SHIFT (17U)SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)SPDIF_SIC_TXRESYN_MASK (0x40000U)SPDIF_SIC_TXRESYN_SHIFT (18U)SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)SPDIF_SIC_TXUNOV_MASK (0x80000U)SPDIF_SIC_TXUNOV_SHIFT (19U)SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)SPDIF_SIC_LOCK_MASK (0x100000U)SPDIF_SIC_LOCK_SHIFT (20U)SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)SPDIF_SIS_RXFIFOFUL_MASK (0x1U)SPDIF_SIS_RXFIFOFUL_SHIFT (0U)SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)SPDIF_SIS_TXEM_MASK (0x2U)SPDIF_SIS_TXEM_SHIFT (1U)SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)SPDIF_SIS_LOCKLOSS_MASK (0x4U)SPDIF_SIS_LOCKLOSS_SHIFT (2U)SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)SPDIF_SIS_RXFIFORESYN_MASK (0x8U)SPDIF_SIS_RXFIFORESYN_SHIFT (3U)SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)SPDIF_SIS_UQERR_MASK (0x20U)SPDIF_SIS_UQERR_SHIFT (5U)SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)SPDIF_SIS_UQSYNC_MASK (0x40U)SPDIF_SIS_UQSYNC_SHIFT (6U)SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)SPDIF_SIS_QRXOV_MASK (0x80U)SPDIF_SIS_QRXOV_SHIFT (7U)SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)SPDIF_SIS_QRXFUL_MASK (0x100U)SPDIF_SIS_QRXFUL_SHIFT (8U)SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)SPDIF_SIS_URXOV_MASK (0x200U)SPDIF_SIS_URXOV_SHIFT (9U)SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)SPDIF_SIS_URXFUL_MASK (0x400U)SPDIF_SIS_URXFUL_SHIFT (10U)SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)SPDIF_SIS_BITERR_MASK (0x4000U)SPDIF_SIS_BITERR_SHIFT (14U)SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)SPDIF_SIS_SYMERR_MASK (0x8000U)SPDIF_SIS_SYMERR_SHIFT (15U)SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)SPDIF_SIS_VALNOGOOD_MASK (0x10000U)SPDIF_SIS_VALNOGOOD_SHIFT (16U)SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)SPDIF_SIS_CNEW_MASK (0x20000U)SPDIF_SIS_CNEW_SHIFT (17U)SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)SPDIF_SIS_TXRESYN_MASK (0x40000U)SPDIF_SIS_TXRESYN_SHIFT (18U)SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)SPDIF_SIS_TXUNOV_MASK (0x80000U)SPDIF_SIS_TXUNOV_SHIFT (19U)SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)SPDIF_SIS_LOCK_MASK (0x100000U)SPDIF_SIS_LOCK_SHIFT (20U)SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)SPDIF_SRL_RXDATALEFT_SHIFT (0U)SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)SPDIF_SRR_RXDATARIGHT_SHIFT (0U)SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)SPDIF_SRU_RXUCHANNEL_SHIFT (0U)SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)¡SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)áSPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)ơSPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)ǡSPDIF_STL_TXDATALEFT_SHIFT (0U)ȡSPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)ˡSPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)̡SPDIF_STR_TXDATARIGHT_SHIFT (0U)͡SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)СSPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)ѡSPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)ҡSPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)աSPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)֡SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)סSPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)ڡSPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)ۡSPDIF_SRFM_FREQMEAS_SHIFT (0U)ܡSPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)ߡSPDIF_STC_TXCLK_DF_MASK (0x7FU)SPDIF_STC_TXCLK_DF_SHIFT (0U)SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)SPDIF_STC_SYSCLK_DF_SHIFT (11U)SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)SPDIF_BASE (0x40380000u)SPDIF ((SPDIF_Type *)SPDIF_BASE)SPDIF_BASE_ADDRS { SPDIF_BASE }SPDIF_BASE_PTRS { SPDIF }SPDIF_IRQS { SPDIF_IRQn }SRC_SCR_LOCKUP_RST_MASK (0x10U)SRC_SCR_LOCKUP_RST_SHIFT (4U)SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK)SRC_SCR_MASK_WDOG_RST_MASK (0x780U)SRC_SCR_MASK_WDOG_RST_SHIFT (7U)SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)SRC_SCR_CORE0_RST_MASK (0x2000U)SRC_SCR_CORE0_RST_SHIFT (13U)SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)SRC_SCR_CORE0_DBG_RST_SHIFT (17U)SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)SRC_SBMR1_BOOT_CFG1_SHIFT (0U)SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)SRC_SBMR1_BOOT_CFG2_SHIFT (8U)SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)SRC_SBMR1_BOOT_CFG3_SHIFT (16U)SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)SRC_SBMR1_BOOT_CFG4_SHIFT (24U)SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)¢SRC_SRSR_IPP_RESET_B_MASK (0x1U)âSRC_SRSR_IPP_RESET_B_SHIFT (0U)ĢSRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)ŢSRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)ƢSRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)ǢSRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)ȢSRC_SRSR_CSU_RESET_B_MASK (0x4U)ɢSRC_SRSR_CSU_RESET_B_SHIFT (2U)ʢSRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)ˢSRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)̢SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)͢SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)΢SRC_SRSR_WDOG_RST_B_MASK (0x10U)ϢSRC_SRSR_WDOG_RST_B_SHIFT (4U)ТSRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)ѢSRC_SRSR_JTAG_RST_B_MASK (0x20U)ҢSRC_SRSR_JTAG_RST_B_SHIFT (5U)ӢSRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)ԢSRC_SRSR_JTAG_SW_RST_MASK (0x40U)բSRC_SRSR_JTAG_SW_RST_SHIFT (6U)֢SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)עSRC_SRSR_WDOG3_RST_B_MASK (0x80U)آSRC_SRSR_WDOG3_RST_B_SHIFT (7U)٢SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)ڢSRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)ۢSRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)ܢSRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)ߢSRC_SBMR2_SEC_CONFIG_MASK (0x3U)SRC_SBMR2_SEC_CONFIG_SHIFT (0U)SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)SRC_SBMR2_BMOD_MASK (0x3000000U)SRC_SBMR2_BMOD_SHIFT (24U)SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)SRC_GPR_COUNT (10U)SRC_BASE (0x400F8000u)SRC ((SRC_Type *)SRC_BASE)SRC_BASE_ADDRS { SRC_BASE }SRC_BASE_PTRS { SRC }SRC_IRQS { SRC_IRQn }SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASKSRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFTSRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASKSRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFTSRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASKSRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFTSRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASKSRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFTSRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASKSRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFTSRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK | SRC_SRSR_JTAG_SW_RST_MASK | SRC_SRSR_JTAG_RST_B_MASK | SRC_SRSR_WDOG_RST_B_MASK | SRC_SRSR_IPP_USER_RESET_B_MASK | SRC_SRSR_CSU_RESET_B_MASK | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK | SRC_SRSR_IPP_RESET_B_MASK)ͣTEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)ΣTEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)ϣTEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)УTEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)ѣTEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)ңTEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)ӣTEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)ԣTEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)գTEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)֣TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)ףTEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)أTEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)٣TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)ڣTEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)ۣTEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)ޣTEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)ߣTEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)¤TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)̤TEMPMON_BASE (0x400D8000u)ΤTEMPMON ((TEMPMON_Type *)TEMPMON_BASE)ФTEMPMON_BASE_ADDRS { TEMPMON_BASE }ҤTEMPMON_BASE_PTRS { TEMPMON }TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)TMR_COMP1_COMPARISON_1_SHIFT (0U)TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)TMR_COMP1_COUNT (4U)TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)TMR_COMP2_COMPARISON_2_SHIFT (0U)TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)TMR_COMP2_COUNT (4U)TMR_CAPT_CAPTURE_MASK (0xFFFFU)TMR_CAPT_CAPTURE_SHIFT (0U)TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)TMR_CAPT_COUNT (4U)TMR_LOAD_LOAD_MASK (0xFFFFU)TMR_LOAD_LOAD_SHIFT (0U)TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)TMR_LOAD_COUNT (4U)TMR_HOLD_HOLD_MASK (0xFFFFU)TMR_HOLD_HOLD_SHIFT (0U)TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)TMR_HOLD_COUNT (4U)TMR_CNTR_COUNTER_MASK (0xFFFFU)TMR_CNTR_COUNTER_SHIFT (0U)TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)TMR_CNTR_COUNT (4U)TMR_CTRL_OUTMODE_MASK (0x7U)TMR_CTRL_OUTMODE_SHIFT (0U)TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)TMR_CTRL_COINIT_MASK (0x8U)TMR_CTRL_COINIT_SHIFT (3U)TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)TMR_CTRL_DIR_MASK (0x10U)TMR_CTRL_DIR_SHIFT (4U)TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)TMR_CTRL_LENGTH_MASK (0x20U)TMR_CTRL_LENGTH_SHIFT (5U)TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)TMR_CTRL_ONCE_MASK (0x40U)TMR_CTRL_ONCE_SHIFT (6U)TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)TMR_CTRL_SCS_MASK (0x180U)TMR_CTRL_SCS_SHIFT (7U)¥TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)åTMR_CTRL_PCS_MASK (0x1E00U)ĥTMR_CTRL_PCS_SHIFT (9U)ťTMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)ƥTMR_CTRL_CM_MASK (0xE000U)ǥTMR_CTRL_CM_SHIFT (13U)ȥTMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)˥TMR_CTRL_COUNT (4U)ΥTMR_SCTRL_OEN_MASK (0x1U)ϥTMR_SCTRL_OEN_SHIFT (0U)ХTMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)ѥTMR_SCTRL_OPS_MASK (0x2U)ҥTMR_SCTRL_OPS_SHIFT (1U)ӥTMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)ԥTMR_SCTRL_FORCE_MASK (0x4U)եTMR_SCTRL_FORCE_SHIFT (2U)֥TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)ץTMR_SCTRL_VAL_MASK (0x8U)إTMR_SCTRL_VAL_SHIFT (3U)٥TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)ڥTMR_SCTRL_EEOF_MASK (0x10U)ۥTMR_SCTRL_EEOF_SHIFT (4U)ܥTMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)ݥTMR_SCTRL_MSTR_MASK (0x20U)ޥTMR_SCTRL_MSTR_SHIFT (5U)ߥTMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)TMR_SCTRL_INPUT_MASK (0x100U)TMR_SCTRL_INPUT_SHIFT (8U)TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)TMR_SCTRL_IPS_MASK (0x200U)TMR_SCTRL_IPS_SHIFT (9U)TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)TMR_SCTRL_IEFIE_MASK (0x400U)TMR_SCTRL_IEFIE_SHIFT (10U)TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)TMR_SCTRL_IEF_MASK (0x800U)TMR_SCTRL_IEF_SHIFT (11U)TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)TMR_SCTRL_TOFIE_MASK (0x1000U)TMR_SCTRL_TOFIE_SHIFT (12U)TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)TMR_SCTRL_TOF_MASK (0x2000U)TMR_SCTRL_TOF_SHIFT (13U)TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)TMR_SCTRL_TCFIE_MASK (0x4000U)TMR_SCTRL_TCFIE_SHIFT (14U)TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)TMR_SCTRL_TCF_MASK (0x8000U)TMR_SCTRL_TCF_SHIFT (15U)TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)TMR_SCTRL_COUNT (4U)TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)TMR_CMPLD1_COUNT (4U)TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)TMR_CMPLD2_COUNT (4U)TMR_CSCTRL_CL1_MASK (0x3U)TMR_CSCTRL_CL1_SHIFT (0U)TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)TMR_CSCTRL_CL2_MASK (0xCU)TMR_CSCTRL_CL2_SHIFT (2U)TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)TMR_CSCTRL_TCF1_MASK (0x10U)TMR_CSCTRL_TCF1_SHIFT (4U)TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)TMR_CSCTRL_TCF2_MASK (0x20U)TMR_CSCTRL_TCF2_SHIFT (5U)TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)TMR_CSCTRL_TCF1EN_MASK (0x40U)TMR_CSCTRL_TCF1EN_SHIFT (6U)TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)TMR_CSCTRL_TCF2EN_MASK (0x80U)TMR_CSCTRL_TCF2EN_SHIFT (7U)TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)TMR_CSCTRL_UP_MASK (0x200U)TMR_CSCTRL_UP_SHIFT (9U)TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)TMR_CSCTRL_TCI_MASK (0x400U)TMR_CSCTRL_TCI_SHIFT (10U)TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)TMR_CSCTRL_ROC_MASK (0x800U)TMR_CSCTRL_ROC_SHIFT (11U)TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)TMR_CSCTRL_ALT_LOAD_SHIFT (12U)TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)TMR_CSCTRL_FAULT_MASK (0x2000U)TMR_CSCTRL_FAULT_SHIFT (13U)TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)TMR_CSCTRL_DBG_EN_MASK (0xC000U)TMR_CSCTRL_DBG_EN_SHIFT (14U)TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)TMR_CSCTRL_COUNT (4U)TMR_FILT_FILT_PER_MASK (0xFFU)TMR_FILT_FILT_PER_SHIFT (0U)TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)TMR_FILT_FILT_CNT_MASK (0x700U)TMR_FILT_FILT_CNT_SHIFT (8U)TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)TMR_FILT_COUNT (4U)ĦTMR_DMA_IEFDE_MASK (0x1U)ŦTMR_DMA_IEFDE_SHIFT (0U)ƦTMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)ǦTMR_DMA_CMPLD1DE_MASK (0x2U)ȦTMR_DMA_CMPLD1DE_SHIFT (1U)ɦTMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)ʦTMR_DMA_CMPLD2DE_MASK (0x4U)˦TMR_DMA_CMPLD2DE_SHIFT (2U)̦TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)ϦTMR_DMA_COUNT (4U)ҦTMR_ENBL_ENBL_MASK (0xFU)ӦTMR_ENBL_ENBL_SHIFT (0U)ԦTMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)צTMR_ENBL_COUNT (4U)TMR1_BASE (0x401DC000u)TMR1 ((TMR_Type *)TMR1_BASE)TMR2_BASE (0x401E0000u)TMR2 ((TMR_Type *)TMR2_BASE)TMR3_BASE (0x401E4000u)TMR3 ((TMR_Type *)TMR3_BASE)TMR4_BASE (0x401E8000u)TMR4 ((TMR_Type *)TMR4_BASE)TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }ѧTRNG_MCTL_SAMP_MODE_MASK (0x3U)ҧTRNG_MCTL_SAMP_MODE_SHIFT (0U)ӧTRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)ԧTRNG_MCTL_OSC_DIV_MASK (0xCU)էTRNG_MCTL_OSC_DIV_SHIFT (2U)֧TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)קTRNG_MCTL_UNUSED4_MASK (0x10U)اTRNG_MCTL_UNUSED4_SHIFT (4U)٧TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)ڧTRNG_MCTL_UNUSED5_MASK (0x20U)ۧTRNG_MCTL_UNUSED5_SHIFT (5U)ܧTRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)ݧTRNG_MCTL_RST_DEF_MASK (0x40U)ާTRNG_MCTL_RST_DEF_SHIFT (6U)ߧTRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)TRNG_MCTL_FOR_SCLK_MASK (0x80U)TRNG_MCTL_FOR_SCLK_SHIFT (7U)TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)TRNG_MCTL_FCT_FAIL_MASK (0x100U)TRNG_MCTL_FCT_FAIL_SHIFT (8U)TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)TRNG_MCTL_FCT_VAL_MASK (0x200U)TRNG_MCTL_FCT_VAL_SHIFT (9U)TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)TRNG_MCTL_ENT_VAL_MASK (0x400U)TRNG_MCTL_ENT_VAL_SHIFT (10U)TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)TRNG_MCTL_TST_OUT_MASK (0x800U)TRNG_MCTL_TST_OUT_SHIFT (11U)TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)TRNG_MCTL_ERR_MASK (0x1000U)TRNG_MCTL_ERR_SHIFT (12U)TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)TRNG_MCTL_TSTOP_OK_MASK (0x2000U)TRNG_MCTL_TSTOP_OK_SHIFT (13U)TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)TRNG_MCTL_LRUN_CONT_MASK (0x4000U)TRNG_MCTL_LRUN_CONT_SHIFT (14U)TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)TRNG_MCTL_PRGM_MASK (0x10000U)TRNG_MCTL_PRGM_SHIFT (16U)TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)TRNG_SCMISC_LRUN_MAX_SHIFT (0U)TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)TRNG_SCMISC_RTY_CT_MASK (0xF0000U)TRNG_SCMISC_RTY_CT_SHIFT (16U)TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)TRNG_PKRRNG_PKR_RNG_SHIFT (0U)TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)TRNG_PKRMAX_PKR_MAX_SHIFT (0U)TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)TRNG_PKRSQ_PKR_SQ_SHIFT (0U)TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)TRNG_SDCTL_ENT_DLY_SHIFT (16U)TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)TRNG_SBLIM_SB_LIM_MASK (0x3FFU)TRNG_SBLIM_SB_LIM_SHIFT (0U)TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)TRNG_TOTSAM_TOT_SAM_SHIFT (0U)TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)TRNG_FRQCNT_FRQ_CT_SHIFT (0U)TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)TRNG_SCMC_MONO_CT_MASK (0xFFFFU)TRNG_SCMC_MONO_CT_SHIFT (0U)TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)TRNG_SCML_MONO_MAX_MASK (0xFFFFU)TRNG_SCML_MONO_MAX_SHIFT (0U)TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)TRNG_SCML_MONO_RNG_SHIFT (16U)TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)¨TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)èTRNG_SCR1C_R1_0_CT_SHIFT (0U)ĨTRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)ŨTRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)ƨTRNG_SCR1C_R1_1_CT_SHIFT (16U)ǨTRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)ʨTRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)˨TRNG_SCR1L_RUN1_MAX_SHIFT (0U)̨TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)ͨTRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)ΨTRNG_SCR1L_RUN1_RNG_SHIFT (16U)ϨTRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)ҨTRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)ӨTRNG_SCR2C_R2_0_CT_SHIFT (0U)ԨTRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)ըTRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)֨TRNG_SCR2C_R2_1_CT_SHIFT (16U)רTRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)ڨTRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)ۨTRNG_SCR2L_RUN2_MAX_SHIFT (0U)ܨTRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)ݨTRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)ިTRNG_SCR2L_RUN2_RNG_SHIFT (16U)ߨTRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)TRNG_SCR3C_R3_0_CT_SHIFT (0U)TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)TRNG_SCR3C_R3_1_CT_SHIFT (16U)TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)TRNG_SCR3L_RUN3_MAX_SHIFT (0U)TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)TRNG_SCR3L_RUN3_RNG_SHIFT (16U)TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)TRNG_SCR4C_R4_0_CT_SHIFT (0U)TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)TRNG_SCR4C_R4_1_CT_SHIFT (16U)TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)TRNG_SCR4L_RUN4_MAX_SHIFT (0U)TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)TRNG_SCR4L_RUN4_RNG_SHIFT (16U)TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)TRNG_SCR5C_R5_0_CT_SHIFT (0U)TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)TRNG_SCR5C_R5_1_CT_SHIFT (16U)TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)TRNG_SCR5L_RUN5_MAX_SHIFT (0U)TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)TRNG_SCR5L_RUN5_RNG_SHIFT (16U)TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)TRNG_STATUS_TF1BR0_MASK (0x1U)TRNG_STATUS_TF1BR0_SHIFT (0U)TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)TRNG_STATUS_TF1BR1_MASK (0x2U)TRNG_STATUS_TF1BR1_SHIFT (1U)TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)TRNG_STATUS_TF2BR0_MASK (0x4U)TRNG_STATUS_TF2BR0_SHIFT (2U)TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)TRNG_STATUS_TF2BR1_MASK (0x8U)TRNG_STATUS_TF2BR1_SHIFT (3U)TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)TRNG_STATUS_TF3BR0_MASK (0x10U)TRNG_STATUS_TF3BR0_SHIFT (4U)TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)TRNG_STATUS_TF3BR1_MASK (0x20U)TRNG_STATUS_TF3BR1_SHIFT (5U)TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)TRNG_STATUS_TF4BR0_MASK (0x40U)TRNG_STATUS_TF4BR0_SHIFT (6U)TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)TRNG_STATUS_TF4BR1_MASK (0x80U)TRNG_STATUS_TF4BR1_SHIFT (7U)TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)TRNG_STATUS_TF5BR0_MASK (0x100U)TRNG_STATUS_TF5BR0_SHIFT (8U)TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)TRNG_STATUS_TF5BR1_MASK (0x200U)TRNG_STATUS_TF5BR1_SHIFT (9U)TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)TRNG_STATUS_TF6PBR0_MASK (0x400U)TRNG_STATUS_TF6PBR0_SHIFT (10U)©TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)éTRNG_STATUS_TF6PBR1_MASK (0x800U)ĩTRNG_STATUS_TF6PBR1_SHIFT (11U)ũTRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)ƩTRNG_STATUS_TFSB_MASK (0x1000U)ǩTRNG_STATUS_TFSB_SHIFT (12U)ȩTRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)ɩTRNG_STATUS_TFLR_MASK (0x2000U)ʩTRNG_STATUS_TFLR_SHIFT (13U)˩TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)̩TRNG_STATUS_TFP_MASK (0x4000U)ͩTRNG_STATUS_TFP_SHIFT (14U)ΩTRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)ϩTRNG_STATUS_TFMB_MASK (0x8000U)ЩTRNG_STATUS_TFMB_SHIFT (15U)ѩTRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)ҩTRNG_STATUS_RETRY_CT_MASK (0xF0000U)өTRNG_STATUS_RETRY_CT_SHIFT (16U)ԩTRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)שTRNG_ENT_ENT_MASK (0xFFFFFFFFU)ةTRNG_ENT_ENT_SHIFT (0U)٩TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)ܩTRNG_ENT_COUNT (16U)ߩTRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)TRNG_SEC_CFG_UNUSED0_MASK (0x1U)TRNG_SEC_CFG_UNUSED0_SHIFT (0U)TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)TRNG_SEC_CFG_UNUSED2_MASK (0x4U)TRNG_SEC_CFG_UNUSED2_SHIFT (2U)TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)TRNG_INT_CTRL_HW_ERR_MASK (0x1U)TRNG_INT_CTRL_HW_ERR_SHIFT (0U)TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)TRNG_INT_CTRL_UNUSED_SHIFT (3U)TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)TRNG_INT_MASK_HW_ERR_MASK (0x1U)TRNG_INT_MASK_HW_ERR_SHIFT (0U)TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)TRNG_INT_MASK_ENT_VAL_MASK (0x2U)TRNG_INT_MASK_ENT_VAL_SHIFT (1U)TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)êTRNG_INT_STATUS_HW_ERR_MASK (0x1U)ĪTRNG_INT_STATUS_HW_ERR_SHIFT (0U)ŪTRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)ƪTRNG_INT_STATUS_ENT_VAL_MASK (0x2U)ǪTRNG_INT_STATUS_ENT_VAL_SHIFT (1U)ȪTRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)ɪTRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)ʪTRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)˪TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)ΪTRNG_VID1_MIN_REV_MASK (0xFFU)ϪTRNG_VID1_MIN_REV_SHIFT (0U)ЪTRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)ѪTRNG_VID1_MAJ_REV_MASK (0xFF00U)ҪTRNG_VID1_MAJ_REV_SHIFT (8U)ӪTRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)ԪTRNG_VID1_IP_ID_MASK (0xFFFF0000U)ժTRNG_VID1_IP_ID_SHIFT (16U)֪TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)٪TRNG_VID2_CONFIG_OPT_MASK (0xFFU)ڪTRNG_VID2_CONFIG_OPT_SHIFT (0U)۪TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)ܪTRNG_VID2_ECO_REV_MASK (0xFF00U)ݪTRNG_VID2_ECO_REV_SHIFT (8U)ުTRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)ߪTRNG_VID2_INTG_OPT_MASK (0xFF0000U)TRNG_VID2_INTG_OPT_SHIFT (16U)TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)TRNG_VID2_ERA_MASK (0xFF000000U)TRNG_VID2_ERA_SHIFT (24U)TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)TRNG_BASE (0x400CC000u)TRNG ((TRNG_Type *)TRNG_BASE)TRNG_BASE_ADDRS { TRNG_BASE }TRNG_BASE_PTRS { TRNG }TRNG_IRQS { TRNG_IRQn }TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U)TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U)TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK)TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U)TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK)TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)«TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)ëTSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)ƫTSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)ǫTSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)ȫTSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)ɫTSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)ʫTSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)˫TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)ΫTSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)ϫTSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)ЫTSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)ѫTSC_INT_EN_DETECT_INT_EN_MASK (0x10U)ҫTSC_INT_EN_DETECT_INT_EN_SHIFT (4U)ӫTSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)ԫTSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)իTSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)֫TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)٫TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)ګTSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)۫TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)ܫTSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)ݫTSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)ޫTSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)߫TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)TSC_INT_STATUS_MEASURE_MASK (0x1U)TSC_INT_STATUS_MEASURE_SHIFT (0U)TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)TSC_INT_STATUS_DETECT_MASK (0x10U)TSC_INT_STATUS_DETECT_SHIFT (4U)TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)TSC_INT_STATUS_VALID_MASK (0x100U)TSC_INT_STATUS_VALID_SHIFT (8U)TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)TSC_INT_STATUS_IDLE_SW_SHIFT (12U)TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)¬TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)ìTSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)ĬTSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)ŬTSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)ƬTSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)ǬTSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)ȬTSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)ɬTSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)ʬTSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)ˬTSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)̬TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)ͬTSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)׬TSC_BASE (0x400E0000u)٬TSC ((TSC_Type *)TSC_BASE)۬TSC_BASE_ADDRS { TSC_BASE }ݬTSC_BASE_PTRS { TSC }߬TSC_IRQS { TSC_DIG_IRQn }TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASKTSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFTTSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x)USB_ID_ID_MASK (0x3FU)USB_ID_ID_SHIFT (0U)USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)USB_ID_NID_MASK (0x3F00U)USB_ID_NID_SHIFT (8U)USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)USB_ID_REVISION_MASK (0xFF0000U)USB_ID_REVISION_SHIFT (16U)USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)íUSB_HWGENERAL_PHYW_MASK (0x30U)ĭUSB_HWGENERAL_PHYW_SHIFT (4U)ŭUSB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)ƭUSB_HWGENERAL_PHYM_MASK (0x1C0U)ǭUSB_HWGENERAL_PHYM_SHIFT (6U)ȭUSB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)ɭUSB_HWGENERAL_SM_MASK (0x600U)ʭUSB_HWGENERAL_SM_SHIFT (9U)˭USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)έUSB_HWHOST_HC_MASK (0x1U)ϭUSB_HWHOST_HC_SHIFT (0U)ЭUSB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)ѭUSB_HWHOST_NPORT_MASK (0xEU)ҭUSB_HWHOST_NPORT_SHIFT (1U)ӭUSB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)֭USB_HWDEVICE_DC_MASK (0x1U)׭USB_HWDEVICE_DC_SHIFT (0U)حUSB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)٭USB_HWDEVICE_DEVEP_MASK (0x3EU)ڭUSB_HWDEVICE_DEVEP_SHIFT (1U)ۭUSB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)ޭUSB_HWTXBUF_TXBURST_MASK (0xFFU)߭USB_HWTXBUF_TXBURST_SHIFT (0U)USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)USB_HWTXBUF_TXCHANADD_SHIFT (16U)USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)USB_HWRXBUF_RXBURST_MASK (0xFFU)USB_HWRXBUF_RXBURST_SHIFT (0U)USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)USB_HWRXBUF_RXADD_MASK (0xFF00U)USB_HWRXBUF_RXADD_SHIFT (8U)USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER0LD_GPTLD_SHIFT (0U)USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)USB_GPTIMER1LD_GPTLD_SHIFT (0U)USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)USB_SBUSCFG_AHBBRST_MASK (0x7U)USB_SBUSCFG_AHBBRST_SHIFT (0U)USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)USB_HCIVERSION_HCIVERSION_SHIFT (0U)USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)USB_HCSPARAMS_N_PORTS_MASK (0xFU)USB_HCSPARAMS_N_PORTS_SHIFT (0U)USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)USB_HCSPARAMS_PPC_MASK (0x10U)USB_HCSPARAMS_PPC_SHIFT (4U)USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)USB_HCSPARAMS_N_PCC_MASK (0xF00U)USB_HCSPARAMS_N_PCC_SHIFT (8U)USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)USB_HCSPARAMS_N_CC_MASK (0xF000U)USB_HCSPARAMS_N_CC_SHIFT (12U)USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)USB_HCSPARAMS_PI_MASK (0x10000U)USB_HCSPARAMS_PI_SHIFT (16U)USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)USB_HCSPARAMS_N_PTT_MASK (0xF00000U)USB_HCSPARAMS_N_PTT_SHIFT (20U)USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)USB_HCSPARAMS_N_TT_MASK (0xF000000U)USB_HCSPARAMS_N_TT_SHIFT (24U)USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)USB_HCCPARAMS_ADC_MASK (0x1U)USB_HCCPARAMS_ADC_SHIFT (0U)USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)USB_HCCPARAMS_PFL_MASK (0x2U)USB_HCCPARAMS_PFL_SHIFT (1U)USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)USB_HCCPARAMS_ASP_MASK (0x4U)USB_HCCPARAMS_ASP_SHIFT (2U)®USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)îUSB_HCCPARAMS_IST_MASK (0xF0U)ĮUSB_HCCPARAMS_IST_SHIFT (4U)ŮUSB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)ƮUSB_HCCPARAMS_EECP_MASK (0xFF00U)ǮUSB_HCCPARAMS_EECP_SHIFT (8U)ȮUSB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)ˮUSB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)̮USB_DCIVERSION_DCIVERSION_SHIFT (0U)ͮUSB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)ЮUSB_DCCPARAMS_DEN_MASK (0x1FU)ѮUSB_DCCPARAMS_DEN_SHIFT (0U)ҮUSB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)ӮUSB_DCCPARAMS_DC_MASK (0x80U)ԮUSB_DCCPARAMS_DC_SHIFT (7U)ծUSB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)֮USB_DCCPARAMS_HC_MASK (0x100U)׮USB_DCCPARAMS_HC_SHIFT (8U)خUSB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)ۮUSB_USBCMD_RS_MASK (0x1U)ܮUSB_USBCMD_RS_SHIFT (0U)ݮUSB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)ޮUSB_USBCMD_RST_MASK (0x2U)߮USB_USBCMD_RST_SHIFT (1U)USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)USB_USBCMD_FS_1_MASK (0xCU)USB_USBCMD_FS_1_SHIFT (2U)USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)USB_USBCMD_PSE_MASK (0x10U)USB_USBCMD_PSE_SHIFT (4U)USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)USB_USBCMD_ASE_MASK (0x20U)USB_USBCMD_ASE_SHIFT (5U)USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)USB_USBCMD_IAA_MASK (0x40U)USB_USBCMD_IAA_SHIFT (6U)USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)USB_USBCMD_ASP_MASK (0x300U)USB_USBCMD_ASP_SHIFT (8U)USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)USB_USBCMD_ASPE_MASK (0x800U)USB_USBCMD_ASPE_SHIFT (11U)USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)USB_USBCMD_ATDTW_MASK (0x1000U)USB_USBCMD_ATDTW_SHIFT (12U)USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)USB_USBCMD_SUTW_MASK (0x2000U)USB_USBCMD_SUTW_SHIFT (13U)USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)USB_USBCMD_FS_2_MASK (0x8000U)USB_USBCMD_FS_2_SHIFT (15U)USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)USB_USBCMD_ITC_MASK (0xFF0000U)USB_USBCMD_ITC_SHIFT (16U)USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)USB_USBSTS_UI_MASK (0x1U)USB_USBSTS_UI_SHIFT (0U)USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)USB_USBSTS_UEI_MASK (0x2U)USB_USBSTS_UEI_SHIFT (1U)USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)USB_USBSTS_PCI_MASK (0x4U)USB_USBSTS_PCI_SHIFT (2U)USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)USB_USBSTS_FRI_MASK (0x8U)USB_USBSTS_FRI_SHIFT (3U)USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)USB_USBSTS_SEI_MASK (0x10U)USB_USBSTS_SEI_SHIFT (4U)USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)USB_USBSTS_AAI_MASK (0x20U)USB_USBSTS_AAI_SHIFT (5U)USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)USB_USBSTS_URI_MASK (0x40U)USB_USBSTS_URI_SHIFT (6U)USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)USB_USBSTS_SRI_MASK (0x80U)USB_USBSTS_SRI_SHIFT (7U)USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)USB_USBSTS_SLI_MASK (0x100U)USB_USBSTS_SLI_SHIFT (8U)USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)USB_USBSTS_ULPII_MASK (0x400U)USB_USBSTS_ULPII_SHIFT (10U)USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)USB_USBSTS_HCH_MASK (0x1000U)USB_USBSTS_HCH_SHIFT (12U)USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)USB_USBSTS_RCL_MASK (0x2000U)USB_USBSTS_RCL_SHIFT (13U)USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)USB_USBSTS_PS_MASK (0x4000U)USB_USBSTS_PS_SHIFT (14U)USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)USB_USBSTS_AS_MASK (0x8000U)USB_USBSTS_AS_SHIFT (15U)USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)USB_USBSTS_NAKI_MASK (0x10000U)USB_USBSTS_NAKI_SHIFT (16U)USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)USB_USBSTS_TI0_MASK (0x1000000U)USB_USBSTS_TI0_SHIFT (24U)USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)USB_USBSTS_TI1_MASK (0x2000000U)USB_USBSTS_TI1_SHIFT (25U)USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)USB_USBINTR_UE_MASK (0x1U)USB_USBINTR_UE_SHIFT (0U)USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)USB_USBINTR_UEE_MASK (0x2U)USB_USBINTR_UEE_SHIFT (1U)USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)USB_USBINTR_PCE_MASK (0x4U)USB_USBINTR_PCE_SHIFT (2U)USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)USB_USBINTR_FRE_MASK (0x8U)USB_USBINTR_FRE_SHIFT (3U)USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)¯USB_USBINTR_SEE_MASK (0x10U)ïUSB_USBINTR_SEE_SHIFT (4U)įUSB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)ůUSB_USBINTR_AAE_MASK (0x20U)ƯUSB_USBINTR_AAE_SHIFT (5U)ǯUSB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)ȯUSB_USBINTR_URE_MASK (0x40U)ɯUSB_USBINTR_URE_SHIFT (6U)ʯUSB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)˯USB_USBINTR_SRE_MASK (0x80U)̯USB_USBINTR_SRE_SHIFT (7U)ͯUSB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)ίUSB_USBINTR_SLE_MASK (0x100U)ϯUSB_USBINTR_SLE_SHIFT (8U)ЯUSB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)ѯUSB_USBINTR_ULPIE_MASK (0x400U)үUSB_USBINTR_ULPIE_SHIFT (10U)ӯUSB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)ԯUSB_USBINTR_NAKE_MASK (0x10000U)կUSB_USBINTR_NAKE_SHIFT (16U)֯USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)ׯUSB_USBINTR_UAIE_MASK (0x40000U)دUSB_USBINTR_UAIE_SHIFT (18U)ٯUSB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)گUSB_USBINTR_UPIE_MASK (0x80000U)ۯUSB_USBINTR_UPIE_SHIFT (19U)ܯUSB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)ݯUSB_USBINTR_TIE0_MASK (0x1000000U)ޯUSB_USBINTR_TIE0_SHIFT (24U)߯USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)USB_USBINTR_TIE1_MASK (0x2000000U)USB_USBINTR_TIE1_SHIFT (25U)USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)USB_FRINDEX_FRINDEX_MASK (0x3FFFU)USB_FRINDEX_FRINDEX_SHIFT (0U)USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)USB_DEVICEADDR_USBADRA_MASK (0x1000000U)USB_DEVICEADDR_USBADRA_SHIFT (24U)USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)USB_DEVICEADDR_USBADR_MASK (0xFE000000U)USB_DEVICEADDR_USBADR_SHIFT (25U)USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)USB_BURSTSIZE_RXPBURST_MASK (0xFFU)USB_BURSTSIZE_RXPBURST_SHIFT (0U)USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)USB_BURSTSIZE_TXPBURST_SHIFT (8U)USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)USB_ENDPTNAK_EPRN_MASK (0xFFU)USB_ENDPTNAK_EPRN_SHIFT (0U)USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)USB_ENDPTNAK_EPTN_MASK (0xFF0000U)USB_ENDPTNAK_EPTN_SHIFT (16U)USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)USB_ENDPTNAKEN_EPRNE_SHIFT (0U)USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)USB_ENDPTNAKEN_EPTNE_SHIFT (16U)USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)USB_CONFIGFLAG_CF_MASK (0x1U)USB_CONFIGFLAG_CF_SHIFT (0U)USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)USB_PORTSC1_CCS_MASK (0x1U)USB_PORTSC1_CCS_SHIFT (0U)USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)USB_PORTSC1_CSC_MASK (0x2U)USB_PORTSC1_CSC_SHIFT (1U)USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)USB_PORTSC1_PE_MASK (0x4U)USB_PORTSC1_PE_SHIFT (2U)USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)USB_PORTSC1_PEC_MASK (0x8U)USB_PORTSC1_PEC_SHIFT (3U)USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)USB_PORTSC1_OCA_MASK (0x10U)USB_PORTSC1_OCA_SHIFT (4U)USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)USB_PORTSC1_OCC_MASK (0x20U)USB_PORTSC1_OCC_SHIFT (5U)USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)USB_PORTSC1_FPR_MASK (0x40U)USB_PORTSC1_FPR_SHIFT (6U)USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)USB_PORTSC1_SUSP_MASK (0x80U)USB_PORTSC1_SUSP_SHIFT (7U)USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)USB_PORTSC1_PR_MASK (0x100U)°USB_PORTSC1_PR_SHIFT (8U)ðUSB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)İUSB_PORTSC1_HSP_MASK (0x200U)ŰUSB_PORTSC1_HSP_SHIFT (9U)ưUSB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)ǰUSB_PORTSC1_LS_MASK (0xC00U)ȰUSB_PORTSC1_LS_SHIFT (10U)ɰUSB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)ʰUSB_PORTSC1_PP_MASK (0x1000U)˰USB_PORTSC1_PP_SHIFT (12U)̰USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)ͰUSB_PORTSC1_PO_MASK (0x2000U)ΰUSB_PORTSC1_PO_SHIFT (13U)ϰUSB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)аUSB_PORTSC1_PIC_MASK (0xC000U)ѰUSB_PORTSC1_PIC_SHIFT (14U)ҰUSB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)ӰUSB_PORTSC1_PTC_MASK (0xF0000U)԰USB_PORTSC1_PTC_SHIFT (16U)հUSB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)ְUSB_PORTSC1_WKCN_MASK (0x100000U)װUSB_PORTSC1_WKCN_SHIFT (20U)ذUSB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)ٰUSB_PORTSC1_WKDC_MASK (0x200000U)ڰUSB_PORTSC1_WKDC_SHIFT (21U)۰USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)ܰUSB_PORTSC1_WKOC_MASK (0x400000U)ݰUSB_PORTSC1_WKOC_SHIFT (22U)ްUSB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)߰USB_PORTSC1_PHCD_MASK (0x800000U)USB_PORTSC1_PHCD_SHIFT (23U)USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)USB_PORTSC1_PFSC_MASK (0x1000000U)USB_PORTSC1_PFSC_SHIFT (24U)USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)USB_PORTSC1_PTS_2_MASK (0x2000000U)USB_PORTSC1_PTS_2_SHIFT (25U)USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)USB_PORTSC1_PSPD_MASK (0xC000000U)USB_PORTSC1_PSPD_SHIFT (26U)USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)USB_PORTSC1_PTW_MASK (0x10000000U)USB_PORTSC1_PTW_SHIFT (28U)USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)USB_PORTSC1_STS_MASK (0x20000000U)USB_PORTSC1_STS_SHIFT (29U)USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)USB_PORTSC1_PTS_1_MASK (0xC0000000U)USB_PORTSC1_PTS_1_SHIFT (30U)USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)USB_OTGSC_VD_MASK (0x1U)USB_OTGSC_VD_SHIFT (0U)USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)USB_OTGSC_VC_MASK (0x2U)USB_OTGSC_VC_SHIFT (1U)USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)USB_OTGSC_OT_MASK (0x8U)USB_OTGSC_OT_SHIFT (3U)USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)USB_OTGSC_DP_MASK (0x10U)USB_OTGSC_DP_SHIFT (4U)USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)USB_OTGSC_IDPU_MASK (0x20U)USB_OTGSC_IDPU_SHIFT (5U)USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)USB_OTGSC_ID_MASK (0x100U)USB_OTGSC_ID_SHIFT (8U)USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)USB_OTGSC_AVV_MASK (0x200U)USB_OTGSC_AVV_SHIFT (9U)USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)USB_OTGSC_ASV_MASK (0x400U)USB_OTGSC_ASV_SHIFT (10U)USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)USB_OTGSC_BSV_MASK (0x800U)USB_OTGSC_BSV_SHIFT (11U)USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)USB_OTGSC_BSE_MASK (0x1000U)USB_OTGSC_BSE_SHIFT (12U)USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)USB_OTGSC_TOG_1MS_MASK (0x2000U)USB_OTGSC_TOG_1MS_SHIFT (13U)USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)USB_OTGSC_DPS_MASK (0x4000U)USB_OTGSC_DPS_SHIFT (14U)USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)USB_OTGSC_IDIS_MASK (0x10000U)USB_OTGSC_IDIS_SHIFT (16U)USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)USB_OTGSC_AVVIS_MASK (0x20000U)USB_OTGSC_AVVIS_SHIFT (17U)USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)USB_OTGSC_ASVIS_MASK (0x40000U)USB_OTGSC_ASVIS_SHIFT (18U)USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)USB_OTGSC_BSVIS_MASK (0x80000U)USB_OTGSC_BSVIS_SHIFT (19U)USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)USB_OTGSC_BSEIS_MASK (0x100000U)USB_OTGSC_BSEIS_SHIFT (20U)USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)USB_OTGSC_STATUS_1MS_MASK (0x200000U)USB_OTGSC_STATUS_1MS_SHIFT (21U)USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)USB_OTGSC_DPIS_MASK (0x400000U)USB_OTGSC_DPIS_SHIFT (22U)USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)USB_OTGSC_IDIE_MASK (0x1000000U)USB_OTGSC_IDIE_SHIFT (24U)USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)USB_OTGSC_AVVIE_MASK (0x2000000U)USB_OTGSC_AVVIE_SHIFT (25U)USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)USB_OTGSC_ASVIE_MASK (0x4000000U)USB_OTGSC_ASVIE_SHIFT (26U)USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)USB_OTGSC_BSVIE_MASK (0x8000000U)USB_OTGSC_BSVIE_SHIFT (27U)USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)USB_OTGSC_BSEIE_MASK (0x10000000U)USB_OTGSC_BSEIE_SHIFT (28U)USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)USB_OTGSC_EN_1MS_MASK (0x20000000U)USB_OTGSC_EN_1MS_SHIFT (29U)USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)USB_OTGSC_DPIE_MASK (0x40000000U)±USB_OTGSC_DPIE_SHIFT (30U)ñUSB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)ƱUSB_USBMODE_CM_MASK (0x3U)DZUSB_USBMODE_CM_SHIFT (0U)ȱUSB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)ɱUSB_USBMODE_ES_MASK (0x4U)ʱUSB_USBMODE_ES_SHIFT (2U)˱USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)̱USB_USBMODE_SLOM_MASK (0x8U)ͱUSB_USBMODE_SLOM_SHIFT (3U)αUSB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)ϱUSB_USBMODE_SDIS_MASK (0x10U)бUSB_USBMODE_SDIS_SHIFT (4U)ѱUSB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)ԱUSB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)ձUSB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)ֱUSB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)ٱUSB_ENDPTPRIME_PERB_MASK (0xFFU)ڱUSB_ENDPTPRIME_PERB_SHIFT (0U)۱USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)ܱUSB_ENDPTPRIME_PETB_MASK (0xFF0000U)ݱUSB_ENDPTPRIME_PETB_SHIFT (16U)ޱUSB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)USB_ENDPTFLUSH_FERB_MASK (0xFFU)USB_ENDPTFLUSH_FERB_SHIFT (0U)USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)USB_ENDPTFLUSH_FETB_SHIFT (16U)USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)USB_ENDPTSTAT_ERBR_MASK (0xFFU)USB_ENDPTSTAT_ERBR_SHIFT (0U)USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)USB_ENDPTSTAT_ETBR_SHIFT (16U)USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)USB_ENDPTCTRL0_RXS_MASK (0x1U)USB_ENDPTCTRL0_RXS_SHIFT (0U)USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)USB_ENDPTCTRL0_RXT_MASK (0xCU)USB_ENDPTCTRL0_RXT_SHIFT (2U)USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)USB_ENDPTCTRL0_RXE_MASK (0x80U)USB_ENDPTCTRL0_RXE_SHIFT (7U)USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)USB_ENDPTCTRL0_TXS_MASK (0x10000U)USB_ENDPTCTRL0_TXS_SHIFT (16U)USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)USB_ENDPTCTRL0_TXT_MASK (0xC0000U)USB_ENDPTCTRL0_TXT_SHIFT (18U)USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)USB_ENDPTCTRL0_TXE_MASK (0x800000U)USB_ENDPTCTRL0_TXE_SHIFT (23U)USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)USB_ENDPTCTRL_RXS_MASK (0x1U)USB_ENDPTCTRL_RXS_SHIFT (0U)USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)USB_ENDPTCTRL_RXD_MASK (0x2U)USB_ENDPTCTRL_RXD_SHIFT (1U)USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)USB_ENDPTCTRL_RXT_MASK (0xCU)USB_ENDPTCTRL_RXT_SHIFT (2U)USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)USB_ENDPTCTRL_RXI_MASK (0x20U)USB_ENDPTCTRL_RXI_SHIFT (5U)USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)USB_ENDPTCTRL_RXR_MASK (0x40U)USB_ENDPTCTRL_RXR_SHIFT (6U)USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)USB_ENDPTCTRL_RXE_MASK (0x80U)USB_ENDPTCTRL_RXE_SHIFT (7U)USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)USB_ENDPTCTRL_TXS_MASK (0x10000U)USB_ENDPTCTRL_TXS_SHIFT (16U)USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)USB_ENDPTCTRL_TXD_MASK (0x20000U)USB_ENDPTCTRL_TXD_SHIFT (17U)USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)USB_ENDPTCTRL_TXT_MASK (0xC0000U)USB_ENDPTCTRL_TXT_SHIFT (18U)USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)USB_ENDPTCTRL_TXI_MASK (0x200000U)USB_ENDPTCTRL_TXI_SHIFT (21U)USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)USB_ENDPTCTRL_TXR_MASK (0x400000U)USB_ENDPTCTRL_TXR_SHIFT (22U)USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)USB_ENDPTCTRL_TXE_MASK (0x800000U)USB_ENDPTCTRL_TXE_SHIFT (23U)USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)USB_ENDPTCTRL_COUNT (7U)USB1_BASE (0x402E0000u)USB1 ((USB_Type *)USB1_BASE)USB2_BASE (0x402E0200u)òUSB2 ((USB_Type *)USB2_BASE)ŲUSB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }DzUSB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }ɲUSB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }˲GPTIMER0CTL GPTIMER0CTRL̲GPTIMER1CTL GPTIMER1CTRLͲUSB_SBUSCFG SBUSCFGβEPLISTADDR ENDPTLISTADDRϲEPSETUPSR ENDPTSETUPSTATвEPPRIME ENDPTPRIMEѲEPFLUSH ENDPTFLUSHҲEPSR ENDPTSTATӲEPCOMPLETE ENDPTCOMPLETEԲEPCR ENDPTCTRLղEPCR0 ENDPTCTRL0ֲUSBHS_ID_ID_MASK USB_ID_ID_MASKײUSBHS_ID_ID_SHIFT USB_ID_ID_SHIFTزUSBHS_ID_ID(x) USB_ID_ID(x)ٲUSBHS_ID_NID_MASK USB_ID_NID_MASKڲUSBHS_ID_NID_SHIFT USB_ID_NID_SHIFT۲USBHS_ID_NID(x) USB_ID_NID(x)ܲUSBHS_ID_REVISION_MASK USB_ID_REVISION_MASKݲUSBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT޲USBHS_ID_REVISION(x) USB_ID_REVISION(x)߲USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASKUSBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFTUSBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASKUSBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFTUSBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASKUSBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFTUSBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASKUSBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFTUSBHS_HWHOST_HC(x) USB_HWHOST_HC(x)USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASKUSBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFTUSBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASKUSBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFTUSBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASKUSBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFTUSBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASKUSBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFTUSBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASKUSBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFTUSBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASKUSBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFTUSBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASKUSBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFTUSBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASKUSBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFTUSBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASKUSBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFTUSBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASKUSBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFTUSBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASKUSBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFTUSBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASKUSBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFTUSBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASKUSBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFTUSBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASKUSBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFTUSBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASKUSBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFTUSBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASKUSBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFTUSBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASKUSBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFTUSBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASKUSBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFTUSBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASKUSBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFTUSBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASKUSBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFTUSBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASKUSBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFTUSBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASKUSBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFTUSBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASKUSBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFTUSBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASKUSBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFTUSBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASKUSBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFTUSBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASKUSBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFTUSBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASKUSBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFTUSBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASKUSBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFTUSBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASKUSBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT³USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)óUSBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASKijUSBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFTųUSBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)ƳUSBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASKdzUSBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFTȳUSBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)ɳUSBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASKʳUSBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT˳USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)̳USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASKͳUSBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFTγUSBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)ϳUSBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASKгUSBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFTѳUSBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)ҳUSBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASKӳUSBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFTԳUSBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)ճUSBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASKֳUSBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT׳USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)سUSBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASKٳUSBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFTڳUSBHS_USBCMD_RST(x) USB_USBCMD_RST(x)۳USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASKܳUSBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFTݳUSBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)޳USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK߳USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFTUSBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASKUSBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFTUSBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASKUSBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFTUSBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASKUSBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFTUSBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASKUSBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFTUSBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASKUSBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFTUSBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASKUSBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFTUSBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASKUSBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFTUSBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASKUSBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFTUSBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASKUSBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFTUSBHS_USBSTS_UI(x) USB_USBSTS_UI(x)USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASKUSBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFTUSBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASKUSBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFTUSBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASKUSBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFTUSBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASKUSBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFTUSBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASKUSBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFTUSBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASKUSBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFTUSBHS_USBSTS_URI(x) USB_USBSTS_URI(x)USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASKUSBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFTUSBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASKUSBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFTUSBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASKUSBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFTUSBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASKUSBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFTUSBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASKUSBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFTUSBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASKUSBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFTUSBHS_USBSTS_PS(x) USB_USBSTS_PS(x)USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASKUSBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFTUSBHS_USBSTS_AS(x) USB_USBSTS_AS(x)USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASKUSBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFTUSBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASKUSBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFTUSBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASKUSBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFTUSBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASKUSBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFTUSBHS_USBINTR_UE(x) USB_USBINTR_UE(x)USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASKUSBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFTUSBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASKUSBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFTUSBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASKUSBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFTUSBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASKUSBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFTUSBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASKUSBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFTUSBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASKUSBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFTUSBHS_USBINTR_URE(x) USB_USBINTR_URE(x)USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK´USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFTôUSBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)ĴUSBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASKŴUSBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFTƴUSBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)ǴUSBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASKȴUSBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFTɴUSBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)ʴUSBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK˴USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT̴USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)ʹUSBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASKδUSBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFTϴUSBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)дUSBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASKѴUSBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFTҴUSBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)ӴUSBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASKԴUSBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFTմUSBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)ִUSBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK״USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFTشUSBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)ٴUSBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASKڴUSBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT۴USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)ܴUSBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASKݴUSBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT޴USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)ߴUSBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASKUSBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFTUSBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASKUSBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFTUSBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASKUSBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFTUSBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASKUSBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFTUSBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASKUSBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFTUSBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASKUSBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFTUSBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASKUSBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFTUSBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASKUSBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFTUSBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASKUSBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFTUSBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASKUSBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFTUSBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASKUSBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFTUSBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASKUSBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFTUSBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASKUSBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFTUSBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASKUSBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFTUSBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASKUSBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFTUSBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASKUSBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFTUSBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASKUSBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFTUSBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASKUSBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFTUSBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASKUSBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFTUSBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASKUSBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFTUSBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASKUSBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFTUSBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASKUSBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFTUSBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASKUSBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFTUSBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASKUSBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFTUSBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASKUSBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFTUSBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASKUSBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFTUSBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASKUSBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFTUSBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASKUSBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFTUSBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASKUSBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFTUSBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASKUSBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFTUSBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASKUSBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFTUSBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASKUSBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFTUSBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASKUSBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFTUSBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)µUSBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASKõUSBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFTĵUSBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)ŵUSBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASKƵUSBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFTǵUSBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)ȵUSBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASKɵUSBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFTʵUSBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)˵USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK̵USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT͵USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)εUSBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASKϵUSBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFTеUSBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)ѵUSBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASKҵUSBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFTӵUSBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)ԵUSBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASKյUSBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFTֵUSBHS_OTGSC_VD(x) USB_OTGSC_VD(x)׵USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASKصUSBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFTٵUSBHS_OTGSC_VC(x) USB_OTGSC_VC(x)ڵUSBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK۵USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFTܵUSBHS_OTGSC_OT(x) USB_OTGSC_OT(x)ݵUSBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK޵USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFTߵUSBHS_OTGSC_DP(x) USB_OTGSC_DP(x)USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASKUSBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFTUSBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASKUSBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFTUSBHS_OTGSC_ID(x) USB_OTGSC_ID(x)USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASKUSBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFTUSBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASKUSBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFTUSBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASKUSBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFTUSBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASKUSBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFTUSBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASKUSBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFTUSBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASKUSBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFTUSBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASKUSBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFTUSBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASKUSBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFTUSBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASKUSBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFTUSBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASKUSBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFTUSBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASKUSBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFTUSBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASKUSBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFTUSBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASKUSBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFTUSBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASKUSBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFTUSBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASKUSBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFTUSBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASKUSBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFTUSBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASKUSBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFTUSBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASKUSBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFTUSBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASKUSBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFTUSBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASKUSBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFTUSBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASKUSBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFTUSBHS_USBMODE_CM(x) USB_USBMODE_CM(x)USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASKUSBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFTUSBHS_USBMODE_ES(x) USB_USBMODE_ES(x)USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASKUSBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFTUSBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASKUSBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFTUSBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASKUSBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFTUSBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASKUSBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFTUSBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASKUSBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFTUSBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASKUSBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFTUSBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASKUSBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFTUSBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASKUSBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFTUSBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASKUSBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT¶USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)öUSBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASKĶUSBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFTŶUSBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)ƶUSBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASKǶUSBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFTȶUSBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)ɶUSBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASKʶUSBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT˶USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)̶USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASKͶUSBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFTζUSBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)϶USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASKжUSBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFTѶUSBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)ҶUSBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASKӶUSBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFTԶUSBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)նUSBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASKֶUSBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT׶USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)ضUSBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASKٶUSBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFTڶUSBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)۶USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASKܶUSBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFTݶUSBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)޶USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK߶USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFTUSBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASKUSBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFTUSBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASKUSBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFTUSBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASKUSBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFTUSBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASKUSBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFTUSBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASKUSBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFTUSBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASKUSBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFTUSBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASKUSBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFTUSBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASKUSBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFTUSBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASKUSBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFTUSBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASKUSBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFTUSBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNTUSBHS_Type USB_TypeUSBHS_BASE_ADDRS { USB1_BASE, USB2_BASE }USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }USBHS_IRQHandler USB_OTG1_IRQHandlerUSBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)·USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)÷USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)ƷUSBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)ǷUSBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)ȷUSBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)ҷUSBNC1_BASE (0x402E0000u)ԷUSBNC1 ((USBNC_Type *)USBNC1_BASE)ַUSBNC2_BASE (0x402E0004u)طUSBNC2 ((USBNC_Type *)USBNC2_BASE)ڷUSBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }ܷUSBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }USBPHY_PWD_RSVD0_MASK (0x3FFU)USBPHY_PWD_RSVD0_SHIFT (0U)USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)USBPHY_PWD_TXPWDFS_MASK (0x400U)USBPHY_PWD_TXPWDFS_SHIFT (10U)USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)USBPHY_PWD_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)USBPHY_PWD_RSVD1_MASK (0x1E000U)USBPHY_PWD_RSVD1_SHIFT (13U)USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)USBPHY_PWD_RXPWDENV_MASK (0x20000U)USBPHY_PWD_RXPWDENV_SHIFT (17U)USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)USBPHY_PWD_RXPWDRX_MASK (0x100000U)USBPHY_PWD_RXPWDRX_SHIFT (20U)USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)USBPHY_PWD_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_RSVD2_SHIFT (21U)USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)USBPHY_PWD_SET_RSVD0_SHIFT (0U)USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)¸USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)øUSBPHY_PWD_SET_RSVD1_MASK (0x1E000U)ĸUSBPHY_PWD_SET_RSVD1_SHIFT (13U)ŸUSBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)ƸUSBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)ǸUSBPHY_PWD_SET_RXPWDENV_SHIFT (17U)ȸUSBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)ɸUSBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)ʸUSBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)˸USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)̸USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)͸USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)θUSBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)ϸUSBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)иUSBPHY_PWD_SET_RXPWDRX_SHIFT (20U)ѸUSBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)ҸUSBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)ӸUSBPHY_PWD_SET_RSVD2_SHIFT (21U)ԸUSBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)׸USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)ظUSBPHY_PWD_CLR_RSVD0_SHIFT (0U)ٸUSBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)ڸUSBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)۸USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)ܸUSBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)ݸUSBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)޸USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)߸USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)USBPHY_PWD_CLR_RSVD1_SHIFT (13U)USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_CLR_RSVD2_SHIFT (21U)USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)USBPHY_PWD_TOG_RSVD0_SHIFT (0U)USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)USBPHY_PWD_TOG_RSVD1_SHIFT (13U)USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)USBPHY_PWD_TOG_RSVD2_SHIFT (21U)USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)USBPHY_TX_D_CAL_MASK (0xFU)USBPHY_TX_D_CAL_SHIFT (0U)USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)USBPHY_TX_RSVD0_MASK (0xF0U)USBPHY_TX_RSVD0_SHIFT (4U)USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)USBPHY_TX_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TXCAL45DN_SHIFT (8U)USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)USBPHY_TX_RSVD1_MASK (0xF000U)USBPHY_TX_RSVD1_SHIFT (12U)USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)USBPHY_TX_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TXCAL45DP_SHIFT (16U)USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)USBPHY_TX_RSVD2_MASK (0x3F00000U)USBPHY_TX_RSVD2_SHIFT (20U)USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_RSVD5_MASK (0xE0000000U)USBPHY_TX_RSVD5_SHIFT (29U)USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)USBPHY_TX_SET_D_CAL_MASK (0xFU)USBPHY_TX_SET_D_CAL_SHIFT (0U)USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)USBPHY_TX_SET_RSVD0_MASK (0xF0U)USBPHY_TX_SET_RSVD0_SHIFT (4U)USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)USBPHY_TX_SET_RSVD1_MASK (0xF000U)USBPHY_TX_SET_RSVD1_SHIFT (12U)USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)USBPHY_TX_SET_RSVD2_SHIFT (20U)¹USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)ùUSBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)ĹUSBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)ŹUSBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)ƹUSBPHY_TX_SET_RSVD5_MASK (0xE0000000U)ǹUSBPHY_TX_SET_RSVD5_SHIFT (29U)ȹUSBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)˹USBPHY_TX_CLR_D_CAL_MASK (0xFU)̹USBPHY_TX_CLR_D_CAL_SHIFT (0U)͹USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)ιUSBPHY_TX_CLR_RSVD0_MASK (0xF0U)ϹUSBPHY_TX_CLR_RSVD0_SHIFT (4U)йUSBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)ѹUSBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)ҹUSBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)ӹUSBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)ԹUSBPHY_TX_CLR_RSVD1_MASK (0xF000U)չUSBPHY_TX_CLR_RSVD1_SHIFT (12U)ֹUSBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)׹USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)عUSBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)ٹUSBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)ڹUSBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)۹USBPHY_TX_CLR_RSVD2_SHIFT (20U)ܹUSBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)ݹUSBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)޹USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)߹USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)USBPHY_TX_CLR_RSVD5_SHIFT (29U)USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)USBPHY_TX_TOG_D_CAL_MASK (0xFU)USBPHY_TX_TOG_D_CAL_SHIFT (0U)USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)USBPHY_TX_TOG_RSVD0_MASK (0xF0U)USBPHY_TX_TOG_RSVD0_SHIFT (4U)USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)USBPHY_TX_TOG_RSVD1_MASK (0xF000U)USBPHY_TX_TOG_RSVD1_SHIFT (12U)USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)USBPHY_TX_TOG_RSVD2_SHIFT (20U)USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)USBPHY_TX_TOG_RSVD5_SHIFT (29U)USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)USBPHY_RX_ENVADJ_MASK (0x7U)USBPHY_RX_ENVADJ_SHIFT (0U)USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)USBPHY_RX_RSVD0_MASK (0x8U)USBPHY_RX_RSVD0_SHIFT (3U)USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)USBPHY_RX_DISCONADJ_MASK (0x70U)USBPHY_RX_DISCONADJ_SHIFT (4U)USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)USBPHY_RX_RSVD1_MASK (0x3FFF80U)USBPHY_RX_RSVD1_SHIFT (7U)USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)USBPHY_RX_RXDBYPASS_MASK (0x400000U)USBPHY_RX_RXDBYPASS_SHIFT (22U)USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)USBPHY_RX_RSVD2_MASK (0xFF800000U)USBPHY_RX_RSVD2_SHIFT (23U)USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)USBPHY_RX_SET_ENVADJ_MASK (0x7U)USBPHY_RX_SET_ENVADJ_SHIFT (0U)USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)USBPHY_RX_SET_RSVD0_MASK (0x8U)USBPHY_RX_SET_RSVD0_SHIFT (3U)USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)USBPHY_RX_SET_DISCONADJ_MASK (0x70U)USBPHY_RX_SET_DISCONADJ_SHIFT (4U)USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)USBPHY_RX_SET_RSVD1_SHIFT (7U)USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)USBPHY_RX_SET_RSVD2_SHIFT (23U)USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)USBPHY_RX_CLR_ENVADJ_MASK (0x7U)USBPHY_RX_CLR_ENVADJ_SHIFT (0U)USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)USBPHY_RX_CLR_RSVD0_MASK (0x8U)USBPHY_RX_CLR_RSVD0_SHIFT (3U)USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)USBPHY_RX_CLR_RSVD1_SHIFT (7U)USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)USBPHY_RX_CLR_RSVD2_SHIFT (23U)USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)USBPHY_RX_TOG_ENVADJ_MASK (0x7U)USBPHY_RX_TOG_ENVADJ_SHIFT (0U)USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)USBPHY_RX_TOG_RSVD0_MASK (0x8U)USBPHY_RX_TOG_RSVD0_SHIFT (3U)USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)ºUSBPHY_RX_TOG_DISCONADJ_SHIFT (4U)úUSBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)ĺUSBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)źUSBPHY_RX_TOG_RSVD1_SHIFT (7U)ƺUSBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)ǺUSBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)ȺUSBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)ɺUSBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)ʺUSBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)˺USBPHY_RX_TOG_RSVD2_SHIFT (23U)̺USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)ϺUSBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)кUSBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)ѺUSBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)ҺUSBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)ӺUSBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)ԺUSBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)պUSBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)ֺUSBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)׺USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)غUSBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)ٺUSBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)ںUSBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)ۺUSBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)ܺUSBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)ݺUSBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)޺USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)ߺUSBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)USBPHY_CTRL_RSVD1_MASK (0x6000000U)USBPHY_CTRL_RSVD1_SHIFT (25U)USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)USBPHY_CTRL_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SFTRST_SHIFT (31U)USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)»USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)ûUSBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)ĻUSBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)ŻUSBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)ƻUSBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)ǻUSBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)ȻUSBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)ɻUSBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)ʻUSBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)˻USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)̻USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)ͻUSBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)λUSBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)ϻUSBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)лUSBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)ѻUSBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)һUSBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)ӻUSBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)ԻUSBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)ջUSBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)ֻUSBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)׻USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)ػUSBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)ٻUSBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)ڻUSBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)ۻUSBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)ܻUSBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)ݻUSBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)޻USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)߻USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)USBPHY_CTRL_SET_RSVD1_SHIFT (25U)USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)USBPHY_CTRL_SET_SFTRST_SHIFT (31U)USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)¼USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)üUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)ļUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)żUSBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)ƼUSBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)ǼUSBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)ȼUSBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)ɼUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)ʼUSBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)˼USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)̼USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)ͼUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)μUSBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)ϼUSBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)мUSBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)ѼUSBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)ҼUSBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)ӼUSBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)ԼUSBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)ռUSBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)ּUSBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)׼USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)ؼUSBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)ټUSBPHY_CTRL_CLR_RSVD1_SHIFT (25U)ڼUSBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)ۼUSBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)ܼUSBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)ݼUSBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)޼USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)߼USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)½USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)ýUSBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)ĽUSBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)ŽUSBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)ƽUSBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)ǽUSBPHY_CTRL_TOG_SFTRST_SHIFT (31U)ȽUSBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)˽USBPHY_STATUS_RSVD0_MASK (0x7U)̽USBPHY_STATUS_RSVD0_SHIFT (0U)ͽUSBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)νUSBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)ϽUSBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)нUSBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)ѽUSBPHY_STATUS_RSVD1_MASK (0x30U)ҽUSBPHY_STATUS_RSVD1_SHIFT (4U)ӽUSBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)ԽUSBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)սUSBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)ֽUSBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)׽USBPHY_STATUS_RSVD2_MASK (0x80U)ؽUSBPHY_STATUS_RSVD2_SHIFT (7U)ٽUSBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)ڽUSBPHY_STATUS_OTGID_STATUS_MASK (0x100U)۽USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)ܽUSBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)ݽUSBPHY_STATUS_RSVD3_MASK (0x200U)޽USBPHY_STATUS_RSVD3_SHIFT (9U)߽USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)USBPHY_STATUS_RSVD4_SHIFT (11U)USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_RSVD0_SHIFT (6U)USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_RSVD1_SHIFT (13U)USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_RSVD2_SHIFT (21U)USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)USBPHY_DEBUG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_RSVD3_SHIFT (31U)USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)¾USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)þUSBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)ƾUSBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)ǾUSBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)ȾUSBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)ɾUSBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)ʾUSBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)˾USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)̾USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU);USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)ξUSBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)ϾUSBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)оUSBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)ѾUSBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)ҾUSBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)ӾUSBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)ԾUSBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)վUSBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)־USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)׾USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)ؾUSBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)پUSBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)ھUSBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)۾USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)ܾUSBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)ݾUSBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)޾USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)߾USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_RSVD0_SHIFT (0U)USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_RSVD1_SHIFT (15U)USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)¿USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)ſUSBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)ƿUSBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)ǿUSBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)ȿUSBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)ɿUSBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)ʿUSBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)˿USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)̿USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)ͿUSBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)пUSBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)ѿUSBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)ҿUSBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)ӿUSBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)ԿUSBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)տUSBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)ֿUSBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)׿USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)ؿUSBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)ۿUSBPHY_VERSION_STEP_MASK (0xFFFFU)ܿUSBPHY_VERSION_STEP_SHIFT (0U)ݿUSBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)޿USBPHY_VERSION_MINOR_MASK (0xFF0000U)߿USBPHY_VERSION_MINOR_SHIFT (16U)USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)USBPHY_VERSION_MAJOR_MASK (0xFF000000U)USBPHY_VERSION_MAJOR_SHIFT (24U)USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)USBPHY1_BASE (0x400D9000u)USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)USBPHY2_BASE (0x400DA000u)USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASKUSBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFTUSBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASKUSBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFTUSBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_COUNT (2U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)USB_ANALOG_CHRG_DETECT_COUNT (2U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_COUNT (2U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_SET_COUNT (2U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_CLR_COUNT (2U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)USB_ANALOG_MISC_TOG_COUNT (2U)USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU)USB_ANALOG_DIGPROG_MINOR_SHIFT (0U)USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK)USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U)USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U)USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK)USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U)USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U)USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK)USB_ANALOG_BASE (0x400D8000u)USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }USB_ANALOG_BASE_PTRS { USB_ANALOG }USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)USDHC_BLK_ATT_BLKCNT_SHIFT (16U)USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)USDHC_CMD_ARG_CMDARG_SHIFT (0U)USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)USDHC_PRES_STATE_CIHB_MASK (0x1U)USDHC_PRES_STATE_CIHB_SHIFT (0U)USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)USDHC_PRES_STATE_CDIHB_MASK (0x2U)USDHC_PRES_STATE_CDIHB_SHIFT (1U)USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)USDHC_PRES_STATE_DLA_MASK (0x4U)USDHC_PRES_STATE_DLA_SHIFT (2U)USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)USDHC_PRES_STATE_SDSTB_MASK (0x8U)USDHC_PRES_STATE_SDSTB_SHIFT (3U)USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)USDHC_PRES_STATE_IPGOFF_MASK (0x10U)USDHC_PRES_STATE_IPGOFF_SHIFT (4U)USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)USDHC_PRES_STATE_HCKOFF_MASK (0x20U)USDHC_PRES_STATE_HCKOFF_SHIFT (5U)USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)USDHC_PRES_STATE_PEROFF_MASK (0x40U)USDHC_PRES_STATE_PEROFF_SHIFT (6U)USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)USDHC_PRES_STATE_SDOFF_MASK (0x80U)USDHC_PRES_STATE_SDOFF_SHIFT (7U)USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)USDHC_PRES_STATE_WTA_MASK (0x100U)USDHC_PRES_STATE_WTA_SHIFT (8U)USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)USDHC_PRES_STATE_RTA_MASK (0x200U)USDHC_PRES_STATE_RTA_SHIFT (9U)USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)USDHC_PRES_STATE_BWEN_MASK (0x400U)USDHC_PRES_STATE_BWEN_SHIFT (10U)USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)USDHC_PRES_STATE_BREN_MASK (0x800U)USDHC_PRES_STATE_BREN_SHIFT (11U)USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)USDHC_PRES_STATE_RTR_MASK (0x1000U)USDHC_PRES_STATE_RTR_SHIFT (12U)USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)USDHC_PRES_STATE_TSCD_MASK (0x8000U)USDHC_PRES_STATE_TSCD_SHIFT (15U)USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)USDHC_PRES_STATE_CINST_MASK (0x10000U)USDHC_PRES_STATE_CINST_SHIFT (16U)USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)USDHC_PRES_STATE_CDPL_MASK (0x40000U)USDHC_PRES_STATE_CDPL_SHIFT (18U)USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)USDHC_PRES_STATE_WPSPL_MASK (0x80000U)USDHC_PRES_STATE_WPSPL_SHIFT (19U)USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)USDHC_PRES_STATE_CLSL_MASK (0x800000U)USDHC_PRES_STATE_CLSL_SHIFT (23U)USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)USDHC_PRES_STATE_DLSL_SHIFT (24U)USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)USDHC_PROT_CTRL_LCTL_MASK (0x1U)USDHC_PROT_CTRL_LCTL_SHIFT (0U)USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)USDHC_PROT_CTRL_DTW_MASK (0x6U)USDHC_PROT_CTRL_DTW_SHIFT (1U)USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)USDHC_PROT_CTRL_D3CD_MASK (0x8U)USDHC_PROT_CTRL_D3CD_SHIFT (3U)USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)USDHC_PROT_CTRL_EMODE_MASK (0x30U)USDHC_PROT_CTRL_EMODE_SHIFT (4U)USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)USDHC_PROT_CTRL_CDTL_MASK (0x40U)USDHC_PROT_CTRL_CDTL_SHIFT (6U)USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)USDHC_PROT_CTRL_CDSS_MASK (0x80U)USDHC_PROT_CTRL_CDSS_SHIFT (7U)USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)USDHC_PROT_CTRL_DMASEL_MASK (0x300U)USDHC_PROT_CTRL_DMASEL_SHIFT (8U)USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)USDHC_PROT_CTRL_CREQ_MASK (0x20000U)USDHC_PROT_CTRL_CREQ_SHIFT (17U)USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)USDHC_PROT_CTRL_RWCTL_SHIFT (18U)USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)USDHC_PROT_CTRL_IABG_MASK (0x80000U)USDHC_PROT_CTRL_IABG_SHIFT (19U)USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)USDHC_PROT_CTRL_WECINT_SHIFT (24U)USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)USDHC_PROT_CTRL_WECINS_SHIFT (25U)USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)USDHC_PROT_CTRL_WECRM_SHIFT (26U)USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)USDHC_SYS_CTRL_DVS_MASK (0xF0U)USDHC_SYS_CTRL_DVS_SHIFT (4U)USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)USDHC_SYS_CTRL_DTOCV_SHIFT (16U)USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)USDHC_SYS_CTRL_RSTA_SHIFT (24U)USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)USDHC_SYS_CTRL_RSTC_SHIFT (25U)USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)USDHC_SYS_CTRL_RSTD_SHIFT (26U)USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)USDHC_SYS_CTRL_INITA_MASK (0x8000000U)USDHC_SYS_CTRL_INITA_SHIFT (27U)USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)USDHC_SYS_CTRL_RSTT_SHIFT (28U)USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)USDHC_INT_STATUS_CC_MASK (0x1U)USDHC_INT_STATUS_CC_SHIFT (0U)USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)USDHC_INT_STATUS_TC_MASK (0x2U)USDHC_INT_STATUS_TC_SHIFT (1U)USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)USDHC_INT_STATUS_BGE_MASK (0x4U)USDHC_INT_STATUS_BGE_SHIFT (2U)USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)USDHC_INT_STATUS_DINT_MASK (0x8U)USDHC_INT_STATUS_DINT_SHIFT (3U)USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)USDHC_INT_STATUS_BWR_MASK (0x10U)USDHC_INT_STATUS_BWR_SHIFT (4U)USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)USDHC_INT_STATUS_BRR_MASK (0x20U)USDHC_INT_STATUS_BRR_SHIFT (5U)USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)USDHC_INT_STATUS_CINS_MASK (0x40U)USDHC_INT_STATUS_CINS_SHIFT (6U)USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)USDHC_INT_STATUS_CRM_MASK (0x80U)USDHC_INT_STATUS_CRM_SHIFT (7U)USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)USDHC_INT_STATUS_CINT_MASK (0x100U)USDHC_INT_STATUS_CINT_SHIFT (8U)USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)USDHC_INT_STATUS_RTE_MASK (0x1000U)USDHC_INT_STATUS_RTE_SHIFT (12U)USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)USDHC_INT_STATUS_TP_MASK (0x4000U)USDHC_INT_STATUS_TP_SHIFT (14U)USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)USDHC_INT_STATUS_CTOE_MASK (0x10000U)USDHC_INT_STATUS_CTOE_SHIFT (16U)USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)USDHC_INT_STATUS_CCE_MASK (0x20000U)USDHC_INT_STATUS_CCE_SHIFT (17U)USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)USDHC_INT_STATUS_CEBE_MASK (0x40000U)USDHC_INT_STATUS_CEBE_SHIFT (18U)USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)USDHC_INT_STATUS_CIE_MASK (0x80000U)USDHC_INT_STATUS_CIE_SHIFT (19U)USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)USDHC_INT_STATUS_DTOE_MASK (0x100000U)USDHC_INT_STATUS_DTOE_SHIFT (20U)USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)USDHC_INT_STATUS_DCE_MASK (0x200000U)USDHC_INT_STATUS_DCE_SHIFT (21U)USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)USDHC_INT_STATUS_DEBE_MASK (0x400000U)USDHC_INT_STATUS_DEBE_SHIFT (22U)USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)USDHC_INT_STATUS_AC12E_MASK (0x1000000U)USDHC_INT_STATUS_AC12E_SHIFT (24U)USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)USDHC_INT_STATUS_TNE_MASK (0x4000000U)USDHC_INT_STATUS_TNE_SHIFT (26U)USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)USDHC_INT_STATUS_DMAE_MASK (0x10000000U)USDHC_INT_STATUS_DMAE_SHIFT (28U)USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)USDHC_WTMK_LVL_RD_WML_SHIFT (0U)USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)USDHC_WTMK_LVL_WR_WML_SHIFT (16U)USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)USDHC_MIX_CTRL_DMAEN_MASK (0x1U)USDHC_MIX_CTRL_DMAEN_SHIFT (0U)USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)USDHC_MIX_CTRL_BCEN_MASK (0x2U)USDHC_MIX_CTRL_BCEN_SHIFT (1U)USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)USDHC_MIX_CTRL_AC12EN_MASK (0x4U)USDHC_MIX_CTRL_AC12EN_SHIFT (2U)USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)USDHC_MIX_CTRL_AC23EN_MASK (0x80U)USDHC_MIX_CTRL_AC23EN_SHIFT (7U)USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)USDHC_VEND_SPEC_VSELECT_MASK (0x2U)USDHC_VEND_SPEC_VSELECT_SHIFT (1U)USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U)USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U)USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK)USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)USDHC1_BASE (0x402C0000u)USDHC1 ((USDHC_Type *)USDHC1_BASE)USDHC2_BASE (0x402C4000u)USDHC2 ((USDHC_Type *)USDHC2_BASE)USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }WDOG_WCR_WDZST_MASK (0x1U)WDOG_WCR_WDZST_SHIFT (0U)WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)WDOG_WCR_WDBG_MASK (0x2U)WDOG_WCR_WDBG_SHIFT (1U)WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)WDOG_WCR_WDE_MASK (0x4U)WDOG_WCR_WDE_SHIFT (2U)WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)WDOG_WCR_WDT_MASK (0x8U)WDOG_WCR_WDT_SHIFT (3U)WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)WDOG_WCR_SRS_MASK (0x10U)WDOG_WCR_SRS_SHIFT (4U)WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)WDOG_WCR_WDA_MASK (0x20U)WDOG_WCR_WDA_SHIFT (5U)WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)WDOG_WCR_SRE_MASK (0x40U)WDOG_WCR_SRE_SHIFT (6U)WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)WDOG_WCR_WDW_MASK (0x80U)WDOG_WCR_WDW_SHIFT (7U)WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)WDOG_WCR_WT_MASK (0xFF00U)WDOG_WCR_WT_SHIFT (8U)WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)WDOG_WSR_WSR_MASK (0xFFFFU)WDOG_WSR_WSR_SHIFT (0U)WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)WDOG_WRSR_SFTW_MASK (0x1U)WDOG_WRSR_SFTW_SHIFT (0U)WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)WDOG_WRSR_TOUT_MASK (0x2U)WDOG_WRSR_TOUT_SHIFT (1U)WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)WDOG_WRSR_POR_MASK (0x10U)WDOG_WRSR_POR_SHIFT (4U)WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)WDOG_WICR_WICT_MASK (0xFFU)WDOG_WICR_WICT_SHIFT (0U)WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)WDOG_WICR_WTIS_MASK (0x4000U)WDOG_WICR_WTIS_SHIFT (14U)WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)WDOG_WICR_WIE_MASK (0x8000U)WDOG_WICR_WIE_SHIFT (15U)WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)WDOG_WMCR_PDE_MASK (0x1U)WDOG_WMCR_PDE_SHIFT (0U)WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)WDOG1_BASE (0x400B8000u)WDOG1 ((WDOG_Type *)WDOG1_BASE)WDOG2_BASE (0x400D0000u)WDOG2 ((WDOG_Type *)WDOG2_BASE)WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }XBARA_SEL0_SEL0_MASK (0x7FU)XBARA_SEL0_SEL0_SHIFT (0U)XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)XBARA_SEL0_SEL1_MASK (0x7F00U)XBARA_SEL0_SEL1_SHIFT (8U)XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)XBARA_SEL1_SEL2_MASK (0x7FU)XBARA_SEL1_SEL2_SHIFT (0U)XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)XBARA_SEL1_SEL3_MASK (0x7F00U)XBARA_SEL1_SEL3_SHIFT (8U)XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)XBARA_SEL2_SEL4_MASK (0x7FU)XBARA_SEL2_SEL4_SHIFT (0U)XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)XBARA_SEL2_SEL5_MASK (0x7F00U)XBARA_SEL2_SEL5_SHIFT (8U)XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)XBARA_SEL3_SEL6_MASK (0x7FU)XBARA_SEL3_SEL6_SHIFT (0U)XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)XBARA_SEL3_SEL7_MASK (0x7F00U)XBARA_SEL3_SEL7_SHIFT (8U)XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)XBARA_SEL4_SEL8_MASK (0x7FU)XBARA_SEL4_SEL8_SHIFT (0U)XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)XBARA_SEL4_SEL9_MASK (0x7F00U)XBARA_SEL4_SEL9_SHIFT (8U)XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)XBARA_SEL5_SEL10_MASK (0x7FU)XBARA_SEL5_SEL10_SHIFT (0U)XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)XBARA_SEL5_SEL11_MASK (0x7F00U)XBARA_SEL5_SEL11_SHIFT (8U)XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)XBARA_SEL6_SEL12_MASK (0x7FU)XBARA_SEL6_SEL12_SHIFT (0U)XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)XBARA_SEL6_SEL13_MASK (0x7F00U)XBARA_SEL6_SEL13_SHIFT (8U)XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)XBARA_SEL7_SEL14_MASK (0x7FU)XBARA_SEL7_SEL14_SHIFT (0U)XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)XBARA_SEL7_SEL15_MASK (0x7F00U)XBARA_SEL7_SEL15_SHIFT (8U)XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)XBARA_SEL8_SEL16_MASK (0x7FU)XBARA_SEL8_SEL16_SHIFT (0U)XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)XBARA_SEL8_SEL17_MASK (0x7F00U)XBARA_SEL8_SEL17_SHIFT (8U)XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)XBARA_SEL9_SEL18_MASK (0x7FU)XBARA_SEL9_SEL18_SHIFT (0U)XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)XBARA_SEL9_SEL19_MASK (0x7F00U)XBARA_SEL9_SEL19_SHIFT (8U)XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)XBARA_SEL10_SEL20_MASK (0x7FU)XBARA_SEL10_SEL20_SHIFT (0U)XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)XBARA_SEL10_SEL21_MASK (0x7F00U)XBARA_SEL10_SEL21_SHIFT (8U)XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)XBARA_SEL11_SEL22_MASK (0x7FU)XBARA_SEL11_SEL22_SHIFT (0U)XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)XBARA_SEL11_SEL23_MASK (0x7F00U)XBARA_SEL11_SEL23_SHIFT (8U)XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)XBARA_SEL12_SEL24_MASK (0x7FU)XBARA_SEL12_SEL24_SHIFT (0U)XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)XBARA_SEL12_SEL25_MASK (0x7F00U)XBARA_SEL12_SEL25_SHIFT (8U)XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)XBARA_SEL13_SEL26_MASK (0x7FU)XBARA_SEL13_SEL26_SHIFT (0U)XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)XBARA_SEL13_SEL27_MASK (0x7F00U)XBARA_SEL13_SEL27_SHIFT (8U)XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)XBARA_SEL14_SEL28_MASK (0x7FU)XBARA_SEL14_SEL28_SHIFT (0U)XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)XBARA_SEL14_SEL29_MASK (0x7F00U)XBARA_SEL14_SEL29_SHIFT (8U)XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)XBARA_SEL15_SEL30_MASK (0x7FU)XBARA_SEL15_SEL30_SHIFT (0U)XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)XBARA_SEL15_SEL31_MASK (0x7F00U)XBARA_SEL15_SEL31_SHIFT (8U)XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)XBARA_SEL16_SEL32_MASK (0x7FU)XBARA_SEL16_SEL32_SHIFT (0U)XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)XBARA_SEL16_SEL33_MASK (0x7F00U)XBARA_SEL16_SEL33_SHIFT (8U)XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)XBARA_SEL17_SEL34_MASK (0x7FU)XBARA_SEL17_SEL34_SHIFT (0U)XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)XBARA_SEL17_SEL35_MASK (0x7F00U)XBARA_SEL17_SEL35_SHIFT (8U)XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)XBARA_SEL18_SEL36_MASK (0x7FU)XBARA_SEL18_SEL36_SHIFT (0U)XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)XBARA_SEL18_SEL37_MASK (0x7F00U)XBARA_SEL18_SEL37_SHIFT (8U)XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)XBARA_SEL19_SEL38_MASK (0x7FU)XBARA_SEL19_SEL38_SHIFT (0U)XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)XBARA_SEL19_SEL39_MASK (0x7F00U)XBARA_SEL19_SEL39_SHIFT (8U)XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)XBARA_SEL20_SEL40_MASK (0x7FU)XBARA_SEL20_SEL40_SHIFT (0U)XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)XBARA_SEL20_SEL41_MASK (0x7F00U)XBARA_SEL20_SEL41_SHIFT (8U)XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)XBARA_SEL21_SEL42_MASK (0x7FU)XBARA_SEL21_SEL42_SHIFT (0U)XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)XBARA_SEL21_SEL43_MASK (0x7F00U)XBARA_SEL21_SEL43_SHIFT (8U)XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)XBARA_SEL22_SEL44_MASK (0x7FU)XBARA_SEL22_SEL44_SHIFT (0U)XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)XBARA_SEL22_SEL45_MASK (0x7F00U)XBARA_SEL22_SEL45_SHIFT (8U)XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)XBARA_SEL23_SEL46_MASK (0x7FU)XBARA_SEL23_SEL46_SHIFT (0U)XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)XBARA_SEL23_SEL47_MASK (0x7F00U)XBARA_SEL23_SEL47_SHIFT (8U)XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)XBARA_SEL24_SEL48_MASK (0x7FU)XBARA_SEL24_SEL48_SHIFT (0U)XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)XBARA_SEL24_SEL49_MASK (0x7F00U)XBARA_SEL24_SEL49_SHIFT (8U)XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)XBARA_SEL25_SEL50_MASK (0x7FU)XBARA_SEL25_SEL50_SHIFT (0U)XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)XBARA_SEL25_SEL51_MASK (0x7F00U)XBARA_SEL25_SEL51_SHIFT (8U)XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)XBARA_SEL26_SEL52_MASK (0x7FU)XBARA_SEL26_SEL52_SHIFT (0U)XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)XBARA_SEL26_SEL53_MASK (0x7F00U)XBARA_SEL26_SEL53_SHIFT (8U)XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)XBARA_SEL27_SEL54_MASK (0x7FU)XBARA_SEL27_SEL54_SHIFT (0U)XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)XBARA_SEL27_SEL55_MASK (0x7F00U)XBARA_SEL27_SEL55_SHIFT (8U)XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)XBARA_SEL28_SEL56_MASK (0x7FU)XBARA_SEL28_SEL56_SHIFT (0U)XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)XBARA_SEL28_SEL57_MASK (0x7F00U)XBARA_SEL28_SEL57_SHIFT (8U)XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)XBARA_SEL29_SEL58_MASK (0x7FU)XBARA_SEL29_SEL58_SHIFT (0U)XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)XBARA_SEL29_SEL59_MASK (0x7F00U)XBARA_SEL29_SEL59_SHIFT (8U)XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)XBARA_SEL30_SEL60_MASK (0x7FU)XBARA_SEL30_SEL60_SHIFT (0U)XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)XBARA_SEL30_SEL61_MASK (0x7F00U)XBARA_SEL30_SEL61_SHIFT (8U)XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)XBARA_SEL31_SEL62_MASK (0x7FU)XBARA_SEL31_SEL62_SHIFT (0U)XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)XBARA_SEL31_SEL63_MASK (0x7F00U)XBARA_SEL31_SEL63_SHIFT (8U)XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)XBARA_SEL32_SEL64_MASK (0x7FU)XBARA_SEL32_SEL64_SHIFT (0U)XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)XBARA_SEL32_SEL65_MASK (0x7F00U)XBARA_SEL32_SEL65_SHIFT (8U)XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)XBARA_SEL33_SEL66_MASK (0x7FU)XBARA_SEL33_SEL66_SHIFT (0U)XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)XBARA_SEL33_SEL67_MASK (0x7F00U)XBARA_SEL33_SEL67_SHIFT (8U)XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)XBARA_SEL34_SEL68_MASK (0x7FU)XBARA_SEL34_SEL68_SHIFT (0U)XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)XBARA_SEL34_SEL69_MASK (0x7F00U)XBARA_SEL34_SEL69_SHIFT (8U)XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)XBARA_SEL35_SEL70_MASK (0x7FU)XBARA_SEL35_SEL70_SHIFT (0U)XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)XBARA_SEL35_SEL71_MASK (0x7F00U)XBARA_SEL35_SEL71_SHIFT (8U)XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)XBARA_SEL36_SEL72_MASK (0x7FU)XBARA_SEL36_SEL72_SHIFT (0U)XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)XBARA_SEL36_SEL73_MASK (0x7F00U)XBARA_SEL36_SEL73_SHIFT (8U)XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)XBARA_SEL37_SEL74_MASK (0x7FU)XBARA_SEL37_SEL74_SHIFT (0U)XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)XBARA_SEL37_SEL75_MASK (0x7F00U)XBARA_SEL37_SEL75_SHIFT (8U)XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)XBARA_SEL38_SEL76_MASK (0x7FU)XBARA_SEL38_SEL76_SHIFT (0U)XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)XBARA_SEL38_SEL77_MASK (0x7F00U)XBARA_SEL38_SEL77_SHIFT (8U)XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)XBARA_SEL39_SEL78_MASK (0x7FU)XBARA_SEL39_SEL78_SHIFT (0U)XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)XBARA_SEL39_SEL79_MASK (0x7F00U)XBARA_SEL39_SEL79_SHIFT (8U)XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)XBARA_SEL40_SEL80_MASK (0x7FU)XBARA_SEL40_SEL80_SHIFT (0U)XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)XBARA_SEL40_SEL81_MASK (0x7F00U)XBARA_SEL40_SEL81_SHIFT (8U)XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)XBARA_SEL41_SEL82_MASK (0x7FU)XBARA_SEL41_SEL82_SHIFT (0U)XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)XBARA_SEL41_SEL83_MASK (0x7F00U)XBARA_SEL41_SEL83_SHIFT (8U)XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)XBARA_SEL42_SEL84_MASK (0x7FU)XBARA_SEL42_SEL84_SHIFT (0U)XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)XBARA_SEL42_SEL85_MASK (0x7F00U)XBARA_SEL42_SEL85_SHIFT (8U)XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)XBARA_SEL43_SEL86_MASK (0x7FU)XBARA_SEL43_SEL86_SHIFT (0U)XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)XBARA_SEL43_SEL87_MASK (0x7F00U)XBARA_SEL43_SEL87_SHIFT (8U)XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)XBARA_SEL44_SEL88_MASK (0x7FU)XBARA_SEL44_SEL88_SHIFT (0U)XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)XBARA_SEL44_SEL89_MASK (0x7F00U)XBARA_SEL44_SEL89_SHIFT (8U)XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)XBARA_SEL45_SEL90_MASK (0x7FU)XBARA_SEL45_SEL90_SHIFT (0U)XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)XBARA_SEL45_SEL91_MASK (0x7F00U)XBARA_SEL45_SEL91_SHIFT (8U)XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)XBARA_SEL46_SEL92_MASK (0x7FU)XBARA_SEL46_SEL92_SHIFT (0U)XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)XBARA_SEL46_SEL93_MASK (0x7F00U)XBARA_SEL46_SEL93_SHIFT (8U)XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)XBARA_SEL47_SEL94_MASK (0x7FU)XBARA_SEL47_SEL94_SHIFT (0U)XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)XBARA_SEL47_SEL95_MASK (0x7F00U)XBARA_SEL47_SEL95_SHIFT (8U)XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)XBARA_SEL48_SEL96_MASK (0x7FU)XBARA_SEL48_SEL96_SHIFT (0U)XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)XBARA_SEL48_SEL97_MASK (0x7F00U)XBARA_SEL48_SEL97_SHIFT (8U)XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)XBARA_SEL49_SEL98_MASK (0x7FU)XBARA_SEL49_SEL98_SHIFT (0U)XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)XBARA_SEL49_SEL99_MASK (0x7F00U)XBARA_SEL49_SEL99_SHIFT (8U)XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)XBARA_SEL50_SEL100_MASK (0x7FU)XBARA_SEL50_SEL100_SHIFT (0U)XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)XBARA_SEL50_SEL101_MASK (0x7F00U)XBARA_SEL50_SEL101_SHIFT (8U)XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)XBARA_SEL51_SEL102_MASK (0x7FU)XBARA_SEL51_SEL102_SHIFT (0U)XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)XBARA_SEL51_SEL103_MASK (0x7F00U)XBARA_SEL51_SEL103_SHIFT (8U)XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)XBARA_SEL52_SEL104_MASK (0x7FU)XBARA_SEL52_SEL104_SHIFT (0U)XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)XBARA_SEL52_SEL105_MASK (0x7F00U)XBARA_SEL52_SEL105_SHIFT (8U)XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)XBARA_SEL53_SEL106_MASK (0x7FU)XBARA_SEL53_SEL106_SHIFT (0U)XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)XBARA_SEL53_SEL107_MASK (0x7F00U)XBARA_SEL53_SEL107_SHIFT (8U)XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)XBARA_SEL54_SEL108_MASK (0x7FU)XBARA_SEL54_SEL108_SHIFT (0U)XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)XBARA_SEL54_SEL109_MASK (0x7F00U)XBARA_SEL54_SEL109_SHIFT (8U)XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)XBARA_SEL55_SEL110_MASK (0x7FU)XBARA_SEL55_SEL110_SHIFT (0U)XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)XBARA_SEL55_SEL111_MASK (0x7F00U)XBARA_SEL55_SEL111_SHIFT (8U)XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)XBARA_SEL56_SEL112_MASK (0x7FU)XBARA_SEL56_SEL112_SHIFT (0U)XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)XBARA_SEL56_SEL113_MASK (0x7F00U)XBARA_SEL56_SEL113_SHIFT (8U)XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)XBARA_SEL57_SEL114_MASK (0x7FU)XBARA_SEL57_SEL114_SHIFT (0U)XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)XBARA_SEL57_SEL115_MASK (0x7F00U)XBARA_SEL57_SEL115_SHIFT (8U)XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)XBARA_SEL58_SEL116_MASK (0x7FU)XBARA_SEL58_SEL116_SHIFT (0U)XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)XBARA_SEL58_SEL117_MASK (0x7F00U)XBARA_SEL58_SEL117_SHIFT (8U)XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)XBARA_SEL59_SEL118_MASK (0x7FU)XBARA_SEL59_SEL118_SHIFT (0U)XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)XBARA_SEL59_SEL119_MASK (0x7F00U)XBARA_SEL59_SEL119_SHIFT (8U)XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)XBARA_SEL60_SEL120_MASK (0x7FU)XBARA_SEL60_SEL120_SHIFT (0U)XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)XBARA_SEL60_SEL121_MASK (0x7F00U)XBARA_SEL60_SEL121_SHIFT (8U)XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)XBARA_SEL61_SEL122_MASK (0x7FU)XBARA_SEL61_SEL122_SHIFT (0U)XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)XBARA_SEL61_SEL123_MASK (0x7F00U)XBARA_SEL61_SEL123_SHIFT (8U)XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)XBARA_SEL62_SEL124_MASK (0x7FU)XBARA_SEL62_SEL124_SHIFT (0U)XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)XBARA_SEL62_SEL125_MASK (0x7F00U)XBARA_SEL62_SEL125_SHIFT (8U)XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)XBARA_SEL63_SEL126_MASK (0x7FU)XBARA_SEL63_SEL126_SHIFT (0U)XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)XBARA_SEL63_SEL127_MASK (0x7F00U)XBARA_SEL63_SEL127_SHIFT (8U)XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)XBARA_SEL64_SEL128_MASK (0x7FU)XBARA_SEL64_SEL128_SHIFT (0U)XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)XBARA_SEL64_SEL129_MASK (0x7F00U)XBARA_SEL64_SEL129_SHIFT (8U)XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)XBARA_SEL65_SEL130_MASK (0x7FU)XBARA_SEL65_SEL130_SHIFT (0U)XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)XBARA_SEL65_SEL131_MASK (0x7F00U)XBARA_SEL65_SEL131_SHIFT (8U)XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)XBARA_CTRL0_DEN0_MASK (0x1U)XBARA_CTRL0_DEN0_SHIFT (0U)XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)XBARA_CTRL0_IEN0_MASK (0x2U)XBARA_CTRL0_IEN0_SHIFT (1U)XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)XBARA_CTRL0_EDGE0_MASK (0xCU)XBARA_CTRL0_EDGE0_SHIFT (2U)XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)XBARA_CTRL0_STS0_MASK (0x10U)XBARA_CTRL0_STS0_SHIFT (4U)XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)XBARA_CTRL0_DEN1_MASK (0x100U)XBARA_CTRL0_DEN1_SHIFT (8U)XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)XBARA_CTRL0_IEN1_MASK (0x200U)XBARA_CTRL0_IEN1_SHIFT (9U)XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)XBARA_CTRL0_EDGE1_MASK (0xC00U)XBARA_CTRL0_EDGE1_SHIFT (10U)XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)XBARA_CTRL0_STS1_MASK (0x1000U)XBARA_CTRL0_STS1_SHIFT (12U)XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)XBARA_CTRL1_DEN2_MASK (0x1U)XBARA_CTRL1_DEN2_SHIFT (0U)XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)XBARA_CTRL1_IEN2_MASK (0x2U)XBARA_CTRL1_IEN2_SHIFT (1U)XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)XBARA_CTRL1_EDGE2_MASK (0xCU)XBARA_CTRL1_EDGE2_SHIFT (2U)XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)XBARA_CTRL1_STS2_MASK (0x10U)XBARA_CTRL1_STS2_SHIFT (4U)XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)XBARA_CTRL1_DEN3_MASK (0x100U)XBARA_CTRL1_DEN3_SHIFT (8U)XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)XBARA_CTRL1_IEN3_MASK (0x200U)XBARA_CTRL1_IEN3_SHIFT (9U)XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)XBARA_CTRL1_EDGE3_MASK (0xC00U)XBARA_CTRL1_EDGE3_SHIFT (10U)XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)XBARA_CTRL1_STS3_MASK (0x1000U)XBARA_CTRL1_STS3_SHIFT (12U)XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)XBARA1_BASE (0x403BC000u)XBARA1 ((XBARA_Type *)XBARA1_BASE)XBARA_BASE_ADDRS { XBARA1_BASE }XBARA_BASE_PTRS { XBARA1 }XBARB_SEL0_SEL0_MASK (0x3FU)XBARB_SEL0_SEL0_SHIFT (0U)XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)XBARB_SEL0_SEL1_MASK (0x3F00U)XBARB_SEL0_SEL1_SHIFT (8U)XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)XBARB_SEL1_SEL2_MASK (0x3FU)XBARB_SEL1_SEL2_SHIFT (0U)XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)XBARB_SEL1_SEL3_MASK (0x3F00U)XBARB_SEL1_SEL3_SHIFT (8U)XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)XBARB_SEL2_SEL4_MASK (0x3FU)XBARB_SEL2_SEL4_SHIFT (0U)XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)XBARB_SEL2_SEL5_MASK (0x3F00U)XBARB_SEL2_SEL5_SHIFT (8U)XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)XBARB_SEL3_SEL6_MASK (0x3FU)XBARB_SEL3_SEL6_SHIFT (0U)XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)XBARB_SEL3_SEL7_MASK (0x3F00U)XBARB_SEL3_SEL7_SHIFT (8U)XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)XBARB_SEL4_SEL8_MASK (0x3FU)XBARB_SEL4_SEL8_SHIFT (0U)XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)XBARB_SEL4_SEL9_MASK (0x3F00U)XBARB_SEL4_SEL9_SHIFT (8U)XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)XBARB_SEL5_SEL10_MASK (0x3FU)XBARB_SEL5_SEL10_SHIFT (0U)XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)XBARB_SEL5_SEL11_MASK (0x3F00U)XBARB_SEL5_SEL11_SHIFT (8U)XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)XBARB_SEL6_SEL12_MASK (0x3FU)XBARB_SEL6_SEL12_SHIFT (0U)XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)XBARB_SEL6_SEL13_MASK (0x3F00U)XBARB_SEL6_SEL13_SHIFT (8U)XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)XBARB_SEL7_SEL14_MASK (0x3FU)XBARB_SEL7_SEL14_SHIFT (0U)XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)XBARB_SEL7_SEL15_MASK (0x3F00U)XBARB_SEL7_SEL15_SHIFT (8U)XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)XBARB2_BASE (0x403C0000u)XBARB2 ((XBARB_Type *)XBARB2_BASE)XBARB3_BASE (0x403C4000u)XBARB3 ((XBARB_Type *)XBARB3_BASE)XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU)XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U)XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U)XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U)XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U)XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)XTALOSC24M_BASE (0x400D8000u)XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }XTALOSC24M_BASE_PTRS { XTALOSC24M }NXP_VAL2FLD(field,value) (((value) << (field ## _SHIFT)) & (field ## _MASK))NXP_FLD2VAL(field,value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) __stdint_h  __ARMCLIB_VERSION 5060037__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS sINT8_MIN -128tINT16_MIN -32768uINT32_MIN (~0x7fffffff)vINT64_MIN __INT64_C(~0x7fffffffffffffff)yINT8_MAX 127zINT16_MAX 32767{INT32_MAX 2147483647|INT64_MAX __INT64_C(9223372036854775807)UINT8_MAX 255UINT16_MAX 65535UINT32_MAX 4294967295uUINT64_MAX __UINT64_C(18446744073709551615)INT_LEAST8_MIN -128INT_LEAST16_MIN -32768INT_LEAST32_MIN (~0x7fffffff)INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_LEAST8_MAX 127INT_LEAST16_MAX 32767INT_LEAST32_MAX 2147483647INT_LEAST64_MAX __INT64_C(9223372036854775807)UINT_LEAST8_MAX 255UINT_LEAST16_MAX 65535UINT_LEAST32_MAX 4294967295uUINT_LEAST64_MAX __UINT64_C(18446744073709551615)INT_FAST8_MIN (~0x7fffffff)INT_FAST16_MIN (~0x7fffffff)INT_FAST32_MIN (~0x7fffffff)INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_FAST8_MAX 2147483647INT_FAST16_MAX 2147483647INT_FAST32_MAX 2147483647INT_FAST64_MAX __INT64_C(9223372036854775807)UINT_FAST8_MAX 4294967295uUINT_FAST16_MAX 4294967295uUINT_FAST32_MAX 4294967295uUINT_FAST64_MAX __UINT64_C(18446744073709551615)INTPTR_MIN INT32_MININTPTR_MAX INT32_MAXUINTPTR_MAX UINT32_MAXINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)INTMAX_MAX __ESCAPE__(9223372036854775807ll)UINTMAX_MAX __ESCAPE__(18446744073709551615ull)PTRDIFF_MIN INT32_MINPTRDIFF_MAX INT32_MAXSIG_ATOMIC_MIN (~0x7fffffff)SIG_ATOMIC_MAX 2147483647SIZE_MAX UINT32_MAXWCHAR_MINWCHAR_MAXWCHAR_MIN 0WCHAR_MAX 65535WINT_MIN (~0x7fffffff)WINT_MAX 2147483647INT8_C(x) (x)INT16_C(x) (x)INT32_C(x) (x)INT64_C(x) __INT64_C(x)UINT8_C(x) (x ## u)UINT16_C(x) (x ## u)UINT32_C(x) (x ## u)UINT64_C(x) __UINT64_C(x)INTMAX_C(x) __ESCAPE__(x ## ll)UINTMAX_C(x) __ESCAPE__(x ## ull)__INT64__LONGLONG VERS 1 UNKNOWN 0ONCHIP 1EXT8BIT 2EXT16BIT 3EXT32BIT 4EXTSPI 5SECTOR_NUM 512PAGE_MAX 65536SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF.FLASH_DRV_VERS (0x0100+VERS)tN ITM_RxBuffer7̼SystemInitUSystemCoreClockUpdate" SystemCoreClockf$flexspi_is_parallel_modeflexspi_is_differential_clock_enableflexspi_is_word_addressableUflexspi_is_ck2_enabledflexspi_is_ddr_mode_enableflexspi_clear_sequence_pointerflexspi_is_padsetting_override_enableflexspi_configure_dllflexspi_get_ticksflexspi_config_mcr1qflexspi_config_flash_control_registersflexspi_config_ahb_bufferslflexspi_command_xfer_ flexspi_update_lut flexspi_device_write_enableR flexspi_device_wait_busy&flexspi_initflexspi_wait_idleflexspi_clear_cacheSflexspi_half_clock_control)mflexspi_nor_flash_init6 flexspi_nor_flash_page_programflexspi_nor_flash_erase_allflexspi_nor_flash_erase_sectorflexspi_nor_flash_erase_block get_page_sector_block_size_from_sfdpflexspi_nor_restore_spi_protocolflexspi_nor_get_configNflexspi_nor_flash_erase[flexspi_nor_flash_readj\BCLOCK_InitUsb1PlliCLOCK_DeinitUsb1PllCLOCK_InitUsb2PllCLOCK_DeinitUsb2PllD CLOCK_GetPllFreqCLOCK_GetSysPfdFreqSCLOCK_InitExternalClkCLOCK_DeinitExternalClkCLOCK_SwitchOscCLOCK_InitRcOsc24MCLOCK_DeinitRcOsc24MECLOCK_GetUsb1PfdFreqCLOCK_GetFreqCLOCK_InitArmPllOCLOCK_DeinitArmPllwCLOCK_InitSysPllCLOCK_DeinitSysPll8CLOCK_InitAudioPllCLOCK_DeinitAudioPllCLOCK_InitVideoPllCLOCK_DeinitVideoPllDCLOCK_InitEnetPllCLOCK_DeinitEnetPllCLOCK_InitSysPfd!CLOCK_DeinitSysPfdWCLOCK_InitUsb1PfdCLOCK_DeinitUsb1PfdCLOCK_EnableUsbhs0ClockmCLOCK_EnableUsbhs1ClockCLOCK_EnableUsbhs0PhyPllClocka CLOCK_EnableUsbhs1PhyPllClock CLOCK_DisableUsbhs0PhyPllClock( CLOCK_DisableUsbhs1PhyPllClock/$g_xtalFreqg_rtcXtalFreqPflexspi_iomux_configflexspi_set_failsafe_settingflexspi_nor_write_persistenthflexspi_nor_read_persistent^̖flexspi_clock_gate_enableCflexspi_clock_gate_disablewget_core_clock/tg_xtalFreq1g_rtcXtalFreq clock_initvflexspi_clock_configflexspi_get_clockflexspi_get_max_supported_freqget_bus_clockflexspi_sw_delay_ustFlashDeviceP`InittUnInitEraseChipEraseSector9ProgramPageconfig.L0Zt  |  .8n(#$d&p&((--224455889499::8*T6p<:AL:W<*X{6LL9(@*\60D*`66?rMi L9^:^:d9{t9H*d6  6 d!u BA PWs6./vG/6Q'!"4'p'( )(#/)$L9>L*ha6T)c0?3O3_3o3L::P*l:64^:af65y666686@767Z6868686868696496h9+89=(A`EIMQU:Yq]ae i. m_ qld k u   M S c s V i }" 0 @D 1.Y _*v    J D *     %  : DO Q] ' n ?  I  a  k   6  j 3  ? j, A @S g  $x %  7 $ [  m > > .  . E < W [ *r  w g  e00!&G&_]'ZvU)c)q) {)) )()&>*>P +rd{+C,P,$,.`.Z S/"%1/2A 3U3$p4{45566ZA7[7y7y7}7}7}77!727?7FO8Y8 f8z888 9594i9 u909:(:6:F:R:$t$d$d.realdataFlashPrg.c.rev16_text.revsh_text.text.bssFlashDev.c.constdatabsp\\src\\clock_config_MIMXRT1051.cbsp\src\clock_config_MIMXRT1051.cbsp\\src\\hardware_init_MIMXRT1051.cbsp\src\hardware_init_MIMXRT1051.cdevices\\MIMXRT1052\\drivers\\fsl_clock.cdevices\MIMXRT1052\drivers\fsl_clock.cCLOCK_GetPeriphClkFreqCLOCK_GetOscFreq.datai.__ARM_common_switch8i.__ARM_common_ll_muluumiddleware\\flexspi_nor\\flexspi_nor_flash.cmiddleware\flexspi_nor\flexspi_nor_flash.cflexspi_nor_exit_no_cmd_modeflexspi_nor_write_enableflexspi_nor_restore_no_cmd_modeflexspi_nor_wait_busyflexspi_change_serial_clockflexspi_nor_read_sfdpprepare_quad_mode_enable_sequenceprobe_dtr_quad_read_dummy_cyclesparse_sfdpflexspi_nor_read_sfdp_infoflexspi_nor_generate_config_block_hyperflashflexspi_nor_generate_config_block_mxic_octalflashflexspi_nor_generate_config_block_micron_octalflashflexspi_nor_generate_config_block_adesto_octalflashprepare_0_4_4_mode_enable_sequenceflexspi_nor_generate_config_block_using_sfdpflexspi_nor_hyperbus_readflexspi_nor_hyperbus_writemiddleware\\flexspi\\fsl_flexspi.cmiddleware\flexspi\fsl_flexspi.cflexspi_device_cmd_configflexspi_swresetflexspi_get_module_baseflexspi_wait_until_ip_idleflexspi_device_workmode_configg_flexSpiInstancesdevices\\MIMXRT1052\\system_MIMXRT1052.cdevices\MIMXRT1052\system_MIMXRT1052.cdc.s../clib/division.c../clib/stdlib.c../clib/string.c../clib/memcpset.c.emb_text../clib/division.s../clib/angel/sysapp.c../clib/angel/rt.s../clib/signal.c../clib/angel/sys.s../clib/signal.sBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$RWPI$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2__aeabi_memcpy4__aeabi_memcpy8__asm___10_FlashPrg_c_Init____REV16__asm___25_clock_config_MIMXRT1051_c_efd8dd31____REV16__asm___26_hardware_init_MIMXRT1051_c_753bbbb7____REV16__asm___11_fsl_clock_c_07a918fd____REV16__asm___19_flexspi_nor_flash_c_93f2e184____REV16__asm___13_fsl_flexspi_c_c729c902____REV16__asm___19_system_MIMXRT1052_c_5d646a67____REV16__asm___10_FlashPrg_c_Init____REVSH__asm___25_clock_config_MIMXRT1051_c_efd8dd31____REVSH__asm___26_hardware_init_MIMXRT1051_c_753bbbb7____REVSH__asm___11_fsl_clock_c_07a918fd____REVSH__asm___19_flexspi_nor_flash_c_93f2e184____REVSH__asm___13_fsl_flexspi_c_c729c902____REVSH__asm___19_system_MIMXRT1052_c_5d646a67____REVSHInitUnInitEraseChipEraseSectorProgramPageclock_initflexspi_clock_gate_enableflexspi_clock_gate_disableflexspi_clock_configflexspi_get_clockflexspi_get_max_supported_freqget_core_clockget_bus_clockflexspi_sw_delay_usflexspi_iomux_configflexspi_set_failsafe_settingflexspi_nor_write_persistentflexspi_nor_read_persistentCLOCK_GetPllFreqCLOCK_GetSysPfdFreqCLOCK_InitExternalClkCLOCK_DeinitExternalClkCLOCK_SwitchOscCLOCK_InitRcOsc24MCLOCK_DeinitRcOsc24MCLOCK_GetUsb1PfdFreqCLOCK_GetFreqCLOCK_InitArmPllCLOCK_DeinitArmPllCLOCK_InitSysPllCLOCK_DeinitSysPllCLOCK_InitUsb1PllCLOCK_DeinitUsb1PllCLOCK_InitUsb2PllCLOCK_DeinitUsb2PllCLOCK_InitAudioPllCLOCK_DeinitAudioPllCLOCK_InitVideoPllCLOCK_DeinitVideoPllCLOCK_InitEnetPllCLOCK_DeinitEnetPllCLOCK_InitSysPfdCLOCK_DeinitSysPfdCLOCK_InitUsb1PfdCLOCK_DeinitUsb1PfdCLOCK_EnableUsbhs0ClockCLOCK_EnableUsbhs1ClockCLOCK_EnableUsbhs0PhyPllClockCLOCK_EnableUsbhs1PhyPllClockCLOCK_DisableUsbhs0PhyPllClockCLOCK_DisableUsbhs1PhyPllClockflexspi_nor_flash_initflexspi_nor_flash_page_programflexspi_nor_flash_erase_allflexspi_nor_flash_erase_sectorflexspi_nor_flash_erase_blockget_page_sector_block_size_from_sfdpflexspi_nor_restore_spi_protocolflexspi_nor_get_configflexspi_nor_flash_eraseflexspi_nor_flash_readflexspi_is_parallel_modeflexspi_is_padsetting_override_enableflexspi_is_differential_clock_enableflexspi_is_word_addressableflexspi_is_ck2_enabledflexspi_is_ddr_mode_enableflexspi_configure_dllflexspi_get_ticksflexspi_config_mcr1flexspi_config_flash_control_registersflexspi_config_ahb_buffersflexspi_clear_sequence_pointerflexspi_command_xferflexspi_update_lutflexspi_device_write_enableflexspi_device_wait_busyflexspi_initflexspi_wait_idleflexspi_clear_cacheflexspi_half_clock_controlSystemInitSystemCoreClockUpdate__aeabi_uldivmod_ll_udivabortmemcmp_memset_w_memset__aeabi_memclr__rt_memclr__aeabi_memclr4__aeabi_memclr8__rt_memclr_w__aeabi_uidiv__aeabi_uidivmod__aeabi_idiv__aeabi_idivmod_sys_exit__rt_SIGABRT__I$use$semihosting__use_no_semihosting_swi__semihosting_library_function__sig_exit__rt_SIGABRT_inner__default_signal_display_ttywrch__ARM_common_ll_muluu__ARM_common_switch8g_xtalFreqg_rtcXtalFreqSystemCoreClockFlashDeviceconfig@ARMComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]ArmLink --strict --load_addr_map_info --map --symbols --diag_suppress=9931,L6305 --cpu=Cortex-M0 --list=.\MIMXRT105x_HYPER.map --output=.\Output\MIMXRT105x_HYPER.axf --scatter=.\Target.lin --info=summarysizes,sizes,totals,unused,veneers C:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\c_pe.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\fz_ps.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\h_pe.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\m_ps.lC:\Keil_v5\ARM\ARMCC\Bin\..\lib\armlib\vfpsupport.lInput Comments:flashprg.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\flashprg.o --vfemode=force Input Comments:p38ac-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide flashprg.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flashprg.o --depend=.\output\flashprg.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1052 -I.\devices\MIMXRT1052\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1052CVL5A FlashPrg.cflashdev.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flashdev.o --depend=.\output\flashdev.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1052 -I.\devices\MIMXRT1052\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1052CVL5A FlashDev.cclock_config_mimxrt1051.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\clock_config_mimxrt1051.o --vfemode=force Input Comments:p291c-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide clock_config_mimxrt1051.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\clock_config_mimxrt1051.o --depend=.\output\clock_config_mimxrt1051.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1052 -I.\devices\MIMXRT1052\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1052CVL5A bsp\src\clock_config_MIMXRT1051.chardware_init_mimxrt1051.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\hardware_init_mimxrt1051.o --vfemode=force Input Comments:p1fb4-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide hardware_init_mimxrt1051.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\hardware_init_mimxrt1051.o --depend=.\output\hardware_init_mimxrt1051.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1052 -I.\devices\MIMXRT1052\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1052CVL5A bsp\src\hardware_init_MIMXRT1051.cfsl_clock.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\fsl_clock.o --vfemode=force Input Comments:p2038-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide fsl_clock.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\fsl_clock.o --depend=.\output\fsl_clock.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1052 -I.\devices\MIMXRT1052\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1052CVL5A devices\MIMXRT1052\drivers\fsl_clock.cflexspi_nor_flash.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\flexspi_nor_flash.o --vfemode=force Input Comments:p1398-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide flexspi_nor_flash.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\flexspi_nor_flash.o --depend=.\output\flexspi_nor_flash.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1052 -I.\devices\MIMXRT1052\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1052CVL5A middleware\flexspi_nor\flexspi_nor_flash.cfsl_flexspi.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\fsl_flexspi.o --vfemode=force Input Comments:p3110-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide fsl_flexspi.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\fsl_flexspi.o --depend=.\output\fsl_flexspi.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1052 -I.\devices\MIMXRT1052\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1052CVL5A middleware\flexspi\fsl_flexspi.csystem_mimxrt1052.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\output\system_mimxrt1052.o --vfemode=force Input Comments:p19e0-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork//ropi/rwpi --no_divide system_mimxrt1052.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --debug -c -o.\output\system_mimxrt1052.o --depend=.\output\system_mimxrt1052.d --cpu=Cortex-M0 --apcs=interwork//ropi/rwpi --diag_suppress=9931 -I.\middleware -I.\CMSIS\Include -I.\devices\MIMXRT1052 -I.\devices\MIMXRT1052\drivers -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\INC\Philips -D__UVISION_VERSION=526 -DCPU_MIMXRT1052CVL5A devices\MIMXRT1052\system_MIMXRT1052.cPrgCodePrgDataDevDscr.debug_abbrev.debug_frame.debug_info.debug_line.debug_loc.debug_macinfo.debug_pubnames.symtab.strtab.note.comment.shstrtab4:<0 ;:: 4: :; : ;: ;K'Q4`@ zxBLGWd('f+2 v+ ~p+\+ +,