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NIOPI:;9QI4 R S TUVW1X4I ,Y4I Z4I[4I,\4I]4I 4 ^4I ,4 _4I4 `4I,4 a4I4 b41 ,c41d41,e41f1g1hI iIjIkI 4 lI ,4 mI4 n1 o1p4I ? q4I? < r4I,s4It5Iu;v=w%x<%%.,armcc+|    (armcc+|  (armcc+|  (armcc+|  (armcc+|  (armcc+|   8 T0plA| \0B~0E~0F~ < X0LAz R b$0rAxCnI {A 0VA| h \|0A~0@Az @ \00.Az ^*   D `$0JA{Bvp {A 0DA~0>rA~0*A~     0 DA~0PA~ &  > H  ` j   6  jA} 2 > jA| @  $B~ $ 6 $B~ Z l >A~ >A~ .A~ .A~ D  V  0h  H d0 *A| 0 6A|ArX| 0 dAwBtn{ 0t BAwAn^{0 PAwBt 0AxAvV{0AwAn0vAyAn0fAxAn0AxAn 06A{CrV{$0.AwAhf {A $0.AxC` {A $0AwBu| {A $0vAwAj {A 0FAxB`$0.6AxBp {A 0d0AxBf{$0AxA\{ 0&!AxCR{$0"4AxAD {A 0 &Ax$0&AwBvc {A 0\'ZAwAnj{ 0'pA|Anu|0&(A{CR0)(A}AtQ}0.)$A}At L h \T) \b) \p) \z) \) \) 0)&AyAt{0*>Az$0+rA{Avt {A 0z+AyAra{B,PB~0,$A~0,Ax0.`Az 0.ZA|Crh|$0R/AwBf {A 0b0AxAn^{0$1AyAr02A~0 3A~03$A| 0>3 0N3 0^30n3A{Ar P l 4H0d4Az(0\5Axw {AA 0^6A~0r6ZB~ 8 06 06 07 07 7 7F>~ 0h80t8 A~ 808 A~08A~084A|08 A~009A~K090AzC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] $>signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_t8 Pint16_t9 Pint32_t: Pint64_t; Puint8_t> Puint16_t? Puint32_t@ Puint64_tA Pint_least8_tG Pint_least16_tH Pint_least32_tI Pint_least64_tJ Puint_least8_tM Puint_least16_tN Puint_least32_tO Puint_least64_tP Pint_fast8_tU Pint_fast16_tV Pint_fast32_tW Pint_fast64_tX Puint_fast8_t[ Puint_fast16_t\ Puint_fast32_t] Puint_fast64_t^ Pintptr_te Puintptr_tf Pintmax_tj!Puintmax_tk!4 .\devices\MIMXRT1052\MIMXRT1052.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash@H>IRQnNotAvail_IRQnNonMaskableInt_IRQnrHardFault_IRQnsMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnDMA0_DMA16_IRQnDMA1_DMA17_IRQnDMA2_DMA18_IRQnDMA3_DMA19_IRQnDMA4_DMA20_IRQnDMA5_DMA21_IRQnDMA6_DMA22_IRQnDMA7_DMA23_IRQnDMA8_DMA24_IRQnDMA9_DMA25_IRQn DMA10_DMA26_IRQn DMA11_DMA27_IRQn DMA12_DMA28_IRQn DMA13_DMA29_IRQn DMA14_DMA30_IRQnDMA15_DMA31_IRQnDMA_ERROR_IRQnCTI0_ERROR_IRQnCTI1_ERROR_IRQnCORE_IRQnLPUART1_IRQnLPUART2_IRQnLPUART3_IRQnLPUART4_IRQnLPUART5_IRQnLPUART6_IRQnLPUART7_IRQnLPUART8_IRQnLPI2C1_IRQnLPI2C2_IRQnLPI2C3_IRQnLPI2C4_IRQnLPSPI1_IRQn LPSPI2_IRQn!LPSPI3_IRQn"LPSPI4_IRQn#CAN1_IRQn$CAN2_IRQn%FLEXRAM_IRQn&KPP_IRQn'TSC_DIG_IRQn(GPR_IRQ_IRQn)LCDIF_IRQn*CSI_IRQn+PXP_IRQn,WDOG2_IRQn-SNVS_HP_WRAPPER_IRQn.SNVS_HP_WRAPPER_TZ_IRQn/SNVS_LP_WRAPPER_IRQn0CSU_IRQn1DCP_IRQn2DCP_VMI_IRQn3Reserved68_IRQn4TRNG_IRQn5SJC_IRQn6BEE_IRQn7SAI1_IRQn8SAI2_IRQn9SAI3_RX_IRQn:SAI3_TX_IRQn;SPDIF_IRQn<ANATOP_EVENT0_IRQn=ANATOP_EVENT1_IRQn>ANATOP_TAMP_LOW_HIGH_IRQn?ANATOP_TEMP_PANIC_IRQnUSB_PHY1_IRQnUSB_PHY2_IRQnADC1_IRQnADC2_IRQnDCDC_IRQnReserved86_IRQnReserved87_IRQnGPIO1_INT0_IRQnGPIO1_INT1_IRQnGPIO1_INT2_IRQnGPIO1_INT3_IRQnGPIO1_INT4_IRQnGPIO1_INT5_IRQnGPIO1_INT6_IRQnGPIO1_INT7_IRQnGPIO1_Combined_0_15_IRQnGPIO1_Combined_16_31_IRQnGPIO2_Combined_0_15_IRQnGPIO2_Combined_16_31_IRQnGPIO3_Combined_0_15_IRQnGPIO3_Combined_16_31_IRQnGPIO4_Combined_0_15_IRQnGPIO4_Combined_16_31_IRQnGPIO5_Combined_0_15_IRQnGPIO5_Combined_16_31_IRQnFLEXIO1_IRQnFLEXIO2_IRQnWDOG1_IRQnRTWDOG_IRQnEWM_IRQnCCM_1_IRQnCCM_2_IRQnGPC_IRQnSRC_IRQnReserved115_IRQnGPT1_IRQnGPT2_IRQnPWM1_0_IRQnPWM1_1_IRQnPWM1_2_IRQnPWM1_3_IRQnPWM1_FAULT_IRQnReserved123_IRQnFLEXSPI_IRQnSEMC_IRQnUSDHC1_IRQnUSDHC2_IRQnUSB_OTG2_IRQnUSB_OTG1_IRQnENET_IRQnENET_1588_Timer_IRQnXBAR1_IRQ_0_1_IRQnXBAR1_IRQ_2_3_IRQnADC_ETC_IRQ0_IRQnADC_ETC_IRQ1_IRQnADC_ETC_IRQ2_IRQnADC_ETC_ERROR_IRQ_IRQnPIT_IRQnACMP1_IRQnACMP2_IRQnACMP3_IRQnACMP4_IRQnReserved143_IRQnReserved144_IRQnENC1_IRQnENC2_IRQnENC3_IRQnENC4_IRQnTMR1_IRQnTMR2_IRQnTMR3_IRQnTMR4_IRQnPWM2_0_IRQnPWM2_1_IRQnPWM2_2_IRQnPWM2_3_IRQnPWM2_FAULT_IRQnPWM3_0_IRQnPWM3_1_IRQnPWM3_2_IRQnPWM3_3_IRQnPWM3_FAULT_IRQnPWM4_0_IRQnPWM4_1_IRQnPWM4_2_IRQnPWM4_3_IRQnPWM4_FAULT_IRQnReserved168_IRQnReserved169_IRQnReserved170_IRQnReserved171_IRQnReserved172_IRQnReserved173_IRQnSJC_ARM_DEBUG_IRQnNMI_WAKEUP_IRQnPIRQn_Type7_dma_request_sourcekDmaRequestMuxFlexIO1Request0Request1kDmaRequestMuxFlexIO2Request0Request1kDmaRequestMuxLPUART1TxkDmaRequestMuxLPUART1RxkDmaRequestMuxLPUART3TxkDmaRequestMuxLPUART3RxkDmaRequestMuxLPUART5TxkDmaRequestMuxLPUART5RxkDmaRequestMuxLPUART7TxkDmaRequestMuxLPUART7Rx kDmaRequestMuxCSI kDmaRequestMuxLPSPI1Rx kDmaRequestMuxLPSPI1TxkDmaRequestMuxLPSPI3RxkDmaRequestMuxLPSPI3TxkDmaRequestMuxLPI2C1kDmaRequestMuxLPI2C3kDmaRequestMuxSai1RxkDmaRequestMuxSai1TxkDmaRequestMuxSai2RxkDmaRequestMuxSai2TxkDmaRequestMuxADC_ETCkDmaRequestMuxADC1kDmaRequestMuxACMP1kDmaRequestMuxACMP2kDmaRequestMuxFlexSPIRxkDmaRequestMuxFlexSPITxkDmaRequestMuxXBAR1Request0kDmaRequestMuxXBAR1Request1kDmaRequestMuxFlexPWM1CaptureSub0 kDmaRequestMuxFlexPWM1CaptureSub1!kDmaRequestMuxFlexPWM1CaptureSub2"kDmaRequestMuxFlexPWM1CaptureSub3#kDmaRequestMuxFlexPWM1ValueSub0$kDmaRequestMuxFlexPWM1ValueSub1%kDmaRequestMuxFlexPWM1ValueSub2&kDmaRequestMuxFlexPWM1ValueSub3'kDmaRequestMuxFlexPWM3CaptureSub0(kDmaRequestMuxFlexPWM3CaptureSub1)kDmaRequestMuxFlexPWM3CaptureSub2*kDmaRequestMuxFlexPWM3CaptureSub3+kDmaRequestMuxFlexPWM3ValueSub0,kDmaRequestMuxFlexPWM3ValueSub1-kDmaRequestMuxFlexPWM3ValueSub2.kDmaRequestMuxFlexPWM3ValueSub3/kDmaRequestMuxQTIMER1CaptTimer00kDmaRequestMuxQTIMER1CaptTimer11kDmaRequestMuxQTIMER1CaptTimer22kDmaRequestMuxQTIMER1CaptTimer33kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer14kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer05kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer36kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer27kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer18kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer19kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1:kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1;kDmaRequestMuxFlexIO1Request2Request3@kDmaRequestMuxFlexIO2Request2Request3AkDmaRequestMuxLPUART2TxBkDmaRequestMuxLPUART2RxCkDmaRequestMuxLPUART4TxDkDmaRequestMuxLPUART4RxEkDmaRequestMuxLPUART6TxFkDmaRequestMuxLPUART6RxGkDmaRequestMuxLPUART8TxHkDmaRequestMuxLPUART8RxIkDmaRequestMuxPxpKkDmaRequestMuxLCDIFLkDmaRequestMuxLPSPI2RxMkDmaRequestMuxLPSPI2TxNkDmaRequestMuxLPSPI4RxOkDmaRequestMuxLPSPI4TxPkDmaRequestMuxLPI2C2QkDmaRequestMuxLPI2C4RkDmaRequestMuxSai3RxSkDmaRequestMuxSai3TxTkDmaRequestMuxSpdifRxUkDmaRequestMuxSpdifTxVkDmaRequestMuxADC2XkDmaRequestMuxACMP3YkDmaRequestMuxACMP4ZkDmaRequestMuxEnetTimer0\kDmaRequestMuxEnetTimer1]kDmaRequestMuxXBAR1Request2^kDmaRequestMuxXBAR1Request3_kDmaRequestMuxFlexPWM2CaptureSub0`kDmaRequestMuxFlexPWM2CaptureSub1akDmaRequestMuxFlexPWM2CaptureSub2bkDmaRequestMuxFlexPWM2CaptureSub3ckDmaRequestMuxFlexPWM2ValueSub0dkDmaRequestMuxFlexPWM2ValueSub1ekDmaRequestMuxFlexPWM2ValueSub2fkDmaRequestMuxFlexPWM2ValueSub3gkDmaRequestMuxFlexPWM4CaptureSub0hkDmaRequestMuxFlexPWM4CaptureSub1ikDmaRequestMuxFlexPWM4CaptureSub2jkDmaRequestMuxFlexPWM4CaptureSub3kkDmaRequestMuxFlexPWM4ValueSub0lkDmaRequestMuxFlexPWM4ValueSub1mkDmaRequestMuxFlexPWM4ValueSub2nkDmaRequestMuxFlexPWM4ValueSub3okDmaRequestMuxQTIMER2CaptTimer0pkDmaRequestMuxQTIMER2CaptTimer1qkDmaRequestMuxQTIMER2CaptTimer2rkDmaRequestMuxQTIMER2CaptTimer3skDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1tkDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0ukDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3vkDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2wkDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1xkDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1ykDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1zkDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1{Pdma_request_source_tf ]_iomuxc_sw_mux_ctl_padkIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 !kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 "kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 #kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 $kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 %kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 &kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 'kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 (kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 )kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 *kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 +kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 ,kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 -kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 .kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 /kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 0kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 1kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 2kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 3kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 4kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 5kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 6kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 7kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 8kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 9kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 :kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 ;kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 <kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 =kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 >kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 ?kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 @kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 AkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 BkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 CkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 DkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 EkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 FkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 GkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 HkIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 IkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 JkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 KkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 LkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 MkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 NkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 OkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 PkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 QkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 RkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 SkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 TkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 UkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 VkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 WkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 XkIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 YkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 ZkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 [kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 \kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 ]kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 ^kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 _kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 `kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 akIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 bkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 ckIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 dkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 ekIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 fkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 gkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 hkIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 ikIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 jkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 kkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 lkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 mkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 nkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 okIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 pkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 qkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 rkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 skIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 tkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 ukIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 vkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 wkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 xkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 ykIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 zkIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 {Piomuxc_sw_mux_ctl_pad_tɃ_iomuxc_sw_pad_ctl_padkIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 !kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 "kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 #kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 $kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 %kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 &kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 'kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 (kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 )kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 *kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 +kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 ,kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 -kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 .kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 /kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 0kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 1kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 2kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 3kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 4kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 5kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 6kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 7kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 8kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 9kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 :kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 ;kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 <kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 =kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 >kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 ?kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 @kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 AkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 BkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 CkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 DkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 EkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 FkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 GkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 HkIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 IkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 JkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 KkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 LkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 MkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 NkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 OkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 PkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 QkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 RkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 SkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 TkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 UkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 VkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 WkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 XkIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 YkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 ZkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 [kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 \kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 ]kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 ^kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 _kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 `kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 akIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 bkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 ckIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 dkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 ekIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 fkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 gkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 hkIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 ikIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 jkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 kkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 lkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 mkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 nkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 okIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 pkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 qkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 rkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 skIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 tkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 ukIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 vkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 wkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 xkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 ykIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 zkIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 {Piomuxc_sw_pad_ctl_pad_t/_iomuxc_select_inputkIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT kIOMUXC_CCM_PMIC_READY_SELECT_INPUT kIOMUXC_CSI_DATA02_SELECT_INPUT kIOMUXC_CSI_DATA03_SELECT_INPUT kIOMUXC_CSI_DATA04_SELECT_INPUT kIOMUXC_CSI_DATA05_SELECT_INPUT kIOMUXC_CSI_DATA06_SELECT_INPUT kIOMUXC_CSI_DATA07_SELECT_INPUT kIOMUXC_CSI_DATA08_SELECT_INPUT kIOMUXC_CSI_DATA09_SELECT_INPUT kIOMUXC_CSI_HSYNC_SELECT_INPUT kIOMUXC_CSI_PIXCLK_SELECT_INPUT kIOMUXC_CSI_VSYNC_SELECT_INPUT kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT kIOMUXC_ENET_MDIO_SELECT_INPUT kIOMUXC_ENET0_RXDATA_SELECT_INPUT kIOMUXC_ENET1_RXDATA_SELECT_INPUT kIOMUXC_ENET_RXEN_SELECT_INPUT kIOMUXC_ENET_RXERR_SELECT_INPUT kIOMUXC_ENET0_TIMER_SELECT_INPUT kIOMUXC_ENET_TXCLK_SELECT_INPUT kIOMUXC_FLEXCAN1_RX_SELECT_INPUT kIOMUXC_FLEXCAN2_RX_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT !kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT "kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT #kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT $kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT %kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT &kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT 'kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT (kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT )kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT *kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT +kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT ,kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT -kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT .kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT /kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT 0kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT 1kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT 2kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT 3kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT 4kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT 5kIOMUXC_LPI2C1_SCL_SELECT_INPUT 6kIOMUXC_LPI2C1_SDA_SELECT_INPUT 7kIOMUXC_LPI2C2_SCL_SELECT_INPUT 8kIOMUXC_LPI2C2_SDA_SELECT_INPUT 9kIOMUXC_LPI2C3_SCL_SELECT_INPUT :kIOMUXC_LPI2C3_SDA_SELECT_INPUT ;kIOMUXC_LPI2C4_SCL_SELECT_INPUT <kIOMUXC_LPI2C4_SDA_SELECT_INPUT =kIOMUXC_LPSPI1_PCS0_SELECT_INPUT >kIOMUXC_LPSPI1_SCK_SELECT_INPUT ?kIOMUXC_LPSPI1_SDI_SELECT_INPUT @kIOMUXC_LPSPI1_SDO_SELECT_INPUT AkIOMUXC_LPSPI2_PCS0_SELECT_INPUT BkIOMUXC_LPSPI2_SCK_SELECT_INPUT CkIOMUXC_LPSPI2_SDI_SELECT_INPUT DkIOMUXC_LPSPI2_SDO_SELECT_INPUT EkIOMUXC_LPSPI3_PCS0_SELECT_INPUT FkIOMUXC_LPSPI3_SCK_SELECT_INPUT GkIOMUXC_LPSPI3_SDI_SELECT_INPUT HkIOMUXC_LPSPI3_SDO_SELECT_INPUT IkIOMUXC_LPSPI4_PCS0_SELECT_INPUT JkIOMUXC_LPSPI4_SCK_SELECT_INPUT KkIOMUXC_LPSPI4_SDI_SELECT_INPUT LkIOMUXC_LPSPI4_SDO_SELECT_INPUT MkIOMUXC_LPUART2_RX_SELECT_INPUT NkIOMUXC_LPUART2_TX_SELECT_INPUT OkIOMUXC_LPUART3_CTS_B_SELECT_INPUT PkIOMUXC_LPUART3_RX_SELECT_INPUT QkIOMUXC_LPUART3_TX_SELECT_INPUT RkIOMUXC_LPUART4_RX_SELECT_INPUT SkIOMUXC_LPUART4_TX_SELECT_INPUT TkIOMUXC_LPUART5_RX_SELECT_INPUT UkIOMUXC_LPUART5_TX_SELECT_INPUT VkIOMUXC_LPUART6_RX_SELECT_INPUT WkIOMUXC_LPUART6_TX_SELECT_INPUT XkIOMUXC_LPUART7_RX_SELECT_INPUT YkIOMUXC_LPUART7_TX_SELECT_INPUT ZkIOMUXC_LPUART8_RX_SELECT_INPUT [kIOMUXC_LPUART8_TX_SELECT_INPUT \kIOMUXC_NMI_SELECT_INPUT ]kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT ^kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT _kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT `kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT akIOMUXC_QTIMER3_TIMER0_SELECT_INPUT bkIOMUXC_QTIMER3_TIMER1_SELECT_INPUT ckIOMUXC_QTIMER3_TIMER2_SELECT_INPUT dkIOMUXC_QTIMER3_TIMER3_SELECT_INPUT ekIOMUXC_SAI1_MCLK2_SELECT_INPUT fkIOMUXC_SAI1_RX_BCLK_SELECT_INPUT gkIOMUXC_SAI1_RX_DATA0_SELECT_INPUT hkIOMUXC_SAI1_RX_DATA1_SELECT_INPUT ikIOMUXC_SAI1_RX_DATA2_SELECT_INPUT jkIOMUXC_SAI1_RX_DATA3_SELECT_INPUT kkIOMUXC_SAI1_RX_SYNC_SELECT_INPUT lkIOMUXC_SAI1_TX_BCLK_SELECT_INPUT mkIOMUXC_SAI1_TX_SYNC_SELECT_INPUT nkIOMUXC_SAI2_MCLK2_SELECT_INPUT okIOMUXC_SAI2_RX_BCLK_SELECT_INPUT pkIOMUXC_SAI2_RX_DATA0_SELECT_INPUT qkIOMUXC_SAI2_RX_SYNC_SELECT_INPUT rkIOMUXC_SAI2_TX_BCLK_SELECT_INPUT skIOMUXC_SAI2_TX_SYNC_SELECT_INPUT tkIOMUXC_SPDIF_IN_SELECT_INPUT ukIOMUXC_USB_OTG2_OC_SELECT_INPUT vkIOMUXC_USB_OTG1_OC_SELECT_INPUT wkIOMUXC_USDHC1_CD_B_SELECT_INPUT xkIOMUXC_USDHC1_WP_SELECT_INPUT ykIOMUXC_USDHC2_CLK_SELECT_INPUT zkIOMUXC_USDHC2_CD_B_SELECT_INPUT {kIOMUXC_USDHC2_CMD_SELECT_INPUT |kIOMUXC_USDHC2_DATA0_SELECT_INPUT }kIOMUXC_USDHC2_DATA1_SELECT_INPUT ~kIOMUXC_USDHC2_DATA2_SELECT_INPUT kIOMUXC_USDHC2_DATA3_SELECT_INPUT kIOMUXC_USDHC2_DATA4_SELECT_INPUT kIOMUXC_USDHC2_DATA5_SELECT_INPUT kIOMUXC_USDHC2_DATA6_SELECT_INPUT kIOMUXC_USDHC2_DATA7_SELECT_INPUT kIOMUXC_USDHC2_WP_SELECT_INPUT kIOMUXC_XBAR1_IN02_SELECT_INPUT kIOMUXC_XBAR1_IN03_SELECT_INPUT kIOMUXC_XBAR1_IN04_SELECT_INPUT kIOMUXC_XBAR1_IN05_SELECT_INPUT kIOMUXC_XBAR1_IN06_SELECT_INPUT kIOMUXC_XBAR1_IN07_SELECT_INPUT kIOMUXC_XBAR1_IN08_SELECT_INPUT kIOMUXC_XBAR1_IN09_SELECT_INPUT kIOMUXC_XBAR1_IN17_SELECT_INPUT kIOMUXC_XBAR1_IN18_SELECT_INPUT kIOMUXC_XBAR1_IN20_SELECT_INPUT kIOMUXC_XBAR1_IN22_SELECT_INPUT kIOMUXC_XBAR1_IN23_SELECT_INPUT kIOMUXC_XBAR1_IN24_SELECT_INPUT kIOMUXC_XBAR1_IN14_SELECT_INPUT kIOMUXC_XBAR1_IN15_SELECT_INPUT kIOMUXC_XBAR1_IN16_SELECT_INPUT kIOMUXC_XBAR1_IN25_SELECT_INPUT kIOMUXC_XBAR1_IN19_SELECT_INPUT kIOMUXC_XBAR1_IN21_SELECT_INPUT Piomuxc_select_input_tA_xbar_input_signalkXBARA1_InputLogicLowkXBARA1_InputLogicHighkXBARA1_InputIomuxXbarIn02kXBARA1_InputIomuxXbarIn03kXBARA1_InputIomuxXbarInout04kXBARA1_InputIomuxXbarInout05kXBARA1_InputIomuxXbarInout06kXBARA1_InputIomuxXbarInout07kXBARA1_InputIomuxXbarInout08kXBARA1_InputIomuxXbarInout09 kXBARA1_InputIomuxXbarInout10 kXBARA1_InputIomuxXbarInout11 kXBARA1_InputIomuxXbarInout12 kXBARA1_InputIomuxXbarInout13 kXBARA1_InputIomuxXbarInout14kXBARA1_InputIomuxXbarInout15kXBARA1_InputIomuxXbarInout16kXBARA1_InputIomuxXbarInout17kXBARA1_InputIomuxXbarInout18kXBARA1_InputIomuxXbarInout19kXBARA1_InputIomuxXbarIn20kXBARA1_InputIomuxXbarIn21kXBARA1_InputIomuxXbarIn22kXBARA1_InputIomuxXbarIn23kXBARA1_InputIomuxXbarIn24kXBARA1_InputIomuxXbarIn25kXBARA1_InputAcmp1OutkXBARA1_InputAcmp2OutkXBARA1_InputAcmp3OutkXBARA1_InputAcmp4OutkXBARA1_InputRESERVED30kXBARA1_InputRESERVED31kXBARA1_InputQtimer3Tmr0Output kXBARA1_InputQtimer3Tmr1Output!kXBARA1_InputQtimer3Tmr2Output"kXBARA1_InputQtimer3Tmr3Output#kXBARA1_InputQtimer4Tmr0Output$kXBARA1_InputQtimer4Tmr1Output%kXBARA1_InputQtimer4Tmr2Output&kXBARA1_InputQtimer4Tmr3Output'kXBARA1_InputFlexpwm1Pwm1OutTrig01(kXBARA1_InputFlexpwm1Pwm2OutTrig01)kXBARA1_InputFlexpwm1Pwm3OutTrig01*kXBARA1_InputFlexpwm1Pwm4OutTrig01+kXBARA1_InputFlexpwm2Pwm1OutTrig01,kXBARA1_InputFlexpwm2Pwm2OutTrig01-kXBARA1_InputFlexpwm2Pwm3OutTrig01.kXBARA1_InputFlexpwm2Pwm4OutTrig01/kXBARA1_InputFlexpwm3Pwm1OutTrig010kXBARA1_InputFlexpwm3Pwm2OutTrig011kXBARA1_InputFlexpwm3Pwm3OutTrig012kXBARA1_InputFlexpwm3Pwm4OutTrig013kXBARA1_InputFlexpwm4Pwm1OutTrig014kXBARA1_InputFlexpwm4Pwm2OutTrig015kXBARA1_InputFlexpwm4Pwm3OutTrig016kXBARA1_InputFlexpwm4Pwm4OutTrig017kXBARA1_InputPitTrigger08kXBARA1_InputPitTrigger19kXBARA1_InputPitTrigger2:kXBARA1_InputPitTrigger3;kXBARA1_InputEnc1PosMatch<kXBARA1_InputEnc2PosMatch=kXBARA1_InputEnc3PosMatch>kXBARA1_InputEnc4PosMatch?kXBARA1_InputDmaDone0@kXBARA1_InputDmaDone1AkXBARA1_InputDmaDone2BkXBARA1_InputDmaDone3CkXBARA1_InputDmaDone4DkXBARA1_InputDmaDone5EkXBARA1_InputDmaDone6FkXBARA1_InputDmaDone7GkXBARA1_InputAoi1Out0HkXBARA1_InputAoi1Out1IkXBARA1_InputAoi1Out2JkXBARA1_InputAoi1Out3KkXBARA1_InputAoi2Out0LkXBARA1_InputAoi2Out1MkXBARA1_InputAoi2Out2NkXBARA1_InputAoi2Out3OkXBARA1_InputAdcEtcXbar0Coco0PkXBARA1_InputAdcEtcXbar0Coco1QkXBARA1_InputAdcEtcXbar0Coco2RkXBARA1_InputAdcEtcXbar0Coco3SkXBARA1_InputAdcEtcXbar1Coco0TkXBARA1_InputAdcEtcXbar1Coco1UkXBARA1_InputAdcEtcXbar1Coco2VkXBARA1_InputAdcEtcXbar1Coco3WkXBARB2_InputLogicLowkXBARB2_InputLogicHighkXBARB2_InputRESERVED2kXBARB2_InputRESERVED3kXBARB2_InputRESERVED4kXBARB2_InputRESERVED5kXBARB2_InputAcmp1OutkXBARB2_InputAcmp2OutkXBARB2_InputAcmp3OutkXBARB2_InputAcmp4Out kXBARB2_InputRESERVED10 kXBARB2_InputRESERVED11 kXBARB2_InputQtimer3Tmr0Output kXBARB2_InputQtimer3Tmr1Output kXBARB2_InputQtimer3Tmr2OutputkXBARB2_InputQtimer3Tmr3OutputkXBARB2_InputQtimer4Tmr0OutputkXBARB2_InputQtimer4Tmr1OutputkXBARB2_InputQtimer4Tmr2OutputkXBARB2_InputQtimer4Tmr3OutputkXBARB2_InputFlexpwm1Pwm1OutTrig01kXBARB2_InputFlexpwm1Pwm2OutTrig01kXBARB2_InputFlexpwm1Pwm3OutTrig01kXBARB2_InputFlexpwm1Pwm4OutTrig01kXBARB2_InputFlexpwm2Pwm1OutTrig01kXBARB2_InputFlexpwm2Pwm2OutTrig01kXBARB2_InputFlexpwm2Pwm3OutTrig01kXBARB2_InputFlexpwm2Pwm4OutTrig01kXBARB2_InputFlexpwm3Pwm1OutTrig01kXBARB2_InputFlexpwm3Pwm2OutTrig01kXBARB2_InputFlexpwm3Pwm3OutTrig01kXBARB2_InputFlexpwm3Pwm4OutTrig01kXBARB2_InputFlexpwm4Pwm1OutTrig01 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kXBARB3_InputFlexpwm4Pwm2OutTrig01!kXBARB3_InputFlexpwm4Pwm3OutTrig01"kXBARB3_InputFlexpwm4Pwm4OutTrig01#kXBARB3_InputPitTrigger0$kXBARB3_InputPitTrigger1%kXBARB3_InputAdcEtcXbar0Coco0&kXBARB3_InputAdcEtcXbar0Coco1'kXBARB3_InputAdcEtcXbar0Coco2(kXBARB3_InputAdcEtcXbar0Coco3)kXBARB3_InputAdcEtcXbar1Coco0*kXBARB3_InputAdcEtcXbar1Coco1+kXBARB3_InputAdcEtcXbar1Coco2,kXBARB3_InputAdcEtcXbar1Coco3-kXBARB3_InputEnc1PosMatch.kXBARB3_InputEnc2PosMatch/kXBARB3_InputEnc3PosMatch0kXBARB3_InputEnc4PosMatch1kXBARB3_InputDmaDone02kXBARB3_InputDmaDone13kXBARB3_InputDmaDone24kXBARB3_InputDmaDone35kXBARB3_InputDmaDone46kXBARB3_InputDmaDone57kXBARB3_InputDmaDone68kXBARB3_InputDmaDone79Pxbar_input_signal_tX_xbar_output_signalkXBARA1_OutputDmaChMuxReq30kXBARA1_OutputDmaChMuxReq31kXBARA1_OutputDmaChMuxReq94kXBARA1_OutputDmaChMuxReq95kXBARA1_OutputIomuxXbarInout04kXBARA1_OutputIomuxXbarInout05kXBARA1_OutputIomuxXbarInout06kXBARA1_OutputIomuxXbarInout07kXBARA1_OutputIomuxXbarInout08kXBARA1_OutputIomuxXbarInout09 kXBARA1_OutputIomuxXbarInout10 kXBARA1_OutputIomuxXbarInout11 kXBARA1_OutputIomuxXbarInout12 kXBARA1_OutputIomuxXbarInout13 kXBARA1_OutputIomuxXbarInout14kXBARA1_OutputIomuxXbarInout15kXBARA1_OutputIomuxXbarInout16kXBARA1_OutputIomuxXbarInout17kXBARA1_OutputIomuxXbarInout18kXBARA1_OutputIomuxXbarInout19kXBARA1_OutputAcmp1SamplekXBARA1_OutputAcmp2SamplekXBARA1_OutputAcmp3SamplekXBARA1_OutputAcmp4SamplekXBARA1_OutputRESERVED24kXBARA1_OutputRESERVED25kXBARA1_OutputFlexpwm1Exta0kXBARA1_OutputFlexpwm1Exta1kXBARA1_OutputFlexpwm1Exta2kXBARA1_OutputFlexpwm1Exta3kXBARA1_OutputFlexpwm1ExtSync0kXBARA1_OutputFlexpwm1ExtSync1kXBARA1_OutputFlexpwm1ExtSync2 kXBARA1_OutputFlexpwm1ExtSync3!kXBARA1_OutputFlexpwm1ExtClk"kXBARA1_OutputFlexpwm1Fault0#kXBARA1_OutputFlexpwm1Fault1$kXBARA1_OutputFlexpwm1234Fault2%kXBARA1_OutputFlexpwm1234Fault3&kXBARA1_OutputFlexpwm1ExtForce'kXBARA1_OutputFlexpwm234Exta0(kXBARA1_OutputFlexpwm234Exta1)kXBARA1_OutputFlexpwm234Exta2*kXBARA1_OutputFlexpwm234Exta3+kXBARA1_OutputFlexpwm2ExtSync0,kXBARA1_OutputFlexpwm2ExtSync1-kXBARA1_OutputFlexpwm2ExtSync2.kXBARA1_OutputFlexpwm2ExtSync3/kXBARA1_OutputFlexpwm234ExtClk0kXBARA1_OutputFlexpwm2Fault01kXBARA1_OutputFlexpwm2Fault12kXBARA1_OutputFlexpwm2ExtForce3kXBARA1_OutputFlexpwm3ExtSync04kXBARA1_OutputFlexpwm3ExtSync15kXBARA1_OutputFlexpwm3ExtSync26kXBARA1_OutputFlexpwm3ExtSync37kXBARA1_OutputFlexpwm3Fault08kXBARA1_OutputFlexpwm3Fault19kXBARA1_OutputFlexpwm3ExtForce:kXBARA1_OutputFlexpwm4ExtSync0;kXBARA1_OutputFlexpwm4ExtSync1<kXBARA1_OutputFlexpwm4ExtSync2=kXBARA1_OutputFlexpwm4ExtSync3>kXBARA1_OutputFlexpwm4Fault0?kXBARA1_OutputFlexpwm4Fault1@kXBARA1_OutputFlexpwm4ExtForceAkXBARA1_OutputEnc1PhaseAInputBkXBARA1_OutputEnc1PhaseBInputCkXBARA1_OutputEnc1IndexDkXBARA1_OutputEnc1HomeEkXBARA1_OutputEnc1TriggerFkXBARA1_OutputEnc2PhaseAInputGkXBARA1_OutputEnc2PhaseBInputHkXBARA1_OutputEnc2IndexIkXBARA1_OutputEnc2HomeJkXBARA1_OutputEnc2TriggerKkXBARA1_OutputEnc3PhaseAInputLkXBARA1_OutputEnc3PhaseBInputMkXBARA1_OutputEnc3IndexNkXBARA1_OutputEnc3HomeOkXBARA1_OutputEnc3TriggerPkXBARA1_OutputEnc4PhaseAInputQkXBARA1_OutputEnc4PhaseBInputRkXBARA1_OutputEnc4IndexSkXBARA1_OutputEnc4HomeTkXBARA1_OutputEnc4TriggerUkXBARA1_OutputQtimer1Tmr0InputVkXBARA1_OutputQtimer1Tmr1InputWkXBARA1_OutputQtimer1Tmr2InputXkXBARA1_OutputQtimer1Tmr3InputYkXBARA1_OutputQtimer2Tmr0InputZkXBARA1_OutputQtimer2Tmr1Input[kXBARA1_OutputQtimer2Tmr2Input\kXBARA1_OutputQtimer2Tmr3Input]kXBARA1_OutputQtimer3Tmr0Input^kXBARA1_OutputQtimer3Tmr1Input_kXBARA1_OutputQtimer3Tmr2Input`kXBARA1_OutputQtimer3Tmr3InputakXBARA1_OutputQtimer4Tmr0InputbkXBARA1_OutputQtimer4Tmr1InputckXBARA1_OutputQtimer4Tmr2InputdkXBARA1_OutputQtimer4Tmr3InputekXBARA1_OutputEwmEwmInfkXBARA1_OutputAdcEtcXbar0Trig0gkXBARA1_OutputAdcEtcXbar0Trig1hkXBARA1_OutputAdcEtcXbar0Trig2ikXBARA1_OutputAdcEtcXbar0Trig3jkXBARA1_OutputAdcEtcXbar1Trig0kkXBARA1_OutputAdcEtcXbar1Trig1lkXBARA1_OutputAdcEtcXbar1Trig2mkXBARA1_OutputAdcEtcXbar1Trig3nkXBARA1_OutputLpi2c1TrgInputokXBARA1_OutputLpi2c2TrgInputpkXBARA1_OutputLpi2c3TrgInputqkXBARA1_OutputLpi2c4TrgInputrkXBARA1_OutputLpspi1TrgInputskXBARA1_OutputLpspi2TrgInputtkXBARA1_OutputLpspi3TrgInputukXBARA1_OutputLpspi4TrgInputvkXBARA1_OutputLpuart1TrgInputwkXBARA1_OutputLpuart2TrgInputxkXBARA1_OutputLpuart3TrgInputykXBARA1_OutputLpuart4TrgInputzkXBARA1_OutputLpuart5TrgInput{kXBARA1_OutputLpuart6TrgInput|kXBARA1_OutputLpuart7TrgInput}kXBARA1_OutputLpuart8TrgInput~kXBARA1_OutputFlexio1TriggerIn0kXBARA1_OutputFlexio1TriggerIn1kXBARA1_OutputFlexio2TriggerIn0kXBARA1_OutputFlexio2TriggerIn1kXBARB2_OutputAoi1In00kXBARB2_OutputAoi1In01kXBARB2_OutputAoi1In02kXBARB2_OutputAoi1In03kXBARB2_OutputAoi1In04kXBARB2_OutputAoi1In05kXBARB2_OutputAoi1In06kXBARB2_OutputAoi1In07kXBARB2_OutputAoi1In08kXBARB2_OutputAoi1In09 kXBARB2_OutputAoi1In10 kXBARB2_OutputAoi1In11 kXBARB2_OutputAoi1In12 kXBARB2_OutputAoi1In13 kXBARB2_OutputAoi1In14kXBARB2_OutputAoi1In15kXBARB3_OutputAoi2In00kXBARB3_OutputAoi2In01kXBARB3_OutputAoi2In02kXBARB3_OutputAoi2In03kXBARB3_OutputAoi2In04kXBARB3_OutputAoi2In05kXBARB3_OutputAoi2In06kXBARB3_OutputAoi2In07kXBARB3_OutputAoi2In08kXBARB3_OutputAoi2In09 kXBARB3_OutputAoi2In10 kXBARB3_OutputAoi2In11 kXBARB3_OutputAoi2In12 kXBARB3_OutputAoi2In13 kXBARB3_OutputAoi2In14kXBARB3_OutputAoi2In15Pxbar_output_signal_t r *Î\܍CHC҆#HSO# OR#$CFGC#DGCC#HGSC#LCVC#POFSC#TCALC#XtYYtIPADC_Type͆ *͐(TRIGn_CTRLC#TRIGn_COUNTERC#TRIGn_CHAIN_1_0C#TRIGn_CHAIN_3_2C# TRIGn_CHAIN_5_4C#TRIGn_CHAIN_7_6C#TRIGn_RESULT_1_0O#TRIGn_RESULT_3_2O#TRIGn_RESULT_5_4O# TRIGn_RESULT_7_6O#$*CTRLC#DONE0_1_IRQC#DONE2_ERR_IRQC#DMA_CTRLC# dTRIG#PADC_ETC_TypeM *TMPRC#ߑ:;RESERVED_0ӈ#OPACRC#@OPACR1C#DOPACR2C#HOPACR3C#LOPACR4C#PPAIPSTZ_TypeÈ*BFCRT01o#BFCRT23o#tI*KBFCRTz#PAOI_Typeu*HCTRLC#ADDR_OFFSET0C#ADDR_OFFSET1C#AES_KEY0_W0C# AES_KEY0_W1C#AES_KEY0_W2C#AES_KEY0_W3C#STATUSC#CTR_NONCE0_W0C# CTR_NONCE0_W1C#$CTR_NONCE0_W2C#(CTR_NONCE0_W3C#,CTR_NONCE1_W0C#0CTR_NONCE1_W1C#4CTR_NONCE1_W2C#8CTR_NONCE1_W3C#<REGION1_TOPC#@REGION1_BOTC#DPBEE_Type*ʖCSC#IDC#WORD0C#WORD1C# *MCRC#CTRL1C#TIMERC#:RESERVED_0u# RXMGMASKC#RX14MASKC#RX15MASKC#ECRC#ESR1C# IMASK2C#$IMASK1C#(IFLAG2C#,IFLAG1C#0CTRL2C#4ESR2O#8:RESERVED_1+#<CRCRO#DRXFGMASKC#HRXFIRO#L:/RESERVED_2r#P?MB#:RESERVED_3# ϙC?RXIMRŌ#:_RESERVED_4݌#GFWRC#PCAN_TypeJ*CCRC#:RESERVED_0,#CSRO#CCSRC# CACRRC#CBCDRC#CBCMRC#CSCMR1C#CSCMR2C# CSCDR1C#$CS1CDRC#(CS2CDRC#,CDCDRC#0:RESERVED_1ۍ#4CSCDR2C#8CSCDR3C#<:RESERVED_2#@CDHIPRO#H͜:RESERVED_3A#LCLPCRC#TCISRC#XCIMRC#\CCOSRC#`CGPRC#dCCGR0C#hCCGR1C#lCCGR2C#pCCGR3C#tCCGR4C#xCCGR5C#|CCGR6C#:RESERVED_4#CMEORC#PCCM_Type*ʨPLL_ARMC#PLL_ARM_SETC#PLL_ARM_CLRC#PLL_ARM_TOGC# PLL_USB1C#PLL_USB1_SETC#PLL_USB1_CLRC#PLL_USB1_TOGC#PLL_USB2C# PLL_USB2_SETC#$PLL_USB2_CLRC#(PLL_USB2_TOGC#,PLL_SYSC#0PLL_SYS_SETC#4PLL_SYS_CLRC#8PLL_SYS_TOGC#<PLL_SYS_SSC#@: RESERVED_0x#DPLL_SYS_NUMC#P: RESERVED_1#TPLL_SYS_DENOMC#`: RESERVED_2ܐ#dPLL_AUDIOC#pPLL_AUDIO_SETC#tPLL_AUDIO_CLRC#xPLL_AUDIO_TOGC#|PLL_AUDIO_NUMC#: RESERVED_3`#PLL_AUDIO_DENOMC#: RESERVED_4#PLL_VIDEOC#PLL_VIDEO_SETC#PLL_VIDEO_CLRC#PLL_VIDEO_TOGC#PLL_VIDEO_NUMC#: RESERVED_5 #PLL_VIDEO_DENOMC#:RESERVED_6W#PLL_ENETC#PLL_ENET_SETC#PLL_ENET_CLRC#PLL_ENET_TOGC#PFD_480C#PFD_480_SETC#PFD_480_CLRC#PFD_480_TOGC#PFD_528C#PFD_528_SETC#PFD_528_CLRC#PFD_528_TOGC#:?RESERVED_7^#MISC0C#MISC0_SETC#MISC0_CLRC#MISC0_TOGC#MISC1C#MISC1_SETC#MISC1_CLRC#MISC1_TOGC#MISC2C#MISC2_SETC#MISC2_CLRC#MISC2_TOGC#PCCM_ANALOG_Type8*CR0#CR1#FPR#SCR#DACCR#MUXCR#t:PCMP_Typeb**PCSICR1C#CSICR2C#CSICR3C#CSISTATFIFOO# CSIRFIFOO#CSIRXCNTC#CSISRC#:RESERVED_04#CSIDMASA_STATFIFOC# CSIDMATS_STATFIFOC#$CSIDMASA_FB1C#(CSIDMASA_FB2C#,CSIFBUF_PARAC#0CSIIMAG_PARAC#4:RESERVED_1ԕ#8CSICR18C#HCSICR19C#LPCSI_TypeŔ+*ǭCCSL(#ʬ:RESERVED_0=#HP0C#:RESERVED_1i#SAC#:RESERVED_2#HPCONTROL0C#PCSU_Type".*REG0C#REG1C#REG2C#REG3C# PDCDC_Typeؖ0*CTRLC#: RESERVED_02#STATC#: RESERVED_1\#CHANNELCTRLC# : RESERVED_2#$CAPABILITY0C#0ʯ: RESERVED_3#4CAPABILITY1O#@: RESERVED_4#DCONTEXTC#P: RESERVED_5#TKEYC#`Ѱ: RESERVED_6E#dKEYDATAC#p: RESERVED_7r#tPACKET0O#: RESERVED_8#PACKET1O#۱: RESERVED_9Ϙ#PACKET2O#: RESERVED_10#PACKET3O#: RESERVED_11.#PACKET4O#: RESERVED_12^#PACKET5O#: RESERVED_13#PACKET6O#ʳ:RESERVED_14#CH0CMDPTRC#: RESERVED_15#CH0SEMAC#: RESERVED_16 #CH0STATC#ܴ: RESERVED_17P#CH0OPTSC#: RESERVED_18#CH1CMDPTRC#: RESERVED_19#CH1SEMAC#: RESERVED_20#CH1STATC#: RESERVED_21#CH1OPTSC#ζ: RESERVED_22B#CH2CMDPTRC#: RESERVED_23t#CH2SEMAC#: RESERVED_24#CH2STATC#: RESERVED_25ԛ#CH2OPTSC#: RESERVED_26#CH3CMDPTRC#¸: RESERVED_276#CH3SEMAC#: RESERVED_28f#CH3STATC#: RESERVED_29#CH3OPTSC#ӹ:RESERVED_30Ɯ#DBGSELECTC#: RESERVED_31#DBGDATAO#: RESERVED_32)#PAGETABLEC#: RESERVED_33[#VERSIONO#PDCP_Type 2SڻNBYTES_MLNOCNBYTES_MLOFFNOCNBYTES_MLOFFYESCSCITER_ELINKNOoCITER_ELINKYESoSBITER_ELINKNOoBITER_ELINKYESo* SADDRC#SOFFo#ATTRo##SLASTC# DADDRC#DOFFo#ڝ#DLAST_SGAC#CSRo##*(CRC#ESO#۽:RESERVED_0Ϟ#ERQC# :RESERVED_1#EEIC#CEEI#SEEI#CERQ#SERQ#CDNE#SSRT#CERR#CINT#:RESERVED_2# INTC#$:RESERVED_3#(ERRC#,߿:RESERVED_4ӟ#0HRSO#4: RESERVED_5#8EARSC#D:RESERVED_6&#HDCHPRI3#DCHPRI2#DCHPRI1#DCHPRI0#DCHPRI7#DCHPRI6#DCHPRI5#DCHPRI4#DCHPRI11#DCHPRI10#DCHPRI9#DCHPRI8#DCHPRI15#DCHPRI14#DCHPRI13#DCHPRI12#DCHPRI19#DCHPRI18#DCHPRI17#DCHPRI16#DCHPRI23#DCHPRI22#DCHPRI21#DCHPRI20#DCHPRI27#DCHPRI26#DCHPRI25#DCHPRI24#DCHPRI31#DCHPRI30#DCHPRI29#DCHPRI28#:RESERVED_7[#0TCD{# PDMA_Type7*CCHCFG#PDMAMUX_TypeB*(CTRLo#FILTo#WTRo#POSDo#POSDHգ#REVo# REVHգ# UPOSo#LPOSo#UPOSHգ#LPOSHգ#UINITo#LINITo#IMRգ#TSTo#CTRL2o#UMODo# LMODo#"UCOMPo#$LCOMPo#&ItϣPENC_TypeբB*TCSRC#TCCRC#* :RESERVED_0#EIRC#EIMRC#:RESERVED_1C# RDARC#TDARC#: RESERVED_2y#ECRC#$:RESERVED_3#(MMFRC#@MSCRC#D:RESERVED_4ؤ#HMIBCC#d:RESERVED_5#hRCRC#:;RESERVED_6,#TCRC#:RESERVED_7W#PALRC#PAURC#OPDC#TXICC#: RESERVED_8#RXICC#:RESERVED_9ե#IAURC#IALRC#GAURC#GALRC#:RESERVED_10(#TFWRC#:7RESERVED_11U#RDSRC#TDSRC#MRBRC#:RESERVED_12#RSFLC#RSEMC#RAEMC#RAFLC#TSEMC#TAEMC#TAFLC#TIPGC#FTRLC#: RESERVED_131#TACCC#RACCC#:7RESERVED_14k#RMON_T_DROPY#RMON_T_PACKETSO#RMON_T_BC_PKTO#RMON_T_MC_PKTO#RMON_T_CRC_ALIGNO#RMON_T_UNDERSIZEO#RMON_T_OVERSIZEO#RMON_T_FRAGO#RMON_T_JABO#RMON_T_COLO#RMON_T_P64O#RMON_T_P65TO127O#RMON_T_P128TO255O#RMON_T_P256TO511O#RMON_T_P512TO1023O#RMON_T_P1024TO2047O#RMON_T_P_GTE2048O#RMON_T_OCTETSO#IEEE_T_DROPY#IEEE_T_FRAME_OKO#IEEE_T_1COLO#IEEE_T_MCOLO#IEEE_T_DEFO#IEEE_T_LCOLO#IEEE_T_EXCOLO#IEEE_T_MACERRO#IEEE_T_CSERRO#IEEE_T_SQEO#IEEE_T_FDXFCO#IEEE_T_OCTETS_OKO#: RESERVED_15'#RMON_R_PACKETSO#RMON_R_BC_PKTO#RMON_R_MC_PKTO#RMON_R_CRC_ALIGNO#RMON_R_UNDERSIZEO#RMON_R_OVERSIZEO#RMON_R_FRAGO#RMON_R_JABO#RMON_R_RESVD_0Y#RMON_R_P64O#RMON_R_P65TO127O#RMON_R_P128TO255O#RMON_R_P256TO511O#RMON_R_P512TO1023O#RMON_R_P1024TO2047O#RMON_R_P_GTE2048O#RMON_R_OCTETSO#IEEE_R_DROPO#IEEE_R_FRAME_OKO#IEEE_R_CRCO#IEEE_R_ALIGNO#IEEE_R_MACERRO#IEEE_R_FDXFCO#IEEE_R_OCTETS_OKO#:RESERVED_16m#ATCRC#ATVRC#ATOFFC#ATPERC#ATCORC#ATINCC#ATSTMPO#:RESERVED_17#TGSRC# CHANNEL# PENET_TypeF*CTRL#SERV#CMPL#CMPH#CLKCTRL#CLKPRESCALER#PEWM_TypeJL*VERIDO#PARAMO#CTRLC#PINO# SHIFTSTATC#SHIFTERRC#TIMSTATC#:RESERVED_0#SHIFTSIENC# SHIFTEIENC#$TIMIENC#(:RESERVED_1i#,SHIFTSDENC#0: RESERVED_2#4SHIFTSTATEC#@:;RESERVED_3Ȯ#DCSHIFTCTL#:oRESERVED_4#CSHIFTCFG #:RESERVED_5;#CSHIFTBUF[#:oRESERVED_6v#CSHIFTBUFBIS#:oRESERVED_7#CSHIFTBUFBYSү#:oRESERVED_8#CSHIFTBUFBBS#:oRESERVED_9-#CTIMCTLL#:oRESERVED_10e#CTIMCFG# :oRESERVED_11# CTIMCMP# :RESERVED_12װ# CSHIFTBUFNBS# :oRESERVED_13# CSHIFTBUFHWS6#:oRESERVED_14T#CSHIFTBUFNISt#PFLEXIO_TypeM*TCM_CTRLC#OCRAM_MAGIC_ADDRC#DTCM_MAGIC_ADDRC#ITCM_MAGIC_ADDRC# INT_STATUSC#INT_STAT_ENC#INT_SIG_ENC#PFLEXRAM_TypeO*MCR0C#MCR1C#MCR2C#AHBCRC# INTENC#INTRC#LUTKEYC#LUTCRC#CAHBRXBUFCR0# :/RESERVED_0ײ#0CFLSHCR0#`CFLSHCR1#pCFLSHCR2'#:RESERVED_1A#FLSHCR4C#:RESERVED_2p#IPCR0C#IPCR1C#:RESERVED_3#IPCMDC#:RESERVED_4س#IPRXFCRC#IPTXFCRC#CDLLCR#:RESERVED_5/#STS0O#STS1O#STS2O#AHBSPNDSTSO#IPRXFSTSO#IPTXFSTSO#:RESERVED_6#ORFDRɴ#CTFDR#C?LUT#PFLEXSPI_TypeOQ*<CNTRC#:RESERVED_04#CIMRR#OISRg#: RESERVED_1|#(IMR5C#4ISR5O#8PGPC_Type#U* DRC#GDIRC#PSRO#ICR1C# ICR2C#IMRC#ISRC#EDGE_SELC#PGPIO_TypeĵU*(CRC#PRC#SRC#IRC# COCRh#OICR}#CNTO#$PGPT_Type;W*VERIDO#PARAMO#TCSRC#TCR1C# TCR2C#TCR3C#TCR4C#TCR5C#CTDR# :RESERVED_0,#0OTFRJ#@:RESERVED_1_#PTMRC#`:#RESERVED_2#dRCSRC#RCR1C#RCR2C#RCR3C#RCR4C#RCR5C#ORDR#:RESERVED_3 #ORFR)#:RESERVED_4?#RMRC#PI2S_TypeY* :RESERVED_0#C{SW_MUX_CTL_PAD#C{SW_PAD_CTL_PAD#CSELECT_INPUT#PIOMUXC_Type|\*hGPR0Y#GPR1C#GPR2C#GPR3C# GPR4C#GPR5C#GPR6C#GPR7C#GPR8C# GPR9Y#$GPR10C#(GPR11C#,GPR12C#0GPR13C#4GPR14C#8GPR15Y#<GPR16C#@GPR17C#DGPR18C#HGPR19C#LGPR20C#PGPR21C#TGPR22C#XGPR23C#\GPR24C#`GPR25C#dPIOMUXC_GPR_Type]*$SW_MUX_CTL_PAD_WAKEUPC#SW_MUX_CTL_PAD_PMIC_ON_REQC#SW_MUX_CTL_PAD_PMIC_STBY_REQC#SW_PAD_CTL_PAD_TEST_MODEC# SW_PAD_CTL_PAD_POR_BC#SW_PAD_CTL_PAD_ONOFFC#SW_PAD_CTL_PAD_WAKEUPC#SW_PAD_CTL_PAD_PMIC_ON_REQC#SW_PAD_CTL_PAD_PMIC_STBY_REQC# PIOMUXC_SNVS_Typec*GPR0Y#GPR1Y#GPR2Y#GPR3C# PIOMUXC_SNVS_GPR_Typed*KPCRo#KPSRo#KDDRo#KPDRo#PKPP_Typee*@PIGEON_0C#: RESERVED_0t#PIGEON_1C#: RESERVED_1#PIGEON_2C# :RESERVED_2м#$*CTRLC#CTRL_SETC#CTRL_CLRC#CTRL_TOGC# CTRL1C#CTRL1_SETC#CTRL1_CLRC#CTRL1_TOGC#CTRL2C# CTRL2_SETC#$CTRL2_CLRC#(CTRL2_TOGC#,TRANSFER_COUNTC#0: RESERVED_0ǽ#4CUR_BUFC#@: RESERVED_1#DNEXT_BUFC#P:RESERVED_2"#TVDCTRL0C#pVDCTRL0_SETC#tVDCTRL0_CLRC#xVDCTRL0_TOGC#|VDCTRL1C#: RESERVED_3#VDCTRL2C#: RESERVED_4Ǿ#VDCTRL3C#: RESERVED_5#VDCTRL4C#:RESERVED_6%#BM_ERROR_STATC#: RESERVED_7[#CRC_STATC#: RESERVED_8#STATO#:KRESERVED_9#THRESC#:RESERVED_10#PIGEONCTRL0C#PIGEONCTRL0_SETC#PIGEONCTRL0_CLRC#PIGEONCTRL0_TOGC#PIGEONCTRL1C#PIGEONCTRL1_SETC#PIGEONCTRL1_CLRC#PIGEONCTRL1_TOGC#PIGEONCTRL2C#PIGEONCTRL2_SETC#PIGEONCTRL2_CLRC#PIGEONCTRL2_TOGC#:RESERVED_11#Ă_ PIGEON:#LUT_CTRLC#: RESERVED_12d#LUT0_ADDRC#: RESERVED_13#LUT0_DATAC#ԃ: RESERVED_14#LUT1_ADDRC#: RESERVED_15#LUT1_DATAC#PLCDIF_Typef*VERIDO#PARAMO#:RESERVED_0`#MCRC#MSRC#MIERC#MDERC#MCFGR0C# MCFGR1C#$MCFGR2C#(MCFGR3C#,:RESERVED_1#0MDMRC#@:RESERVED_2#DMCCR0C#Hņ:RESERVED_39#LMCCR1C#P:RESERVED_4d#TMFCRC#XMFSRO#\MTDRC#`: RESERVED_5#dMRDRO#p݇:RESERVED_6#tSCRC#SSRC#SIERC#SDERC#:RESERVED_7!#SCFGR1C#SCFGR2C#:RESERVED_8^#SAMRC#: RESERVED_9#SASRO#STARC#ω:RESERVED_10#STDRC#: RESERVED_11#SRDRO#PLPI2C_Type@o*xVERIDO#PARAMO#܊:RESERVED_0P#CRC#SRC#IERC#DERC#CFGR0C# CFGR1C#$:RESERVED_1#(DMR0C#0DMR1C#4:RESERVED_2#8CCRC#@:RESERVED_3#DFCRC#XFSRO#\TCRC#`TDRC#d:RESERVED_4[#hRSRO#pRDRO#tPLPSPI_Type1s*Ž0VERIDO#PARAMO#GLOBALC#PINCFGC# BAUDC#STATC#CTRLC#DATAC#MATCHC# MODIRC#$FIFOC#(WATERC#,PLPUART_Typeu* CTRLC#CTRL_SETC#CTRL_CLRC#CTRL_TOGC# TIMINGC#: RESERVED_0#DATAC# ܏: RESERVED_1#$READ_CTRLC#0: RESERVED_2#4READ_FUSE_DATAC#@: RESERVED_33#DSW_STICKYC#P: RESERVED_4b#TSCSC#`SCS_SETC#dSCS_CLRC#hSCS_TOGC#lđ:RESERVED_5#pVERSIONO#:kRESERVED_6#TIMING2C#:RESERVED_7#LOCKC#Β: RESERVED_8B#CFG0C#: RESERVED_9n#CFG1C#: RESERVED_10#CFG2C#ӓ: RESERVED_11#CFG3C#: RESERVED_12#CFG4C#: RESERVED_13!#CFG5C#ڔ: RESERVED_14N#CFG6C#: RESERVED_15{#MEM0C# : RESERVED_16# MEM1C# : RESERVED_17# MEM2C# : RESERVED_18# MEM3C# : RESERVED_19/# MEM4C# : RESERVED_20\# ANA0C# : RESERVED_21# ANA1C# —: RESERVED_22# ANA2C# :RESERVED_23# SRK0C# : RESERVED_24# SRK1C# ʘ: RESERVED_25># SRK2C# : RESERVED_26k# SRK3C# : RESERVED_27# SRK4C# љ: RESERVED_28# SRK5C# : RESERVED_29# SRK6C# : RESERVED_30# SRK7C# ؚ: RESERVED_31L# SJC_RESP0C# : RESERVED_32~# SJC_RESP1C# : RESERVED_33# MAC0C# : RESERVED_34# MAC1C# : RESERVED_35 # GP3C# œ:RESERVED_366# GP1C# : RESERVED_37b# GP2C# : RESERVED_38# SW_GP1C# ɝ: RESERVED_39# SW_GP20C# : RESERVED_40# SW_GP21C# : RESERVED_41# SW_GP22C# ٞ: RESERVED_42M# SW_GP23C# : RESERVED_43}# MISC_CONF0C# : RESERVED_44# MISC_CONF1C# : RESERVED_45# SRK_REVOKEC# POCOTP_TypeVy*:RESERVED_00#MEGA_CTRLC#MEGA_PUPSCRC#MEGA_PDNSCRC#MEGA_SRC#:oRESERVED_1#CPU_CTRLC#CPU_PUPSCRC#CPU_PDNSCRC#CPU_SRC#PPGC_Type*}*ȢLDVALC#CVALO#TCTRLC#TFLGC# *ңMCRC#:RESERVED_0Y#LTMR64HO#LTMR64LO#:RESERVED_1#CHANNEL#PPIT_TypeH~*:RESERVED_0#REG_1P1C#REG_1P1_SETC#REG_1P1_CLRC#REG_1P1_TOGC#REG_3P0C#REG_3P0_SETC#REG_3P0_CLRC#REG_3P0_TOGC#REG_2P5C#REG_2P5_SETC#REG_2P5_CLRC#REG_2P5_TOGC#REG_COREC#REG_CORE_SETC#REG_CORE_CLRC#REG_CORE_TOGC#MISC0C#MISC0_SETC#MISC0_CLRC#MISC0_TOGC#MISC1C#MISC1_SETC#MISC1_CLRC#MISC1_TOGC#MISC2C#MISC2_SETC#MISC2_CLRC#MISC2_TOGC#PPMU_Type*`CNTգ#INITo#CTRL2o#CTRLo#ۨ:RESERVED_0O#VAL0o# FRACVAL1o# VAL1o#FRACVAL2o#VAL2o#FRACVAL3o#VAL3o#FRACVAL4o#VAL4o#FRACVAL5o#VAL5o#FRCTRLo# OCTRLo#"STSo#$INTENo#&DMAENo#(TCTRLo#*ܪoDISMAPR#,DTCNT0o#0DTCNT1o#2CAPTCTRLAo#4CAPTCOMPAo#6CAPTCTRLBo#8CAPTCOMPBo#:CAPTCTRLXo#<CAPTCOMPXo#>CVAL0գ#@CVAL0CYCգ#BCVAL1գ#DCVAL1CYCգ#FCVAL2գ#HCVAL2CYCգ#JCVAL3գ#LCVAL3CYCգ#NCVAL4գ#PCVAL4CYCգ#RCVAL5գ#TCVAL5CYCգ#V:RESERVED_1#X*ɭSM#OUTENo#MASKo#SWCOUTo#DTSRCSELo#MCTRLo#MCTRL2o#FCTRLo#FSTSo#FFILTo#FTSTo#FCTRL2o#PPWM_Type*CTRLC#CTRL_SETC#CTRL_CLRC#CTRL_TOGC# STATC#STAT_SETC#STAT_CLRC#STAT_TOGC#OUT_CTRLC# OUT_CTRL_SETC#$OUT_CTRL_CLRC#(OUT_CTRL_TOGC#,OUT_BUFC#0: RESERVED_0\#4OUT_BUF2C#@: RESERVED_1#DOUT_PITCHC#Pű: RESERVED_2#TOUT_LRCC#`: RESERVED_3#dOUT_PS_ULCC#p: RESERVED_4#tOUT_PS_LRCC#Ӳ: RESERVED_5G#OUT_AS_ULCC#: RESERVED_6y#OUT_AS_LRCC#: RESERVED_7#PS_CTRLC#PS_CTRL_SETC#PS_CTRL_CLRC#PS_CTRL_TOGC#PS_BUFC#: RESERVED_8%#PS_UBUFC#: RESERVED_9T#PS_VBUFC#: RESERVED_10#PS_PITCHC#: RESERVED_11#PS_BACKGROUNDC#: RESERVED_12#PS_SCALEC#: RESERVED_13#PS_OFFSETC#ٶ: RESERVED_14M#PS_CLRKEYLOWC#: RESERVED_15#PS_CLRKEYHIGHC#ķ: RESERVED_16#AS_CTRLC#: RESERVED_17#AS_BUFC#: RESERVED_18#AS_PITCHC#Ը: RESERVED_19H#AS_CLRKEYLOWC#: RESERVED_20}#AS_CLRKEYHIGHC#: RESERVED_21#CSC1_COEF0C#: RESERVED_22#CSC1_COEF1C#: RESERVED_23#CSC1_COEF2C#ٺ:RESERVED_24L#POWERC#:RESERVED_25{#NEXTC#:;RESERVED_26#PORTER_DUFF_CTRLC#PPXP_Type*Ž:RESERVED_0#CROMPATCHD#ROMPATCHCNTLC#ROMPATCHENHY#ROMPATCHENLC#CROMPATCHAu#:RESERVED_1#ROMPATCHSRC#PROMC_Type*CSC#CNTC#TOVALC#WINC# PRTWDOG_Type*MCRC#IOCRC#BMCR0C#BMCR1C# CBRW#:RESERVED_0k#4INTENC#8INTRC#<SDRAMCR0C#@SDRAMCR1C#DSDRAMCR2C#HSDRAMCR3C#LNANDCR0C#PNANDCR1C#TNANDCR2C#XNANDCR3C#\NORCR0C#`NORCR1C#dNORCR2C#hNORCR3Y#lSRAMCR0C#pSRAMCR1C#tSRAMCR2C#xSRAMCR3Y#|DBICR0C#DBICR1C#:RESERVED_1#IPCR0C#IPCR1C#IPCR2C#IPCMDC#IPTXDATC#: RESERVED_2#IPRXDATO#: RESERVED_3J#STS0O#STS1Y#STS2O#STS3Y#STS4Y#STS5Y#STS6Y#STS7Y#STS8Y#STS9Y#STS10Y#STS11Y#STS12O#STS13Y#STS14Y#STS15Y#PSEMC_Type *HPLRC#HPCOMRC#HPCRC#HPSICRC# HPSVCRC#HPSRC#HPSVSRC#HPHACIVRC#HPHACRO# HPRTCMRC#$HPRTCLRC#(HPTAMRC#,HPTALRC#0LPLRC#4LPCRC#8LPMKCRC#<LPSVCRC#@:RESERVED_0[#DLPTDCRC#HLPSRC#LLPSRTCMRC#PLPSRTCLRC#TLPTARC#XLPSMCMRO#\LPSMCLRO#`LPPGDRC#dLPGPR0_LEGACY_ALIASC#hCLPZMKR#l:RESERVED_1#CLPGPR_ALIAS>#:_RESERVED_2\#CLPGPR{#:RESERVED_3#HPVIDR1O#HPVIDR2O#PSNVS_TypemSSICCSISO*TSCRC#SRCDC#SRPCC#SIEC# #SRLO#SRRO#SRCSHO#SRCSLO# SRUO#$SRQO#(STLC#,STRC#0STCSCHC#4STCSCLC#8:RESERVED_0#<SRFMO#D:RESERVED_1#HSTCC#PPSPDIF_Type*HSCRC#SBMR1O#SRSRC#:RESERVED_0A# SBMR2O#C GPRl# PSRC_Type*:RESERVED_0#TEMPSENSE0C#TEMPSENSE0_SETC#TEMPSENSE0_CLRC#TEMPSENSE0_TOGC#TEMPSENSE1C#TEMPSENSE1_SETC#TEMPSENSE1_CLRC#TEMPSENSE1_TOGC#:RESERVED_1i#TEMPSENSE2C#TEMPSENSE2_SETC#TEMPSENSE2_CLRC#TEMPSENSE2_TOGC#PTEMPMON_Type* COMP1o#COMP2o#CAPTo#LOADo#HOLDo#CNTRo# CTRLo# SCTRLo#CMPLD1o#CMPLD2o#CSCTRLo#FILTo#DMAo#:RESERVED_0#ENBLo#*CHANNEL#PTMR_TypeSPKRMAXCPKRSQOSSBLIMCTOTSAMOSFRQCNTOFRQMAXCSSCMCOSCMLCSSCR1COSCR1LCSSCR2COSCR2LCSSCR3COSCR3LCSSCR4COSCR4LCSSCR5COSCR5LCSSCR6PCOSCR6PLC*MCTLC#SCMISCC#PKRRNGC## SDCTLC##FRQMINC#4#P# h#$#(#,#0#4#8STATUSO#<OENT#@PKRCNT10O#PKRCNT32O#PKRCNT54O#PKRCNT76O#PKRCNT98O#PKRCNTBAO#PKRCNTDCO#PKRCNTFEO#SEC_CFGC#INT_CTRLC#INT_MASKC#INT_STATUSO#:?RESERVED_0#VID1O#VID2O#PTRNG_Typeŧ*BASIC_SETTINGC#: RESERVED_0#PS_INPUT_BUFFER_ADDRC#: RESERVED_11#FLOW_CONTROLC# : RESERVED_2c#$MEASEURE_VALUEO#0: RESERVED_3#4INT_ENC#@: RESERVED_4#DINT_SIG_ENC#P: RESERVED_5#TINT_STATUSC#`: RESERVED_6##dDEBUG_MODEC#p: RESERVED_7S#tDEBUG_MODE2C#PTSC_TypeSDEVICEADDRCPERIODICLISTBASECSASYNCLISTADDRCENDPTLISTADDRC*IDO#HWGENERALO#HWHOSTO#HWDEVICEO# HWTXBUFO#HWRXBUFO#:gRESERVED_0I#GPTIMER0LDC#GPTIMER0CTRLC#GPTIMER1LDC#GPTIMER1CTRLC#SBUSCFGC#:kRESERVED_1#CAPLENGTH#:RESERVED_2#HCIVERSIONգ#HCSPARAMSO#HCCPARAMSO#:RESERVED_3N#DCIVERSIONգ#:RESERVED_4#DCCPARAMSO#:RESERVED_5#USBCMDC#USBSTSC#USBINTRC#FRINDEXC#:RESERVED_6###:RESERVED_7?#BURSTSIZEC#TXFILLTUNINGC#:RESERVED_8#ENDPTNAKC#ENDPTNAKENC#CONFIGFLAGO#PORTSC1C#:RESERVED_9#OTGSCC#USBMODEC#ENDPTSETUPSTATC#ENDPTPRIMEC#ENDPTFLUSHC#ENDPTSTATO#ENDPTCOMPLETEC#ENDPTCTRL0C#CENDPTCTRL#:tPUSB_Type*:RESERVED_0#USB_OTGn_CTRLC#:RESERVED_1#USB_OTGn_PHY_CTRL_0C#PUSBNC_Type*PWDC#PWD_SETC#PWD_CLRC#PWD_TOGC# TXC#TX_SETC#TX_CLRC#TX_TOGC#RXC# RX_SETC#$RX_CLRC#(RX_TOGC#,CTRLC#0CTRL_SETC#4CTRL_CLRC#8CTRL_TOGC#<STATUSC#@: RESERVED_0T#DDEBUGrC#PDEBUG_SETC#TDEBUG_CLRC#XDEBUG_TOGC#\DEBUG0_STATUSO#`: RESERVED_1#dDEBUG1C#pDEBUG1_SETC#tDEBUG1_CLRC#xDEBUG1_TOGC#|VERSIONO#PUSBPHY_Typed*`VBUS_DETECTC#VBUS_DETECT_SETC#VBUS_DETECT_CLRC#VBUS_DETECT_TOGC# CHRG_DETECTC#CHRG_DETECT_SETC#CHRG_DETECT_CLRC#CHRG_DETECT_TOGC#VBUS_DETECT_STATO# : RESERVED_0#$CHRG_DETECT_STATO#0:RESERVED_1S#4MISCC#PMISC_SETC#TMISC_CLRC#XMISC_TOGC#\*:RESERVED_0#PINSTANCE#DIGPROGO#PUSB_ANALOG_Type*DS_ADDRC#BLK_ATTC#CMD_ARGC#CMD_XFR_TYPC# CMD_RSP0O#CMD_RSP1O#CMD_RSP2O#CMD_RSP3O#DATA_BUFF_ACC_PORTC# PRES_STATEO#$PROT_CTRLC#(SYS_CTRLC#,INT_STATUSC#0INT_STATUS_ENC#4INT_SIGNAL_ENC#8AUTOCMD12_ERR_STATUSC#<HOST_CTRL_CAPC#@WTMK_LVLC#DMIX_CTRLC#H:RESERVED_0x#LFORCE_EVENTC#PADMA_ERR_STATUSO#TADMA_SYS_ADDRC#X:RESERVED_1#\DLL_CTRLC#`DLL_STATUSO#dCLK_TUNE_CTRL_STATUSC#h:SRESERVED_21#lVEND_SPECC#MMC_BOOTC#VEND_SPEC2C#TUNING_CTRLC#PUSDHC_Type* WCRo#WSRo#WRSRգ#WICRo#WMCRo#PWDOG_Type*SEL0o#SEL1o#SEL2o#SEL3o#SEL4o#SEL5o# SEL6o# SEL7o#SEL8o#SEL9o#SEL10o#SEL11o#SEL12o#SEL13o#SEL14o#SEL15o#SEL16o# SEL17o#"SEL18o#$SEL19o#&SEL20o#(SEL21o#*SEL22o#,SEL23o#.SEL24o#0SEL25o#2SEL26o#4SEL27o#6SEL28o#8SEL29o#:SEL30o#<SEL31o#>SEL32o#@SEL33o#BSEL34o#DSEL35o#FSEL36o#HSEL37o#JSEL38o#LSEL39o#NSEL40o#PSEL41o#RSEL42o#TSEL43o#VSEL44o#XSEL45o#ZSEL46o#\SEL47o#^SEL48o#`SEL49o#bSEL50o#dSEL51o#fSEL52o#hSEL53o#jSEL54o#lSEL55o#nSEL56o#pSEL57o#rSEL58o#tSEL59o#vSEL60o#xSEL61o#zSEL62o#|SEL63o#~SEL64o#SEL65o#CTRL0o#CTRL1o#PXBARA_Type*SEL0o#SEL1o#SEL2o#SEL3o#SEL4o#SEL5o# SEL6o# SEL7o#PXBARB_Type*:RESERVED_0 #MISC0C#MISC0_SETC#MISC0_CLRC#MISC0_TOGC#:RESERVED_1m#LOWPWR_CTRLC#LOWPWR_CTRL_SETC#LOWPWR_CTRL_CLRC#LOWPWR_CTRL_TOGC#:RESERVED_2#OSC_CONFIG0C#OSC_CONFIG0_SETC#OSC_CONFIG0_CLRC#OSC_CONFIG0_TOGC#OSC_CONFIG1C#OSC_CONFIG1_SETC#OSC_CONFIG1_CLRC#OSC_CONFIG1_TOGC#OSC_CONFIG2C#OSC_CONFIG2_SETC#OSC_CONFIG2_CLRC#OSC_CONFIG2_TOGC#PXTALOSC24M_Type| .\middleware\flexspi/fsl_flexspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash;<_Bool"YPflexspi_serial_clk_freq_ttPflexspi_read_sample_clk_tPflexspi_ipcmd_error_tPflexspi_lut_seq_tPflexspi_dll_time_t Pflexspi_mem_config_t# Pflexspi_operation_t(Pflexspi_xfer_tkFlexSpiClock_CoreClock kFlexSpiClock_AhbClock kFlexSpiClock_SerialRootClock kFlexSpiClock_IpgClock Pflexspi_clock_type_t_FlexSpiSerialClockFreqkFlexSpiSerialClk_30MHz kFlexSpiSerialClk_50MHz kFlexSpiSerialClk_60MHz kFlexSpiSerialClk_75MHz kFlexSpiSerialClk_80MHz kFlexSpiSerialClk_100MHz kFlexSpiSerialClk_133MHz kFlexSpiSerialClk_166MHz kFlexSpiSerialClk_200MHz kFlexSpiClk_SDR kFlexSpiClk_DDR  _FlashReadSampleClkSourcekFlexSPIReadSampleClk_LoopbackInternally kFlexSPIReadSampleClk_LoopbackFromDqsPad kFlexSPIReadSampleClk_LoopbackFromSckPad kFlexSPIReadSampleClk_ExternalInputFromDqsPad  _FlexSpiIpCmdErrorkFlexSpiIpCmdError_NoError kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode kFlexSpiIpCmdError_JumpOnCsInIpCmd kFlexSpiIpCmdError_UnknownOpCode kFlexSpiIpCmdError_SdrDummyInDdrSequence kFlexSpiIpCmdError_DDRDummyInSdrSequence kFlexSpiIpCmdError_InvalidAddress kFlexSpiIpCmdError_SequenceExecutionTimeout kFlexSpiIpCmdError_FlashBoundaryAcrosss  _flexspi_statuskStatus_FLEXSPI_SequenceExecutionTimeoutXkStatus_FLEXSPI_InvalidSequenceYkStatus_FLEXSPI_DeviceTimeoutZkFlexSpiMiscOffset_DiffClkEnable kFlexSpiMiscOffset_Ck2Enable kFlexSpiMiscOffset_ParallelEnable kFlexSpiMiscOffset_WordAddressableEnable kFlexSpiMiscOffset_SafeConfigFreqEnable kFlexSpiMiscOffset_PadSettingOverrideEnable kFlexSpiMiscOffset_DdrModeEnable kFlexSpiMiscOffset_UseValidTimeForAllFreq kFlexSpiDeviceType_SerialNOR kFlexSpiDeviceType_SerialNAND kFlexSpiDeviceType_SerialRAM kFlexSpiDeviceType_MCP_NOR_NAND kFlexSpiDeviceType_MCP_NOR_RAM kSerialFlash_1Pad kSerialFlash_2Pads kSerialFlash_4Pads kSerialFlash_8Pads )_lut_sequenceseqNum:#seqId:#reservedI#kDeviceConfigCmdType_Generic kDeviceConfigCmdType_QuadEnable kDeviceConfigCmdType_Spi2Xpi kDeviceConfigCmdType_Xpi2Spi kDeviceConfigCmdType_Spi2NoCmd kDeviceConfigCmdType_Reset *time_100ps:#delay_cells:#)_FlexSPIConfigtagY#versionY#reserved0Y#readSampleClkSrc:# dataHoldTime:# dataSetupTime:#columnAddressWidth:#deviceModeCfgEnable:#deviceModeType:#waitTimeCfgCommandsI#deviceModeSeq]#deviceModeArgY#configCmdEnable:#:configModeTypeb #]configCmdSeqs # reserved1Y#,YconfigCmdArgs #0reserved2Y#<controllerMiscOptionY#@deviceType:#DsflashPadType:#EserialClkFreq:#FlutCustomSeqEnable:#GYreserved3c #HsflashA1SizeY#PsflashA2SizeY#TsflashB1SizeY#XsflashB2SizeY#\csPadSettingOverrideY#`sclkPadSettingOverrideY#ddataPadSettingOverrideY#hdqsPadSettingOverrideY#ltimeoutInMsY#pcommandIntervalY#twdataValidTime #xbusyOffsetI#|busyBitPolarityI#~Y?lookupTable #] lutCustomSeq #Yreserved4 #_FlexSPIOperationTypekFlexSpiOperation_Command kFlexSpiOperation_Config kFlexSpiOperation_Write kFlexSpiOperation_Read kFlexSpiOperation_End )_FlexSpiXfer$operation#baseAddressY#seqIdY#seqNumY# isParallelModeEnable#txBuffer#txSizeY#rxBuffer#rxSizeY#  .\devices\MIMXRT1052\drivers\fsl_common.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashdA=_status_groupskStatusGroup_Generic kStatusGroup_FLASH kStatusGroup_LPSPI kStatusGroup_FLEXIO_SPI kStatusGroup_DSPI kStatusGroup_FLEXIO_UART kStatusGroup_FLEXIO_I2C kStatusGroup_LPI2C kStatusGroup_UART kStatusGroup_I2C kStatusGroup_LPSCI kStatusGroup_LPUART kStatusGroup_SPI kStatusGroup_XRDC kStatusGroup_SEMA42 kStatusGroup_SDHC kStatusGroup_SDMMC kStatusGroup_SAI kStatusGroup_MCG kStatusGroup_SCG kStatusGroup_SDSPI kStatusGroup_FLEXIO_I2S kStatusGroup_FLEXIO_MCULCD kStatusGroup_FLASHIAP kStatusGroup_FLEXCOMM_I2C kStatusGroup_I2S kStatusGroup_IUART kStatusGroup_CSI kStatusGroup_MIPI_DSI kStatusGroup_SDRAMC #kStatusGroup_POWER 'kStatusGroup_ENET (kStatusGroup_PHY )kStatusGroup_TRGMUX *kStatusGroup_SMARTCARD +kStatusGroup_LMEM ,kStatusGroup_QSPI -kStatusGroup_DMA 2kStatusGroup_EDMA 3kStatusGroup_DMAMGR 4kStatusGroup_FLEXCAN 5kStatusGroup_LTC 6kStatusGroup_FLEXIO_CAMERA 7kStatusGroup_LPC_SPI 8kStatusGroup_LPC_USART 9kStatusGroup_DMIC :kStatusGroup_SDIF ;kStatusGroup_SPIFI <kStatusGroup_OTP =kStatusGroup_MCAN >kStatusGroup_CAAM ?kStatusGroup_ECSPI @kStatusGroup_USDHC AkStatusGroup_LPC_I2C BkStatusGroup_DCP CkStatusGroup_MSCAN DkStatusGroup_ESAI EkStatusGroup_FLEXSPI FkStatusGroup_MMDC GkStatusGroup_MICFIL HkStatusGroup_SDMA IkStatusGroup_ICS JkStatusGroup_SPDIF KkStatusGroup_NOTIFIER bkStatusGroup_DebugConsole ckStatusGroup_SEMC dkStatusGroup_ApplicationRangeStart e_generic_statuskStatus_Success kStatus_Fail kStatus_ReadOnly kStatus_OutOfRange kStatus_InvalidArgument kStatus_Timeout kStatus_NoTransferInProgress Pstatus_t ; EnableIRQ$`interrupta__result; DisableIRQ$`interrupta__result; DisableGlobalIRQYa__resultY\regPrimaskY< EnableGlobalIRQ$Yprimask| middleware\flexspi\fsl_flexspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash0_Bool"YPflexspi_serial_clk_freq_trPflexspi_read_sample_clk_tPflexspi_ipcmd_error_tPflexspi_lut_seq_tPflexspi_dll_time_t Pflexspi_mem_config_t! Pflexspi_operation_t&Pflexspi_xfer_tkFlexSpiClock_CoreClock kFlexSpiClock_AhbClock kFlexSpiClock_SerialRootClock kFlexSpiClock_IpgClock Pflexspi_clock_type_t_FlexSpiSerialClockFreqkFlexSpiSerialClk_30MHz kFlexSpiSerialClk_50MHz kFlexSpiSerialClk_60MHz kFlexSpiSerialClk_75MHz kFlexSpiSerialClk_80MHz kFlexSpiSerialClk_100MHz kFlexSpiSerialClk_133MHz kFlexSpiSerialClk_166MHz kFlexSpiSerialClk_200MHz kFlexSpiClk_SDR kFlexSpiClk_DDR  _FlashReadSampleClkSourcekFlexSPIReadSampleClk_LoopbackInternally kFlexSPIReadSampleClk_LoopbackFromDqsPad kFlexSPIReadSampleClk_LoopbackFromSckPad kFlexSPIReadSampleClk_ExternalInputFromDqsPad  _FlexSpiIpCmdErrorkFlexSpiIpCmdError_NoError kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode kFlexSpiIpCmdError_JumpOnCsInIpCmd kFlexSpiIpCmdError_UnknownOpCode kFlexSpiIpCmdError_SdrDummyInDdrSequence kFlexSpiIpCmdError_DDRDummyInSdrSequence kFlexSpiIpCmdError_InvalidAddress kFlexSpiIpCmdError_SequenceExecutionTimeout kFlexSpiIpCmdError_FlashBoundaryAcrosss  _flexspi_statuskStatus_FLEXSPI_SequenceExecutionTimeoutXkStatus_FLEXSPI_InvalidSequenceYkStatus_FLEXSPI_DeviceTimeoutZkFlexSpiMiscOffset_DiffClkEnable kFlexSpiMiscOffset_Ck2Enable kFlexSpiMiscOffset_ParallelEnable kFlexSpiMiscOffset_WordAddressableEnable kFlexSpiMiscOffset_SafeConfigFreqEnable kFlexSpiMiscOffset_PadSettingOverrideEnable kFlexSpiMiscOffset_DdrModeEnable kFlexSpiMiscOffset_UseValidTimeForAllFreq kFlexSpiDeviceType_SerialNOR kFlexSpiDeviceType_SerialNAND kFlexSpiDeviceType_SerialRAM kFlexSpiDeviceType_MCP_NOR_NAND kFlexSpiDeviceType_MCP_NOR_RAM kSerialFlash_1Pad kSerialFlash_2Pads kSerialFlash_4Pads kSerialFlash_8Pads )_lut_sequenceseqNum:#seqId:#reservedI#kDeviceConfigCmdType_Generic kDeviceConfigCmdType_QuadEnable kDeviceConfigCmdType_Spi2Xpi kDeviceConfigCmdType_Xpi2Spi kDeviceConfigCmdType_Spi2NoCmd kDeviceConfigCmdType_Reset *time_100ps:#delay_cells:#)_FlexSPIConfigtagY#versionY#reserved0Y#readSampleClkSrc:# dataHoldTime:# dataSetupTime:#columnAddressWidth:#deviceModeCfgEnable:#deviceModeType:#waitTimeCfgCommandsI#deviceModeSeq[#deviceModeArgY#configCmdEnable:#:configModeType` #[configCmdSeqs # reserved1Y#,YconfigCmdArgs #0reserved2Y#<controllerMiscOptionY#@deviceType:#DsflashPadType:#EserialClkFreq:#FlutCustomSeqEnable:#GYreserved3a #HsflashA1SizeY#PsflashA2SizeY#TsflashB1SizeY#XsflashB2SizeY#\csPadSettingOverrideY#`sclkPadSettingOverrideY#ddataPadSettingOverrideY#hdqsPadSettingOverrideY#ltimeoutInMsY#pcommandIntervalY#tudataValidTime #xbusyOffsetI#|busyBitPolarityI#~Y?lookupTable #[ lutCustomSeq #Yreserved4#_FlexSPIOperationTypekFlexSpiOperation_Command kFlexSpiOperation_Config kFlexSpiOperation_Write kFlexSpiOperation_Read kFlexSpiOperation_End )_FlexSpiXfer$operation#baseAddressY#seqIdY#seqNumY# isParallelModeEnable#txBuffer#txSizeY#rxBuffer#rxSizeY#  middleware\flexspi_nor\flexspi_nor_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash<_flexspi_nor_statuskStatusGroup_FLEXSPINOR kStatus_FLEXSPINOR_ProgramFail NkStatus_FLEXSPINOR_EraseSectorFail!NkStatus_FLEXSPINOR_EraseAllFail"NkStatus_FLEXSPINOR_WaitTimeout#NkStatus_FlexSPINOR_NotSupported$NkStatus_FlexSPINOR_WriteAlignmentError%NkStatus_FlexSPINOR_CommandFailure&NkStatus_FlexSPINOR_SFDP_NotFound'NkStatus_FLEXSPINOR_Unsupported_SFDP_Version(NkStatus_FLEXSPINOR_Flash_NotFound)NkStatus_FLEXSPINOR_DTRRead_DummyProbeFailed*N kSerialNorCfgOption_Tag kSerialNorCfgOption_DeviceType_ReadSFDP_SDR kSerialNorCfgOption_DeviceType_ReadSFDP_DDR kSerialNorCfgOption_DeviceType_HyperFLASH1V8 kSerialNorCfgOption_DeviceType_HyperFLASH3V0 kSerialNorCfgOption_DeviceType_MacronixOctalDDR kSerialNorCfgOption_DeviceType_MacronixOctalSDR kSerialNorCfgOption_DeviceType_MicronOctalDDR kSerialNorCfgOption_DeviceType_MicronOctalSDR kSerialNorCfgOption_DeviceType_AdestoOctalDDR kSerialNorCfgOption_DeviceType_AdestoOctalSDR  kSerialNorQuadMode_NotConfig kSerialNorQuadMode_StatusReg1_Bit6 kSerialNorQuadMode_StatusReg2_Bit1 kSerialNorQuadMode_StatusReg2_Bit7 kSerialNorQuadMode_StatusReg2_Bit1_0x31  kSerialNorEnhanceMode_Disabled kSerialNorEnhanceMode_0_4_4_Mode kSerialNorEnhanceMode_0_8_8_Mode kSerialNorEnhanceMode_DataOrderSwapped kSerialNorEnhanceMode_2ndPinMux *!max_freqY#!misc_modeY#!quad_mode_settingY#!cmd_padsY#!query_padsY# !device_typeY#!option_sizeY#!tagY#SB_UY*!dummy_cyclesY#!status_overrideY#!reservedY#SB,UY)_serial_nor_config_optionoption0#option1{#Pserial_nor_config_option_t*por_mode:#current_mode:#exit_no_cmd_sequence:#restore_sequence:#SBUYPflash_run_context_tSkRestoreSequence_None kRestoreSequence_HW_Reset kRestoreSequence_4QPI_FF kRestoreSequence_5QPI_FF kRestoreSequence_8QPI_FF kRestoreSequence_Send_F0 kRestoreSequence_Send_66_99 kRestoreSequence_Send_6699_9966 kRestoreSequence_Send_06_FF kFlashInstMode_ExtendedSpi kFlashInstMode_0_4_4_SDR kFlashInstMode_0_4_4_DDR kFlashInstMode_QPI_SDR AkFlashInstMode_QPI_DDR BkFlashInstMode_OPI_SDR kFlashInstMode_OPI_DDR )_flexspi_nor_configmemConfig#pageSizeY#sectorSizeY#ipcmdSerialClkFreq:#isUniformBlockSize:#isDataOrderSwapped:#:reserved0 #serialNorType:#needExitNoCmdMode:#halfClkForNonReadCmd:#needRestoreNoCmdMode:#blockSizeY#Y reserve2 #Pflexspi_nor_config_tQ h devices\MIMXRT1052\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash *_BoolPclock_name_tPclock_ip_name_tPclock_osc_tPclock_gate_value_tPclock_mode_t Pclock_mux_tkPclock_div_tPclock_arm_pll_config_tBPclock_usb_pll_config_trPclock_sys_pll_config_tPclock_audio_pll_config_tPclock_video_pll_config_tiPclock_enet_pll_config_t_clock_pllkCLOCK_PllArm kCLOCK_PllSys kCLOCK_PllUsb1 kCLOCK_PllAudio kCLOCK_PllVideo kCLOCK_PllEnet0 kCLOCK_PllEnet1 kCLOCK_PllEnet2 kCLOCK_PllUsb2 Pclock_pll_tQ_clock_pfdkCLOCK_Pfd0 kCLOCK_Pfd1 kCLOCK_Pfd2 kCLOCK_Pfd3 Pclock_pfd_t_clock_usb_srckCLOCK_Usb480M kCLOCK_UsbSrcUnusedPclock_usb_src_tz_clock_usb_phy_srckCLOCK_Usbphy480M Pclock_usb_phy_src_t<CLOCK_SetMux$jmux$Yvalue\busyShiftY; CLOCK_GetMuxY$jmuxa__resultY< CLOCK_SetDiv$~divider$Yvalue\busyShiftY; CLOCK_GetDivY$~dividera__resultY\valueY< CLOCK_ControlGate$name$:value\indexY\shiftY\reg]tY"W< CLOCK_EnableClock$name< CLOCK_DisableClock$name< CLOCK_SetMode$Umode; CLOCK_GetCpuClkFreqYa__resultY< CLOCK_SetXtalFreq$Yfreq< CLOCK_SetRtcXtalFreq$Yfreq8 CLOCK_GetOscFreqYa__resultY8 CLOCK_GetRtcFreqYa__resultY_clock_namekCLOCK_CpuClk kCLOCK_AhbClk kCLOCK_SemcClk kCLOCK_IpgClk kCLOCK_OscClk kCLOCK_RtcClk kCLOCK_ArmPllClk kCLOCK_Usb1PllClk kCLOCK_Usb1PllPfd0Clk kCLOCK_Usb1PllPfd1Clk kCLOCK_Usb1PllPfd2Clk kCLOCK_Usb1PllPfd3Clk kCLOCK_Usb2PllClk kCLOCK_SysPllClk kCLOCK_SysPllPfd0Clk kCLOCK_SysPllPfd1Clk kCLOCK_SysPllPfd2Clk kCLOCK_SysPllPfd3Clk kCLOCK_EnetPll0Clk kCLOCK_EnetPll1Clk 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kCLOCK_Sai3 kCLOCK_Lpuart1 kCLOCK_Lpuart7 kCLOCK_SnvsHp kCLOCK_SnvsLp kCLOCK_UsbOh3 kCLOCK_Usdhc1 kCLOCK_Usdhc2 kCLOCK_Dcdc kCLOCK_Ipmux4 kCLOCK_FlexSpi kCLOCK_Trng kCLOCK_Lpuart8 kCLOCK_Timer4 kCLOCK_Aips_tz3 kCLOCK_SimPer kCLOCK_Anadig kCLOCK_Lpi2c4 kCLOCK_Timer1 kCLOCK_Timer2 kCLOCK_Timer3 _clock_osckCLOCK_RcOsc kCLOCK_XtalOsc  _clock_gate_valuekCLOCK_ClockNotNeeded kCLOCK_ClockNeededRun kCLOCK_ClockNeededRunWait  _clock_mode_tkCLOCK_ModeRun kCLOCK_ModeWait kCLOCK_ModeStop %_clock_muxkCLOCK_Pll3SwMux kCLOCK_PeriphMux9kCLOCK_SemcAltMux'kCLOCK_SemcMux&kCLOCK_PrePeriphMuxrkCLOCK_TraceMuxnkCLOCK_PeriphClk2MuxlkCLOCK_LpspiMuxdkCLOCK_FlexspiMux}kCLOCK_Usdhc2Mux1kCLOCK_Usdhc1Mux0kCLOCK_Sai3MuxnkCLOCK_Sai2MuxlkCLOCK_Sai1MuxjkCLOCK_PerclkMux&kCLOCK_Flexio2Mux skCLOCK_CanMux hkCLOCK_UartMux$&kCLOCK_SpdifMux0tkCLOCK_Flexio1Mux0gkCLOCK_Lpi2cMux82kCLOCK_Lcdif1PreMux8kCLOCK_Lcdif1Mux8kCLOCK_CsiMuxunsigned longunsigned shortcharunsigned char)FlashDevice!Vers#DevName,#DevType#DevAdr#szDev#szPage#Res#valEmpty#toProg#toErase#sectors#)FlashSectorsszSector#AddrSector#  middleware\flexspi\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash_Bool""YY"tY" "%":9h flexspi_swreset$base9p flexspi_unlock_lut$base9v flexspi_lock_lut$base8|flexspi_is_parallel_mode$configa__result8flexspi_is_differential_clock_enable$configa__result8flexspi_is_word_addressable$configa__result8flexspi_is_ck2_enabled$configa__result8flexspi_is_ddr_mode_enable$configa__result8flexspi_get_module_base$Yinstancea__result\baseAddr9 flexspi_clear_ip_txfifo$base9 flexspi_clear_ip_rxfifo$base9 flexspi_wait_until_ip_idle$base9flexspi_clear_error_status$base9 flexspi_clear_sequence_pointer$Yinstance\indexY\base8  flexspi_extract_parallel_dataw$dst0$dst1$src$Ylengtha__resultw\statusw \dst0Byte\dst1Byte\srcByte8  flexspi_device_workmode_configw$Yinstance$config$YbaseAddra__resultw\statusw \base\read_cmd_padsY\flashXfer%8  flexspi_device_workmode_config_all_chipsw$Yinstance$configa__resultw\statusw \baseAddrY\indexY\currentFlashSizeY\flashSizeStart8  flexspi_device_cmd_config_all_chipsw$Yinstance$configa__resultw\statusw \baseAddrY\indexY\currentFlashSizeY\flashSizeStartkFlexSpiDelayCellUnit_Min KkFlexSpiDelayCellUnit_Max " middleware\flexspi_nor\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash_BoolPlut_seq_tiPsfdp_header_t Psfdp_parameter_header_t Pjedec_flash_param_table_tPjedec_4byte_addressing_inst_table_tPjedec_info_table_t"5Y"""Y""1"D"f":"B2tY8 flexspi_nor_flash_initw$Yinstance$configa__resultw\statusw8 prepare_0_4_4_mode_enable_sequencew$Yinstance$config$tbl$optiona__resultw\statuswY\lut_seq\xfer\status_valY8 flexspi_nor_generate_config_block_using_sfdpw$Yinstance$config$optiona__resultw\statusw\k_sdfp_lut~\jedec_info_tbl8 flexspi_nor_hyperbus_readw$Yinstance$Yaddr$buffer$Ybytesa__resultw\xfer\statusw8  flexspi_nor_hyperbus_writew$Yinstance$Yaddr$buffer$Ybytesa__resultw\xfer\statuswkSerialNorCmd_BasicRead_3B kSerialNorCmd_BasicRead_4B kSerialNorCmd_PageProgram_1_1_1_3B kSerialNorCmd_PageProgram_1_1_1_4B kSerialNorCmd_PageProgram_1_4_4_4B >kSerialNorCmd_PageProgram_1_1_4_4B 4kSerialNorCmd_Read_SDR_1_4_4_3B kSerialNorCmd_Read_DDR_1_4_4_3B kSerialNorCmd_Read_SDR_1_4_4_4B kSerialNorCmd_Read_SDR_1_1_4_4B lkSerialNorCmd_Read_DDR_1_4_4_4B kSerialNorCmd_ChipErase `kSerialNorCmd_WriteEnable kSerialNorCmd_WriteStatusReg1 kSerialNorCmd_ReadStatusReg1 kSerialNorCmd_WriteStatusReg2 >kSerialNorCmd_ReadStatusReg2 ?kSerialNorCmd_ReadFlagReg pkSerialNorCmd_SE4K_3B kSerialNorCmd_SE4K_4B !kSerialNorCmd_SE64K_3B kSerialNorCmd_SE64K_4B kSerialNorQpiMode_NotConfig kSerialNorQpiMode_Cmd_0x38 kSerialNorQpiMode_Cmd_0x38_QE kSerialNorQpiMode_Cmd_0x35 kSerialNorQpiMode_Cmd_0x71 kSerialNorQpiMode_Cmd_0x61 kSerialNorType_StandardSPI kSerialNorType_HyperBus kSerialNorType_XPI kSerialNorType_NoCmd )_lut_seqYlut#kSerialNOR_IndividualMode kSerialNOR_ParallelMode kFlexSpiSerialClk_Update kFlexSpiSerialClk_Restore kSerialFlash_ReadSFDP ZkSerialFlash_ReadManufacturerId kSfdp_Version_Major_1_0 kSfdp_Version_Minor_0 kSfdp_Version_Minor_A kSfdp_Version_Minor_B kSfdp_Version_Minor_C kSfdp_BasicProtocolTableSize_Rev0 $kSfdp_BasicProtocolTableSize_RevA @kSfdp_BasicProtocolTableSize_RevB @kSfdp_BasicProtocolTableSize_RevC P)_sfdp_headersignatureY#minor_rev:#major_rev:#param_hdr_num:#sfdp_access_protocol:#kParameterID_BasicSpiProtocolkParameterID_SectorMapkParameterID_4ByteAddressInstructionTablekParameterID_xSpiProfile1_0kParameterID_xSpiOrofile2_0kParameterID_StaCtrlCfgRegMapkParameterID_OpiEnableSeq )_sfdp_parameter_headerparameter_id_lsb:#minor_rev:#major_rev:#table_length_in_32bit:#:parameter_table_pointer #parameter_id_msb:#*!erase_sizeY#!write_granularityY#!reserved0Y#!unused0Y#!erase4k_instY#!support_1_1_2_fast_readY#!address_bitsY# !support_ddr_clockingY# !support_1_2_2_fast_readY# !supports_1_4_4_fast_readY# !support_1_1_4_fast_readY# !unused1Y# *!dummy_clocks_1_4_4_readY#!mode_clocks_1_4_4_readY#!inst_1_4_4_readY#!dummy_clocks_1_1_4_readY# !mode_clocks_1_1_4_readY#!inst_1_1_4_readY#*!dummy_clocks_1_2_2_readY#!mode_clocks_1_2_2_readY#!inst_1_2_2_readY#!dummy_clocks_1_1_2_readY# !mode_clocks_1_1_2_readY#!inst_1_1_2_readY#* !support_2_2_2_fast_readY#!reserved0Y#!support_4_4_4_fast_readY#!reserved1Y#*!!reserved0Y#!dummy_clocks_2_2_2_readY# !mode_clocks_2_2_2_readY#!inst_2_2_2_readY#*"!reserved0Y#!dummy_clocks_4_4_4_readY# !mode_clocks_4_4_4_readY#!inst_4_4_4_readY#*"size:#inst:#*#!reserved0Y#!page_sizeY#!reserved1Y#*#suspend_resume_specY#suspend_resume_instY#*$!reserved0Y#!busy_status_pollingY#!reserved1Y#*&!mode_4_4_4_disable_seqY#!mode_4_4_4_enable_seqY#!support_mode_0_4_4Y#!mode_0_4_4_exit_methodY#!mode_0_4_4_entry_methodY# !quad_enable_requirementY# !hold_reset_disableY#!reserved0Y#*'!status_reg_write_enableY#!reserved0Y#!soft_reset_rescue_supportY#!exit_4_byte_addressingY# !enter_4_byte_addrssingY#*)!dummy_clocks_1_8_8_readY#!mode_clocks_1_8_8_readY#!inst_1_8_8_readY#!dummy_clocks_1_1_8_readY# !mode_clocks_1_1_8_readY#!inst_1_1_8_readY#*+!reservedY#!output_driver_strengthY# !jedec_spi_protocol_resetY#!dqs_waveform_type_sdrY#!dqs_support_in_qpi_sdrY#!dqs_support_in_qpi_ddrY#!dqs_support_in_opi_strY#!cmd_and_extension_in_opi_ddrY#!byte_order_in_opi_ddrY#*-!opi_sdr_disable_seqY#!opi_sdr_enable_deqY#!support_mode_0_8_8Y#!mode_0_8_8_exit_methodY#!mode_0_8_8_entry_methodY# !octal_enable_requirementY# !reservedY# */!qpi_sdr_no_dqsY#!qpi_sdr_with_dqsY#!qpi_ddr_no_dqsY#!qpi_ddr_with_dqsY#!opi_sdr_no_dqsY# !opi_sdr_with_dqsY#!opi_ddr_no_dqsY#!opi_ddr_with_dqsY#)2_jedec_flash_param_tablePmisc #flash_densityY#read_1_4_info)#read_1_2_info# read_22_44_check#read_2_2_info8#read_4_4_info#04erase_infoX#erase_timingY#$chip_erase_progrm_infoU#(suspend_resume_info#,busy_status_info#4mode_4_4_info,#8mode_config_info5#<read_1_8_info#@xpi_misc_info#Dmode_octal_info#Hmax_speed_info_xpi#L*9!support_1_1_1_readY#!support_1_1_1_fast_readY#!support_1_1_2_fast_readY#!support_1_2_2_fast_readY#!support_1_1_4_fast_readY#!support_1_4_4_fast_readY#!support_1_1_1_page_programY#!support_1_1_4_page_programY#!support_1_4_4_page_programY#!support_erase_type1_sizeY#!support_erase_type2_sizeY#!support_erase_type3_sizeY#!support_erase_type4_sizeY#!support_1_1_1_dtr_readY#!support_1_2_2_dtr_readY#!support_1_4_4_dtr_readY#!support_volatile_sector_lock_read_cmdY#!support_volatile_sector_lock_write_cmdY#!support_nonvolatile_sector_lock_read_cmdY# !support_nonvolatile_sector_lock_write_cmdY# !reservedY# *99:erase_inst#):_jedec_4byte_addressing_inst_tablecmd_4byte_support_infoc#erase_inst_info#);_jdec_query_tabledstandard_versionY#flash_param_tbl_sizeY#flash_param_tblD#has_4b_addressing_inst_table#Xflash_4b_inst_tblf#\ devices\MIMXRT1052\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash x)_BoolJ7"7"i7" 7"7"!7"+YtY9CLOCK_InitUsb1Pll$config9CLOCK_DeinitUsb1Pll9CLOCK_InitUsb2Pll$config9CLOCK_DeinitUsb2Pll .\devices\MIMXRT1052\drivers\fsl_common.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash%l6_status_groupskStatusGroup_Generic kStatusGroup_FLASH kStatusGroup_LPSPI kStatusGroup_FLEXIO_SPI kStatusGroup_DSPI kStatusGroup_FLEXIO_UART kStatusGroup_FLEXIO_I2C kStatusGroup_LPI2C kStatusGroup_UART kStatusGroup_I2C kStatusGroup_LPSCI kStatusGroup_LPUART kStatusGroup_SPI kStatusGroup_XRDC kStatusGroup_SEMA42 kStatusGroup_SDHC kStatusGroup_SDMMC kStatusGroup_SAI kStatusGroup_MCG kStatusGroup_SCG kStatusGroup_SDSPI kStatusGroup_FLEXIO_I2S kStatusGroup_FLEXIO_MCULCD kStatusGroup_FLASHIAP kStatusGroup_FLEXCOMM_I2C kStatusGroup_I2S kStatusGroup_IUART kStatusGroup_CSI kStatusGroup_MIPI_DSI kStatusGroup_SDRAMC #kStatusGroup_POWER 'kStatusGroup_ENET (kStatusGroup_PHY )kStatusGroup_TRGMUX *kStatusGroup_SMARTCARD +kStatusGroup_LMEM ,kStatusGroup_QSPI -kStatusGroup_DMA 2kStatusGroup_EDMA 3kStatusGroup_DMAMGR 4kStatusGroup_FLEXCAN 5kStatusGroup_LTC 6kStatusGroup_FLEXIO_CAMERA 7kStatusGroup_LPC_SPI 8kStatusGroup_LPC_USART 9kStatusGroup_DMIC :kStatusGroup_SDIF ;kStatusGroup_SPIFI <kStatusGroup_OTP =kStatusGroup_MCAN >kStatusGroup_CAAM ?kStatusGroup_ECSPI @kStatusGroup_USDHC AkStatusGroup_LPC_I2C BkStatusGroup_DCP CkStatusGroup_MSCAN DkStatusGroup_ESAI EkStatusGroup_FLEXSPI FkStatusGroup_MMDC GkStatusGroup_MICFIL HkStatusGroup_SDMA IkStatusGroup_ICS JkStatusGroup_SPDIF KkStatusGroup_NOTIFIER bkStatusGroup_DebugConsole ckStatusGroup_SEMC dkStatusGroup_ApplicationRangeStart e_generic_statuskStatus_Success kStatus_Fail kStatus_ReadOnly kStatus_OutOfRange kStatus_InvalidArgument kStatus_Timeout kStatus_NoTransferInProgress Pstatus_t;EnableIRQ$`interrupta__result;DisableIRQ$`interrupta__result;DisableGlobalIRQYa__resultY\regPrimaskY<EnableGlobalIRQ$Yprimask bsp\src\hardware_init_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash02"Y"Y bsp\src\clock_config_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flashp$5kMaxAHBClockD"YtY9flexspi_clock_gate_enable$Yinstance9flexspi_clock_gate_disable$Yinstance8 get_core_clockYa__resultY .\devices\MIMXRT1052\drivers\fsl_clock.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash+\7_BoolPclock_name_tPclock_ip_name_tPclock_osc_tPclock_gate_value_tPclock_mode_tJPclock_mux_tPclock_div_tPclock_arm_pll_config_tlPclock_usb_pll_config_tPclock_sys_pll_config_tPclock_audio_pll_config_t$Pclock_video_pll_config_tPclock_enet_pll_config_t_clock_pllkCLOCK_PllArm kCLOCK_PllSys kCLOCK_PllUsb1 kCLOCK_PllAudio kCLOCK_PllVideo kCLOCK_PllEnet0 kCLOCK_PllEnet1 kCLOCK_PllEnet2 kCLOCK_PllUsb2 Pclock_pll_tS_clock_pfdkCLOCK_Pfd0 kCLOCK_Pfd1 kCLOCK_Pfd2 kCLOCK_Pfd3 Pclock_pfd_t_clock_usb_srckCLOCK_Usb480M kCLOCK_UsbSrcUnusedPclock_usb_src_t|_clock_usb_phy_srckCLOCK_Usbphy480M Pclock_usb_phy_src_tqg_xtalFreqYqg_rtcXtalFreqY< CLOCK_SetMux$lmux$Yvalue\busyShiftY; CLOCK_GetMuxY$lmuxa__resultY< CLOCK_SetDiv$divider$Yvalue\busyShiftY; CLOCK_GetDivY$dividera__resultY\valueY< CLOCK_ControlGate$name$<value\indexY\shiftY\regtY"< CLOCK_EnableClock$name< CLOCK_DisableClock$name< CLOCK_SetMode$Wmode; CLOCK_GetCpuClkFreqYa__resultY; CLOCK_GetOscFreqYa__resultY; CLOCK_GetRtcFreqYa__resultY< CLOCK_SetRtcXtalFreq$Yfreq9 CLOCK_SetXtalFreq$Yfreq_clock_namekCLOCK_CpuClk kCLOCK_AhbClk kCLOCK_SemcClk kCLOCK_IpgClk kCLOCK_OscClk kCLOCK_RtcClk kCLOCK_ArmPllClk kCLOCK_Usb1PllClk kCLOCK_Usb1PllPfd0Clk kCLOCK_Usb1PllPfd1Clk kCLOCK_Usb1PllPfd2Clk kCLOCK_Usb1PllPfd3Clk kCLOCK_Usb2PllClk kCLOCK_SysPllClk kCLOCK_SysPllPfd0Clk kCLOCK_SysPllPfd1Clk kCLOCK_SysPllPfd2Clk kCLOCK_SysPllPfd3Clk kCLOCK_EnetPll0Clk kCLOCK_EnetPll1Clk kCLOCK_EnetPll2Clk kCLOCK_AudioPllClk kCLOCK_VideoPllClk _clock_ip_namekCLOCK_IpInvalidkCLOCK_Aips_tz1kCLOCK_Aips_tz2kCLOCK_Dcp kCLOCK_Lpuart3 kCLOCK_Can1kCLOCK_Can1SkCLOCK_Can2kCLOCK_Can2SkCLOCK_TracekCLOCK_Gpt2kCLOCK_Gpt2SkCLOCK_Lpuart2kCLOCK_Gpio2kCLOCK_Lpspi1kCLOCK_Lpspi2kCLOCK_Lpspi3kCLOCK_Lpspi4kCLOCK_Adc_5hckCLOCK_EnetkCLOCK_PitkCLOCK_Aoi2kCLOCK_Adc1kCLOCK_Gpt1kCLOCK_Gpt1SkCLOCK_Lpuart4kCLOCK_Gpio1kCLOCK_CsukCLOCK_Gpio5kCLOCK_CsikCLOCK_IomuxcSnvskCLOCK_Lpi2c1kCLOCK_Lpi2c2kCLOCK_Lpi2c3kCLOCK_OcotpkCLOCK_Xbar3kCLOCK_Ipmux1kCLOCK_Ipmux2kCLOCK_Ipmux3kCLOCK_Xbar1kCLOCK_Xbar2kCLOCK_Gpio3kCLOCK_LcdkCLOCK_PxpkCLOCK_Flexio2kCLOCK_Lpuart5kCLOCK_SemckCLOCK_Lpuart6kCLOCK_Aoi1kCLOCK_LcdPixelkCLOCK_Gpio4kCLOCK_Ewm0kCLOCK_Wdog1kCLOCK_FlexRamkCLOCK_Acmp1kCLOCK_Acmp2kCLOCK_Acmp3kCLOCK_Acmp4kCLOCK_OcramkCLOCK_IomuxcSnvsGprkCLOCK_IomuxckCLOCK_IomuxcGprkCLOCK_BeekCLOCK_SimM7kCLOCK_TsckCLOCK_SimMkCLOCK_SimEmskCLOCK_Pwm1kCLOCK_Pwm2kCLOCK_Pwm3kCLOCK_Pwm4kCLOCK_Enc1kCLOCK_Enc2kCLOCK_Enc3kCLOCK_Enc4kCLOCK_Rom kCLOCK_Flexio1 kCLOCK_Wdog3 kCLOCK_Dma kCLOCK_Kpp kCLOCK_Wdog2 kCLOCK_Aips_tz4 kCLOCK_Spdif kCLOCK_SimMain kCLOCK_Sai1 kCLOCK_Sai2 kCLOCK_Sai3 kCLOCK_Lpuart1 kCLOCK_Lpuart7 kCLOCK_SnvsHp kCLOCK_SnvsLp kCLOCK_UsbOh3 kCLOCK_Usdhc1 kCLOCK_Usdhc2 kCLOCK_Dcdc kCLOCK_Ipmux4 kCLOCK_FlexSpi kCLOCK_Trng kCLOCK_Lpuart8 kCLOCK_Timer4 kCLOCK_Aips_tz3 kCLOCK_SimPer kCLOCK_Anadig kCLOCK_Lpi2c4 kCLOCK_Timer1 kCLOCK_Timer2 kCLOCK_Timer3 _clock_osckCLOCK_RcOsc kCLOCK_XtalOsc  _clock_gate_valuekCLOCK_ClockNotNeeded kCLOCK_ClockNeededRun kCLOCK_ClockNeededRunWait !_clock_mode_tkCLOCK_ModeRun kCLOCK_ModeWait kCLOCK_ModeStop %_clock_muxkCLOCK_Pll3SwMux kCLOCK_PeriphMux9kCLOCK_SemcAltMux'kCLOCK_SemcMux&kCLOCK_PrePeriphMuxrkCLOCK_TraceMuxnkCLOCK_PeriphClk2MuxlkCLOCK_LpspiMuxdkCLOCK_FlexspiMux}kCLOCK_Usdhc2Mux1kCLOCK_Usdhc1Mux0kCLOCK_Sai3MuxnkCLOCK_Sai2MuxlkCLOCK_Sai1MuxjkCLOCK_PerclkMux&kCLOCK_Flexio2Mux skCLOCK_CanMux hkCLOCK_UartMux$&kCLOCK_SpdifMux0tkCLOCK_Flexio1Mux0gkCLOCK_Lpi2cMux82kCLOCK_Lcdif1PreMux8kCLOCK_Lcdif1Mux8kCLOCK_CsiMuxflexspi_is_padsetting_override_enableb)p)iconfig'P___resultIPp)z)o,Qwb7QPIFQz))onQdcyQFIQ))oQ3cQIQ))oQcQ> flexspi_configure_dllw)*niinstanceYiconfig'Pm^__resultwPZstatuswOZmdisConfigRequired)*ZbaseBV&\isUnifiedConfigYflexspiRootClkY\YYflexspiDllPZdllValueYZtempY)*\useDLL)*ZiY**ZdataValidTimeHY\dataValidTimeLY**YmaxFreqYXZis_ddr_enabled>  flexspi_get_ticksw*+Niticks-PjiintervalNsYAifreqY.iunitY^__resultwP<Zstatusw *+XcalculatedTicksP(ZcycleNsY>  flexspi_config_mcr1w+z+ iinstanceYiconfig'P___resultwQYseqWaitTicksYXYahbBusWaitTicksY\YserialRootClockFreqY`YahbBusClockFreqYdZbaseBVo>  flexspi_config_flash_control_registerswz+B,iinstanceYiconfig'P^__resultwPZstatusw +>,ZindexYsYflashSizeYZtempY7YserialClockFrequencyYXYcsIntervalTicksYHZbaseBVZflashSizeStart-PU> flexspi_config_ahb_bufferswB,,ibaseBViconfig'P^__resultwPNZtempYZindexYZstatuswIS,,o/Sc>S,,JSbMSP> flexspi_command_xferw,.riinstanceYixferGP?___resultw ZstatuswZbaseBV,.ZtempYZisParallelMode,-ZxferRemainingSizeYZxferBufferPtr-Pq\rx_fifo_sizeY\watermarkYZburst_rx_sizeYS,-Zrx_fifo_regCP5Z--Zburst_rx_roundY,-YbufYdZsrcMP ZdstMP ,-XindexYS-.ZxferRemainingSize ZxferBufferPtr-P \tx_fifo_sizeY\watermarkYZburst_tx_sizeYk Zis_transfer_startedB .^.Ztx_fifo_regCP .^.Zburst_tx_roundY FR,, fRFR:-H- fRFUR-. fvR> flexspi_update_lutw..RiinstanceY iseqIndexY ilutBase9P iseqNumberY{ ^__resultwP^Zstatusw[ ..ZbaseBVH Zstart_indexY5 Zend_indexY" ZflexspiLutPtrCP FuP.. fPFP.. fP> flexspi_device_write_enablew.R/iinstanceY iconfig'P iisParallelMode ibaseAddrY ^__resultwPVZstatusw /N/YflashXfer%H> flexspi_device_wait_busywR/b0iinstanceYb iconfig'PD iisParallelMode ibaseAddrY ___resultw Zstatusw Z/b0YYstatusDataBuffer HZbusyMaskYw ZbusyPolarityY; ZisBusy Ystatus0Y@Ystatus1YDYflashXfer%ZenableTimeoutCheck ZremainingMsi FXS/0 oS oS oS oS eSdS /0ScSf cSS cS5 > flexspi_device_cmd_configwb0$1iinstanceYiconfig'PibaseAddrYz^__resultwPZstatuswFj0 1ZbaseBVYflashXfer%ZindexY01Yread_cmd_padsY>! flexspi_initw$12oiinstanceYiconfig'Pf^__resultwPZmcr0YZstatuswH,12ZbaseBV Zneed_safe_freqF T 2`2 oToTueTcTb 2`2Uc UNcU0b$ULc;UF!PUl22 oU oUeUcU!p22UcUcUbULcU?! flexspi_wait_idle2 3OiinstanceY!23ZbaseBVx?" flexspi_clear_cache 33/iinstanceYe" 33XbaseBVP?# flexspi_half_clock_control3>3iinstanceYRioptionY4#3<3ZbaseBV!I#SP>3N3okPI$RN3^3o*Rb9RPcGRI$R^3n3oRI%Sn34o To/Txo:TObITPcYT1%z34fTciTbrTbTH middleware\flexspi\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashYg_flexSpiInstancesLV y"$middleware\\flexspi\\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashhlP__asm___13_fsl_flexspi_c_c729c902____REVSHhl$middleware\\flexspi\\fsl_flexspi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashLP__asm___13_fsl_flexspi_c_c729c902____REV16LPmiddleware\flexspi_nor\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash R)_BoolIIX onX:9o}X9bXP(bXU> flexspi_nor_exit_no_cmd_modew  iinstanceY 9iconfigX8iisParallelMode8ibaseAddrY8^__resultwP2YflashXferH> flexspi_nor_write_enablew t XiinstanceY8iconfigX8iisParallelModet8ibaseAddrYU8^__resultwP`Zstatusw#8YZlut_tmp68>flexspi_nor_restore_no_cmd_modewt iinstanceY8iconfigX7iisParallelMode7ibaseAddrY7^__resultwP>Zstatusw7~ YflashXfer> flexspi_nor_wait_busyw iinstanceYx7iconfigXe7iisParallModeG7ibaseAddrY)7^__resultwPNZstatusw6YZlut_tmp 6? flexspi_change_serial_clockiinstanceY6iconfigX6ioperationYo6 YisClockChangeRequiredZisDdrModeEnabledQ6Yserial_clockYXYcore_clockY\\dummy_cntY>  flexspi_nor_flash_page_programwviinstanceY&6iconfigX5idstAddrY5isrcX5^__resultwPZstatusw5YflashXferYmemCfgXZisParallelMode5>  flexspi_nor_flash_erase_allwvfaiinstanceYY5iconfigX.5^__resultwPZflashSizeStartX4YcurrentFlashSizeY\YbaseAddrY\ZindexY4Zstatusw5YflashXferZmemCfgX4> flexspi_nor_flash_erase_sectorwf4iinstanceYu4iconfigXL4iaddressY#4^__resultwPZstatusw3YflashXferZisParallelMode4YmemCfgX> flexspi_nor_flash_erase_blockwiinstanceY3iconfigX3iaddressYu3^__resultwPZstatuswD3YflashXferZisParallelModeW3YmemCfgX> flexspi_nor_read_sfdpwiinstanceY&3iaddrY3ibufferX2ibytesY2^__resultwP2YflashXferHZstatusw2> prepare_quad_mode_enable_sequencew.iinstanceYv2iconfigX!2itbl!X2ioption%X1___resultw}1Ystatusw,Zenter_quad_mode_optionY1YYlut_seq HT,YxferYstatus_valY> probe_dtr_quad_read_dummy_cyclesw.CiinstanceYF1iconfigX1idummy_cyclesX0___resultw0Zstatusw+0Zdummy_cycle_detected0YflashXferYYlut_seq DB XYprobe_pattern+ YYbufferL \need_program_patternZmax_probe_tryY0Zprobe_cntYr0Zprobe_dummy_cyclesYI0> get_page_sector_block_size_from_sfdpwiconfigX/itbl!X/isector_erase_cmdX/iblock_erase_cmdXV/___resultw*.Zparam_tbl+X.Zflash_4b_tbl/X.Yflash_sizeYZflash_densityY.Zpage_sizeY.Zsector_sizeYv.Zblock_sizeYc.Zblock_erase_typeY-/Zsector_erase_typeY/ZindexYP.Zcurrent_erase_sizeY=.> parse_sfdpwFiinstanceY-iconfigX-itbl!X,ioption%X ,___resultw,(ZstatuswX+FZparam_tbl+X*Zflash_4b_tbl/X*Zsupport_ddr_mode*Yread_cmd:Ydummy_cyclesYZmode_cycles:)Ysector_erase_cmdYPYblock_erase_cmdYTZaddress_bitsY(Zaddress_padsY#)Ycmd_padsYZenhance_modeYp(*Zentry_methodY](Zexit_methodY?(FZmode_instY(>" flexspi_nor_read_sfdp_infowF.iinstanceY'itbl!X'iaddress_shift_enablew'^__resultwPZstatuswN'"F,Ysfdp_headerfWZaddressY&Yparameter_header_numberY |W Ysfdp_param_hdrshZmax_hdr_countY.'"F*XiYVh""Zparameter_idY&""Xtable_sizeYW"Zindex&>$ flexspi_nor_generate_config_block_hyperflashw.dFiinstanceY&iconfigX^&iis_1v8K&___resultw&Zstatusw"&$4b#YYlut_seq@YdataYX#YYbufferP>& flexspi_nor_restore_spi_protocolwd iinstanceY%iconfigX%irun_ctx=X{%^__resultwPZstatuswR%Yxfer&dZpadY4%Zcmd_instY%%YYlut_seq&dYwait_cntCX\>* flexspi_nor_generate_config_block_mxic_octalflashw&!iinstanceY$iconfigXt$ioption%X%$^__resultwPZstatusw"Yxfer~'YYmfg_idZis_sdr_mode#'3XYk_rdid_lut*"!Zcmd_padsYx#Zquery_padsY.#ZindexY"\mfg_id_buffer7XZenableDTR")PYrun_ctxB2~) Yrun_ctxB2~* !Zcmd_instYt"Zaddr_instYa"Zdummy_instYM"Zread_instY8"Ywrite_instY~>- flexspi_nor_generate_config_block_micron_octalflashw&!"iinstanceY"iconfigX!ioption%X!^__resultwPZstatuswA!+3XYk_sdfp_lutZis_sdr_mode!-F!"Yjedec_info_tblW~Ysector_erase_cmdY~Yblock_erase_cmdY~\opi_mode_enable-P!"Yrun_ctxB2~-!"Zaddress_bitsY.!Ypage_program_cmdY-""Yrun_ctxB2~>3 flexspi_nor_generate_config_block_adesto_octalflashw" &UiinstanceY!iconfigX ioption%X ___resultw0kSfdp_LutIndex_Sdr_1_1 kSfdp_LutIndex_Sdr_4_4 kSfdp_LutIndex_Sdr_8_8 kSfdp_LutIndex_Ddr_4_4 kSfdp_LutIndex_Ddr_8_8 Zstatusw Zis_sdr_mode03XYk_sdfp_lut+3#&Zaddress_shift_enableZquery_padsYZcmd_padsY+ZlutIndexY Yjedec_info_tblW~Ysector_erase_cmdYXYblock_erase_cmdY\Zaddr_padsY\dummy_padsY\write_padsY\read_padsYZaddr_instYZdummy_instYZread_instYYwrite_instY~Yrun_ctxB2~30#&Yrun_ctxB2~>4 flexspi_nor_get_configw &&5iinstanceYiconfigXcioption%XE^__resultwPZstatusw'>6 flexspi_nor_flash_erasew&\'iinstanceYiconfigXistartYilengthY___resultwAZaligned_startYrZaligned_endY_Zstatusw6'V'Zis_addr_block_aligned.Zremaining_sizeY>8 flexspi_nor_flash_readw\''iinstanceYiconfigXidstXistartYibytesYm^__resultwPVZstatuswO8f''YflashXferYisParallelModeYmemCfgX8''XreadLengthYUI9X'&(oX<oXoXoX bYPlbYb,Y`9'"(8Yb;Y6bFY6I:YY&()RoYoYoYbYPcYbY :H()YbY~NI;Z).)o.Zmo=ZZoHZGoSZ4b_ZP$boZPbzZI;Z.)R)oZ!oZoZoZbZP"bZPbZ4middleware\\flexspi_nor\\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flashdh(__asm___19_flexspi_nor_flash_c_93f2e184____REVSHdh4middleware\\flexspi_nor\\flexspi_nor_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashHL$)__asm___19_flexspi_nor_flash_c_93f2e184____REV16HL devices\MIMXRT1052\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash| *_Bool> CLOCK_GetPllFreqY<ipll8A___resultY@ZfreqYvAZdivSelectY@ZfreqTmpiMAEuYenetRefClkFreq~X> CLOCK_GetSysPfdFreqY>|<ipfd9@___resultY@ZfreqY@>5CLOCK_GetPeriphClkFreqY>\<___resultY9@ZfreqYm@?sCLOCK_InitExternalClk<<ibypassXtalOsc&@?CLOCK_DeinitExternalClk(<?CLOCK_SwitchOsc<iosc6@?CLOCK_InitRcOsc24M<?CLOCK_DeinitRcOsc24M ;> CLOCK_GetUsb1PfdFreqY P;ipfd9?___resultY?ZfreqY?> CLOCK_GetFreqYP& ;iname6?___resultY>?ZfreqY?F3< eR<?CLOCK_InitArmPll& > ;iconfigu+??CLOCK_DeinitArmPll> H ;? CLOCK_InitSysPllH ` p;iconfigu?? CLOCK_DeinitSysPll` j \;I Quj H;olu?I xu 4;I u ;ou>I u ;? CLOCK_InitAudioPll 2 :iconfig-u>ZpllAudioY>Zmisc2Y>? CLOCK_DeinitAudioPll2 > :? CLOCK_InitVideoPll> :iconfig7u>ZpllVideoYr>Zmisc2YT>? CLOCK_DeinitVideoPll :? CLOCK_InitEnetPll :iconfigAuA>Zenet_pllY.>? CLOCK_DeinitEnetPll |:?CLOCK_InitSysPfd $ \:ipfd9>ipfdFrac:>ZpfdIndexY=Xpfd528YR?CLOCK_DeinitSysPfd$ 6 H:ipfd9=?CLOCK_InitUsb1Pfd6 Z (:ipfd9=ipfdFrac:=ZpfdIndexY=Xpfd480YR?CLOCK_DeinitUsb1PfdZ l :ipfd9=>CLOCK_EnableUsbhs0Clockl 9isrcr9=ifreqYp=^__resultP<l YiKux>CLOCK_EnableUsbhs1Clock 9isrcr9]=ifreqYJ=^__resultP< YiKux>CLOCK_EnableUsbhs0PhyPllClock  9isrc97=ifreqY$=^__resultP,Yg_ccmConfigUsbPllux>CLOCK_EnableUsbhs1PhyPllClock D 9isrc9=ifreqY<^__resultP,Yg_ccmConfigUsbPllux?CLOCK_DisableUsbhs0PhyPllClockD V 9FxuD J ?CLOCK_DisableUsbhs1PhyPllClockV h l9FuV \ I<h | X9c"<< devices\MIMXRT1052\drivers\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flashpg_xtalFreqY y"pg_rtcXtalFreqY y"(devices\\MIMXRT1052\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash`d1__asm___11_fsl_clock_c_07a918fd____REVSH`d(devices\\MIMXRT1052\\drivers\\fsl_clock.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashDH02__asm___11_fsl_clock_c_07a918fd____REV16DHbsp\src\hardware_init_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash0D3?qflexspi_iomux_config0^BiinstanceYCiconfigdBZcsPadCtlValueYBZdqsPadCtlValueYBZsclkPadCtlValueYBZdataPadCtlValueY{B> flexspi_set_failsafe_setting}^AiconfigdhB^__result}P(Zstatus}JB> flexspi_nor_write_persistent}Aidataj7B^__result}P> flexspi_nor_read_persistent}Aidatap$B^__result}P0bsp\\src\\hardware_init_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash\`4__asm___26_hardware_init_MIMXRT1051_c_753bbbb7____REVSH\`0bsp\\src\\hardware_init_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash@DL5__asm___26_hardware_init_MIMXRT1051_c_753bbbb7____REV16@Dbsp\src\clock_config_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashL$8?>clock_initLR'DXahb_dividerYU|F·PV@fIRbDoqFIbrCoހ^F?flexspi_clock_configrCiinstanceY?Fifreq?FisampleClkModeYE)_flexspi_clock_paramfrac:#podf:#Pflexspi_clock_param_tZpfd480YEZcscmr1YEZfracYEZpodfYmEl Yk_sdr_clock_configpl Yk_ddr_clock_configLZflexspi_config_arrayE"l> flexspi_get_clock}hCiinstanceYZEitypeGEifreq{E___result}DZclockFrequencyY EZstatus}DYahbBusDividerYYseralRootClkDividerYZarm_clockYD.`YpfdFracYXpfdClkYP,\flexspi_clk_srcY>  flexspi_get_max_supported_freq}h|CiinstanceYDifreq{DiclkModeYD^__result}PZstatus}pDI |qCb P>  get_bus_clockYQC^__resultYPYahbBusDividerY? flexspi_sw_delay_us0CiusiGDXticksPerUsYV YticksCounthF e 0bsp\\src\\clock_config_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashX\ ;__asm___25_clock_config_MIMXRT1051_c_efd8dd31____REVSHX\0bsp\\src\\clock_config_MIMXRT1051.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash<@t;__asm___25_clock_config_MIMXRT1051_c_efd8dd31____REV16<@FlashDev.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashpFlashDevice y"FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flashp.?intunsigned longunsigned char">InitpFiadrGiclkrGifnc_G^__resultPj\statuswYoption]p>IUnInitFifncLG^__resultP>UEraseChipF^__resultPYstatusw>iEraseSectorF$adr^__resultPYstatusw>ProgramPage.F$adrisz9GibufG^__resultPYstatuswFlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashpconfigN y"FlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_FlashTX @__asm___10_FlashPrg_c_Init____REVSHTXFlashPrg.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\nxa12829\OneDrive - NXP\work\task\2017\i.MXRT1050\flashloader\MDK_QSPI_flashloader\_Template_Flash8<t@__asm___10_FlashPrg_c_Init____REV168<L> devices\MIMXRT1052\system_MIMXRT1052.c4 ~x   /  #u#y  = qfl  * V.ek F} + w1;~-klP8 .\\CMSIS\\Include\\cmsis_armcc.hlP8 .\\CMSIS\\Include\\cmsis_armcc.hP middleware\flexspi\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\MIMXRT1052\middleware\flexspi\fsl_flexspi.cfsl_flexspi.hassert.hstdbool.hfsl_device_registers.hfsl_flexspi.cpf middleware\flexspi\.\devices\MIMXRT1052\drivers\fsl_flexspi.hfsl_common.h 8 middleware\flexspi\fsl_flexspi.cT)  ~  ~   ~  ~  ~   7 %*m! -   %&Q7 4  !1U ! %w! y -I{ %  %  (   |!/ -  !&&,-  - k-" u     !"d/"d/ j4~K' &- /%'/ !] & y   "'   $~ ~+   ~1|~ ) 2  y "{ ! }{ L $ $ {   96~# ~(0~&-2~7X />% $ z- & 99~6 ~!# w  #X .  "  n} z~ ! 6 <y & ~y | |  +% - ?* { ,'-H + - !?,   }+   )w  $!& vz     (4&88?& 3U+1$ !  ?!: 9 %   x " G   !  " %' *"""""~ "~  !~{ &v%   ~  ~{ 2 &v%   !A!       z u  ~ o &  % 0 -?, n 0 ;)P8 .\\CMSIS\\Include\\cmsis_armcc.hhP8 .\\CMSIS\\Include\\cmsis_armcc.hL C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\middleware\middleware\flexspi_nor\middleware\flexspi_nor\flexspi_nor_flash.cstring.hstdlib.hstdbool.hflexspi/fsl_flexspi.hflexspi_nor_flash.hflexspi_nor_flash.c middleware\flexspi_nor\.\devices\MIMXRT1052\drivers\.\middleware\flexspi_nor_flash.hfsl_common.hflexspi/fsl_flexspi.h(B middleware\flexspi_nor\flexspi_nor_flash.c  . /&) {   /&   ~[. 1 * @)4 z   ! ~  Z % x%"($ 2  . ! &  %( 8 Y! ! !~$ *2+ + ! F,2 '6'ws'  -/  2E& i H v2'2 k'$# )2+ - @,2 ' 1'$# )2+ - @,2 ' 1'~ *{   *  w   o r 8 ! G}  - 2!  z *1  v&fczv  s) ':&,J  7, 4&,      %} & - &3 &   |qg7 ,` .+i7~7*{*y  }x  0 znj h &8> )'  7!sZ;%  -  )" z. @  {& +.{.; v+     | v% 3 '   ,!&  H>Bp z$\n|!  A).1 (~T0'   &  ! h 8I+!!| !##!^ 0 B= C= C=B % }8',&& ! x 9 ]~6+ 1O 3P 9w"  2 y   ! * "A   3! # 4 $)}%",,V5   |u    ) ~|.  1 ,,~+ ' ~,   , u %! ( t !! +! % z   ! | E  E  ! o }1l"|+ V2!   &,)(C+ C~w{{%# ,j . e7 ,     ! ~  ~  & x    9&  ~  z  ',   cu n p%| ~#    u   u- e7* .:!/; .9!/; EQ553?|9~/7zC@ #}#  / %h  ,  !&# ~ +,-  9b e@ < '/||" n%< " t t t #  } I $ &    ,J   $  ~|  ~  & ( ( :&.,8-9,7-9 ]Y|1G3/~ ~ , (; #* ~   " q+  ~   m {"  p&&|/&&&  !| x  2},#&y',g) /&,w &wu { {"3& !; 2~r n  t  ~2 &#} # $, (2 ( ?,35~)(~(P8 .\\CMSIS\\Include\\cmsis_armcc.hdP8 .\\CMSIS\\Include\\cmsis_armcc.hH devices\MIMXRT1052\drivers\devices\MIMXRT1052\drivers\fsl_clock.cfsl_common.hfsl_clock.hfsl_clock.c devices\MIMXRT1052\drivers\.\devices\MIMXRT1052\C:\Keil_v5\ARM\ARMCC\Bin\..\include\fsl_clock.hfsl_device_registers.hstdint.hstdbool.hassert.hM devices\MIMXRT1052\drivers\fsl_clock.cfsl_clock.h%{% %7  7 -}9  ~jp  ~~?n= L ~?n= uO  n s  w/) } 7 j j+ s  wz b 7 q  " ^U  ^"zgl~       }   } 7 j j+ s  w{  zt  $  %   >z H) Z l { :  :  < < ~,'~  xf  s 1.  b&~ +'~  xf  s 1'  c&4|    &|("&,|("&,  #/~#/2  #/~#/25  !*5  !%{!{ N[P8 .\\CMSIS\\Include\\cmsis_armcc.h`P8 .\\CMSIS\\Include\\cmsis_armcc.hD .\devices\MIMXRT1052\.\middleware\bsp\src\hardware_init_MIMXRT1051.cfsl_device_registers.hflexspi/fsl_flexspi.hflexspi_nor/flexspi_nor_flash.h9 bsp\src\hardware_init_MIMXRT1051.c0z .     ![% (   # '      !Q/ |  ' P8 .\\CMSIS\\Include\\cmsis_armcc.h\P8 .\\CMSIS\\Include\\cmsis_armcc.h@ .\devices\MIMXRT1052\.\devices\MIMXRT1052\drivers\.\middleware\bsp\src\clock_config_MIMXRT1051.cfsl_device_registers.hfsl_clock.hflexspi/fsl_flexspi.h .\devices\MIMXRT1052\drivers\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\MIMXRT1052\fsl_common.hassert.hstdbool.hstdint.hstring.hstdlib.hfsl_device_registers.hfsl_clock.h .\devices\MIMXRT1052\drivers\.\devices\MIMXRT1052\C:\Keil_v5\ARM\ARMCC\Bin\..\include\fsl_clock.hfsl_device_registers.hstdint.hstdbool.hassert.he .\devices\MIMXRT1052\drivers\bsp\src\clock_config_MIMXRT1051.cfsl_clock.hL>xx " ' = %7 1`)(5=';&&R tR  4 %    }~    Y7{|x x % _ d & &'  d  |!  ,u u  & ! ~ | 7P8 .\\CMSIS\\Include\\cmsis_armcc.hXP8 .\\CMSIS\\Include\\cmsis_armcc.h<8. FlashDev.cFlashOS.H .\middleware\.\devices\MIMXRT1052\drivers\flexspi_nor/flexspi_nor_flash.hfsl_common.hflexspi/fsl_flexspi.hth .\middleware\.\devices\MIMXRT1052\drivers\flexspi/fsl_flexspi.hfsl_common.h .\devices\MIMXRT1052\drivers\C:\Keil_v5\ARM\ARMCC\Bin\..\include\.\devices\MIMXRT1052\fsl_common.hassert.hstdbool.hstdint.hstring.hstdlib.hfsl_device_registers.hfsl_clock.hdrivers\fsl_common.hxo .\devices\MIMXRT1052\.\CMSIS\Include\MIMXRT1052.hcore_cm7.hsystem_MIMXRT1052.hPD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h,  FlashOS.H! FlashPrg.cpD #~Dv ,&   ~& %}, K~K|&P8 .\\CMSIS\\Include\\cmsis_armcc.hTP8 .\\CMSIS\\Include\\cmsis_armcc.h8HJ}J}H}UP PWWWPP  }  } }8  } } } } } } } } }}} }8}} }}}}$}}}}}}8}DF}F}bd}dD} >@}@b}}>}&(}(*}*}8}}} }( "}"&}(vx}x}PR}RT}Tt}0tv}BP}4B}&4}&}}}* 8 P& F U U R F V V " Q" F T T & P& F W W P  P P  Q P T Q U P P P P& Z W$ Z V" Z H H P Z Ub f U Z \ V W  W HP U  U \lpPtP2TlT T Z Tb T2TlT T Z Tb T2V VQ2UlU U Z Ub UP2dld d Z db d6ZTT ZWWWZVVVVRZhhQZUUUPZ``PWWSSPQQRRSPQxVVVVvTTT2Vp4VTpTTTT6PPPP"SRVdpdddQVUPV\p\\\PSRQPTQS|PZTNhhDHSHWDJRJUDNQNVDTP>@PSSPPP^^^\\\QQQRRRLbQJZ\^b\S SQ&BQ^n^PnPRnRdWxT|TTT6Tj`|`:@`bfQfV|VVVVbjPjUJ\Q>DP*6PSPQP<RUQWWVVV>RTTT>RUU&8Q>RTTT&0P>Rddd"P$&PT"$TQVPW"$WUUPvzSzTTvRv|Q|VVv~P~WW8dPWPWQWPT4TdUUnU^TpvTPXQXVVZVPXPXddd4dJLPNPPBDP<>P@BP46P.0P24P&(PPPPP P PP~}} }0VX}XZ} Z|}0|~} vx}x~}~V}} } t}tv}}}$}}}"}$"h}(hj}j}(pr}r} <>}>@} @b}bd}dp}vx}x~} ~:}:<}}} t}tv}}} }}~ } } }}} } } ~ } " }" $ }$$ j }j l }l }  } }$ }, } },~}} }} }PR}RT}$T } "}"~}}"}"N}8NP}hj}jl} l}}} h}}}} }  }$ }VX}XZ} Z}(}} }$ V}0}}$}}`b}bf}$f}0}*,},.}.^}8^`}}*}~S~R~Q~PVzSVzRVfQVzPTDVTv|R|RVv~Q~RUvPRWR,S Q pT PPPTTSWWRVVQP\\vRvPfjPPBV8TT$TPZlPPPPS8R"Q"W"P"\xWWptRtVpvQvTpvPv```dP(~(^(S(UPPUU(UUUDUHPUdhUWW~~VV(VVV@VFT~~~~(~~~p~<BRBTUU<DQDTTT(TTT@T<DPDT``RU6VVdVVV.<V~6~Vd~~v|R|6WVdWvQ6TVdTvP6`~Xt^jS8W"W4<WfWPLbVVVV"V4<VfVbvVUdUpUU(U04U@Ddp"WdWpWWW04WR@hDdhphhhQdTpTTT"T4<TfTbhTP@`Dd`p`V&VU&UUUURWQT&TvTP`&`v`PPPPP~ R~ Q U6U~ P ``` & P B RV b R Q  Q ( W( N QV h Q X z X T B TR ~ T R h h z h Q U z U P ` ` z `n r Q Qh l P Q Q Qr P P  Pl x P P @ 0 @ @ @  @" @ @H T @n @ @ D 0 D D D  D" @ DH T D V V 0 V V V V  V" @ VH T Vn V  V  0     " @ H T n   ( B N X  L 0 L L L" @ L  0     " @ H T n    0      " @ H T n   ( X d x   $ S$ R h h 0 h h h  h" @ hH T hn h h $ R$ R d d 0 d d d  d" @ dH T dn d d R Q W 0 W W W  W" @ WH T Wn W  W( X Wl r W ( P \ 0 \ \ \  \" @ \H T \n \ \ PpRdPbT`UTZP$P(TBTT(SBSS(\B\\(^B^^ S(hBh h R(dBdd (QBQQ P(\B\PT TVV VTTXX`WW~R`hh h~Q`UUU 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(64)1FlexSPI_AHB_RX_BUF_COUNT (4U)3FlexSPI_ASFM_BASE (0x00000000U)5FlexSPI_AHB_RX_BUF_DEPTH (512U)7FlexSPI_AHB_TX_BUF_DEPTH (32U)9FlexSPI_IP_RX_BUF_DEPTH (256U);FlexSPI_IP_TX_BUF_DEPTH (256U)>FLEXSPI_CFG_BLK_TAG (0x42464346UL)?FLEXSPI_CFG_BLK_VERSION (0x56010400UL)@FLEXSPI_CFG_BLK_SIZE (512)CFLEXSPI_FEATURE_HAS_PARALLEL_MODE 1FCMD_INDEX_READ 0GCMD_INDEX_READSTATUS 1HCMD_INDEX_WRITEENABLE 2ICMD_INDEX_WRITE 4KCMD_LUT_SEQ_IDX_READ 0LCMD_LUT_SEQ_IDX_READSTATUS 1MCMD_LUT_SEQ_IDX_WRITEENABLE 3NCMD_LUT_SEQ_IDX_WRITE 9PCMD_SDR 0x01QCMD_DDR 0x21RRADDR_SDR 0x02SRADDR_DDR 0x22TCADDR_SDR 0x03UCADDR_DDR 0x23VMODE1_SDR 0x04WMODE1_DDR 0x24XMODE2_SDR 0x05YMODE2_DDR 0x25ZMODE4_SDR 0x06[MODE4_DDR 0x26\MODE8_SDR 0x07]MODE8_DDR 0x27^WRITE_SDR 0x08_WRITE_DDR 0x28`READ_SDR 0x09aREAD_DDR 0x29bLEARN_SDR 0x0AcLEARN_DDR 0x2AdDATSZ_SDR 0x0BeDATSZ_DDR 0x2BfDUMMY_SDR 0x0CgDUMMY_DDR 0x2ChDUMMY_RWDS_SDR 0x0DiDUMMY_RWDS_DDR 0x2DjJMP_ON_CS 0x1FkSTOP 0mFLEXSPI_1PAD 0nFLEXSPI_2PAD 1oFLEXSPI_4PAD 2pFLEXSPI_8PAD 3rFLEXSPI_LUT_SEQ(cmd0,pad0,op0,cmd1,pad1,op1) (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset))&'()*0MAX_24BIT_ADDRESSING_SIZE (16UL * 1024 * 1024)2NOR_CMD_LUT_FOR_IP_CMD 1~SFDP_SIGNATURE 0x50444653'__FLEXSPI_NOR_FLASH_H__ )*-NOR_CMD_INDEX_READ CMD_INDEX_READ.NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS/NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE0NOR_CMD_INDEX_ERASESECTOR 31NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE2NOR_CMD_INDEX_CHIPERASE 53NOR_CMD_INDEX_DUMMY 64NOR_CMD_INDEX_ERASEBLOCK 76NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ7NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS9NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2;NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE=NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4?NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5@NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8ANOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITECNOR_CMD_LUT_SEQ_IDX_CHIPERASE 11DNOR_CMD_LUT_SEQ_IDX_READ_SFDP 13ENOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14GNOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15_FSL_CLOCK_H_ !"#$.CCM_TUPLE(reg,shift,mask,busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))/CCM_TUPLE_REG(base,tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU))))0CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)1CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))2CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)4CCM_NO_BUSY_WAIT (0x20U)AFSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0GFSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))_CLOCK_SetXtal0Freq CLOCK_SetXtalFreq`CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreqcADC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Adc1 }iADC_5HC_CLOCKS { kCLOCK_Adc_5hc }oAOI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 }uBEE_CLOCKS { kCLOCK_Bee }{CMP_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 }CSI_CLOCKS { kCLOCK_Csi }DCDC_CLOCKS { kCLOCK_Dcdc }DCP_CLOCKS { kCLOCK_Dcp }DMAMUX_CLOCKS { kCLOCK_Dma }EDMA_CLOCKS { kCLOCK_Dma }ENC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 }ENET_CLOCKS { kCLOCK_Enet }EWM_CLOCKS { kCLOCK_Ewm0 }FLEXCAN_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 }FLEXCAN_PERIPH_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S }FLEXIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 }FLEXRAM_CLOCKS { kCLOCK_FlexRam }FLEXSPI_CLOCKS { kCLOCK_FlexSpi }GPIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 }GPT_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 }KPP_CLOCKS { kCLOCK_Kpp }LCDIF_CLOCKS { kCLOCK_Lcd }LCDIF_PERIPH_CLOCKS { kCLOCK_LcdPixel }LPI2C_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 }LPSPI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 }LPUART_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 }PIT_CLOCKS { kCLOCK_Pit }PWM_CLOCKS { { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid } , { kCLOCK_Pwm1, kCLOCK_Pwm1,kCLOCK_Pwm1, kCLOCK_Pwm1 } , { kCLOCK_Pwm2, kCLOCK_Pwm2,kCLOCK_Pwm2, kCLOCK_Pwm2 } , { kCLOCK_Pwm3, kCLOCK_Pwm3,kCLOCK_Pwm3, kCLOCK_Pwm3 } , { kCLOCK_Pwm4, kCLOCK_Pwm4,kCLOCK_Pwm4, kCLOCK_Pwm4 } }PXP_CLOCKS { kCLOCK_Pxp }RTWDOG_CLOCKS { kCLOCK_Wdog3 }SAI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 }SEMC_CLOCKS { kCLOCK_Semc }TMR_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 }TRNG_CLOCKS { kCLOCK_Trng }TSC_CLOCKS { kCLOCK_Tsc }WDOG_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 }USDHC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 }SPDIF_CLOCKS { kCLOCK_Spdif }XBARA_CLOCKS { kCLOCK_Xbar1 }XBARB_CLOCKS { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 }kCLOCK_CoreSysClk kCLOCK_CpuClkCLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq %FREQ_396MHz (396000000U)&FREQ_480MHz (480000000U)'FREQ_528MHz (528000000U)(FREQ_24MHz (24000000U)+SW_MUX_CTL_PAD_FLEXSPIB_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05,SW_MUX_CTL_PAD_FLEXSPIB_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00-SW_MUX_CTL_PAD_FLEXSPIB_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01.SW_MUX_CTL_PAD_FLEXSPIB_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02/SW_MUX_CTL_PAD_FLEXSPIB_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_030SW_MUX_CTL_PAD_FLEXSPIB_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_041SW_MUX_CTL_PAD_FLEXSPIB_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_012SW_MUX_CTL_PAD_FLEXSPIB_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_044SW_MUX_CTL_PAD_FLEXSPIA_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_055SW_MUX_CTL_PAD_FLEXSPIA_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_066SW_MUX_CTL_PAD_FLEXSPIA_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_007SW_MUX_CTL_PAD_FLEXSPIA_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_078SW_MUX_CTL_PAD_FLEXSPIA_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_089SW_MUX_CTL_PAD_FLEXSPIA_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09:SW_MUX_CTL_PAD_FLEXSPIA_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10;SW_MUX_CTL_PAD_FLEXSPIA_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11SW_PAD_CTL_PAD_FLEXSPIB_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05?SW_PAD_CTL_PAD_FLEXSPIB_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00@SW_PAD_CTL_PAD_FLEXSPIB_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01ASW_PAD_CTL_PAD_FLEXSPIB_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02BSW_PAD_CTL_PAD_FLEXSPIB_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03CSW_PAD_CTL_PAD_FLEXSPIB_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04DSW_PAD_CTL_PAD_FLEXSPIB_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01ESW_PAD_CTL_PAD_FLEXSPIB_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04GSW_PAD_CTL_PAD_FLEXSPIA_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05HSW_PAD_CTL_PAD_FLEXSPIA_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06ISW_PAD_CTL_PAD_FLEXSPIA_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00JSW_PAD_CTL_PAD_FLEXSPIA_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07KSW_PAD_CTL_PAD_FLEXSPIA_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08LSW_PAD_CTL_PAD_FLEXSPIA_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09MSW_PAD_CTL_PAD_FLEXSPIA_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10NSW_PAD_CTL_PAD_FLEXSPIA_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11OSW_PAD_CTL_PAD_FLEXSPIA_SCLK_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04QFLEXSPIA_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1)RFLEXSPIB_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1)SFLEXSPIA_SS1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(6)TFLEXSPIB_SS1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(6)UFLEXSPIB_SS0_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4)VFLEXSPIB_DQS_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4)]FLEXSPI_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(0) | IOMUXC_SW_PAD_CTL_PAD_PUS(0))gFLEXSPI_DQS_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | IOMUXC_SW_PAD_CTL_PAD_HYS(1)) %FREQ_396MHz (396UL * 1000 * 1000)&FREQ_528MHz (528UL * 1000 * 1000)'FREQ_24MHz (24UL * 1000 * 1000)(FREQ_480MHz (480UL * 1000 * 1000) _FSL_COMMON_H_ "#$%&,8MAKE_STATUS(group,code) ((((group)*100) + (code)));MAKE_VERSION(major,minor,bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))@FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))DDEBUG_CONSOLE_DEVICE_TYPE_NONE 0UEDEBUG_CONSOLE_DEVICE_TYPE_UART 1UFDEBUG_CONSOLE_DEVICE_TYPE_LPUART 2UGDEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3UHDEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4UIDEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5UJDEBUG_CONSOLE_DEVICE_TYPE_IUART 6UKDEBUG_CONSOLE_DEVICE_TYPE_VUSART 7UMIN(a,b) ((a) < (b) ? (a) : (b))MAX(a,b) ((a) > (b) ? (a) : (b))ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))USEC_TO_COUNT(us,clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)COUNT_TO_USEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)MSEC_TO_COUNT(ms,clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)COUNT_TO_MSEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)SDK_ALIGN(var,alignbytes) __align(alignbytes) varSDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) varSDK_SIZEALIGN(var,alignbytes) ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) varAT_NONCACHEABLE_SECTION_ALIGN(var,alignbytes) __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) varAT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) varAT_NONCACHEABLE_SECTION_ALIGN_INIT(var,alignbytes) __attribute__((section("NonCacheable.init"))) __align(alignbytes) varALIGN_DOWN(x,a) ((x) & -(a))ALIGN_UP(x,a) (-(-(x) & -(a)))_FSL_CLOCK_H_ !"#$.CCM_TUPLE(reg,shift,mask,busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))/CCM_TUPLE_REG(base,tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU))))0CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)1CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))2CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)4CCM_NO_BUSY_WAIT (0x20U)AFSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0GFSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))_CLOCK_SetXtal0Freq CLOCK_SetXtalFreq`CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreqcADC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Adc1 }iADC_5HC_CLOCKS { kCLOCK_Adc_5hc }oAOI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 }uBEE_CLOCKS { kCLOCK_Bee }{CMP_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 }CSI_CLOCKS { kCLOCK_Csi }DCDC_CLOCKS { kCLOCK_Dcdc }DCP_CLOCKS { kCLOCK_Dcp }DMAMUX_CLOCKS { kCLOCK_Dma }EDMA_CLOCKS { kCLOCK_Dma }ENC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 }ENET_CLOCKS { kCLOCK_Enet }EWM_CLOCKS { kCLOCK_Ewm0 }FLEXCAN_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 }FLEXCAN_PERIPH_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S }FLEXIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 }FLEXRAM_CLOCKS { kCLOCK_FlexRam }FLEXSPI_CLOCKS { kCLOCK_FlexSpi }GPIO_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 }GPT_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 }KPP_CLOCKS { kCLOCK_Kpp }LCDIF_CLOCKS { kCLOCK_Lcd }LCDIF_PERIPH_CLOCKS { kCLOCK_LcdPixel }LPI2C_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 }LPSPI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 }LPUART_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 }PIT_CLOCKS { kCLOCK_Pit }PWM_CLOCKS { { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid } , { kCLOCK_Pwm1, kCLOCK_Pwm1,kCLOCK_Pwm1, kCLOCK_Pwm1 } , { kCLOCK_Pwm2, kCLOCK_Pwm2,kCLOCK_Pwm2, kCLOCK_Pwm2 } , { kCLOCK_Pwm3, kCLOCK_Pwm3,kCLOCK_Pwm3, kCLOCK_Pwm3 } , { kCLOCK_Pwm4, kCLOCK_Pwm4,kCLOCK_Pwm4, kCLOCK_Pwm4 } }PXP_CLOCKS { kCLOCK_Pxp }RTWDOG_CLOCKS { kCLOCK_Wdog3 }SAI_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 }SEMC_CLOCKS { kCLOCK_Semc }TMR_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 }TRNG_CLOCKS { kCLOCK_Trng }TSC_CLOCKS { kCLOCK_Tsc }WDOG_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 }USDHC_CLOCKS { kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 }SPDIF_CLOCKS { kCLOCK_Spdif }XBARA_CLOCKS { kCLOCK_Xbar1 }XBARB_CLOCKS { kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 }kCLOCK_CoreSysClk kCLOCK_CpuClkCLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq '__FLEXSPI_NOR_FLASH_H__ )*-NOR_CMD_INDEX_READ CMD_INDEX_READ.NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS/NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE0NOR_CMD_INDEX_ERASESECTOR 31NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE2NOR_CMD_INDEX_CHIPERASE 53NOR_CMD_INDEX_DUMMY 64NOR_CMD_INDEX_ERASEBLOCK 76NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ7NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS9NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2;NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE=NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4?NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5@NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8ANOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITECNOR_CMD_LUT_SEQ_IDX_CHIPERASE 11DNOR_CMD_LUT_SEQ_IDX_READ_SFDP 13ENOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14GNOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15'__FSL_FLEXSPI_H__ )/FlexSPI_LUT_COUNT (64)1FlexSPI_AHB_RX_BUF_COUNT (4U)3FlexSPI_ASFM_BASE (0x00000000U)5FlexSPI_AHB_RX_BUF_DEPTH (512U)7FlexSPI_AHB_TX_BUF_DEPTH (32U)9FlexSPI_IP_RX_BUF_DEPTH (256U);FlexSPI_IP_TX_BUF_DEPTH (256U)>FLEXSPI_CFG_BLK_TAG (0x42464346UL)?FLEXSPI_CFG_BLK_VERSION (0x56010400UL)@FLEXSPI_CFG_BLK_SIZE (512)CFLEXSPI_FEATURE_HAS_PARALLEL_MODE 1FCMD_INDEX_READ 0GCMD_INDEX_READSTATUS 1HCMD_INDEX_WRITEENABLE 2ICMD_INDEX_WRITE 4KCMD_LUT_SEQ_IDX_READ 0LCMD_LUT_SEQ_IDX_READSTATUS 1MCMD_LUT_SEQ_IDX_WRITEENABLE 3NCMD_LUT_SEQ_IDX_WRITE 9PCMD_SDR 0x01QCMD_DDR 0x21RRADDR_SDR 0x02SRADDR_DDR 0x22TCADDR_SDR 0x03UCADDR_DDR 0x23VMODE1_SDR 0x04WMODE1_DDR 0x24XMODE2_SDR 0x05YMODE2_DDR 0x25ZMODE4_SDR 0x06[MODE4_DDR 0x26\MODE8_SDR 0x07]MODE8_DDR 0x27^WRITE_SDR 0x08_WRITE_DDR 0x28`READ_SDR 0x09aREAD_DDR 0x29bLEARN_SDR 0x0AcLEARN_DDR 0x2AdDATSZ_SDR 0x0BeDATSZ_DDR 0x2BfDUMMY_SDR 0x0CgDUMMY_DDR 0x2ChDUMMY_RWDS_SDR 0x0DiDUMMY_RWDS_DDR 0x2DjJMP_ON_CS 0x1FkSTOP 0mFLEXSPI_1PAD 0nFLEXSPI_2PAD 1oFLEXSPI_4PAD 2pFLEXSPI_8PAD 3rFLEXSPI_LUT_SEQ(cmd0,pad0,op0,cmd1,pad1,op1) (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset)) _FSL_COMMON_H_ "#$%&,8MAKE_STATUS(group,code) ((((group)*100) + (code)));MAKE_VERSION(major,minor,bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))@FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))DDEBUG_CONSOLE_DEVICE_TYPE_NONE 0UEDEBUG_CONSOLE_DEVICE_TYPE_UART 1UFDEBUG_CONSOLE_DEVICE_TYPE_LPUART 2UGDEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3UHDEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4UIDEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5UJDEBUG_CONSOLE_DEVICE_TYPE_IUART 6UKDEBUG_CONSOLE_DEVICE_TYPE_VUSART 7UMIN(a,b) ((a) < (b) ? (a) : (b))MAX(a,b) ((a) > (b) ? (a) : (b))ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))USEC_TO_COUNT(us,clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)COUNT_TO_USEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)MSEC_TO_COUNT(ms,clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)COUNT_TO_MSEC(count,clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)SDK_ALIGN(var,alignbytes) __align(alignbytes) varSDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) varSDK_SIZEALIGN(var,alignbytes) ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) varAT_NONCACHEABLE_SECTION_ALIGN(var,alignbytes) __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) varAT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) varAT_NONCACHEABLE_SECTION_ALIGN_INIT(var,alignbytes) __attribute__((section("NonCacheable.init"))) __align(alignbytes) varALIGN_DOWN(x,a) ((x) & -(a))ALIGN_UP(x,a) (-(-(x) & -(a)))B_MIMXRT1052_H_ FMCU_MEM_MAP_VERSION 0x0000UHMCU_MEM_MAP_VERSION_MINOR 0x0001UUNUMBER_OF_INT_VECTORS 176__MPU_PRESENT 1__ICACHE_PRESENT 1__DCACHE_PRESENT 1__DTCM_PRESENT 1__NVIC_PRIO_BITS 4__Vendor_SysTickConfig 0__FPU_PRESENT 1 ADC_HC_ADCH_MASK (0x1FU) ADC_HC_ADCH_SHIFT (0U) ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) ADC_HC_AIEN_MASK (0x80U) ADC_HC_AIEN_SHIFT (7U) ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) ADC_HC_COUNT (8U) ADC_HS_COCO0_MASK (0x1U) ADC_HS_COCO0_SHIFT (0U) ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) ADC_R_CDATA_MASK (0xFFFU) ADC_R_CDATA_SHIFT (0U) ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) ADC_R_COUNT (8U) ADC_CFG_ADICLK_MASK (0x3U) ADC_CFG_ADICLK_SHIFT (0U) ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) ADC_CFG_MODE_MASK (0xCU) ADC_CFG_MODE_SHIFT (2U) ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) ADC_CFG_ADLSMP_MASK (0x10U) ADC_CFG_ADLSMP_SHIFT (4U) ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) ADC_CFG_ADIV_MASK (0x60U) ADC_CFG_ADIV_SHIFT (5U) ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) ADC_CFG_ADLPC_MASK (0x80U) ADC_CFG_ADLPC_SHIFT (7U) ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) ADC_CFG_ADSTS_MASK (0x300U) ADC_CFG_ADSTS_SHIFT (8U) ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) ADC_CFG_ADHSC_MASK (0x400U) ADC_CFG_ADHSC_SHIFT (10U) ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) ADC_CFG_REFSEL_MASK (0x1800U) ADC_CFG_REFSEL_SHIFT (11U) ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) ADC_CFG_ADTRG_MASK (0x2000U) ADC_CFG_ADTRG_SHIFT (13U) ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) ADC_CFG_AVGS_MASK (0xC000U) ADC_CFG_AVGS_SHIFT (14U) ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) ADC_CFG_OVWREN_MASK (0x10000U) ADC_CFG_OVWREN_SHIFT (16U) ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) ADC_GC_ADACKEN_MASK (0x1U) ADC_GC_ADACKEN_SHIFT (0U) ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) ADC_GC_DMAEN_MASK (0x2U) ADC_GC_DMAEN_SHIFT (1U) ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) ADC_GC_ACREN_MASK (0x4U) ADC_GC_ACREN_SHIFT (2U) ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) ADC_GC_ACFGT_MASK (0x8U) ADC_GC_ACFGT_SHIFT (3U) ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) ADC_GC_ACFE_MASK (0x10U) ADC_GC_ACFE_SHIFT (4U) ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) ADC_GC_AVGE_MASK (0x20U) ADC_GC_AVGE_SHIFT (5U) ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) ADC_GC_ADCO_MASK (0x40U) ADC_GC_ADCO_SHIFT (6U) ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) ADC_GC_CAL_MASK (0x80U) ADC_GC_CAL_SHIFT (7U) ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) ADC_GS_ADACT_MASK (0x1U) ADC_GS_ADACT_SHIFT (0U) ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) ADC_GS_CALF_MASK (0x2U) ADC_GS_CALF_SHIFT (1U) ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) ADC_GS_AWKST_MASK (0x4U) ADC_GS_AWKST_SHIFT (2U) ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) ADC_CV_CV1_MASK (0xFFFU) ADC_CV_CV1_SHIFT (0U) ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) ADC_CV_CV2_MASK (0xFFF0000U) ADC_CV_CV2_SHIFT (16U) ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) ADC_OFS_OFS_MASK (0xFFFU) ADC_OFS_OFS_SHIFT (0U) ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) ADC_OFS_SIGN_MASK (0x1000U) ADC_OFS_SIGN_SHIFT (12U) ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) ADC_CAL_CAL_CODE_MASK (0xFU) ADC_CAL_CAL_CODE_SHIFT (0U) ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) ADC1_BASE (0x400C4000u) ADC1 ((ADC_Type *)ADC1_BASE) ADC2_BASE (0x400C8000u) ADC2 ((ADC_Type *)ADC2_BASE) ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) ADC_ETC_CTRL_SOFTRST_SHIFT (31U) ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) ADC_ETC_TRIGn_CTRL_COUNT (8U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) ADC_ETC_TRIGn_COUNTER_COUNT (8U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)ADC_ETC_BASE (0x403B0000u)ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }ADC_ETC_BASE_PTRS { ADC_ETC }ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }AIPSTZ_MPR_MPROT5_MASK (0xF00U)AIPSTZ_MPR_MPROT5_SHIFT (8U)AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)AIPSTZ_MPR_MPROT3_MASK (0xF0000U)AIPSTZ_MPR_MPROT3_SHIFT (16U)AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)AIPSTZ_MPR_MPROT2_MASK (0xF00000U)AIPSTZ_MPR_MPROT2_SHIFT (20U)AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)AIPSTZ_MPR_MPROT1_MASK (0xF000000U)AIPSTZ_MPR_MPROT1_SHIFT (24U)AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)AIPSTZ_MPR_MPROT0_SHIFT (28U)AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)AIPSTZ_OPACR_OPAC7_MASK (0xFU)AIPSTZ_OPACR_OPAC7_SHIFT (0U)AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)AIPSTZ_OPACR_OPAC6_MASK (0xF0U)AIPSTZ_OPACR_OPAC6_SHIFT (4U)AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)AIPSTZ_OPACR_OPAC5_MASK (0xF00U)AIPSTZ_OPACR_OPAC5_SHIFT (8U)AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)AIPSTZ_OPACR_OPAC4_MASK (0xF000U)AIPSTZ_OPACR_OPAC4_SHIFT (12U)AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)AIPSTZ_OPACR_OPAC3_SHIFT (16U)AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)AIPSTZ_OPACR_OPAC2_SHIFT (20U)AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)AIPSTZ_OPACR_OPAC1_SHIFT (24U)AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)AIPSTZ_OPACR_OPAC0_SHIFT (28U)AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)AIPSTZ_OPACR1_OPAC15_MASK (0xFU)AIPSTZ_OPACR1_OPAC15_SHIFT (0U)AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)AIPSTZ_OPACR1_OPAC14_SHIFT (4U)AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)AIPSTZ_OPACR1_OPAC13_SHIFT (8U)AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)AIPSTZ_OPACR1_OPAC12_SHIFT (12U)AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)AIPSTZ_OPACR1_OPAC11_SHIFT (16U)AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)AIPSTZ_OPACR1_OPAC10_SHIFT (20U)AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)AIPSTZ_OPACR1_OPAC9_SHIFT (24U)AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)AIPSTZ_OPACR1_OPAC8_SHIFT (28U)AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)AIPSTZ_OPACR2_OPAC23_MASK (0xFU)AIPSTZ_OPACR2_OPAC23_SHIFT (0U)AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)AIPSTZ_OPACR2_OPAC22_SHIFT (4U)AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)AIPSTZ_OPACR2_OPAC21_SHIFT (8U)AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)AIPSTZ_OPACR2_OPAC20_SHIFT (12U)AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)AIPSTZ_OPACR2_OPAC19_SHIFT (16U)AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)AIPSTZ_OPACR2_OPAC18_SHIFT (20U)AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)AIPSTZ_OPACR2_OPAC17_SHIFT (24U)AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)AIPSTZ_OPACR2_OPAC16_SHIFT (28U)AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)AIPSTZ_OPACR3_OPAC31_MASK (0xFU)AIPSTZ_OPACR3_OPAC31_SHIFT (0U)AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)AIPSTZ_OPACR3_OPAC30_SHIFT (4U)AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)AIPSTZ_OPACR3_OPAC29_SHIFT (8U)AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)AIPSTZ_OPACR3_OPAC28_SHIFT (12U)AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)AIPSTZ_OPACR3_OPAC27_SHIFT (16U)AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)AIPSTZ_OPACR3_OPAC26_SHIFT (20U)AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)AIPSTZ_OPACR3_OPAC25_SHIFT (24U)AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)AIPSTZ_OPACR3_OPAC24_SHIFT (28U)AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)AIPSTZ_OPACR4_OPAC33_SHIFT (24U)AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)AIPSTZ_OPACR4_OPAC32_SHIFT (28U)AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)AIPSTZ1_BASE (0x4007C000u)AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)AIPSTZ2_BASE (0x4017C000u)AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)AIPSTZ3_BASE (0x4027C000u)AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)AIPSTZ4_BASE (0x4037C000u)AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }AOI_BFCRT01_PT1_DC_MASK (0x3U)AOI_BFCRT01_PT1_DC_SHIFT (0U)AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)AOI_BFCRT01_PT1_CC_MASK (0xCU)AOI_BFCRT01_PT1_CC_SHIFT (2U)AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)AOI_BFCRT01_PT1_BC_MASK (0x30U)AOI_BFCRT01_PT1_BC_SHIFT (4U)AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)AOI_BFCRT01_PT1_AC_MASK (0xC0U)AOI_BFCRT01_PT1_AC_SHIFT (6U)AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)AOI_BFCRT01_PT0_DC_MASK (0x300U)AOI_BFCRT01_PT0_DC_SHIFT (8U)AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)AOI_BFCRT01_PT0_CC_MASK (0xC00U)AOI_BFCRT01_PT0_CC_SHIFT (10U)AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)AOI_BFCRT01_PT0_BC_MASK (0x3000U)AOI_BFCRT01_PT0_BC_SHIFT (12U)AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)AOI_BFCRT01_PT0_AC_MASK (0xC000U)AOI_BFCRT01_PT0_AC_SHIFT (14U)AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)AOI_BFCRT01_COUNT (4U)AOI_BFCRT23_PT3_DC_MASK (0x3U)AOI_BFCRT23_PT3_DC_SHIFT (0U)AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)AOI_BFCRT23_PT3_CC_MASK (0xCU)AOI_BFCRT23_PT3_CC_SHIFT (2U)AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)AOI_BFCRT23_PT3_BC_MASK (0x30U)AOI_BFCRT23_PT3_BC_SHIFT (4U)AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)AOI_BFCRT23_PT3_AC_MASK (0xC0U)AOI_BFCRT23_PT3_AC_SHIFT (6U)AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)AOI_BFCRT23_PT2_DC_MASK (0x300U)AOI_BFCRT23_PT2_DC_SHIFT (8U)AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)AOI_BFCRT23_PT2_CC_MASK (0xC00U)AOI_BFCRT23_PT2_CC_SHIFT (10U)AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)AOI_BFCRT23_PT2_BC_MASK (0x3000U)AOI_BFCRT23_PT2_BC_SHIFT (12U)AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)AOI_BFCRT23_PT2_AC_MASK (0xC000U)AOI_BFCRT23_PT2_AC_SHIFT (14U)AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)AOI_BFCRT23_COUNT (4U)AOI1_BASE (0x403B4000u)AOI1 ((AOI_Type *)AOI1_BASE)AOI2_BASE (0x403B8000u)AOI2 ((AOI_Type *)AOI2_BASE)AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }BEE_CTRL_BEE_ENABLE_MASK (0x1U)BEE_CTRL_BEE_ENABLE_SHIFT (0U)BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)BEE_CTRL_KEY_VALID_MASK (0x10U)BEE_CTRL_KEY_VALID_SHIFT (4U)BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)BEE_CTRL_AC_PROT_EN_MASK (0x40U)BEE_CTRL_AC_PROT_EN_SHIFT (6U)BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU)BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U)BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U)BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK)BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W0_KEY0_SHIFT (0U)BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W1_KEY1_SHIFT (0U)BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W2_KEY2_SHIFT (0U)BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)BEE_AES_KEY0_W3_KEY3_SHIFT (0U)BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)BEE_STATUS_IRQ_VEC_MASK (0xFFU)BEE_STATUS_IRQ_VEC_SHIFT (0U)BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)BEE_STATUS_BEE_IDLE_MASK (0x100U)BEE_STATUS_BEE_IDLE_SHIFT (8U)BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)BEE_BASE (0x403EC000u)BEE ((BEE_Type *)BEE_BASE)BEE_BASE_ADDRS { BEE_BASE }BEE_BASE_PTRS { BEE }CAN_MCR_MAXMB_MASK (0x7FU)CAN_MCR_MAXMB_SHIFT (0U)CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)CAN_MCR_IDAM_MASK (0x300U)CAN_MCR_IDAM_SHIFT (8U)CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)CAN_MCR_AEN_MASK (0x1000U)CAN_MCR_AEN_SHIFT (12U)CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)CAN_MCR_LPRIOEN_MASK (0x2000U)CAN_MCR_LPRIOEN_SHIFT (13U)CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)CAN_MCR_IRMQ_MASK (0x10000U)CAN_MCR_IRMQ_SHIFT (16U)CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)CAN_MCR_SRXDIS_MASK (0x20000U)CAN_MCR_SRXDIS_SHIFT (17U)CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)CAN_MCR_WAKSRC_MASK (0x80000U)CAN_MCR_WAKSRC_SHIFT (19U)CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)CAN_MCR_LPMACK_MASK (0x100000U)CAN_MCR_LPMACK_SHIFT (20U)CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)CAN_MCR_WRNEN_MASK (0x200000U)CAN_MCR_WRNEN_SHIFT (21U)CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)CAN_MCR_SLFWAK_MASK (0x400000U)CAN_MCR_SLFWAK_SHIFT (22U)CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)CAN_MCR_SUPV_MASK (0x800000U)CAN_MCR_SUPV_SHIFT (23U)CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)CAN_MCR_FRZACK_MASK (0x1000000U)CAN_MCR_FRZACK_SHIFT (24U)CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)CAN_MCR_SOFTRST_MASK (0x2000000U)CAN_MCR_SOFTRST_SHIFT (25U)CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)CAN_MCR_WAKMSK_MASK (0x4000000U)CAN_MCR_WAKMSK_SHIFT (26U)CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)CAN_MCR_NOTRDY_MASK (0x8000000U)CAN_MCR_NOTRDY_SHIFT (27U)CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)CAN_MCR_HALT_MASK (0x10000000U)CAN_MCR_HALT_SHIFT (28U)CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)CAN_MCR_RFEN_MASK (0x20000000U)CAN_MCR_RFEN_SHIFT (29U)CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)CAN_MCR_FRZ_MASK (0x40000000U)CAN_MCR_FRZ_SHIFT (30U)CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)CAN_MCR_MDIS_MASK (0x80000000U)CAN_MCR_MDIS_SHIFT (31U)CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)CAN_CTRL1_PROPSEG_MASK (0x7U)CAN_CTRL1_PROPSEG_SHIFT (0U)CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)CAN_CTRL1_LOM_MASK (0x8U)CAN_CTRL1_LOM_SHIFT (3U)CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)CAN_CTRL1_LBUF_MASK (0x10U)CAN_CTRL1_LBUF_SHIFT (4U)CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)CAN_CTRL1_TSYN_MASK (0x20U)CAN_CTRL1_TSYN_SHIFT (5U)CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)CAN_CTRL1_BOFFREC_MASK (0x40U)CAN_CTRL1_BOFFREC_SHIFT (6U)CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)CAN_CTRL1_SMP_MASK (0x80U)CAN_CTRL1_SMP_SHIFT (7U)CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)CAN_CTRL1_RWRNMSK_MASK (0x400U)CAN_CTRL1_RWRNMSK_SHIFT (10U)CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)CAN_CTRL1_TWRNMSK_MASK (0x800U)CAN_CTRL1_TWRNMSK_SHIFT (11U)CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)CAN_CTRL1_LPB_MASK (0x1000U)CAN_CTRL1_LPB_SHIFT (12U)CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)CAN_CTRL1_ERRMSK_MASK (0x4000U)CAN_CTRL1_ERRMSK_SHIFT (14U)CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)CAN_CTRL1_BOFFMSK_MASK (0x8000U)CAN_CTRL1_BOFFMSK_SHIFT (15U)CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)CAN_CTRL1_PSEG2_MASK (0x70000U)CAN_CTRL1_PSEG2_SHIFT (16U)CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)CAN_CTRL1_PSEG1_MASK (0x380000U)CAN_CTRL1_PSEG1_SHIFT (19U)CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)CAN_CTRL1_RJW_MASK (0xC00000U)CAN_CTRL1_RJW_SHIFT (22U)CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)CAN_CTRL1_PRESDIV_MASK (0xFF000000U)CAN_CTRL1_PRESDIV_SHIFT (24U)CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)CAN_TIMER_TIMER_MASK (0xFFFFU)CAN_TIMER_TIMER_SHIFT (0U)CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)CAN_RXMGMASK_MG_SHIFT (0U)CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)CAN_RX14MASK_RX14M_SHIFT (0U)CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)CAN_RX15MASK_RX15M_SHIFT (0U)CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)CAN_ESR1_WAKINT_MASK (0x1U)CAN_ESR1_WAKINT_SHIFT (0U)CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)CAN_ESR1_ERRINT_MASK (0x2U)CAN_ESR1_ERRINT_SHIFT (1U)CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)CAN_ESR1_BOFFINT_MASK (0x4U)CAN_ESR1_BOFFINT_SHIFT (2U)CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)CAN_ESR1_RX_MASK (0x8U)CAN_ESR1_RX_SHIFT (3U)CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)CAN_ESR1_FLTCONF_MASK (0x30U)CAN_ESR1_FLTCONF_SHIFT (4U)CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)CAN_ESR1_TX_MASK (0x40U)CAN_ESR1_TX_SHIFT (6U)CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)CAN_ESR1_IDLE_MASK (0x80U)CAN_ESR1_IDLE_SHIFT (7U)CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)CAN_ESR1_RXWRN_MASK (0x100U)CAN_ESR1_RXWRN_SHIFT (8U)CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)CAN_ESR1_TXWRN_MASK (0x200U)CAN_ESR1_TXWRN_SHIFT (9U)CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)CAN_ESR1_STFERR_MASK (0x400U)CAN_ESR1_STFERR_SHIFT (10U)CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)CAN_ESR1_FRMERR_MASK (0x800U)CAN_ESR1_FRMERR_SHIFT (11U)CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)CAN_ESR1_CRCERR_MASK (0x1000U)CAN_ESR1_CRCERR_SHIFT (12U)CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)CAN_ESR1_ACKERR_MASK (0x2000U)CAN_ESR1_ACKERR_SHIFT (13U)CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)CAN_ESR1_BIT0ERR_MASK (0x4000U)CAN_ESR1_BIT0ERR_SHIFT (14U)CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)CAN_ESR1_BIT1ERR_MASK (0x8000U)CAN_ESR1_BIT1ERR_SHIFT (15U)CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)CAN_ESR1_RWRNINT_MASK (0x10000U)CAN_ESR1_RWRNINT_SHIFT (16U)CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)CAN_ESR1_TWRNINT_MASK (0x20000U)CAN_ESR1_TWRNINT_SHIFT (17U)CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)CAN_ESR1_SYNCH_MASK (0x40000U)CAN_ESR1_SYNCH_SHIFT (18U)CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)CAN_IMASK2_BUFHM_SHIFT (0U)CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)CAN_IMASK1_BUFLM_SHIFT (0U)CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)CAN_IFLAG2_BUFHI_SHIFT (0U)CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)CAN_IFLAG1_BUF4TO0I_SHIFT (0U)CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)CAN_IFLAG1_BUF5I_MASK (0x20U)CAN_IFLAG1_BUF5I_SHIFT (5U)CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)CAN_IFLAG1_BUF6I_MASK (0x40U)CAN_IFLAG1_BUF6I_SHIFT (6U)CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)CAN_IFLAG1_BUF7I_MASK (0x80U)CAN_IFLAG1_BUF7I_SHIFT (7U)CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)CAN_IFLAG1_BUF31TO8I_SHIFT (8U)CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)CAN_CTRL2_EACEN_MASK (0x10000U)CAN_CTRL2_EACEN_SHIFT (16U)CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)CAN_CTRL2_RRS_MASK (0x20000U)CAN_CTRL2_RRS_SHIFT (17U)CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)CAN_CTRL2_MRP_MASK (0x40000U)CAN_CTRL2_MRP_SHIFT (18U)CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)CAN_CTRL2_TASD_MASK (0xF80000U)CAN_CTRL2_TASD_SHIFT (19U)CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)CAN_CTRL2_RFFN_MASK (0xF000000U)CAN_CTRL2_RFFN_SHIFT (24U)CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)CAN_CTRL2_WRMFRZ_MASK (0x10000000U)CAN_CTRL2_WRMFRZ_SHIFT (28U)CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)CAN_ESR2_IMB_MASK (0x2000U)CAN_ESR2_IMB_SHIFT (13U)CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)CAN_ESR2_VPS_MASK (0x4000U)CAN_ESR2_VPS_SHIFT (14U)CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)CAN_ESR2_LPTM_MASK (0x7F0000U)CAN_ESR2_LPTM_SHIFT (16U)CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)CAN_CRCR_TXCRC_MASK (0x7FFFU)CAN_CRCR_TXCRC_SHIFT (0U)CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)CAN_CRCR_MBCRC_MASK (0x7F0000U)CAN_CRCR_MBCRC_SHIFT (16U)CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)CAN_RXFGMASK_FGM_SHIFT (0U)CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)CAN_RXFIR_IDHIT_MASK (0x1FFU)CAN_RXFIR_IDHIT_SHIFT (0U)CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)CAN_CS_TIME_STAMP_MASK (0xFFFFU)CAN_CS_TIME_STAMP_SHIFT (0U)CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)CAN_CS_DLC_MASK (0xF0000U)CAN_CS_DLC_SHIFT (16U)CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)CAN_CS_RTR_MASK (0x100000U)CAN_CS_RTR_SHIFT (20U)CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)CAN_CS_IDE_MASK (0x200000U)CAN_CS_IDE_SHIFT (21U)CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)CAN_CS_SRR_MASK (0x400000U)CAN_CS_SRR_SHIFT (22U)CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)CAN_CS_CODE_MASK (0xF000000U)CAN_CS_CODE_SHIFT (24U)CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)CAN_CS_COUNT (64U)CAN_ID_EXT_MASK (0x3FFFFU)CAN_ID_EXT_SHIFT (0U)CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)CAN_ID_STD_MASK (0x1FFC0000U)CAN_ID_STD_SHIFT (18U)CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)CAN_ID_PRIO_MASK (0xE0000000U)CAN_ID_PRIO_SHIFT (29U)CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)CAN_ID_COUNT (64U)CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)CAN_WORD0_DATA_BYTE_3_SHIFT (0U)CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)CAN_WORD0_DATA_BYTE_2_SHIFT (8U)CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)CAN_WORD0_DATA_BYTE_1_SHIFT (16U)CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)CAN_WORD0_DATA_BYTE_0_SHIFT (24U)CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)CAN_WORD0_COUNT (64U)CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)CAN_WORD1_DATA_BYTE_7_SHIFT (0U)CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)CAN_WORD1_DATA_BYTE_6_SHIFT (8U)CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)CAN_WORD1_DATA_BYTE_5_SHIFT (16U)CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)CAN_WORD1_DATA_BYTE_4_SHIFT (24U)CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)CAN_WORD1_COUNT (64U)CAN_RXIMR_MI_MASK (0xFFFFFFFFU)CAN_RXIMR_MI_SHIFT (0U)CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)CAN_RXIMR_COUNT (64U)CAN_GFWR_GFWR_MASK (0xFFU)CAN_GFWR_GFWR_SHIFT (0U)CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)CAN1_BASE (0x401D0000u)CAN1 ((CAN_Type *)CAN1_BASE)CAN2_BASE (0x401D4000u)CAN2 ((CAN_Type *)CAN2_BASE)CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASKCAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFTCAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASKCAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFTCAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)CCM_CCR_OSCNT_MASK (0xFFU)CCM_CCR_OSCNT_SHIFT (0U)CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)CCM_CCR_COSC_EN_MASK (0x1000U)CCM_CCR_COSC_EN_SHIFT (12U)CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)CCM_CCR_RBC_EN_MASK (0x8000000U)CCM_CCR_RBC_EN_SHIFT (27U)CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)CCM_CSR_REF_EN_B_MASK (0x1U)CCM_CSR_REF_EN_B_SHIFT (0U)CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)CCM_CSR_CAMP2_READY_MASK (0x8U)CCM_CSR_CAMP2_READY_SHIFT (3U)CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)CCM_CSR_COSC_READY_MASK (0x20U)CCM_CSR_COSC_READY_SHIFT (5U)CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)CCM_CACRR_ARM_PODF_MASK (0x7U)CCM_CACRR_ARM_PODF_SHIFT (0U)CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)CCM_CBCDR_IPG_PODF_MASK (0x300U)CCM_CBCDR_IPG_PODF_SHIFT (8U)CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)CCM_CBCDR_AHB_PODF_MASK (0x1C00U)CCM_CBCDR_AHB_PODF_SHIFT (10U)CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)CCM_CBCDR_SEMC_PODF_MASK (0x70000U)CCM_CBCDR_SEMC_PODF_SHIFT (16U)CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)CCM_CBCMR_LCDIF_PODF_SHIFT (23U)CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)CCM_CBCMR_LPSPI_PODF_SHIFT (26U)CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)CCM_CSCDR1_TRACE_PODF_MASK (0xE000000U)CCM_CSCDR1_TRACE_PODF_SHIFT (25U)CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0xE00U)CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9U)CCM_CSCDR2_LCDIF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_CLK_SEL_MASK)CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)CCM_CSCDR3_CSI_PODF_MASK (0x3800U)CCM_CSCDR3_CSI_PODF_SHIFT (11U)CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)CCM_CLPCR_LPM_MASK (0x3U)CCM_CLPCR_LPM_SHIFT (0U)CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)CCM_CLPCR_SBYOS_MASK (0x40U)CCM_CLPCR_SBYOS_SHIFT (6U)CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)CCM_CLPCR_VSTBY_MASK (0x100U)CCM_CLPCR_VSTBY_SHIFT (8U)CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)CCM_CLPCR_STBY_COUNT_MASK (0x600U)CCM_CLPCR_STBY_COUNT_SHIFT (9U)CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)CCM_CISR_LRF_PLL_MASK (0x1U)CCM_CISR_LRF_PLL_SHIFT (0U)CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)CCM_CISR_COSC_READY_MASK (0x40U)CCM_CISR_COSC_READY_SHIFT (6U)CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_